Method for improving hot carriers of RFID electronic tag chip

Abstract

The invention discloses a method for improving a hot carrier of an RFID (Radio Frequency Identification Device) electronic tag chip, which relates to the field of RFID tag chips and comprises the following steps of: forming field oxide on the surface of a substrate based on an etching process and a wet oxidation mode; forming a protection ring between the field oxide and the substrate; impurity ions are injected into the protection ring to form a protection ring structure; forming a field effect transistor preliminary structure of the RFID electronic tag chip on the surface of the trap; depositing an insulating layer on the surface of the substrate, and exposing the preliminary structure of the field effect transistor and the protection ring structure from the insulating layer; filling contact holes in the primary structure of the effect transistor and the protection ring structure, and forming a metal layer outside the contact holes to obtain a field effect transistor structure of the RFID electronic tag chip; and annealing the field effect transistor structure. According to the invention, a large amount of hot carriers are effectively prevented from being injected into the gate oxide layer and the substrate, continuous damage of the hot carriers to the chip is reduced, and the service life of the chip is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of RFID tag chips, and in particular to a method for improving hot carriers of RFID electronic tag chips. Background Art

[0002] With the continuous progress of microelectronics process technology, very large scale integrated circuits (VLSI) have been driven to develop in the direction of deep submicron level. The feature size of devices has gradually decreased. The increase in circuit integration will bring higher yield and lower cost. More circuits can be integrated into one chip, which can also increase the speed of devices and reduce device losses. But at the same time, the reduction of applied voltage is limited. This will lead to an increase in the lateral electric field of the channel of the device. As the lateral electric field of the channel increases, the acceleration of carriers in the channel will become faster and faster, and the energy obtained by the carriers will become larger and larger, or the electrons will be "heated". These "heated" carriers are called hot carriers. These carriers are not in thermal equilibrium with the lattice. When their energy reaches or exceeds the Si / SiO2 interface barrier, they will be injected into the oxide layer, generating interface states, oxide layer traps or being captured by traps, causing the oxide layer charge to increase or fluctuate unstably. This is the hot carrier effect.

[0003] The generation of hot carriers causes the device characteristics to degrade, affecting the reliability and life of the chip. For a long time, the hot carrier effect has been considered the main factor limiting the reduction of device size.

[0004] In order to improve the hot carrier effect, the current industry often uses the light doped drain (LDD) process technology to reduce the peak electric field near the gate end to the drain end of the device. The lightly doped LDD structure acts as a connection area to make the electric field appear a slow change process, weakening the peak electric field strength to improve the hot carrier effect. However, as the size of MOSFET devices continues to shrink, in the current advanced process, the traditional LDD structure has limited ability to improve the hot carrier effect, making the life and reliability of the device very serious. New technologies are urgently needed to further improve the hot carrier effect.

[0005] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention

[0006] In view of the problems in the related art, the present invention proposes a method for improving hot carriers of RFID electronic tag chips to overcome the above technical problems existing in the existing related art.

[0007] To this end, the specific technical solution adopted by the present invention is as follows:

[0008] A method for improving hot carriers of an RFID electronic tag chip, the method comprising:

[0009] S1. Based on the etching process and wet oxidation method, field oxygen is formed on the surface of the substrate; a guard ring is formed between the field oxygen and the substrate by using an injection well;

[0010] S2, injecting impurity ions into the guard ring to form a guard ring structure; forming a preliminary structure of a field effect transistor of the RFID electronic tag chip on the well surface by means of deposition and ion injection;

[0011] S3, depositing an insulating layer on the surface of the substrate, and exposing the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer;

[0012] S4, filling the contact holes in the preliminary structure of the field effect transistor and the guard ring structure, and forming a metal layer outside the contact hole to obtain the field effect transistor structure of the RFID electronic tag chip;

[0013] S5. Perform annealing on the field effect transistor structure of the RFID electronic tag chip to obtain a corresponding ohmic contact electrode.

[0014] Further, based on the etching process and the wet oxidation method, field oxide is formed on the surface of the substrate, including:

[0015] Forming a first oxide layer and a first nitride layer on the substrate in sequence, and etching the first nitride layer, the first oxide layer and the substrate in sequence by using a dry etching process to form a groove;

[0016] Filling the trench with a shallow trench isolation material, and removing the first oxide layer and the first nitride layer;

[0017] An oxide layer is grown on the surface of the substrate by wet oxidation, and the oxide layer is exposed, photoresist is removed and wet etched to form field oxide.

[0018] Furthermore, the oxidation thickness of the oxide layer is associated with the oxidation time, and the relationship between the oxidation thickness of the oxide layer and the required oxidation time is:

[0019]

[0020] Where, T ox is the oxide thickness, t is the oxidation time;

[0021] A, B and τ are parameters that describe the oxidation rate.

[0022] Furthermore, forming a guard ring between the field oxide and the substrate by means of an implant well includes:

[0023] Wells are implanted into the area between the field oxygens and on the top of the substrate to form a guard ring.

[0024] Furthermore, the impurity ions are implanted into the guard ring to form the guard ring structure, including:

[0025] The field oxygen on the surface of the guard ring is removed by etching, and impurity ions are injected into the guard ring to form a guard ring structure.

[0026] Furthermore, by means of deposition and ion implantation, a preliminary structure of a field effect transistor of an RFID electronic tag chip is formed on the well surface, including:

[0027] forming an oxide insulating layer and a polysilicon layer in sequence on the surface of the well to obtain a gate structure;

[0028] Implanting lightly doped ions on both sides of the oxide insulating layer and the polysilicon layer to form a source region and a drain region;

[0029] Forming side walls of the insulating layer on both sides of the gate structure, and forming a final source region and a final drain region by injecting source and drain ions on both sides of the side walls and on the surfaces of the source region and the drain region;

[0030] Wherein, the preliminary structure of the field effect transistor of the RFID electronic tag chip includes a gate structure, a final source region and a final drain region.

[0031] Further, depositing an insulating layer on the surface of the substrate and exposing the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer includes:

[0032] depositing a contact resistance reducing layer on the surface of the field effect transistor preliminary structure and the guard ring structure;

[0033] An insulating layer is deposited on the surface of the substrate by chemical vapor deposition, and the insulating layer is etched to expose the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer, and to form a plurality of contact holes.

[0034] Further, the contact holes in the preliminary structure of the field effect transistor and the guard ring structure are filled, and a metal layer is formed outside the contact hole, so that the field effect transistor structure of the RFID electronic tag chip is obtained, including:

[0035] Filling the contact hole by sputtering a thin film on the surface of the preliminary structure of the effect transistor and the guard ring structure and depositing a metal tungsten layer on the thin film;

[0036] On the surface of the field effect transistor preliminary structure and the guard ring structure, a metal layer is formed by combining deposition and etching to obtain the field effect transistor structure of the RFID electronic tag chip.

[0037] Furthermore, the metal layer includes a first titanium layer, an aluminum layer, a second titanium layer and a titanium nitride layer.

[0038] Further, the impurity ions include P-type impurity ions and N-type impurity ions, and the guard ring structure includes a P-type guard ring structure and an N-type guard ring structure.

[0039] The beneficial effects of the present invention are:

[0040] (1) The present invention effectively blocks a large number of hot carriers from being injected into the gate oxide layer and the substrate, reduces the continuous damage of hot carriers to the chip, and increases the service life of the chip. In the manufacture of chip MOSFET devices, a substrate ohmic contact protection ring structure is added. By surrounding the device, it attracts most of the carriers generated by high electric field collision, prevents a large number of hot carriers from being injected into the gate oxide layer, generates interface states, and solves the adverse effects of hot carrier effects on the reliability and service life of chip devices.

[0041] (2) By adding a guard ring structure around the device, it is only necessary to apply a low level to the ohmic contact electrode near one end of the drain region. Most of the carriers generated by the collision under the action of the high electric field will be attracted by the guard ring structure with a low level, and thus flow directly through the substrate to the vicinity of the source, effectively preventing a large number of hot carriers from being injected into the vicinity of the gate oxide layer, thereby preventing high-energy electrons from crossing the potential barrier to impact the gate oxide, thereby solving the problem of continuous damage to the chip caused by the hot carrier effect and improving the service life of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 is one of the schematic diagrams for manufacturing an NMOS device according to an embodiment of the present invention;

[0044] Figure 2 is a second schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0045] Figure 3 is a third schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0046] Figure 4 is a fourth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0047] Figure 5is a fifth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0048] Figure 6 is the sixth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0049] Figure 7 is the seventh schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0050] Figure 8 is an eighth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0051] Fig. 9 is a ninth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0052] Fig.10 is a tenth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0053] Fig.11 is the eleventh schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0054] Fig.12 is a twelfth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0055] Fig.13 is the thirteenth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0056] Fig.14 is the fourteenth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0057] Fig.15 is the fifteenth schematic diagram of manufacturing an NMOS device according to an embodiment of the present invention;

[0058] Fig.16 The present invention is a flowchart of a method for improving hot carriers in an RFID electronic tag chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0059] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in the field should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0060] According to an embodiment of the present invention, a method for improving hot carriers of an RFID electronic tag chip is provided.

[0061] The present invention is further described with reference to the accompanying drawings and specific embodiments. Fig.16 As shown, the method for improving hot carriers of an RFID electronic tag chip according to an embodiment of the present invention includes:

[0062] S1. Based on the etching process and wet oxidation method, field oxygen is formed on the surface of the substrate; by using the injection well method, a guard ring is formed between the field oxygen and the substrate.

[0063] S2. Inject impurity ions into the guard ring to form a guard ring structure; and form a preliminary structure of a field effect transistor of the RFID electronic tag chip on the well surface by means of deposition and ion injection.

[0064] S3. Deposit an insulating layer on the surface of the substrate, and expose the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer.

[0065] S4, filling the contact holes in the preliminary structure of the field effect transistor and the guard ring structure, and forming a metal layer outside the contact hole to obtain the field effect transistor structure of the RFID electronic tag chip.

[0066] S5. Perform annealing on the field effect transistor structure of the RFID electronic tag chip to obtain a corresponding ohmic contact electrode.

[0067] In one embodiment, forming field oxide on the surface of the substrate based on an etching process and a wet oxidation method includes:

[0068] A first oxide layer and a first nitride layer are sequentially formed on the substrate, and the first nitride layer, the first oxide layer and the substrate are sequentially etched using a dry etching process to form a groove.

[0069] The trench is filled with a shallow trench isolation material, and the first oxide layer and the first nitride layer are removed.

[0070] An oxide layer is grown on the surface of the substrate by wet oxidation, and the oxide layer is exposed, photoresist is removed and wet etched to form field oxide.

[0071] In one embodiment, the oxidation thickness of the oxide layer is associated with the oxidation time, and the relationship between the oxidation thickness of the oxide layer and the required oxidation time is:

[0072]

[0073] Where, T ox is the oxidation thickness, t is the oxidation time; A, B and τ are all parameters that describe the oxidation rate.

[0074] In one embodiment, forming a guard ring between the field oxide and the substrate by means of an implant well includes:

[0075] Wells are implanted into the area between the field oxygens and on the top of the substrate to form a guard ring.

[0076] In one embodiment, implanting impurity ions into the guard ring to form the guard ring structure includes:

[0077] The field oxygen on the surface of the guard ring is removed by etching, and impurity ions are injected into the guard ring to form a guard ring structure.

[0078] In one embodiment, the preliminary structure of the field effect transistor of the RFID electronic tag chip is formed on the well surface by deposition and ion implantation, including:

[0079] An oxide insulating layer and a polysilicon layer are sequentially formed on the surface of the well to obtain a gate structure.

[0080] Lightly doped ions are implanted on both sides of the oxide insulating layer and the polysilicon layer to form a source region and a drain region.

[0081] The sidewalls of the insulating layer are formed on both sides of the gate structure, and source and drain ions are implanted on both sides of the sidewalls and on the surfaces of the source and drain regions to form a final source region and a final drain region.

[0082] Wherein, the preliminary structure of the field effect transistor of the RFID electronic tag chip includes a gate structure, a final source region and a final drain region.

[0083] In one embodiment, depositing an insulating layer on the surface of the substrate and exposing the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer comprises:

[0084] A contact resistance reducing layer is deposited on the surface of the field effect transistor preliminary structure and the guard ring structure.

[0085] An insulating layer is deposited on the surface of the substrate by chemical vapor deposition, and the insulating layer is etched to expose the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer, and to form a plurality of contact holes.

[0086] In one embodiment, the contact holes in the field effect transistor preliminary structure and the guard ring structure are filled, and a metal layer is formed outside the contact hole to obtain the field effect transistor structure of the RFID electronic tag chip, including:

[0087] The contact hole is filled by sputtering a thin film on the surface of the preliminary structure of the effect transistor and the guard ring structure, and depositing a metal tungsten layer on the thin film.

[0088] On the surface of the field effect transistor preliminary structure and the guard ring structure, a metal layer is formed by combining deposition and etching to obtain the field effect transistor structure of the RFID electronic tag chip. RFID refers to radio frequency identification technology.

[0089] In one embodiment, the metal layer includes a first titanium layer, an aluminum layer, a second titanium layer, and a titanium nitride layer.

[0090] In one embodiment, the impurity ions include P-type impurity ions and N-type impurity ions, and the guard ring structure includes a P-type guard ring structure and an N-type guard ring structure.

[0091] In order to facilitate understanding of the above technical solutions of the present invention, the above technical solutions of the present invention are further explained below from the perspectives of architecture and principle.

[0092] NMOS device manufacturing method:

[0093] Step 1, providing a silicon-on-insulator (SOI) substrate 101, the substrate can be defined as an active area, for the sake of simplicity, here only a blank represents the substrate 101; firstly, a first oxide layer and a first nitride layer are sequentially formed on the substrate 101; then, a dry etching process is performed to sequentially etch the first nitride layer, the first oxide layer and the substrate 101 to form a trench 102; then, a shallow trench isolation material is filled in the trench to form a first sub-shallow trench isolation structure; finally, the first oxide layer and the first nitride layer are removed to form a trench 102 as shown in FIG. Figure 1 The structure shown.

[0094] Step 2: grow an oxide layer 103 on the substrate 101 to serve as a hard mask for subsequent etching. To ensure that the oxide layer 103 is not easily broken through or over-etched during the etching process, a wet oxidation method is used to grow a 1 μm oxide layer 103. The oxide layer 103 has an oxidation thickness T ox The relationship with the required oxidation time t is as follows:

[0095]

[0096] Among them, A and B are parameters describing the oxidation rate, and the specific values ​​are related to the oxidation temperature. The wet oxygen oxidation temperature of the present invention is 1100°C. It can be seen from the table that A = 0.11 μm, B = 0.51 μm at this time 2 / h, τ=0. When the oxide thickness T ox When the thickness of the oxide layer 103 is 1 μm, the required oxidation time can be calculated to be about 2.18 h. Therefore, when the wet oxygen temperature is 1100°C, the oxidation time can be controlled to be 2.18 h to obtain the expected 1 μm oxide layer 103. Figure 2 shown.

[0097] Step 3: Expose the oxide layer 103 to remove the photoresist; and wet-etch the oxide layer 103 to retain only a portion of the field oxide 104, such as Figure 3 shown.

[0098] Step 4: perform well implantation on the area between the field oxides 104 and above the substrate 101 to form a well 105, and form a guard ring 106 below the field oxides 104, as shown in FIG. Figure 4 shown.

[0099] Step 5: Remove the field oxide 104 on the surface above the guard ring 106 by etching, and inject P-type impurity ions into the guard ring 106 to form a P-type guard ring structure, such as Figure 5 shown.

[0100] Step 6: Form an oxide insulating layer 107 on the substrate 101 above the well 105, and deposit a polysilicon layer 108 on the oxide insulating layer 107 to form a gate structure. Figure 6 shown.

[0101] Step 7: Lightly doped ions (LDD ions) are implanted on both sides of the oxide insulating layer 107 and the polysilicon layer 108 to form source / drain regions 109 on both sides of the gate structure. Figure 7 shown.

[0102] Step eight, deposit an insulating layer on the polysilicon layer 108, then etch back the insulating layer to etch away the oxide on the upper surface of the polysilicon layer 108, retain the insulating layer on both sides thereof, and form sidewalls 110 on both sides of the gate structure, such as Figure 7 shown.

[0103] Step nine, injecting source and drain ions on both sides of the sidewall 110 and above the source and drain regions 109, forming source and drain ion N-type doping regions on both sides of the gate structure, so as to form effective source regions 111 and drain regions 112, as shown in FIG. Figure 8 shown.

[0104] Step 10: Using a conventional self-alignment method and process, a layer of silicide 113 is deposited on the gate structure, the source region, the drain region and the area above the P-type guard ring 106 to reduce the contact resistance. Fig.10 shown.

[0105] Step 11: deposit a layer of borophosphosilicate glass (BPSG) 114 on the device surface by chemical vapor deposition (CVD). This insulating layer is used to isolate the device from the metal. Fig.11 shown.

[0106] Step twelve, etching the borophosphosilicate glass layer 114 to expose the gate structure, source region, drain region and P-type guard ring 106 structure, and forming contact holes 115 respectively so that metal can be connected to these structures. Fig.12 shown.

[0107] Step 13, a layer of TIN film 116 is sputtered on the surface of the device, a metal tungsten layer 117 is deposited on the TIN film 116 so that the contact hole 115 is filled, and the TIN film 116 and the metal tungsten 117 on the surface are removed by planing, leaving the contact hole filled with the TIN film 116 and the metal tungsten 117, as shown in FIG. Fig.13 shown.

[0108] Step 14: TI / AL / TI / TIN are deposited in sequence on the device by magnetron sputtering to form a metal layer 118, and then the metal layer 118 on the gate structure, source region, drain region and P-type guard ring 106 structure is etched. Fig.14 TI is titanium, AL is aluminum, and TIN is aluminum nitride.

[0109] Step 15: Finally, after low temperature annealing, an ohmic contact electrode is formed above the P-type guard ring region. Fig.15 shown.

[0110] Similarly, for PMOS devices, an N-type guard ring structure is added around the device in the same way to collect high-speed electrons under high electric fields and introduce the collected electrons into the grounded end of the drain region, ultimately achieving the purpose of protecting the gate.

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for improving hot carriers in RFID electronic tag chips, characterized in that: The method includes: S1. Based on the etching process and wet oxidation method, field oxygen is formed on the surface of the substrate; a guard ring is formed between the field oxygen and the substrate by using an injection well; S2, injecting impurity ions into the guard ring to form a guard ring structure; forming a preliminary structure of a field effect transistor of the RFID electronic tag chip on the well surface by means of deposition and ion injection; S3, depositing an insulating layer on the surface of the substrate, and exposing the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer; S4, filling the contact holes in the preliminary structure of the field effect transistor and the guard ring structure, and forming a metal layer outside the contact hole to obtain the field effect transistor structure of the RFID electronic tag chip; S5. Perform annealing on the field effect transistor structure of the RFID electronic tag chip to obtain a corresponding ohmic contact electrode.

2. A method for improving hot carriers of RFID electronic tag chips according to claim 1, characterized in that: The method of forming field oxide on the substrate surface based on etching process and wet oxidation method includes: Forming a first oxide layer and a first nitride layer on the substrate in sequence, and etching the first nitride layer, the first oxide layer and the substrate in sequence by using a dry etching process to form a groove; Filling the trench with a shallow trench isolation material, and removing the first oxide layer and the first nitride layer; An oxide layer is grown on the surface of the substrate by wet oxidation, and the oxide layer is exposed, photoresist is removed and wet etched to form field oxide.

3. A method for improving hot carriers of RFID electronic tag chips according to claim 2, characterized in that: The oxidation thickness of the oxide layer is associated with the oxidation time, and the relationship between the oxidation thickness of the oxide layer and the required oxidation time is: Where, T ox is the oxide thickness, t is the oxidation time; A, B and τ are parameters that describe the oxidation rate.

4. The method for improving hot carriers of RFID electronic tag chips according to claim 1, characterized in that: The method of forming a guard ring between the field oxide and the substrate by using an implant well comprises: Wells are implanted into the area between the field oxygens and on the top of the substrate to form a guard ring.

5. A method for improving hot carriers of RFID electronic tag chips according to claim 4, characterized in that: The step of injecting impurity ions into the guard ring to form the guard ring structure comprises: The field oxygen on the surface of the guard ring is removed by etching, and impurity ions are injected into the guard ring to form a guard ring structure.

6. The method for improving hot carriers of RFID electronic tag chips according to claim 1, characterized in that: The preliminary structure of the field effect transistor of the RFID electronic tag chip formed on the well surface by deposition and ion injection includes: An oxide insulating layer and a polysilicon layer are sequentially formed on the surface of the well to obtain a gate structure; Implanting lightly doped ions on both sides of the oxide insulating layer and the polysilicon layer to form a source region and a drain region; Forming side walls of the insulating layer on both sides of the gate structure, and forming a final source region and a final drain region by injecting source and drain ions on both sides of the side walls and on the surfaces of the source region and the drain region; Wherein, the preliminary structure of the field effect transistor of the RFID electronic tag chip includes a gate structure, a final source region and a final drain region.

7. A method for improving hot carriers of RFID electronic tag chips according to claim 6, characterized in that: The step of depositing an insulating layer on the surface of the substrate and exposing the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer comprises: depositing a contact resistance reducing layer on the surface of the field effect transistor preliminary structure and the guard ring structure; An insulating layer is deposited on the surface of the substrate by chemical vapor deposition, and the insulating layer is etched to expose the preliminary structure of the field effect transistor and the guard ring structure from the insulating layer, and to form a plurality of contact holes.

8. The method for improving hot carriers of RFID electronic tag chips according to claim 7, characterized in that: The contact holes in the preliminary structure of the field effect transistor and the guard ring structure are filled, and a metal layer is formed outside the contact hole to obtain the field effect transistor structure of the RFID electronic tag chip, including: Filling the contact hole by sputtering a thin film on the surface of the preliminary structure of the effect transistor and the guard ring structure and depositing a metal tungsten layer on the thin film; On the surface of the field effect transistor preliminary structure and the guard ring structure, a metal layer is formed by combining deposition and etching to obtain the field effect transistor structure of the RFID electronic tag chip.

9. The method for improving hot carriers of RFID electronic tag chips according to claim 8, characterized in that: The metal layer includes a first titanium layer, an aluminum layer, a second titanium layer and a titanium nitride layer.

10. The method for improving hot carriers of RFID electronic tag chips according to claim 5, characterized in that: The impurity ions include P-type impurity ions and N-type impurity ions, and the guard ring structure includes a P-type guard ring structure and an N-type guard ring structure.

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