Level conversion circuit, display device and driving method

Abstract

The embodiment of the invention provides a level conversion circuit, a display device and a driving method. The level conversion circuit comprises a logic processing circuit, a time delay circuit and a level output circuit, the logic processing circuit is configured to generate at least one initial clock signal according to the first clock reference signal and the second clock reference signal; the time delay circuit is electrically connected with the logic processing circuit and the level output circuit, and the time delay circuit is configured to respond to the first working instruction, carry out time delay processing on the initial clock signal and transmit the initial clock signal to the level output circuit; the level output circuit is configured to output a target clock signal according to the clock signal output by the time delay circuit. The clock signal is generated through the time delay processing of the time delay circuit, and the target clock signal can be independently adjusted according to the clock signal, so that the time sequence of the clock signal can be flexibly adjusted according to the requirements of the display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a level conversion circuit, a display device and a driving method. Background Art

[0002] In displays such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED), multiple pixel units are generally included. Each pixel unit may include: multiple sub-pixels of different colors. By controlling the brightness corresponding to each sub-pixel, the desired color is mixed to display a color image. Summary of the invention

[0003] The level conversion circuit provided by the embodiment of the present disclosure includes: a logic processing circuit, a delay circuit and a level output circuit;

[0004] The logic processing circuit is configured to generate at least one initial clock signal based on the first clock reference signal and the second clock reference signal;

[0005] The delay circuit is electrically connected to the logic processing circuit and the level output circuit, and the delay circuit is configured to perform delay processing on the initial clock signal and transmit the delay processing to the level output circuit in response to the first working instruction;

[0006] The level output circuit is configured to output a target clock signal according to the clock signal output by the delay circuit.

[0007] In some embodiments, the delay circuit is further configured to, in response to the first working instruction, delay at least one of a rising edge and a falling edge of the initial clock signal.

[0008] In some embodiments, the delay circuit is further configured to transmit the initial clock signal to the level output circuit in response to a second working instruction.

[0009] The display device provided by the embodiment of the present disclosure includes: a display panel, a timing controller and the above-mentioned level conversion circuit;

[0010] The timing controller is configured to obtain display data of the display panel, and output a first clock reference signal and a second clock reference signal according to the display data, and output a first working instruction or a second working instruction;

[0011] The level conversion circuit is connected to the timing controller and the display panel respectively, and is configured to receive a first clock reference signal and a second clock reference signal, and the first working instruction or the second working instruction, and output a target clock signal to the display panel.

[0012] In some embodiments, the display panel operates at multiple refresh frequencies, and the timing controller is further configured to: determine that the refresh frequency of the display panel is reduced, and output the first working instruction.

[0013] In some embodiments, the timing controller is further configured to: determine that a current refresh frequency of the display panel is less than a maximum refresh frequency, and output the first working instruction.

[0014] In some embodiments, the timing controller is further configured to: determine that the current refresh frequency of the display panel is the maximum refresh frequency, and output the second working instruction.

[0015] In some embodiments, the display panel includes: a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines;

[0016] Two gate lines are correspondingly arranged in each row of sub-pixels, and two adjacent sub-pixels in each row of sub-pixels are electrically connected to the two gate lines correspondingly arranged in the row of sub-pixels in a one-to-one correspondence;

[0017] A column of sub-pixels is electrically connected to one of the data lines.

[0018] In some embodiments, the sub-pixels in odd columns in each row of the sub-pixels are connected to the same gate line, and the sub-pixels in even columns are connected to the same gate line.

[0019] In some embodiments, the timing controller is further configured to output the first working instruction.

[0020] In some embodiments, the display panel includes: a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines;

[0021] Two gate lines are correspondingly arranged in each row of sub-pixels, and two adjacent sub-pixels in each row of sub-pixels are electrically connected to the two gate lines correspondingly arranged in the row of sub-pixels in a one-to-one correspondence;

[0022] Two adjacent sub-pixels in each row of sub-pixels are electrically connected to the same data line.

[0023] In some embodiments, the timing controller is further configured to output the first working instruction.

[0024] The driving method of a display device provided by an embodiment of the present disclosure includes:

[0025] Acquire display data of the display panel, and output a first clock reference signal and a second clock reference signal according to the display data, and output a first working instruction or a second working instruction;

[0026] A first clock reference signal and a second clock reference signal, and the first working instruction or the second working instruction are received, and a target clock signal is output to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural schematic diagram of a level conversion circuit in the related art;

[0028] Figure 2 A schematic diagram of the structure of a level conversion circuit provided in an embodiment of the present disclosure;

[0029] Figure 3 Some structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0030] Figure 4 Some other structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0031] Figure 5 is a signal timing diagram in the related art;

[0032] Figure 6 Some signal timing diagrams provided for embodiments of the present disclosure;

[0033] Figure 7 Some structural schematic diagrams of display panels provided by embodiments of the present disclosure;

[0034] Figure 8 Some other structural schematic diagrams of display panels provided by embodiments of the present disclosure;

[0035] Fig. 9 Other signal timing diagrams provided for embodiments of the present disclosure;

[0036] Fig.10 Some further structural schematic diagrams of display panels provided by embodiments of the present disclosure;

[0037] Fig.11 Some further signal timing diagrams provided for embodiments of the present disclosure;

[0038] Fig.12 A flowchart of a driving method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0041] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0042] The current level shift (LS) circuit generally works in a way of less input and more output, such as Figure 1 As shown, a 4-input 12-output level conversion circuit 300 is used as an example for explanation. The logic processing circuit 10 in the level conversion circuit 300 responds to the signals of the clock reference signal terminals CPV1, CPV2, CPV3, and CPV4 to provide an initial clock signal, so that the level output circuit 30 provides a clock signal to the clock signal terminals CLK1 to CLK12 according to the initial clock signal, wherein the odd-numbered clock signal terminals (e.g. Figure 1 The rising edge of the clock signal of CLK1, CLK3, CLK5, CLK7, CLK9, CLK11) is generated according to the rising edge of the first clock reference signal of the input signal terminal CPV1, and the odd-numbered clock signal terminals (e.g. Figure 1 The falling edge of the clock signal of CLK1, CLK3, CLK5, CLK7, CLK9, CLK11) in the input signal terminal CPV2 is generated according to the rising edge of the second clock reference signal; the even-numbered clock signal terminals (e.g. Figure 1The rising edge of the clock signal of CLK2, CLK4, CLK6, CLK8, CLK10, CLK12 in the input signal terminal CPV3 is generated according to the rising edge of the first clock reference signal. The even clock signal terminals (e.g. Figure 1 The falling edge of the clock signal (CLK2, CLK4, CLK6, CLK8, CLK10, CLK12) is generated according to the rising edge of the second clock reference signal of the input signal terminal CPV4; therefore, when it is necessary to adjust the clock signal of the clock signal terminal, only the timing of the clock signal of the odd-numbered clock signal terminal or the timing of the clock signal of the even-numbered clock signal terminal can be adjusted at the same time, and the timing of the clock signal of a certain clock signal terminal cannot be adjusted separately, so it is not conducive to flexibly adjusting the timing of the clock signal according to the requirements of the display device.

[0043] As display products gradually develop towards high refresh rates and low costs, in practical applications, more and more problems related to image quality and the timing of clock signals are encountered. These problems can be well solved by adjusting the timing of one or some clock signals, but currently it is not possible to adjust the timing of the clock signal at the clock signal end separately.

[0044] Based on the above problems, the level conversion circuit provided by the embodiment of the present disclosure is as follows: Figure 2 As shown, it includes: a logic processing circuit 10, a delay circuit 20 and a level output circuit 30;

[0045] The logic processing circuit 10 is configured to generate at least one initial clock signal according to the first clock reference signal and the second clock reference signal;

[0046] The delay circuit 20 is electrically connected to the logic processing circuit 10 and the level output circuit 30. The delay circuit 20 is configured to perform delay processing on the initial clock signal in response to the first working instruction and transmit the delay processing to the level output circuit 30.

[0047] The level output circuit 30 is configured to output a target clock signal according to the clock signal output by the delay circuit 20 .

[0048] The disclosed embodiment achieves this by mutual cooperation among a logic processing circuit, a delay circuit, and a level output circuit, that is, by enabling the logic processing circuit to generate at least one initial clock signal according to a first clock reference signal and a second clock reference signal, and the delay circuit performs delay processing on the initial clock signal in response to a first working instruction and transmits the delay signal to the level output circuit, so that the level output circuit outputs a target clock signal according to the clock signal output by the delay circuit, and the timing of the target clock signal can be adjusted as required; that is, a clock signal is generated through delay processing of the delay circuit, and the target clock signal can be adjusted separately according to the clock signal, so that the timing of the clock signal can be flexibly adjusted according to the requirements of the display device.

[0049] In some embodiments of the present disclosure, Figure 2 As shown, the delay circuit 20 is further configured to, in response to the first working instruction, delay at least one of the rising edge and the falling edge of the initial clock signal.

[0050] Exemplarily, the delay circuit delays the rising edge of the initial clock signal, so that the rising edge of the initial clock signal is not aligned with the rising edge of the first clock reference signal; or, the delay circuit delays the falling edge of the initial clock signal, so that the falling edge of the initial clock signal is not aligned with the rising edge of the second clock reference signal; or, the delay circuit delays the rising edge and the falling edge of the initial clock signal, so that the rising edge of the initial clock signal is not aligned with the rising edge of the first clock reference signal and the falling edge is not aligned with the rising edge of the second clock reference signal.

[0051] In some embodiments of the present disclosure, Figure 2 As shown, the delay circuit 20 is further configured to transmit the initial clock signal to the level output circuit 30 in response to the second working instruction.

[0052] Exemplarily, when there is no need to perform delay processing on the initial clock signal, the delay circuit directly transmits the initial clock signal to the level output circuit.

[0053] Based on the same inventive concept, the display device provided by the embodiment of the present disclosure is as follows: Figure 3 and Figure 4 As shown, it includes: a display panel 100, a timing controller 200 and a level conversion circuit 300;

[0054] The timing controller 200 is configured to obtain display data of the display panel 100, and output a first clock reference signal and a second clock reference signal according to the display data, and output a first working instruction or a second working instruction;

[0055] The level conversion circuit 300 is connected to the timing controller 200 and the display panel 100 respectively, and is configured to receive the first clock reference signal and the second clock reference signal, and the first working instruction or the second working instruction, and output a target clock signal to the display panel 100 .

[0056] Exemplarily, the timing controller 200 is electrically connected to the logic processing circuit 10 in the level conversion circuit 300 through the clock reference signal terminals CPV1, CPV2, CPV3, and CPV4; the timing controller 200 provides a first clock reference signal to the clock reference signal terminals CPV1 and CPV3, and provides a second clock reference signal to the clock reference signal terminals CPV2 and CPV4.

[0057] Exemplarily, the display panel 100 includes a plurality of pixel units arranged in an array, and each pixel unit includes a plurality of sub-pixels of different colors. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color display can be achieved by mixing red, green, and blue. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color display can be achieved by mixing red, green, blue, and white. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following is an example in which a pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0058] For example, Figure 4 As shown, the display device also includes: a plurality of gate lines GA, a plurality of data lines DA, a gate driving circuit 110 and a source driving circuit 120; the gate driving circuit 110 is electrically connected to the gate line GA, and the source driving circuit 120 is electrically connected to the data line DA. Among them, the timing controller 200 can input the target clock signal to the gate driving circuit 110 through the level conversion circuit 300, thereby driving the gate line GA. The timing controller 200 inputs a control signal to the source driving circuit 120, so that the source driving circuit 120 inputs a data signal to the data line DA, thereby charging the sub-pixel, so that the sub-pixel inputs the corresponding data signal, and realizes the screen display function. Among them, the source driving circuit 120 can be set to 2, one of which is connected to half of the number of data lines, and the other is connected to the other half of the number of data lines. Of course, the source driving circuit 120 can also be set to 3, 4, or more, which can be designed and determined according to the needs of actual applications, and is not limited here.

[0059] For example, the display device supports a hardware super resolution mode (HSR), and can support refresh rates of 240 Hz and 330 Hz in the hardware super resolution mode. According to experimental tests, in the hardware super resolution mode, the duty cycle of the clock signal needs to be set to 5 / 12. However, in actual tests, when the refresh rate is 330 Hz, the odd-numbered clock signal terminals (e.g. Figure 1 The duty cycle of the clock signal of CLK1, CLK3, CLK5, CLK7, CLK9, CLK11 in is 41.77%, and the duty cycle of the even-numbered clock signal terminals (e.g. Figure 1The duty cycle of the clock signals of CLK2, CLK4, CLK6, CLK8, CLK10, and CLK12 in FIG. 1 is 41.55%. It can be seen that the duty cycle of the clock signals of the odd-numbered clock signal terminals and the clock signals of the even-numbered clock signal terminals basically satisfies 5 / 12; however, when the refresh frequency is reduced, that is, when the refresh frequency is 240 Hz, the duty cycle of the clock signals of the odd-numbered clock signal terminals (for example Figure 1 The duty cycle of the clock signals CLK1, CLK3, CLK5, CLK7, CLK9, and CLK11 in FIG. 1 is 43.98%, and the duty cycle of the clock signal terminals (e.g. Figure 1 The duty cycle of the clock signals of CLK2, CLK4, CLK6, CLK8, CLK10, and CLK12 in the image is 39.29%. It can be seen that the duty cycle of the clock signals of the odd-numbered clock signal terminals and the clock signals of the even-numbered clock signal terminals does not meet the preset 5 / 12. According to multiple experimental tests, in the hardware super-resolution mode, when the refresh rate is reduced, the odd-numbered clock signal terminals (e.g. Figure 1 The duty cycle of the clock signals CLK1, CLK3, CLK5, CLK7, CLK9, CLK11) in the even-numbered clock signal terminals (e.g. Figure 1 The clock signals CLK2, CLK4, CLK6, CLK8, CLK10, and CLK12 in the display are reduced, which will result in poor display effect and affect the display quality.

[0060] It should be noted that the above problem is determined by the timing mechanism of the timing controller generating the clock reference signal, so it is impossible to solve the above problem by adjusting the timing of the timing controller generating the clock reference signal. Figure 5The signal timing diagram shown is used to explain that in the hardware super-resolution mode with a refresh frequency of 330Hz, the rising edge of the control signal DE generated by the timing controller always remains consistent with the rising edge of the data transmission signal VBO DATA. The period of the data transmission signal VBO DATA is 1H, and the falling edge of the control signal DE is fixed in position according to the internal fixed frequency of the timing controller. The time from the rising edge of the signal cpv1 at the clock reference signal end CPV1 to the rising edge of the control signal DE is set to A, the time from the rising edge of the signal cpv2 at the clock reference signal end CPV2 to the rising edge of the control signal DE is set to B, the time from the rising edge of the signal cpv3 at the clock reference signal end CPV3 to the rising edge of the control signal DE is set to B, and the time from the rising edge of the signal cpv4 at the clock reference signal end CPV4 to the rising edge of the control signal DE is set to A; wherein, the high level width of the signals cpv1, cpv2, cpv3 and cpv4 is W, and currently W is set to AB = 0.5H (W can also be set to other values), then the period of the clock signal clk1 is 6H + AA = 6H, the high level width of the clock signal clk1 is 3H + BA, and the duty cycle of the clock signal clk1 is The period of the clock signal clk2 is 6H+BB=6H, the high level width of the clock signal clk2 is 2H+AB, and the duty cycle of the clock signal clk2 is When the refresh frequency decreases, the time of 1H increases, and AB is a fixed value, so the duty cycle of the clock signal clk1 increases, and the duty cycle of the clock signal clk2 decreases, that is, when the refresh frequency decreases, the duty cycle of the clock signal at the odd clock signal end increases, and the clock signal at the even clock signal end decreases, which will result in poor display effect and affect the display quality. This problem cannot be solved by adjusting the TCON timing.

[0061] In some embodiments of the present disclosure, Figure 3 As shown, the display panel 100 operates at multiple refresh frequencies, and the timing controller 200 is further configured to: determine that the refresh frequency of the display panel 100 is reduced, and output a first working instruction.

[0062] In the embodiment of the present disclosure, the timing controller determines that the refresh frequency of the display panel is reduced and outputs a first working instruction. Then, the delay circuit in the level conversion circuit responds to the first working instruction, delays the initial clock signal and transmits it to the level output circuit. Thus, the level output circuit outputs a target clock signal according to the clock signal output by the delay circuit, and the timing of the target clock signal can be adjusted as required. That is, the clock signal is generated through the delay processing of the delay circuit, and the target clock signal can be adjusted separately according to the clock signal, so that the timing of a certain clock signal can be set and adjusted separately according to the requirements of the display device.

[0063] In some embodiments of the present disclosure, Figure 3 As shown, the timing controller 200 is further configured to: determine that the current refresh frequency of the display panel 100 is less than the maximum refresh frequency, and output a first working instruction.

[0064] In some embodiments of the present disclosure, Figure 3 As shown, the timing controller 200 is further configured to: determine that the current refresh frequency of the display panel 100 is the maximum refresh frequency, and output a second working instruction.

[0065] The following will Figure 3 As an example, combining the structure shown Figure 6 The signal timing diagram shown is explained in detail.

[0066] like Figure 6 As shown, cpv1 represents the first clock reference signal of the clock reference signal terminal CPV1, cpv2 represents the second clock reference signal of the clock reference signal terminal CPV2, cpv3 represents the first clock reference signal of the clock reference signal terminal CPV3, cpv4 represents the second clock reference signal of the clock reference signal terminal CPV4, vclk1 represents the initial clock signal, vclk2 represents the initial clock signal, clk1 represents the target clock signal, and clk2 represents the target clock signal.

[0067] The timing controller 200 obtains the display data of the display panel 100, and outputs the first clock reference signals cpv1, cpv3 and the second clock reference signals cpv2 and cpv4 according to the display data, and determines that the current refresh frequency of the display panel 100 is less than the maximum refresh frequency, and outputs the first working instruction; the logic processing circuit 10 generates the initial clock signal vclk1 according to the first clock reference signal cpv1 and the second clock reference signal cpv2, and the logic processing circuit 10 generates the initial clock signal vclk2 according to the first clock reference signal cpv3 and the second clock reference signal cpv4; the delay circuit 20 delays the rising edge of the initial clock signal vclk1 according to the first working instruction, and the delay time is t1, the falling edge of the initial clock signal vclk1 is delayed for a delay time of t2, and the falling edge of the initial clock signal vclk2 is delayed for a delay time of t3, then the level output circuit 30 outputs the target clock signals clk1 and clk2 according to the clock signal output after the delay circuit 10 delays the processing; wherein, the duty cycle of the initial clock signal vclk1 is greater than 5 / 12, that is, the high level time of the initial clock signal vclk1 is too long, and the duty cycle of the initial clock signal vclk2 is less than 5 / 12, that is, the high level time of the initial clock signal vclk2 is too short, then the rising edge time difference between the initial clock signal vclk1 and the initial clock signal vclk2 is greater than 1H, which does not meet the preset value. After the delay processing, the phase difference between the rising edge of the target clock signal clk1 and the rising edge of the clock signal clk2 is 1H, which meets the preset value. And the duty cycle of the target clock signal clk1 is the same as the duty cycle of the target clock signal clk2. This can avoid the problem that in hardware super-resolution mode, when the refresh rate is reduced, odd-numbered clock signal terminals (such as Figure 3 The duty cycle of the target clock signal clk1 in CLK1 increases, and the even-numbered clock signal terminals (e.g. Figure 3 The duty cycle of the target clock signal clk2 (CLK2 in FIG. 1 ) is reduced, thereby improving the display effect and improving the display quality.

[0068] Exemplarily, the delay lengths t1, t2, and t3 are debugged to the optimal state, and then the parameter information about the delay lengths t1, t2, and t3 is saved in the timing controller. When the timing controller detects that the first working instruction needs to be output, the parameter information is provided to the delay circuit in the level conversion circuit.

[0069] In some embodiments of the present disclosure, two gate lines are arranged corresponding to each row of sub-pixels, and two adjacent sub-pixels in each row of sub-pixels are electrically connected to the two gate lines arranged corresponding to the row of sub-pixels respectively; a column of sub-pixels is electrically connected to a data line.

[0070] For example, Figure 7As shown, the gate lines GA1 and GA2 are set corresponding to the sub-pixels spx in the first row, and two adjacent sub-pixels spx in the sub-pixels spx in the first row are electrically connected to the gate lines GA1 and GA2 respectively; the gate lines GA3 and GA4 are set corresponding to the sub-pixels spx in the second row, and two adjacent sub-pixels spx in the sub-pixels spx in the second row are electrically connected to the gate lines GA3 and GA4 respectively; the gate lines GA5 and GA6 are set corresponding to the sub-pixels spx in the third row, and two adjacent sub-pixels spx in the sub-pixels spx in the third row are electrically connected to the gate lines GA5 and GA6 respectively; the gate lines GA7 and GA8 are set corresponding to the sub-pixels spx in the fourth row, and two adjacent sub-pixels spx in the sub-pixels spx in the fourth row are electrically connected to the gate lines GA7 and GA8 respectively. The sub-pixel spx in the first column is electrically connected to the data line DA1, the sub-pixel spx in the second column is electrically connected to the data line DA2, the sub-pixel spx in the third column is electrically connected to the data line DA2, the sub-pixel spx in the fourth column is electrically connected to the data line DA3, the sub-pixel spx in the fifth column is electrically connected to the data line DA3, the sub-pixel spx in the sixth column is electrically connected to the data line DA4, the sub-pixel spx in the seventh column is electrically connected to the data line DA4, the sub-pixel spx in the eighth column is electrically connected to the data line DA5, the sub-pixel spx in the ninth column is electrically connected to the data line DA5, the sub-pixel spx in the tenth column is electrically connected to the data line DA6, the sub-pixel spx in the eleventh column is electrically connected to the data line DA6, and the sub-pixel spx in the twelfth column is electrically connected to the data line DA7.

[0071] In some embodiments of the present disclosure, odd-numbered columns of sub-pixels in each row of sub-pixels are connected to the same gate line, and even-numbered columns of sub-pixels are connected to the same gate line.

[0072] For example, Figure 8 As shown, the 1st, 3rd, 5th, 7th, 9th, and 11th sub-pixels spx in the 1st row of sub-pixels spx are electrically connected to the gate line GA1, and the 2nd, 4th, 6th, 8th, 10th, and 12th sub-pixels spx in the 1st row of sub-pixels spx are electrically connected to the gate line GA2; the 1st, 3rd, 5th, 7th, 9th, and 11th sub-pixels spx in the 2nd row of sub-pixels spx are electrically connected to the gate line GA3, and the 2nd, 4th, 6th, 8th, 10th, and 12th sub-pixels spx in the 2nd row of sub-pixels spx are electrically connected to the gate line GA4. The 1st, 3rd, 5th, 7th, 9th and 11th sub-pixels spx in the 3rd row of sub-pixels spx are electrically connected to the gate line GA5, and the 2nd, 4th, 6th, 8th, 10th and 12th sub-pixels spx in the 3rd row of sub-pixels spx are electrically connected to the gate line GA6; the 1st, 3rd, 5th, 7th, 9th and 11th sub-pixels spx in the 4th row of sub-pixels spx are electrically connected to the gate line GA7, and the 2nd, 4th, 6th, 8th, 10th and 12th sub-pixels spx in the 4th row of sub-pixels spx are electrically connected to the gate line GA8.

[0073] For example, Figure 7 and Figure 8 As shown, each sub-pixel spx may include a transistor 01 and a pixel electrode 02. The gate of the transistor 01 is electrically connected to the corresponding gate line, the source of the transistor 01 is electrically connected to the corresponding data line, and the drain of the transistor 01 is electrically connected to the pixel electrode 02.

[0074] For example, Figure 7 and Figure 8 The structure of the display panel shown in the figure, after multiple frame flips, due to polarity reasons, the change in polarity causes the insufficient charging of the pixel electrodes in the upper and lower rows of sub-pixels to increase. For example, the pixel electrodes of the sub-pixels corresponding to the first row of gate lines are poorly charged compared to the pixel electrodes of the sub-pixels corresponding to the next three rows of gate lines, resulting in monochrome, mixed color and grayscale horizontal stripe problems on the display panel.

[0075] In some embodiments of the present disclosure, the timing controller 200 is further configured to output the first working instruction.

[0076] In the embodiment of the present disclosure, by making the timing controller output the first working instruction, the delay circuit in the level conversion circuit responds to the first working instruction, delays the initial clock signal and transmits it to the level output circuit, so that the level output circuit outputs the target clock signal according to the clock signal output by the delay circuit, and the timing of the target clock signal can be adjusted as required; thus, the charging time of each row of sub-pixels can be adjusted by adjusting the target clock signal, thereby avoiding the problem of insufficient charging of pixel electrodes in the upper and lower row sub-pixels due to the change in polarity, thereby improving the monochrome, mixed color and grayscale horizontal stripe problems of the display panel.

[0077] The following will Figure 3 as well as Figure 7 As an example, combining the structure shown Fig. 9 The signal timing diagram shown is explained in detail.

[0078] like Fig. 9 As shown, cpv1 represents the first clock reference signal of the clock reference signal end CPV1, cpv2 represents the second clock reference signal of the clock reference signal end CPV2, cpv3 represents the first clock reference signal of the clock reference signal end CPV3, cpv4 represents the second clock reference signal of the clock reference signal end CPV4, vclk1 represents the initial clock signal, vclk2 represents the initial clock signal, vclk3 represents the initial clock signal, vclk4 represents the initial clock signal, clk1 represents the target clock signal, clk2 represents the target clock signal, clk3 represents the target clock signal, clk4 represents the target clock signal, and data represents the data signal.

[0079] The timing controller 200 obtains the display data of the display panel 100, and outputs the first clock reference signals cpv1, cpv3, the second clock reference signals cpv2, cpv4 and the first working instruction according to the display data; the logic processing circuit 10 generates the initial clock signals vclk1, vclk3 according to the first clock reference signal cpv1 and the second clock reference signal cpv2, and the logic processing circuit 10 generates the initial clock signals vclk2, vclk4 according to the first clock reference signal cpv3 and the second clock reference signal cpv4; the delay circuit 20 delays the rising edge of the initial clock signal vclk1 according to the first working instruction, and the delay time is t1, delays the rising edge of the initial clock signal vclk2, and the delay time is t2, delays the rising edge of the initial clock signal vclk3, and the delay time is t3, and does not delay the rising edge of the initial clock signal vclk4, that is, delays the rising edge of the initial clock signal vclk4. When the time length is 0, wherein t1>t2>t3>0; the level output circuit 30 outputs the target clock signals clk1, clk2, clk3, and clk4 according to the clock signal output after the delay processing of the delay circuit 10; the target clock signal clk1 is loaded on the gate line GA1, the target clock signal clk2 is loaded on the gate line GA2, the target clock signal clk3 is loaded on the gate line GA3, and the target clock signal clk4 is loaded on the gate line GA4, then the charging time of the sub-pixel corresponding to the 1st row of gate lines is T1, the charging time of the sub-pixel corresponding to the 2nd row of gate lines is T2, the charging time of the sub-pixel corresponding to the 3rd row of gate lines is T3, and the charging time of the sub-pixel corresponding to the 4th row of gate lines is T4, wherein T1>T2>T3>T4; then, the pixel electrode charging time of the sub-pixel corresponding to the 1st row of gate lines is longer, and the pixel electrode charging time of the sub-pixel corresponding to the last 3 rows of gate lines is shorter, so the problems of monochrome, mixed color and grayscale horizontal stripes of the display panel can be avoided.

[0080] In some embodiments of the present disclosure, two gate lines are set corresponding to each row of sub-pixels, and two adjacent sub-pixels in each row of sub-pixels are electrically connected to the two gate lines corresponding to the row of sub-pixels respectively; two adjacent sub-pixels in each row of sub-pixels are electrically connected to the same data line.

[0081] For example, Fig.10As shown, the gate lines GA1 and GA2 are set corresponding to the sub-pixels spx in the first row, and two adjacent sub-pixels spx in the sub-pixels spx in the first row are electrically connected to the gate lines GA1 and GA2 respectively; the gate lines GA3 and GA4 are set corresponding to the sub-pixels spx in the second row, and two adjacent sub-pixels spx in the sub-pixels spx in the second row are electrically connected to the gate lines GA3 and GA4 respectively; the gate lines GA5 and GA6 are set corresponding to the sub-pixels spx in the third row, and two adjacent sub-pixels spx in the sub-pixels spx in the third row are electrically connected to the gate lines GA5 and GA6 respectively; the gate lines GA7 and GA8 are set corresponding to the sub-pixels spx in the fourth row, and two adjacent sub-pixels spx in the sub-pixels spx in the fourth row are electrically connected to the gate lines GA7 and GA8 respectively. The sub-pixel spx in the first column is electrically connected to the data line DA1, the sub-pixel spx in the second column is electrically connected to the data line DA2, the sub-pixel spx in the third column is electrically connected to the data line DA2, the sub-pixel spx in the fourth column is electrically connected to the data line DA3, the sub-pixel spx in the fifth column is electrically connected to the data line DA3, the sub-pixel spx in the sixth column is electrically connected to the data line DA4, the sub-pixel spx in the seventh column is electrically connected to the data line DA4, the sub-pixel spx in the eighth column is electrically connected to the data line DA5, the sub-pixel spx in the ninth column is electrically connected to the data line DA5, the sub-pixel spx in the tenth column is electrically connected to the data line DA6, the sub-pixel spx in the eleventh column is electrically connected to the data line DA6, and the sub-pixel spx in the twelfth column is electrically connected to the data line DA7.

[0082] For example, Fig.10 As shown, for the first row of sub-pixels and the second row of sub-pixels, the first sub-pixel and the second sub-pixel in the two rows of sub-pixels are electrically connected to the data line DA1, the third sub-pixel and the fourth sub-pixel in the two rows of sub-pixels are electrically connected to the data line DA2, the fifth sub-pixel and the sixth sub-pixel in the two rows of sub-pixels are electrically connected to the data line DA3, the seventh sub-pixel and the eighth sub-pixel in the two rows of sub-pixels are electrically connected to the data line DA4, the ninth sub-pixel and the tenth sub-pixel in the two rows of sub-pixels are electrically connected to the data line DA5, and the eleventh sub-pixel and the twelfth sub-pixel in the two rows of sub-pixels are electrically connected to the data line DA6. For the 3rd row of sub-pixels and the 4th row of sub-pixels, the 1st sub-pixel and the 2nd sub-pixel in these two rows of sub-pixels are electrically connected to the data line DA2, the 3rd sub-pixel and the 4th sub-pixel in these two rows of sub-pixels are electrically connected to the data line DA3, the 5th sub-pixel and the 6th sub-pixel in these two rows of sub-pixels are electrically connected to the data line DA4, the 7th sub-pixel and the 8th sub-pixel in these two rows of sub-pixels are electrically connected to the data line DA5, the 9th sub-pixel and the 10th sub-pixel in these two rows of sub-pixels are electrically connected to the data line DA6, and the 11th sub-pixel and the 12th sub-pixel in these two rows of sub-pixels are electrically connected to the data line DA7.

[0083] For example, Fig.10 The structure of the display panel shown in the hardware super-resolution mode sequentially loads clock signals to the gate lines GA1, GA3, GA2, and GA4 in the display panel, so that the color mixing problem can be avoided and the luminous colors of two adjacent rows of sub-pixels can be ensured to be the same. In order to sequentially load signals to the gate lines GA1, GA3, GA2, and GA4 in the display panel, in the embodiment disclosed in the present invention, the timing controller is further configured to output a first working instruction. That is, by making the timing controller output the first working instruction, the delay circuit in the level conversion circuit responds to the first working instruction, delays the initial clock signal and transmits it to the level output circuit, so that the level output circuit outputs a target clock signal according to the clock signal output by the delay circuit, and the timing of the target clock signal can be adjusted according to the demand; thereby, it can be ensured that the gate lines GA1, GA3, GA2, and GA4 in the display panel are sequentially loaded with signals, the color mixing problem can be avoided, and the luminous colors of two adjacent rows of sub-pixels can be ensured to be the same, thereby improving the display effect.

[0084] The following will Figure 3 as well as Fig.10 As an example, combining the structure shown Fig.11 The signal timing diagram shown is explained in detail.

[0085] like Fig.11 As shown, cpv1 represents the first clock reference signal of the clock reference signal end CPV1, cpv2 represents the second clock reference signal of the clock reference signal end CPV2, cpv3 represents the first clock reference signal of the clock reference signal end CPV3, cpv4 represents the second clock reference signal of the clock reference signal end CPV4, vclk1 represents the initial clock signal, vclk2 represents the initial clock signal, vclk3 represents the initial clock signal, vclk4 represents the initial clock signal, clk1 represents the target clock signal, clk2 represents the target clock signal, clk3 represents the target clock signal, clk4 represents the target clock signal, and data represents the data signal.

[0086] The timing controller 200 obtains the display data of the display panel 100, and outputs the first clock reference signals cpv1, cpv3, the second clock reference signals cpv2, cpv4 and the first working instruction according to the display data; the logic processing circuit 10 generates the initial clock signals vclk1, vclk3 according to the first clock reference signal cpv1 and the second clock reference signal cpv2, and the logic processing circuit 10 generates the initial clock signals vclk2, vclk4 according to the first clock reference signal cpv3 and the second clock reference signal cpv4; the delay circuit 20 delays the rising edge of the initial clock signal vclk1 according to the first working instruction, and the delay time is 1H, and delays the rising edge of the initial clock signal vclk2, and the delay time is 2H, and the delay time is 1H. The rising edge of k3 is not delayed, that is, the delay time is 0, and the rising edge of the initial clock signal vclk4 is delayed for 1H; then the level output circuit 30 outputs the target clock signals clk1, clk3, clk2, and clk4 in sequence according to the clock signal output after the delay processing by the delay circuit 10; the target clock signal clk1 is loaded on the gate line GA1, the target clock signal clk2 is loaded on the gate line GA2, the target clock signal clk3 is loaded on the gate line GA3, and the target clock signal clk4 is loaded on the gate line GA4. Then, by adopting the delay circuit, the target clock signals are loaded to the gate lines GA1, GA3, GA2, and GA4 in the display panel in sequence, so as to avoid the problem of color mixing and ensure that the light-emitting colors of two adjacent rows of sub-pixels are the same, thereby improving the display effect.

[0087] Based on the same inventive concept, the embodiment of the present disclosure also provides a driving method of a display device, such as Fig.12 As shown, the following steps are included:

[0088] S100, acquiring display data of a display panel, and outputting a first clock reference signal and a second clock reference signal according to the display data, and outputting a first working instruction or a second working instruction;

[0089] S200, receiving a first clock reference signal and a second clock reference signal, and a first working instruction or a second working instruction, and outputting a target clock signal to a display panel.

[0090] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0091] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0092] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0093] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0094] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0095] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0096] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A level conversion circuit, wherein: include: Logic processing circuit, time delay circuit and level output circuit; The logic processing circuit is configured to generate at least one initial clock signal based on the first clock reference signal and the second clock reference signal; The delay circuit is electrically connected to the logic processing circuit and the level output circuit, and the delay circuit is configured to perform delay processing on the initial clock signal and transmit the delay processing to the level output circuit in response to the first working instruction; The level output circuit is configured to output a target clock signal according to the clock signal output by the delay circuit.

2. The level conversion circuit according to claim 1, wherein: The delay circuit is further configured to, in response to the first working instruction, delay at least one of a rising edge and a falling edge of the initial clock signal.

3. The level conversion circuit according to claim 1 or 2, wherein: The delay circuit is further configured to transmit the initial clock signal to the level output circuit in response to a second working instruction.

4. A display device, wherein: include: A display panel, a timing controller, and a level conversion circuit as claimed in any one of claims 1 to 3; The timing controller is configured to obtain display data of the display panel, and output a first clock reference signal and a second clock reference signal according to the display data, and output a first working instruction or a second working instruction; The level conversion circuit is connected to the timing controller and the display panel respectively, and is configured to receive a first clock reference signal and a second clock reference signal, and the first working instruction or the second working instruction, and output a target clock signal to the display panel.

5. The display device according to claim 4, wherein: The display panel operates at a plurality of refresh frequencies, and the timing controller is further configured to: determine that the refresh frequency of the display panel is reduced, and output the first operation instruction.

6. The display device according to claim 5, wherein: The timing controller is further configured to: determine that a current refresh frequency of the display panel is less than a maximum refresh frequency, and output the first working instruction.

7. The display device according to claim 5 or 6, wherein: The timing controller is further configured to: determine that the current refresh frequency of the display panel is the maximum refresh frequency, and output the second working instruction.

8. The display device according to claim 4, wherein: The display panel includes: a plurality of sub-pixels, a plurality of data lines and a plurality of gate lines; Two gate lines are correspondingly arranged in each row of sub-pixels, and two adjacent sub-pixels in each row of sub-pixels are electrically connected to the two gate lines correspondingly arranged in the row of sub-pixels in a one-to-one correspondence; A column of sub-pixels is electrically connected to one of the data lines.

9. The display device according to claim 8, wherein: The sub-pixels in odd columns in each row of sub-pixels are connected to the same gate line, and the sub-pixels in even columns are connected to the same gate line.

10. The display device according to claim 8, wherein: The timing controller is further configured to output the first working instruction.

11. The display device according to claim 4, wherein: The display panel includes: a plurality of sub-pixels, a plurality of data lines and a plurality of gate lines; Two gate lines are correspondingly arranged in each row of sub-pixels, and two adjacent sub-pixels in each row of sub-pixels are electrically connected to the two gate lines correspondingly arranged in the row of sub-pixels in a one-to-one correspondence; Two adjacent sub-pixels in each row of sub-pixels are electrically connected to the same data line.

12. The display device according to claim 11, wherein: The timing controller is further configured to output the first working instruction.

13. A method for driving a display device, wherein: include: Acquire display data of the display panel, and output a first clock reference signal and a second clock reference signal according to the display data, and output a first working instruction or a second working instruction; A first clock reference signal and a second clock reference signal, and the first working instruction or the second working instruction are received, and a target clock signal is output to the display panel.

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