Driving method and driving circuit

Abstract

The invention discloses a driving method and a driving circuit, the driving method is used for driving a display panel, a plurality of data lines are divided into a plurality of data line groups, each data line group at least comprises two data lines, and the driving method comprises the following steps: detecting a refresh rate of a next frame, and judging whether the refresh rate is greater than a preset refresh rate; if the refresh rate of the next frame is smaller than or equal to the preset refresh rate, the double-data-line input mode is not started, and different analog voltages are input into the data lines in the data line set so as to be output to the pixel electrodes of the corresponding pixels; and if the refresh rate of the next frame is greater than the preset refresh rate, starting a double-data-line input mode, and inputting the same analog voltage to all the data lines in the data line group so as to output the same analog voltage to the pixel electrodes of the corresponding pixels. The same analog voltage is input into the adjacent data lines, half of the data transmission quantity in one frame is reduced, and the refresh rate is at least doubled under the same transmission rate, so that the dynamic image quality displayed by a product is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving method and a driving circuit. Background Art

[0002] Currently, TFT-LCD (Thin Film Transistor Liquid Crystal Display) has the largest market share, followed by OLED (Organic Light-Emitting Diode) panels, also known as organic electroluminescence display and organic light-emitting semiconductor (OLED). The current technological development direction of improving LCD display effects is still one of the main improvement directions of today's products.

[0003] In order to save chip costs, triple gate is currently mainly used. The three RGB sub-pixels of a pixel are arranged vertically, which can triple the number of gate lines and reduce the number of data lines to 1 / 3. Taking UD resolution 3840*2160 as an example, in the existing panel design, 3840*3 source lines and 2160 gate lines are required. Taking each source driver IC outputting 960 channels as an example, 12 sourcedriver ICs are required. When triple gate is used, only 3840 source lines are needed, which is equivalent to the output channels of 4 source driver ICs, and 2160*3 gate lines are required. However, the gate lines are generated by the line-by-line scanning circuit, and there will not be much cost increase in essence. However, the reduction of 8 source driver ICs can greatly reduce the cost, but the refresh rate remains unchanged and the dynamic image quality is poor. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a driving method and a driving circuit for increasing the refresh rate to improve the dynamic image quality of a display panel.

[0005] The present application discloses a driving method for driving a display panel, wherein the display panel includes a plurality of scan lines and data lines, and a plurality of pixels connected to the scan lines and the data lines, and the plurality of data lines are divided into a plurality of data line groups, each of which includes at least two data lines. The driving method includes the following steps: S1: Detect the refresh rate of the next frame and determine whether the refresh rate of the next frame is greater than the preset refresh rate; S2: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group respectively to output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, and the same analog voltage is input to all the data lines in the data line group to output to the pixel electrodes of the corresponding pixels.

[0006] Optionally, the data line group includes two data lines, namely a first data line and a second data line, a switch control circuit is provided between the first data line and the second data line in each data line group, the switch control circuit is provided at one end close to the data driver chip, each data line in the data line group is respectively connected to a different pin of the data driver chip, and the step S2 includes: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not turned on, and a first control signal is generated to control the switch control circuit to be non-conductive, and different pins of the data driver chip respectively input different analog voltages to the data lines in the data line group to output them to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the switch control circuit is controlled to be conductive, and the pin connected to the first data line on the data driver chip outputs an analog voltage to the first data line and to the second data line through the switch control circuit to output it to the pixel electrode of the corresponding pixel.

[0007] Optionally, the data line group includes two data lines, namely a first data line and a second data line, the first data line and the second data line are respectively connected to different pins of a data driving chip, the data driving chip includes a digital-to-analog conversion module and a data replication module, and the step S2 includes: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not turned on, and different analog voltages are respectively input to the data lines in the data line group to be output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the digital voltage is output to the data driver chip and stored in the register area. When all the digital voltages of the current row are output to the data driver chip, the data driver chip generates a data latch signal. At the rising edge stage of the data latch signal, the data copy module copies the digital voltage stored in the register area to store it in the temporary storage area of ​​the data driver chip. At the falling edge stage of the data latch signal, the digital-to-analog conversion module converts the digital voltage into an analog voltage and outputs it to the first data line and the second data line.

[0008] Optionally, the data line group includes a first data line group, a second data line group and a third data line group, the second data line group is arranged between the first data line group and the third data line group, the number of the second data line group is greater than the number of the first data line group and the third data line group, the number of data lines in all the second data line groups is greater than the sum of the number of data lines in all the first data line groups and the number of data lines in all the second data line groups, the area where the first data line group is arranged is a first area of ​​the display area of ​​the display panel, the area where the second data line group is arranged is a second area of ​​the display area of ​​the display panel, and the area where the third data line group is arranged is a third area of ​​the display area of ​​the display panel, and the step S1 includes: Detecting a refresh rate of a next frame of the second area of ​​the display panel, and determining whether the refresh rate of the next frame of the second area is greater than a preset refresh rate; The S2 step includes: If the refresh rate of the next frame of the second area is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are respectively input to the data lines in the data line group to be output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame of the second area is greater than the preset refresh rate, the dual data line input mode is enabled, and the same analog voltage is input to all the data lines in the data line group to be output to the pixel electrodes of the corresponding pixels; The first area and the third area do not enable the dual data line input mode, and different analog voltages are respectively input to the data lines in the data line group to be output to the pixel electrodes of the corresponding pixels.

[0009] Optionally, the data driving chip includes a judgment module, which detects and determines whether the refresh rate of the next frame is greater than a preset refresh rate, and generates a corresponding control signal to output to the switch control circuit to control the switch control circuit to connect the first data line and the second data line. The switch control circuit includes a first transistor, the input end of the first transistor is connected to the first data line and the pin connected to the first data line, the output end is connected to the second data line, and the control end is connected to the judgment module. Along the scanning line direction, the threshold of the transistor in the middle of the display area of ​​the display panel is greater than the threshold of the transistors on both sides.

[0010] Optionally, the switch control circuit also includes a second transistor, which is arranged between the second data line and the pin of the data driver chip corresponding to the second data line. When the dual data line input mode is enabled, the judgment module generates a corresponding control signal to control the first transistor to turn on, and the judgment module generates a corresponding control signal to control the second transistor to turn off.

[0011] Optionally, the step of detecting the refresh rate of the next frame and determining whether the refresh rate of the next frame is greater than a preset refresh rate includes: Monitoring the blank time length of the blank area of ​​the next frame according to the acquired frame rate signal, determining the refresh rate of the next frame based on the blank time length, and judging whether the refresh rate of the next frame is greater than the preset refresh rate; The driving method further comprises the following steps: Determine the refresh rate interval where the next frame refresh rate is located, and set different compensation intervals based on different refresh rate intervals; Among them, the refresh rate interval less than the preset refresh rate is divided into a first refresh rate interval and a second refresh rate interval, and the refresh rate interval greater than the preset refresh rate is divided into a third refresh rate interval and a fourth refresh rate interval, the compensation values ​​corresponding to the refresh rate values ​​located in the first refresh rate interval and the second refresh rate interval are smaller than the compensation values ​​corresponding to the refresh rate values ​​located in the third refresh rate interval and the fourth refresh rate interval, and the difference in compensation values ​​corresponding to adjacent refresh rate values ​​located in the third refresh rate interval is smaller than the difference in compensation values ​​corresponding to adjacent refresh rate values ​​located in the fourth refresh rate interval.

[0012] Optionally, pixels in the same row connected to the data lines in each data line group have the same polarity and color, and pixels in two adjacent rows have different colors and polarities.

[0013] The present application also discloses a driving circuit, which drives a display panel using any of the driving methods described above, wherein the driving circuit includes a timing control chip and a data driving chip, wherein the timing control chip outputs a digital voltage to the data driving chip, wherein the display panel includes a plurality of scan lines and data lines, and a plurality of pixels connected to the scan lines and the data lines, wherein the plurality of data lines are divided into a plurality of data line groups including at least two data lines; The data driver chip detects the refresh rate of the next frame and determines whether the refresh rate of the next frame is greater than the preset refresh rate; if the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not turned on, and different analog voltages are input to the data lines in the data line group respectively to output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the digital Dynaudio is converted into an analog circuit, and the same analog voltage is input to all the data lines in the data line group to output to the pixel electrodes of the corresponding pixels.

[0014] Optionally, the data driving chip includes a judgment module, the data line group includes two data lines, namely a first data line and a second data line, a switch control circuit is provided between the first data line and the second data line in each data line group, the switch control circuit includes a first transistor and a second transistor, the input end of the first transistor is connected to the first data line and a pin connected to the first data line, the output end is connected to the second data line, and the control end is connected to the judgment module, the second transistor is arranged between the second data line and a pin of the data driving chip corresponding to the second data line, and when the dual data line input mode is enabled, the judgment module generates a corresponding control signal to control the first transistor to be turned on, and the judgment module generates a corresponding control signal to control the second transistor to be turned off.

[0015] Compared with the current triple gate solution, the present application divides multiple data lines into multiple data line groups, each data line group includes at least two data lines, detects the refresh rate of the next frame, and determines whether the refresh rate of the next frame is greater than the preset refresh rate; if the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group respectively to output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, and the same analog voltage is input to all the data lines in the data line group to output to the pixel electrodes of the corresponding pixels, which can reduce the amount of data transmission in one frame by half. At the same transmission rate, reducing the amount of data in one frame can increase the frame rate, that is, the refresh rate is at least doubled, thereby improving the dynamic picture quality of the product display. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 is a schematic flow chart of a driving method according to a first embodiment of the present application; Figure 2 is a schematic flow chart of a driving method according to a second embodiment of the present application; Figure 3 is a schematic diagram of the structure of a display panel according to a second embodiment of the present application; Figure 4 is a schematic diagram of the structure of a driving circuit of the third embodiment of the present application; Figure 5is a schematic flow chart of a driving method according to a fourth embodiment of the present application; Figure 6 is a schematic diagram of the structure of a display panel according to a fourth embodiment of the present application; Figure 7 is a data transmission schematic diagram of the fourth embodiment of the present application; Figure 8 is a schematic flow chart of a driving method according to a fifth embodiment of the present application; Fig. 9 is a schematic structural diagram of a display panel according to a fifth embodiment of the present application; Fig.10 is a schematic flow chart of a driving method according to a sixth embodiment of the present application; Fig.11 is a schematic structural diagram of a driving circuit of a seventh embodiment of the present application; Fig.12 It is a schematic diagram of the structure of the driving circuit of the eighth embodiment of the present application.

[0017] Among them, 100, display panel; 110, data line group; 111, first data line group; 112, second data line group; 113, third data line group; 120, display area; 121, first area; 122, second area; 123, third area; 200, driving circuit; 210, switch control circuit; 211, first transistor; 212, second transistor; 220, data driving chip; 221, digital-to-analog conversion module; 222, data replication module; 223, judgment module; 300, timing control chip; G1-Gn, scan line; S1-first data line; S2-second data line; TP-data latch signal. DETAILED DESCRIPTION

[0018] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0019] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0020] refer to Figure 1 As shown, as a first embodiment of the present application, a driving method is disclosed, the driving method is used to drive a display panel, the display panel includes a plurality of scan lines and data lines, and a plurality of pixels connected to the scan lines and the data lines, the plurality of data lines are divided into a plurality of data line groups, each data line group includes at least two data lines, the driving method includes: S1: Detect the refresh rate of the next frame and determine whether the refresh rate of the next frame is greater than the preset refresh rate; S2: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group respectively to output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, and the same analog voltage is input to all the data lines in the data line group to output to the pixel electrodes of the corresponding pixels.

[0021] For high-resolution display products, due to the high resolution, the amount of data required for each frame is relatively large. If you want to increase the refresh rate of the product, you need a data driver chip with a higher transmission rate specification, that is, a driver IC, which is a great challenge to the existing IC specifications. Moreover, the faster the transmission rate, the more expensive the IC will be. Therefore, when you want to improve the specifications of high-resolution products, you can increase the refresh rate of the display product by turning on the DLS (dual line source) mode, that is, the dual data line input mode. Before turning on the DLS mode, it will consider whether the refresh rate of the next frame meets the standard for turning on the DLS mode. The refresh rate of the next frame is first detected to determine whether the refresh rate of the next frame is greater than the preset refresh rate. If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not turned on, and different analog voltages are input to the data lines in the data line group respectively to output to the pixel electrodes of the corresponding pixels. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the same analog voltage is input to all the data lines in the data line group to output to the pixel electrodes of the corresponding pixels, thereby reducing the amount of data transmitted in one frame. At the same transmission rate, the refresh rate of the product can be increased.

[0022] like Figure 2 As shown, as the second embodiment of the present application, it is a further refinement and improvement of the above-mentioned first embodiment, referring to Figure 2 and Figure 3 As shown, the data line group 110 includes two data lines, namely a first data line S1 and a second data line S2. A switch control circuit 210 is provided between the first data line S1 and the second data line S2 in each data line group 110. The switch control circuit 210 is provided at one end close to the data driving chip 220. Each data line in the data line group 110 is respectively connected to different pins of the data driving chip 220. The pixels in the same row connected by the data lines in each data line group 110 have the same polarity and the same color. The pixels in two adjacent rows have different colors and different polarities. The S2 step includes: S221: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not turned on, and a first control signal is generated to control the switch control circuit to be non-conductive, and different pins of the data driver chip respectively input different analog voltages to the data lines in the data line group to output them to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the switch control circuit is controlled to be conductive, and the pin connected to the first data line S1 on the data driver chip outputs an analog voltage to the first data line S1 and outputs it to the second data line S2 through the switch control circuit to output it to the pixel electrode of the corresponding pixel.

[0023] By setting a switch control circuit 210 between the pin of the data driving chip 220 and the odd and even column data lines, the switch control circuit 210 is generally in a normally closed state. When the DLS mode is turned on, that is, when it is determined that the refresh rate of the next frame is greater than the preset refresh rate, the switch control circuit 210 is controlled to be turned on, and the pin connected to the first data line S1 on the data driving chip 220 outputs an analog voltage to the first data line S1 and to the second data line S2 through the switch control circuit 210, so that the odd and even column data lines of two adjacent columns are short-circuited together to output the same voltage to the pixel electrodes of the corresponding pixels to drive the liquid crystal deflection.

[0024] Furthermore, the data driving chip 220 includes a judgment module 223, which detects whether the refresh rate of the next frame is greater than the preset refresh rate, and generates a corresponding control signal to output to the switch control circuit 210 to control the switch control circuit 210 to connect the first data line S1 and the second data line S2. The switch control circuit 210 includes a first transistor 211, the input end of the first transistor 211 is connected to the first data line S1 and the pin connected to the first data line S1, the output end is connected to the second data line S2, and the control end is connected to the judgment module 223. Along the scanning line direction, the threshold of the transistor in the middle of the display area 120 of the display panel 100 is greater than the threshold of the transistors on both sides.

[0025] By detecting the refresh rate of the next frame through the judgment module 223 and comparing it with the preset refresh rate to generate a control signal, and then controlling the switch control circuit 210 to connect the first data line S1 and the second data line S2, it is possible to flexibly adjust the refresh rate-related operations according to actual needs, which is helpful to optimize the display effect and power consumption and other performance in different scenarios. For example, it can respond in time when a high refresh rate is required to display dynamic images, and in a relatively static image scene, the refresh rate can be appropriately reduced to save energy; considering the characteristic that the threshold of the transistor in the middle of the display area 120 of the display panel 100 is greater than the threshold of the transistors on both sides, combined with the control of the data line connection by the above-mentioned switch control circuit 210, the working state of the transistors at different positions can be adjusted in a targeted manner to a certain extent, thereby improving the uniformity of the display of the entire display area 120, reducing the unevenness of the display brightness, color, etc. that may be caused by the difference in transistor thresholds, improving the crosstalk problem, and improving the overall display quality.

[0026] like Figure 4 As shown, as the third embodiment of the present application, it is a further improvement on the above-mentioned second embodiment. The switch control circuit 210 also includes a second transistor 212, and the second transistor 212 is arranged between the second data line S2 and the pin of the data driving chip 220 corresponding to the second data line S2. When the dual data line input mode is enabled, the judgment module 223 generates a corresponding control signal to control the first transistor 211 to be turned on, and the judgment module 223 generates a corresponding control signal to control the second transistor 212 to be turned off.

[0027] This solution is an expansion on the basis of the original switch control circuit 210, and a second transistor 212 is added. The second transistor 212 is located between the second data line S2 and the pin of the data driving chip 220 corresponding to the second data line S2; when in the specific working state of the dual data line input mode, the judgment module 223 will play its function, on the one hand, generating a corresponding control signal to turn on the first transistor 211, and on the other hand, it will also generate a corresponding control signal to turn off the second transistor 212; through the judgment module 223, different control signals are generated according to whether the dual data line input mode is enabled, and the first transistor 211 is controlled to be turned on and the second transistor 212 is controlled to be turned off, respectively, so that the dual data line input mode can be smoothly switched between other possible modes, so as to meet different requirements for data transmission methods in different application scenarios, and enhance the flexibility and adaptability of the entire circuit system in dealing with multiple working modes.

[0028] In the dual data line input mode, precise control of the conduction of the first transistor 211 can ensure that data can be transmitted through an appropriate path, and timely shutting down the second transistor 212 can effectively avoid unnecessary signal interference or short circuit problems, thereby ensuring the accuracy and stability of data transmission, improving the efficiency and quality of overall data transmission, and facilitating the normal and high-quality development of subsequent operations such as related display.

[0029] like Figure 5 As shown, as the fourth embodiment of the present application, it is a further improvement and refinement of the above-mentioned first embodiment. The data line group 110 includes two data lines, namely a first data line S1 and a second data line S2. The first data line S1 and the second data line S2 are respectively connected to different pins of a data driver chip 220. The data driver chip 220 includes a digital-to-analog conversion module 221 and a data replication module 222. The S2 step includes: S251: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group respectively to be output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, and the digital voltage is output to the data driver chip and stored in the register area. When all the digital voltages of the current row are output to the data driver chip, the data driver chip generates a data latch signal TP. At the rising edge stage of the data latch signal TP, the data copy module copies the digital voltage stored in the register area to store it in the temporary storage area of ​​the data driver chip. At the falling edge stage of the data latch signal TP, the digital-to-analog conversion module converts the digital voltage into an analog voltage and outputs it to the first data line S1 and the second data line S2.

[0030] The pixel voltage value is mainly transmitted by the front-end timing control chip 300 to the data driver chip 220 (source driver IC) in the form of digital voltage, and then converted into an analog voltage by the digital-to-analog conversion module 221 of the data driver chip 220, and output to the pixel electrode by copying the data to achieve the purpose of doubling the refresh rate.

[0031] refer to Figure 6 As shown, in DLS mode, DA1 is the first data transmitted from the timing control chip 300 to the data driver chip 220, and DA2 is the data received by the data driver chip 220 and stored in the register area (input register). When all the data of this row are transmitted to the data driver chip 220, as shown in FIG. Figure 7As shown, a TP (latch signal) rising edge signal is generated, at which time the data driver chip 220 pushes the data in the input Register to the temporary storage area (data latch). In this process, the data of DA2 can be copied to DA3 and synchronously saved in the data latch. After the data is converted and processed by the digital-to-analog conversion module 221, at the falling edge of TP, the converted analog voltage is transmitted to the pixel electrodes of the sub-pixels in the plane for charging, wherein DA2 is charged to the first column of sub-pixels, and DA3 is charged to the second column of sub-pixels.

[0032] Similar to the second embodiment, because the data of two adjacent columns are copied, the data actually transmitted from the timing control chip 300 to the data driving chip 220 in one frame is only half of that in the normal mode. If the data transmission rate remains unchanged, the refresh rate can be doubled.

[0033] like Figure 8 As shown, as the fifth embodiment of the present application, it is a further refinement and improvement of any of the above embodiments, refer to Figure 8 and Fig. 9 As shown, the data line group 110 includes a first data line group 111, a second data line group 112 and a third data line group 113, the second data line group 112 is arranged between the first data line group 111 and the third data line group 113, the number of the second data line group 112 is greater than the number of the first data line group 111 and the third data line group 113, the number of data lines in all the second data line groups 112 is greater than the sum of the number of data lines in all the first data line groups 111 and the number of data lines in all the second data line groups 112, the area where the first data line group 111 is arranged is the first area 121 of the display area 120 of the display panel 100, the area where the second data line group 112 is arranged is the second area 122 of the display area 120 of the display panel 100, and the area where the third data line group 113 is arranged is the third area 123 of the display area 120 of the display panel 100, and the step S1 includes: S181: Detecting a refresh rate of a next frame of a second area of ​​the display panel, and determining whether the refresh rate of the next frame of the second area is greater than a preset refresh rate; The S2 step includes: S281: If the refresh rate of the next frame of the second area is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are respectively input to the data lines in the data line group to output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame of the second area is greater than the preset refresh rate, the dual data line input mode is enabled, and the same analog voltage is input to all the data lines in the data line group to output to the pixel electrodes of the corresponding pixels; S282: The first region and the third region do not enable the dual data line input mode, and input different analog voltages to the data lines in the data line group respectively, so as to output them to the pixel electrodes of the corresponding pixels.

[0034] This embodiment mainly takes into account the different display requirements of different areas of the display area 120 of the display panel 100. The middle area generally displays dynamic images and is also an area where the human eye is more sensitive. Therefore, the display area 120 is divided into three areas. The data lines in different areas are divided into multiple data line groups 110. However, when the refresh rate is changed, only the middle area starts the dual data line input mode to increase the refresh rate of the middle area and improve the display effect of the middle area.

[0035] like Fig.10 As shown, as the sixth embodiment of the present application, it is a further refinement and improvement of the above first embodiment, and the S1 step includes: S11: monitoring the blank time length of the blank area of ​​the next frame according to the acquired frame rate signal, determining the refresh rate of the next frame based on the blank time length, and judging whether the refresh rate of the next frame is greater than the preset refresh rate; The driving method further comprises the following steps: S3: determining a refresh rate interval where the next frame refresh rate is located, and setting different compensation intervals based on different refresh rate intervals; Among them, the refresh rate interval less than the preset refresh rate is divided into a first refresh rate interval and a second refresh rate interval, and the refresh rate interval greater than the preset refresh rate is divided into a third refresh rate interval and a fourth refresh rate interval, the compensation values ​​corresponding to the refresh rate values ​​located in the first refresh rate interval and the second refresh rate interval are smaller than the compensation values ​​corresponding to the refresh rate values ​​located in the third refresh rate interval and the fourth refresh rate interval, and the difference in compensation values ​​corresponding to adjacent refresh rate values ​​located in the third refresh rate interval is smaller than the difference in compensation values ​​corresponding to adjacent refresh rate values ​​located in the fourth refresh rate interval.

[0036] The entire driving method also includes the step of determining the refresh rate interval where the next frame refresh rate is located (S3), and setting different compensation intervals corresponding to different refresh rate intervals. By using the frame rate signal to monitor the length of the blank area to determine the refresh rate, the actual refresh rate of each frame can be obtained more accurately, providing an accurate data basis for subsequent collaboration with other systems or optimization of the display effect. For example, the display brightness, clarity and other parameters can be adjusted in real time according to different refresh rates to achieve a better visual experience.

[0037] By setting different compensation intervals according to different refresh rate intervals, display compensation can be performed more finely for different refresh rate conditions. For the part that is less than the preset refresh rate, since its refresh rate is relatively low, the impact on the display effect may be relatively small, so a relatively small compensation value is set; and for the part that is greater than the preset refresh rate, because its refresh rate is high, the potential impact on the display effect is relatively large, so a larger compensation value is set. In this way, system resources can be reasonably allocated while ensuring the display effect, avoiding resource waste caused by over-compensation. Differentiating the difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the third refresh rate interval and the fourth refresh rate interval can further optimize the transition of the display effect. This makes the display effect change smoother and more natural in different refresh rate intervals, reduces display flickering, stuttering and other problems caused by changes in refresh rate, and improves the overall visual comfort and picture smoothness.

[0038] like Fig.11 As shown, as the seventh embodiment of the present application, a driving circuit 200 is disclosed, which drives a display panel 100 using the driving method described in any of the above embodiments, wherein the driving circuit 200 includes a timing control chip 300 and a data driving chip 220, wherein the timing control chip 300 outputs a digital voltage to the data driving chip 220, and the display panel 100 includes a plurality of scan lines and data lines, and a plurality of pixels connected to the scan lines and the data lines, wherein the plurality of data lines are divided into a plurality of data line groups 110 including at least two data lines; The data driver chip 220 detects the refresh rate of the next frame and determines whether the refresh rate of the next frame is greater than the preset refresh rate; if the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not turned on, and different analog voltages are input to the data lines in the data line group 110 respectively to output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the digital voltage is converted into an analog circuit, and the same analog voltage is input to all the data lines in the data line group 110 to output to the pixel electrodes of the corresponding pixels.

[0039] In this embodiment, the data driver chip 220 detects the refresh rate of the next frame and compares it with the preset refresh rate. Specifically, if it is detected that the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode will not be turned on, but different analog voltages will be input to each data line in the data line group 110, and these input analog voltages will be transmitted to the pixel electrodes of the corresponding pixels. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode will be turned on, and the digital signal will be converted into an analog signal at the same time, and then the same analog voltage will be input to all data lines in the data line group 110, and these voltages will also be output to the pixel electrodes of the corresponding pixels.

[0040] According to the comparison result between the next frame refresh rate and the preset refresh rate, you can flexibly choose whether to enable the dual data line input mode and different voltage input methods, which can well adapt to the display requirements in different frame rate scenarios. For example, in a low refresh rate scenario, by inputting different analog voltages to different data lines, the basic display effect can be guaranteed so that the picture can be presented normally; in a high refresh rate scenario, enabling the dual data line input mode and inputting the same analog voltage will help to quickly complete the picture update, reduce display anomalies caused by changes in refresh rate, and improve the overall display fluency and stability.

[0041] Not enabling the dual data line input mode when the refresh rate is low can avoid unnecessary energy waste, because all data lines do not need to be operated at a uniform high frequency. Using a unified analog voltage input and dual data line input mode at a high refresh rate can simplify the circuit operation process, improve the efficiency of data processing and transmission, and make the entire display driving process more efficient. While ensuring the display effect, it can also reduce power consumption to a certain extent, extend the battery life of the device, etc.

[0042] like Fig.12As shown, as the eighth embodiment of the present application, it is a further improvement and refinement of the seventh embodiment. The data driving chip 220 includes a judgment module 223. The data line group 110 includes two data lines, namely a first data line S1 and a second data line S2. A switch control circuit 210 is provided between the first data line S1 and the second data line S2 in each data line group 110. The switch control circuit 210 includes a first transistor 211 and a second transistor 212. The input end of the first transistor 211 is connected to the first data line S1 and the pin connected to the first data line S1, the output end is connected to the second data line S2, and the control end is connected to the judgment module 223. The second transistor 212 is arranged between the second data line S2 and the pin of the data driving chip 220 corresponding to the second data line S2. When the dual data line input mode is enabled, the judgment module 223 generates a corresponding control signal to control the first transistor 211 to be turned on, and the judgment module 223 generates a corresponding control signal to control the second transistor 212 to be turned off.

[0043] In this embodiment, a judgment module 223 is provided in the data driver chip 220 in this scheme, and the entire data line group 110 is composed of a first data line S1 and a second data line S2; in each data line group 110, a switch control circuit 210 is configured between the first data line S1 and the second data line S2, and the circuit includes a first transistor 211 and a second transistor 212. Among them, the input end of the first transistor 211 is connected to the first data line S1 and its corresponding connected pin, the output end is connected to the second data line S2, and the control end is connected to the judgment module 223. The second transistor 212 is between the second data line S2 and its corresponding data driver chip 220 pin. When the dual data line input mode is enabled, the judgment module 223 generates a corresponding control signal to turn on the first transistor 211, and also generates a control signal to turn off the second transistor 212. By using the judgment module 223 to accurately generate a control signal according to whether the dual data line input mode is enabled, the on / off control of the first transistor 211 and the second transistor 212 is realized, and the single data line input mode and the dual data line input mode can be efficiently switched. This switching function allows the circuit to flexibly adjust the working state according to actual needs, adapt to different data transmission and display scenarios, and enhance the operability and compatibility of the entire circuit system.

[0044] By reasonably controlling the states of the two transistors, turning on the first transistor 211 and turning off the second transistor 212 in the dual data line input mode, it is possible to ensure that data is accurately transmitted in the corresponding lines, avoiding signal interference, short circuits and other problems caused by incorrect transistor states, and effectively ensuring the accuracy and stability of data transmission. It provides strong support for the subsequent pixel electrodes to receive correct and stable analog voltage signals, thereby helping to improve display quality and enable the display image to be presented clearly and stably.

[0045] It should be noted that the limitations of the various steps involved in this scheme, without affecting the implementation of the specific scheme, are not considered to limit the order of the steps, that is, the steps written in front can be executed first, or can be executed later, or even simultaneously. As long as this scheme can be implemented, it should be considered to belong to the scope of protection of this application. The inventive concept of this application can form a lot of embodiments, but the length of the application document is limited and cannot be listed one by one. Therefore, under the premise of no conflict, the various embodiments or technical features described above can be arbitrarily combined to form a new embodiment. After the various embodiments or technical features are combined, the original technical effect will be enhanced.

[0046] The above contents are further detailed descriptions of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A driving method for driving a display panel, wherein the display panel comprises a plurality of scan lines and data lines, and a plurality of pixels connected to the scan lines and the data lines, wherein: Divide a plurality of data lines into a plurality of data line groups, each data line group includes at least two data lines, and the driving method includes the following steps: S1: Detect the refresh rate of the next frame and determine whether the refresh rate of the next frame is greater than the preset refresh rate; S2: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group respectively to output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, and the same analog voltage is input to all the data lines in the data line group to output to the pixel electrodes of the corresponding pixels.

2. The driving method according to claim 1, characterized in that: The data line group includes two data lines, namely a first data line and a second data line. A switch control circuit is provided between the first data line and the second data line in each data line group. The switch control circuit is provided at one end close to the data driver chip. Each data line in the data line group is connected to a different pin of the data driver chip. The step S2 includes: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not turned on, and a first control signal is generated to control the switch control circuit to be non-conductive, and different pins of the data driver chip respectively input different analog voltages to the data lines in the data line group to output them to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the switch control circuit is controlled to be conductive, and the pin connected to the first data line on the data driver chip outputs an analog voltage to the first data line and to the second data line through the switch control circuit to output it to the pixel electrode of the corresponding pixel.

3. The driving method according to claim 1, characterized in that: The data line group includes two data lines, namely a first data line and a second data line, the first data line and the second data line are respectively connected to different pins of a data driving chip, the data driving chip includes a digital-to-analog conversion module and a data replication module, and the step S2 includes: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not turned on, and different analog voltages are respectively input to the data lines in the data line group to be output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the digital voltage is output to the data driver chip and stored in the register area. When all the digital voltages of the current row are output to the data driver chip, the data driver chip generates a data latch signal. At the rising edge stage of the data latch signal, the data copy module copies the digital voltage stored in the register area to store it in the temporary storage area of ​​the data driver chip. At the falling edge stage of the data latch signal, the digital-to-analog conversion module converts the digital voltage into an analog voltage and outputs it to the first data line and the second data line.

4. The driving method according to any one of claims 1 to 3, characterized in that: The data line group includes a first data line group, a second data line group and a third data line group, the second data line group is arranged between the first data line group and the third data line group, the number of the second data line group is greater than the number of the first data line group and the third data line group, the number of data lines in all the second data line groups is greater than the sum of the number of data lines in all the first data line groups and the number of data lines in all the second data line groups, the area where the first data line group is arranged is a first area of ​​the display area of ​​the display panel, the area where the second data line group is arranged is a second area of ​​the display area of ​​the display panel, and the area where the third data line group is arranged is a third area of ​​the display area of ​​the display panel, and the step S1 includes: Detecting a refresh rate of a next frame of the second area of ​​the display panel, and determining whether the refresh rate of the next frame of the second area is greater than a preset refresh rate; The S2 step includes: If the refresh rate of the next frame of the second area is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are respectively input to the data lines in the data line group to be output to the pixel electrodes of the corresponding pixels; if the refresh rate of the next frame of the second area is greater than the preset refresh rate, the dual data line input mode is enabled, and the same analog voltage is input to all the data lines in the data line group to be output to the pixel electrodes of the corresponding pixels; The first area and the third area do not enable the dual data line input mode, and different analog voltages are respectively input to the data lines in the data line group to be output to the pixel electrodes of the corresponding pixels.

5. The driving method according to claim 2, characterized in that: The data driving chip includes a judgment module, which detects and determines whether the refresh rate of the next frame is greater than the preset refresh rate, and generates a corresponding control signal to output to the switch control circuit to control the switch control circuit to connect the first data line and the second data line. The switch control circuit includes a first transistor, the input end of the first transistor is connected to the first data line and the pin connected to the first data line, the output end is connected to the second data line, and the control end is connected to the judgment module. Along the scanning line direction, the threshold of the transistor in the middle of the display area of ​​the display panel is greater than the threshold of the transistors on both sides.

6. The driving method according to claim 5, characterized in that: The switch control circuit also includes a second transistor, which is arranged between the second data line and the pin of the data driving chip corresponding to the second data line. When the dual data line input mode is enabled, the judgment module generates a corresponding control signal to control the first transistor to turn on, and the judgment module generates a corresponding control signal to control the second transistor to turn off.

7. The driving method according to claim 1, characterized in that: The step of detecting the refresh rate of the next frame and determining whether the refresh rate of the next frame is greater than the preset refresh rate includes: Monitoring the blank time length of the blank area of ​​the next frame according to the acquired frame rate signal, determining the refresh rate of the next frame based on the blank time length, and judging whether the refresh rate of the next frame is greater than the preset refresh rate; The driving method further comprises the following steps: Determine the refresh rate interval where the next frame refresh rate is located, and set different compensation intervals based on different refresh rate intervals; Among them, the refresh rate interval less than the preset refresh rate is divided into a first refresh rate interval and a second refresh rate interval, and the refresh rate interval greater than the preset refresh rate is divided into a third refresh rate interval and a fourth refresh rate interval, the compensation values ​​corresponding to the refresh rate values ​​located in the first refresh rate interval and the second refresh rate interval are smaller than the compensation values ​​corresponding to the refresh rate values ​​located in the third refresh rate interval and the fourth refresh rate interval, and the difference in compensation values ​​corresponding to adjacent refresh rate values ​​located in the third refresh rate interval is smaller than the difference in compensation values ​​corresponding to adjacent refresh rate values ​​located in the fourth refresh rate interval.

8. The driving method according to claim 1, characterized in that: The pixels in the same row connected by the data lines in each data line group have the same polarity and color, and the pixels in two adjacent rows have different colors and polarities.

9. A driving circuit, using the driving method according to any one of claims 1 to 8 to drive a display panel, characterized in that: The driving circuit includes a timing control chip and a data driving chip, the timing control chip outputs a digital voltage to the data driving chip, the display panel includes a plurality of scan lines and data lines, and a plurality of pixels connected to the scan lines and the data lines, and the plurality of data lines are divided into a plurality of data line groups including at least two data lines; The data driving chip detects the refresh rate of the next frame and determines whether the refresh rate of the next frame is greater than a preset refresh rate; If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group respectively to be output to the pixel electrodes of the corresponding pixels; If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is turned on, and the digital Dynaudio is converted into an analog circuit, and the same analog voltage is input to all data lines in the data line group to output to the pixel electrode of the corresponding pixel.

10. The driving circuit according to claim 9, characterized in that: The data driving chip includes a judgment module, the data line group includes two data lines, namely a first data line and a second data line, a switch control circuit is provided between the first data line and the second data line in each data line group, the switch control circuit includes a first transistor and a second transistor, the input end of the first transistor is connected to the first data line and the pin connected to the first data line, the output end is connected to the second data line, and the control end is connected to the judgment module, the second transistor is arranged between the second data line and the pin of the data driving chip corresponding to the second data line, and when the dual data line input mode is enabled, the judgment module generates a corresponding control signal to control the first transistor to be turned on, and the judgment module generates a corresponding control signal to control the second transistor to be turned off.

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