Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display. The display panel comprises a driving backboard and a light emitting device, the driving backboard comprises a plurality of pixel circuits which are distributed in an array mode in the row direction and the column direction, each pixel circuit comprises a plurality of transistors, and the transistors in any pixel circuit comprise a driving transistor; the driving transistor and at least part of other transistors in any pixel circuit are metal oxide transistors; the driving back plate comprises a substrate, and a semiconductor layer and at least one source-drain layer which are distributed along a direction far away from the substrate; at least part of channel parts of the transistors are located in the semiconductor layer; the source drain layer is overlapped with at least part of the channel part of the metal oxide transistor; the light-emitting device is arranged on one side of the driving backboard and comprises a first electrode, a light-emitting layer and a second electrode which are distributed in the direction away from the driving backboard. The first electrode of the driving transistor is connected with the first electrode of the light-emitting device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] For display panels that use organic light emitting diodes as light emitting devices, the brightness of the light emitting devices is generally controlled through pixel circuits. If the pixel circuit uses metal oxide transistors, it is easily affected by light and has a threshold voltage shift, affecting the picture quality.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present disclosure provides a display panel and a display device.

[0005] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0006] A driving backplane, comprising a plurality of pixel circuits arranged in an array along row and column directions, wherein the pixel circuits comprise a plurality of transistors, and the transistors in any of the pixel circuits comprise a driving transistor; the driving transistor and at least some of the other transistors in any of the pixel circuits are metal oxide transistors; the driving backplane comprises a substrate, a semiconductor layer and at least one source-drain layer arranged in a direction away from the substrate; the channel portions of at least some of the transistors are located in the semiconductor layer; the source-drain layer overlaps with the channel portions of at least some of the metal oxide transistors;

[0007] The light emitting device is arranged on one side of the driving backplane and comprises a first electrode, a light emitting layer and a second electrode distributed in a direction away from the driving backplane; the first electrode of the driving transistor is connected to the first electrode of the light emitting device.

[0008] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a storage capacitor, and the transistor of the pixel circuit further includes a first reset circuit, a second reset circuit, a write circuit, and a light emitting control circuit;

[0009] The first reset circuit is connected to the gate of the driving transistor and is used to transmit a first reset signal in response to a first reset scan signal; the second reset circuit is connected to the first electrode of the driving transistor and is used to transmit a second reset signal in response to a second reset scan signal; the write circuit is connected to the gate of the driving transistor and is used to transmit a data signal in response to a write scan signal; the light-emitting control circuit is used to receive a first power supply signal and is connected to the second electrode of the driving transistor, and is used to be turned on in response to a light-emitting control signal; the storage capacitor is connected to the gate and the first electrode of the driving transistor.

[0010] In an exemplary embodiment of the present disclosure, the driving backplane further includes a first power line and a data line extending in the column direction and a first reset scan line, a second reset scan line, a write scan line, a light emitting control line, a first reset signal line, and a second reset signal line extending in the row direction;

[0011] The first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the write circuit includes a write transistor, and the light emitting control circuit includes a light emitting control transistor; each of the transistors in the pixel circuit is a metal oxide transistor;

[0012] The first reset scan line is connected to the gate of the first reset transistor and is used to transmit the first reset scan signal; the first reset signal line is connected to the gate of the driving transistor through the first reset transistor and is used to transmit the first reset signal;

[0013] The second reset scan line is connected to the gate of the second reset transistor for transmitting the second reset scan signal; the second reset signal line is connected to the first electrode of the driving transistor through the second reset transistor for transmitting the second reset signal;

[0014] The first power line is connected to the second electrode of the driving transistor through the light emitting control transistor, and is used to transmit the first power signal;

[0015] The write scan line is connected to the gate of the write transistor for transmitting the write scan signal; the data line is connected to the gate of the drive transistor through the write transistor for transmitting the data signal;

[0016] The light emitting control line is connected to the gate of the light emitting control transistor and is used for transmitting the light emitting control signal.

[0017] In an exemplary embodiment of the present disclosure, the driving backplane further includes a second power line extending along the column direction and a first auxiliary power line and a second auxiliary power line extending along the row direction;

[0018] The first auxiliary power line and the first power line are located in different layers and are connected through a contact hole;

[0019] The second power line and the second auxiliary power line are located in different layers and are connected through a contact hole; the second power line is connected to the second electrode for transmitting a second power signal.

[0020] In an exemplary embodiment of the present disclosure, the driving backplane further includes a first auxiliary reset line extending along the column direction, the first auxiliary reset line and the first reset signal line are located in different layers and are connected through a contact hole.

[0021] In an exemplary embodiment of the present disclosure, the driving backplane further includes a second auxiliary reset line extending along the column direction, the second auxiliary reset line and the second reset signal line are located in different layers and are connected through a contact hole.

[0022] In an exemplary embodiment of the present disclosure, one of the data lines is connected to a write transistor of a column of the pixel circuit; one of the first power lines is connected to a light emission control transistor of a column of the pixel circuit;

[0023] The data lines and the first power lines connected to the same column of pixel circuits are defined as a column line group YG, and between two adjacent column line groups there is provided the second power line, one of the first auxiliary reset line and the second auxiliary reset line.

[0024] In an exemplary embodiment of the present disclosure, a row of the pixel circuits is simultaneously connected to one of the first reset scan lines, one of the second reset scan lines, one of the write scan lines, one of the light emission control lines, one of the first reset signal lines, and one of the second reset signal lines;

[0025] The first reset scan line, the second reset scan line, the write scan line, the light emission control line, the first reset signal line and the second reset signal line connected to the pixel circuits in the same row are defined as a row line group;

[0026] A first auxiliary power line and a second auxiliary power line are disposed between two adjacent row line groups.

[0027] In an exemplary embodiment of the present disclosure, the source-drain layer includes a first source-drain layer and a second source-drain layer distributed in a direction away from the substrate;

[0028] Channel portions of the write transistor and the second reset transistor overlap with the first source-drain layer; channel portions of the first reset transistor and the light emission control transistor overlap with the second source-drain layer.

[0029] In an exemplary embodiment of the present disclosure, the semiconductor layer includes a first semiconductor portion and a second semiconductor portion spaced apart along the row direction, and the first semiconductor portion and the second semiconductor portion extend along the row direction;

[0030] The channel portions of the first reset transistor and the write transistor are located in the first semiconductor portion along the column direction; the channel portions of the light emission control transistor, the drive transistor and the second reset transistor are located in the second semiconductor portion along the column direction;

[0031] A channel portion of the write transistor overlaps with one of the write scan lines; a channel portion of the second reset transistor overlaps with one of the second reset scan lines;

[0032] The first power line overlaps with channel portions of the second reset transistor, the drive transistor, and the light emission control transistor.

[0033] In an exemplary embodiment of the present disclosure, at least a portion of the second semiconductor portion has a boundary of an orthographic projection of the substrate in the row direction located within a boundary of an orthographic projection of the first power line on the substrate in the row direction.

[0034] In an exemplary embodiment of the present disclosure, a boundary of at least a portion of the second semiconductor portion in the row direction of an orthographic projection of the substrate is taken as a first boundary, and a boundary of the first power line in the row direction of an orthographic projection of the substrate is taken as a second boundary;

[0035] The first boundary is located inside the second boundary, and a distance between the first boundary and the second boundary is less than 2 μm.

[0036] In an exemplary embodiment of the present disclosure, the first reset scan line, the second reset scan line, the write scan line, the light emitting control line, the first reset signal line, the second reset signal line, the first auxiliary power line and the second auxiliary power line are located in the first source-drain layer;

[0037] The first power line, the second power line, the data line, the first auxiliary reset line and the second auxiliary reset line are located in the second source-drain layer.

[0038] In an exemplary embodiment of the present disclosure, the driving backplane further includes:

[0039] A light shielding layer is provided on one side of the substrate and includes a light shielding portion; the semiconductor layer is provided on a side of the light shielding layer away from the substrate, the light shielding portion overlaps with the channel portion of the driving transistor, and the light shielding portion is reused as a first plate of the storage capacitor;

[0040] A first gate layer is provided on a side of the light shielding layer away from the substrate and includes a second electrode plate of the storage capacitor; the semiconductor layer is provided on a side of the first gate layer away from the substrate, and the first electrode plate overlaps with a channel portion of the driving transistor;

[0041] The second gate layer is arranged on a side of the semiconductor layer away from the substrate and overlaps with the channel portion of the driving transistor; the first source and drain layer is arranged on a side of the second gate layer away from the substrate.

[0042] In an exemplary embodiment of the present disclosure, the first gate layer further includes a first gate portion, a second gate portion, a third gate portion, and a fourth gate portion; the second gate layer includes a fifth gate portion, a sixth gate portion, a seventh gate portion, an eighth gate portion, and a ninth gate portion;

[0043] The first gate portion and the fifth gate portion overlap with the channel portion of the first reset transistor, and the first gate portion and the fifth gate portion are connected;

[0044] The second gate portion and the sixth gate portion overlap with the channel portion of the write transistor, and the second gate portion and the sixth gate portion are connected;

[0045] The third gate portion and the seventh gate portion overlap with the channel portion of the light emission control transistor, and the third gate portion and the seventh gate portion are connected;

[0046] The fourth gate portion and the eighth gate portion overlap with the channel portion of the second reset transistor, and the fourth gate portion and the eighth gate portion are connected;

[0047] The ninth gate portion overlaps with a channel portion of the driving transistor.

[0048] In an exemplary embodiment of the present disclosure, a boundary of the first gate portion and the fifth gate portion in the column direction of the orthographic projection of the substrate is located within a boundary of the orthographic projection of one of the second power line, the first auxiliary reset line and the second auxiliary reset line in the column direction of the substrate; and the first gate portion and the fifth gate portion are connected to the first reset scan line;

[0049] The boundary between the orthographic projection of the third gate portion and the seventh gate portion in the column direction of the substrate is located within the boundary of the orthographic projection of the first power line in the column direction of the substrate; and the third gate portion and the seventh gate portion are connected to the light emitting control line;

[0050] The boundary of the orthographic projection of the second gate portion and the sixth gate portion in the column direction of the substrate is located within the boundary of the orthographic projection of the write scan line in the column direction of the substrate; and the second gate portion and the sixth gate portion are connected to the first reset scan line;

[0051] The boundary of the fourth gate portion and the eighth gate portion in the column direction of the orthographic projection of the substrate is located within the boundary of the orthographic projection of the substrate in the column direction; and the fourth gate portion and the eighth gate portion are connected to the second reset scan line.

[0052] In an exemplary embodiment of the present disclosure, a first electrode at least overlaps with a channel portion of the driving transistor.

[0053] In an exemplary embodiment of the present disclosure, the first electrode includes an electrode body and an extension portion connected to an edge of the electrode body, and the extension portion is connected to a first electrode of the driving transistor;

[0054] At least a portion of the first electrode further includes an extension portion connected to an edge of the electrode body, and the extension portion overlaps with a channel portion of the driving transistor;

[0055] The display panel further includes:

[0056] The pixel definition layer is arranged on the same side of the driving backplane as the light-emitting device and has a pixel opening exposing each of the first electrodes; the boundary of the positive projection of the pixel opening on the substrate is located within the boundary of the electrode body of the exposed first electrode.

[0057] In an exemplary embodiment of the present disclosure, at least a portion of the first electrode overlaps with channel portions of a plurality of the driving transistors at the same time.

[0058] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0059] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0061] Figure 1 It is a top view schematic diagram of an embodiment of a display panel disclosed in the present invention.

[0062] Figure 2 It is a cross-sectional schematic diagram of an embodiment of the display panel disclosed in the present invention.

[0063] Figure 3 FIG. 4 is a schematic diagram of a pixel opening of an embodiment of a display panel disclosed herein.

[0064] Figure 4 FIG. 4 is a schematic diagram of a pixel circuit in an embodiment of a display panel disclosed herein.

[0065] Figure 5 FIG. 4 is a driving timing diagram of a pixel circuit in an embodiment of a display panel disclosed herein.

[0066] Figure 6 FIG. 4 is a schematic diagram of a pixel circuit in an initialization stage in an embodiment of a display panel disclosed herein.

[0067] Figure 7 FIG. 4 is a schematic diagram of a pixel circuit in a compensation stage in an embodiment of a display panel disclosed herein.

[0068] Figure 8 FIG. 4 is a schematic diagram of a pixel circuit in a writing stage in an embodiment of a display panel disclosed herein.

[0069] Fig. 9 FIG. 4 is a schematic diagram of a pixel circuit in a light-emitting stage in an embodiment of a display panel disclosed herein.

[0070] Fig.10 It is a partial top view of an embodiment of the display panel disclosed in the present invention.

[0071] Fig.11 It is a partial top view of the light shielding layer to the second source and drain layer in one embodiment of the display panel disclosed in the present invention.

[0072] Fig.12 It is a partial top view of the light shielding layer to the first source and drain layer in one embodiment of the display panel disclosed in the present invention.

[0073] Fig.13 for Fig.12 AA cross-section diagram.

[0074] Fig.14 for Fig.12 BB cross-section diagram.

[0075] Fig.15 for Fig.12 CC cross-section diagram.

[0076] Fig.16 It is a partial top view from the light shielding layer to the second gate layer in one embodiment of the display panel disclosed in the present invention.

[0077] Fig.17 It is a partial top view of the first gate layer to the second gate layer in one embodiment of the display panel disclosed in the present invention.

[0078] Fig.18 FIG. 1 is a partial top view of a first gate layer and a semiconductor layer in an embodiment of a display panel disclosed herein.

[0079] Fig.19 It is a partial top view of the semiconductor layer and the second gate layer in one embodiment of the display panel disclosed herein.

[0080] Fig. 20 It is a partial top view of a light shielding layer and a first gate layer in one embodiment of a display panel disclosed in the present invention.

[0081] Figure 21 to Figure 26 They are respectively partial top views of multiple film layers of the display panel of the present disclosure.

[0082] Fig. 27 FIG. 4 is a top view of a first electrode in an embodiment of a display panel disclosed herein.

[0083] Fig.28 It is a partial top view of a first power line and a second semiconductor portion in one embodiment of a display panel disclosed herein.

[0084] Fig.29 FIG. 4 is a partial top view of another embodiment of the display panel disclosed in the present invention.

[0085] Fig.30 It is a partial top view of the light shielding layer to the second source and drain layer in another embodiment of the display panel disclosed in the present invention. DETAILED DESCRIPTION

[0086] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0087] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0088] The row direction X and the column direction Y herein are two intersecting directions, which may be perpendicular to each other. In the drawings of the present disclosure, the row direction X is horizontal and the column direction Y is vertical, but this is not limited thereto. It is known to those skilled in the art that if the display panel is rotated, the actual directions of the row direction X and the column direction Y may change.

[0089] The "overlap" of A and B herein means that the orthographic projection of A on the substrate and the orthographic projection of B on the substrate at least partially overlap. Of course, the orthographic projections of A and B on a plane parallel to the substrate may also at least partially overlap. The "different layers" of A and B herein means that A and B are different film layers formed at different times.

[0090] The present disclosure provides a display panel. Figure 1 As shown, it may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA, or may be a discontinuous area surrounding the display area AA.

[0091] like Figure 2 As shown, the display panel may include a driving backplane BP and a plurality of light emitting devices LD arranged on one side of the driving backplane BP. Each light emitting device LD may be distributed in an array along a row direction X and a column direction Y. The driving circuit in the driving backplane BP may drive the light emitting device LD to emit light to display an image.

[0092] like Figure 1 and Figure 2 As shown, the light-emitting device LD can be located in the display area AA, and it can be an OLED (organic light-emitting diode) of organic light-emitting material; it can also be an LED (light-emitting diode) using inorganic light-emitting materials, for example, Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also be a device such as QLED (quantum dot diode). The specific structure of the light-emitting device LD is not particularly limited here.

[0093] like Figure 2 and Figure 3As shown, taking the light-emitting device LD using OLED as an example, it may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked in sequence in a direction away from the driving backplane BP. By applying a first power signal VDD to the first electrode ANO and applying a second power signal VSS to the second electrode CAT, the light-emitting layer EL may be stimulated to emit light. The specific principle is not described in detail here. At the same time, in order to limit the range of the light-emitting device LD, a pixel definition layer PDL may be provided on the driving backplane BP. The pixel definition layer PDL and the first electrode ANO are located on the same surface of the driving backplane BP, and the pixel definition layer PDL may have a pixel opening PH exposing each first electrode ANO, so that the range of the light-emitting device LD can be limited by each pixel opening PH.

[0094] The driving circuit may include a pixel circuit PC located in the display area AA and a peripheral circuit located in the peripheral area WA. The pixel circuit PC may be distributed in an array along the row direction X and the column direction Y. A pixel circuit PC may be connected to a first electrode ANO of a light-emitting device LD. Of course, the same pixel circuit PC may also be connected to the first electrodes of multiple light-emitting devices LD.

[0095] The peripheral circuit can be connected to the light emitting device LD through the pixel circuit PC, and a first power signal VDD is applied to the first electrode ANO of the light emitting device LD. The peripheral circuit can also include a gate driving circuit and a light emitting driving circuit for scanning the pixel circuit PC. At the same time, the peripheral circuit can also be connected to the second electrode CAT of the light emitting device LD, and a second power signal VSS is applied to the second electrode CAT. The current passing through the light emitting device LD can be controlled through the pixel circuit PC, thereby controlling the brightness of the light emitting device LD.

[0096] The pixel circuit PC may include a plurality of transistors, and any of the transistors of the pixel circuit PC includes at least a driving transistor T5, and the driving transistor T5 may be a metal oxide transistor, and at least a portion of other transistors may also be metal oxide transistors. Of course, only the driving transistor T5 may be a metal oxide transistor. A metal oxide transistor refers to a transistor whose active layer material is IGZO (Indium Gallium Zinc Oxide), or IZO (Indium Zinc Oxide), etc. The active layer of the transistor includes a channel and a conductor portion connected to the channel.

[0097] Each transistor may include a gate, a first electrode, and a second electrode. The first electrode and the second electrode may be turned on and off by controlling the voltage of the gate. The first electrode may be a source electrode, and the second electrode may be a drain electrode. Of course, the first electrode may also be a drain electrode, and the second electrode may also be a source electrode. Specifically, if a signal is input from the first electrode, the first electrode is the source electrode, and the second electrode is the drain electrode. If a signal is input from the second electrode, the second electrode is the source electrode, and the first electrode is the drain electrode. In other words, the source electrode and the drain electrode may be interchanged depending on the change of the input signal.

[0098] For a P-type transistor, when the gate receives a high level, the first and second electrodes are turned off; when the gate receives a low level, the first and second electrodes are turned on. For an N-type transistor, when the gate receives a high level, the first and second electrodes are turned on; when the gate receives a low level, the first and second electrodes are turned off.

[0099] Take a pixel circuit PC as an example, Figure 4 As shown, the pixel circuit PC may include a driving transistor T5, a writing circuit 1, a first reset circuit 2, a second reset circuit 3 and a light emitting control circuit 4, wherein:

[0100] The first reset circuit 2 is connected to the gate of the driving transistor T5 and can be turned on or off in response to the first reset scanning signal Gate2. The first reset circuit 2 can receive the first reset signal Vref and transmit the first reset signal Vref when turned on.

[0101] The second reset circuit 3 is connected to the first electrode of the driving transistor T5 and can be turned on or off in response to the second reset scanning signal Gate3. The second reset circuit 3 can receive the second reset signal Vinit and transmit the second reset signal Vinit when turned on.

[0102] The write circuit 1 is connected to the gate of the driving transistor T5, and the write circuit 1 can be turned on or off in response to the write scan signal Gate1. The write circuit 1 can receive the data signal Data, and can transmit the data signal Data when turned on.

[0103] The light emitting control circuit 4 can receive the first power supply signal VDD and be connected to the second electrode of the driving transistor T5. The light emitting control circuit 4 can be turned on or off in response to the light emitting control signal EM, and when turned on, it can transmit the first power supply signal VDD to the driving transistor T5. The storage capacitor Cst is connected to the gate and the first electrode of the driving transistor T5.

[0104] Further, in some embodiments of the present disclosure, Figure 1 , Figure 4 , Fig.11 and Fig.12The pixel circuit PC shown is a 5T1C structure, where T means 5 transistors and 1 capacitor. Specifically, the first reset circuit 2 includes a first reset transistor T2, the second reset circuit 3 includes a second reset transistor T3, the write circuit 1 includes a write transistor T1, and the light-emitting control circuit 4 includes a light-emitting control transistor T4; each transistor of the pixel circuit PC is a metal oxide transistor. At the same time, in order to facilitate signal transmission, the driving backplane BP may also include a first power line VDL, a data line DAL, a first reset scan line GL2, a second reset scan line GL3, a write scan line GL1, a light-emitting control line EML, a first reset signal line VRL, and a second reset signal line VIL; wherein: the first power line VDL and the data line DAL may extend along the column direction Y and may be distributed along the row direction X. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the light-emitting control line EML, the first reset signal line VRL, and the second reset signal line VIL may extend along the row direction X and may be distributed along the column direction Y.

[0105] The first reset scan line GL2 is connected to the gate of the first reset transistor T2 and is used to transmit the first reset scan signal Gate2. The first reset signal line VRL is connected to the first electrode of the first reset transistor T2 and can transmit the first reset signal Vref. The second electrode of the first reset transistor T2 is connected to the gate of the driving transistor T5 and is connected to the N1 node. The first reset scan signal Gate2 can control the first reset transistor T2 to be turned on or off, and when turned on, the first reset signal Vref can be transmitted to the gate of the driving transistor T5 through the first reset transistor T2, that is, the first reset signal Vref is transmitted to the N1 node.

[0106] The second reset scan line GL3 is connected to the gate of the second reset transistor T3 and is used to transmit the second reset scan signal Gate3; the second reset signal line VIL is connected to the first electrode of the second reset transistor T3 and can transmit the second reset signal Vinit; the second electrode of the second reset transistor T3 is connected to the first electrode of the driving transistor T5 and can be connected to the N3 node. The second reset scan signal Gate3 can control the second reset transistor T3 to be turned on or off, and when turned on, the second reset signal Vinit can be transmitted to the first electrode of the driving transistor T5 through the second reset transistor T3, that is, the second reset signal Vinit is transmitted to the N3 node.

[0107] The light emitting control line EML is connected to the gate of the light emitting control transistor T4, and is used to transmit the light emitting control signal EM; the first power line VDL is connected to the first electrode of the light emitting control transistor T4, and the second electrode of the light emitting control transistor T4 is connected to the second electrode of the driving transistor T5, and can be connected to the N2 node. The first power line VDL is used to transmit the first power signal VDD. The light emitting control transistor T4 can be turned on or off by the light emitting control signal EM, and when turned on, the first power signal VDD can be transmitted to the second electrode of the driving transistor T5 through the light emitting control transistor T4.

[0108] The write scan line GL1 is connected to the gate of the write transistor T1 and is used to transmit the write scan signal Gate1; the data line DAL is connected to the first electrode of the write transistor T1 and can transmit the data signal Data; the second electrode of the write transistor T1 is connected to the gate of the drive transistor T5 and can be connected to the N1 node. The write scan signal Gate1 can control the write transistor T1 to be turned on or off, and when turned on, the data signal Data can be transmitted to the gate of the drive transistor T5 through the write transistor T1, that is, the data signal Data is transmitted to the N1 node.

[0109] Meanwhile, the storage capacitor Cst has a first plate Cst1 and a second plate Cst2 opposite to each other, the first plate Cst1 is connected to the first electrode of the driving transistor T5 and can be connected to the N3 node, the second plate Cst2 is connected to the gate of the driving transistor T5 and can be connected to the N1 node. The first electrode of the driving transistor T5 and the second electrode of the second reset transistor T3 can be connected to the first electrode ANO of the light emitting device and can be connected to the N3 node.

[0110] In some embodiments of the present disclosure, Figure 1 , Fig.11 and Fig.12 The driving backplane BP further includes a second power line VSL, a first auxiliary power line VDLs and a second auxiliary power line VSLs, wherein:

[0111] The second power line VSL may extend along the column direction Y, and the number of the second power line VSL may be multiple, and may be distributed along the row direction X. Of course, the number of the second power line VSL may also be one. The second power line VSL is used to transmit the second second power signal VSS, and may be connected to the second electrode of the light-emitting device. For example, the driving backplane BP is provided with a first power bus for transmitting the first power signal VDD and a second power bus for transmitting the second power signal VSS in the peripheral area. Each first power line VDL may be connected to the first power bus, and the second power line VSL may be connected to the second power bus. At the same time, the second electrode of the light-emitting device may extend to the peripheral area and be directly or indirectly connected to the second power bus. The second power line VSL and the second power bus may form a whole for transmitting the second power signal VSS. While the second power signal VSS may be transmitted to the second electrode through the second power bus, the second power line VSL may play a role in reducing resistance and voltage drop, which is conducive to maintaining signal stability and uniformity. Of course, in some embodiments, the second power line VSL may not be provided.

[0112] The first auxiliary power lines VDLs may extend along the row direction X, and there may be multiple first auxiliary power lines VDLs, which may be distributed along the column direction Y. Of course, there may also be only one first auxiliary power line VDLs. At the same time, the first auxiliary power lines VDLs may cross the first power lines VDL in space, but are located in different layers and may be connected through contact holes, so that the first auxiliary power lines VDLs and the first power lines VDL form a network for transmitting the first power signal VDD, which is beneficial to reducing resistance, reducing voltage drop, and maintaining signal stability and uniformity.

[0113] The second power line VSL may extend along the row direction X, and the number of the second power line VSL may be multiple and distributed along the column direction Y. Of course, there may be only one second power line VSLs. Meanwhile, the second auxiliary power line VSLs may cross the second power line VSL in space, but be located at different layers and may be connected through contact holes, so that the second auxiliary power line VSLs and the second power line VSL form a network for transmitting the second power signal VSS, which is beneficial to reduce resistance, reduce voltage drop, and keep the signal stable and uniform.

[0114] Further, in some embodiments of the present disclosure, Figures 10 to 12 As shown, the driving backplane BP also includes a plurality of first auxiliary reset lines VRLs extending along the column direction Y, and the number of the first auxiliary reset lines VRLs can be multiple and distributed along the column direction Y. Of course, there can also be only one. At the same time, the first auxiliary reset lines VRLs and the first reset signal lines VRL are located in different layers and connected through contact holes, so as to form a network for transmitting the first reset signal Vref, which is conducive to reducing resistance, reducing voltage drop, and maintaining signal stability and uniformity.

[0115] Further, in some embodiments of the present disclosure, Figures 10 to 12As shown, the driving backplane BP also includes a second auxiliary reset line VILs extending along the column direction Y, and the number of the second auxiliary reset lines VILs can be multiple and distributed along the column direction Y. Of course, there can also be only one. At the same time, the second auxiliary reset line VILs and the second reset signal line VIL are located in different layers and are connected through contact holes, so as to form a network for transmitting the second reset signal Vinit, which is conducive to reducing resistance, reducing voltage drop, and maintaining signal stability and uniformity.

[0116] The following is an example of the distribution of the above wiring:

[0117] In some embodiments of the present disclosure, Figure 1 , Fig.11 and Fig.26 As shown, a data line DAL is connected to the write transistor T1 of a column of pixel circuits PC; a first power line VDL is connected to the light-emitting control transistor T4 of a column of pixel circuits PC. The data line DAL and the first power line VDL connected to the same column of pixel circuits PC can be defined as a column line group YG, that is, each column of pixel circuits PC can be connected to a column line group YG. At the same time, one of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs can be provided between two adjacent column line groups YG, that is, the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs are distributed in the space between the column line groups YG; at the same time, two of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs are provided on both sides of the same column line group YG. In this way, the space can be fully utilized to make the distribution of the routing in the column direction Y more uniform.

[0118] For example, Figure 1 , Fig.11 and Fig.26 As shown, the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs can all be defined as auxiliary lines, and the auxiliary lines and the above-mentioned column line groups YG can be alternately distributed along the row direction X. In the row direction X, if the nth auxiliary line is the second power line VSL, then the n+1th auxiliary line is the second auxiliary reset line VILs, and the n+2th auxiliary line is the first auxiliary reset line VRLs, and n is a positive integer. Of course, the auxiliary lines can also be arranged in other arrangement orders, which will not be described in detail here.

[0119] In some embodiments of the present disclosure, Figure 1 , Fig.12 and Fig.25As shown, a row of pixel circuits PC is simultaneously connected to a first reset scan line GL2, a second reset scan line GL3, a write scan line GL1, a light-emitting control line EML, a first reset signal line VRL, and a second reset signal line VIL. The specific connection relationship has been described in the above content of the pixel circuit PC, and will not be repeated here. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the light-emitting control line EML, the first reset signal line VRL, and the second reset signal line VIL connected to the same row of pixel circuits PC can be defined as a row line group XG, that is, each row of pixel circuits PC is connected to a row line group XG. At the same time, a first auxiliary power line VDLs and a second auxiliary power line VSLs can be provided between two adjacent row line groups XG. A row line group XG is located between a first auxiliary power line VDLs and a second auxiliary power line VSLs.

[0120] The structure of the pixel circuit PC based on the above-mentioned embodiment and its driving method are described below:

[0121] like Figure 4 As shown, taking the above-mentioned 5T1C structure pixel circuit PC as an example, each transistor is a metal oxide transistor and is an N-type transistor. Figure 5 As shown, the driving method of the embodiment of the present disclosure may include:

[0122] like Figure 5 and Figure 6 As shown, in the initialization stage t1: the first reset scan signal Gate2 is at a high level, the first reset transistor T2 and the second reset transistor T3 are turned on, the first reset signal Vref is transmitted to the gate of the driving transistor T5, and the second reset signal Vinit is transmitted to the first electrode of the driving transistor T5 and the first electrode ANO of the light-emitting device, that is, the second reset signal Vinit is transmitted to the N3 node; at the same time, the write scan signal Gate1 and the light-emitting control signal EM are at a low level, and the write transistor T1 and the light-emitting control transistor T4 are turned off. The gate and the first electrode of the driving transistor T5 and the first electrode ANO of the light-emitting device are initialized by the first reset signal Vref and the second reset signal Vinit, that is, the N1 node and the N3 node are initialized. At this time, the voltage of the N1 node = Vref, and the voltage of the N3 node = Vinit.

[0123] like Figure 5 and Figure 7As shown, in the compensation stage t2: the first reset scanning signal Gate2 maintains a high level, the second reset scanning signal Gate3 is a low level, the first reset transistor T2 continues to be turned on, and transmits the first reset signal Vref to the gate of the driving transistor T5, that is, transmits the first reset signal Vref to the N1 node, and the second reset transistor T3 is turned off. At the same time, the light emitting control signal EM is a high level, and the light emitting control transistor T4 is turned on.

[0124] When the voltage difference between the first reset signal Vref and the second reset signal Vinit is greater than the threshold voltage of the driving transistor T5, that is, when the voltage difference between the N1 node and the N3 node is greater than the threshold voltage, the driving transistor T5 is turned on; the first power supply signal VDD charges the first electrode of the driving transistor T5 until the difference between the first reset signal Vref and the threshold voltage of the driving transistor T5 is reached, that is, when the voltage of the N3 node is Vref-Vth, the driving transistor T5 is turned off, thereby writing the threshold voltage into the first electrode of the driving transistor T5. At this time, the voltage of the N1 node = Vref, and the voltage of the N3 node = Vref-Vth.

[0125] like Figure 5 and Figure 8 As shown, in the writing stage t3, the first reset scanning signal Gate2, the second reset scanning signal Gate3 and the light-emitting control signal EM are all at low level, and the writing scanning signal Gate1 is at high level; the first reset transistor T2, the second reset transistor T3 and the light-emitting control transistor T4 are turned off, and the writing transistor T1 is turned on. The data signal Data is written to the N1 node through the writing transistor T1, that is, the data signal Data is written to the gate of the driving transistor T5 and the second plate Cst2 of the storage capacitor Cst; at this time, the voltage Vg of the N1 node = Vdata, the voltage of the N3 node = Vld + Vss = Vref - Vth, and Vld is the voltage of the light-emitting device LD, that is, the voltage of the capacitor Co of the light-emitting device LD itself.

[0126] like Figure 5 and Fig. 9 As shown, in the light-emitting stage t4: the light-emitting control signal EM is at a high level, the first reset scanning signal Gate2, the second reset scanning signal Gate3 and the write scanning signal Gate1 are at a low level, the light-emitting control transistor T4 is turned on, and the first reset transistor T2, the second reset transistor T3 and the write transistor T1 are turned off; under the action of the storage capacitor Cst, the driving transistor T5 outputs a current, and the output current satisfies the following formula:

[0127] I=(μWCox / 2L)(Vgs-Vth) 2 ;

[0128] I is the output current of the driving transistor T5; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T5, and L is the channel length of the driving transistor T5.

[0129] According to the above output current formula, the voltage difference Vgs between the gate voltage and the source voltage of the driving transistor T5 in the pixel circuit PC of the present disclosure is substituted into the above formula to obtain: the output current I of the driving transistor T5 = (μWCox / 2L)(Vgs-Vth) 2

[0130] =(μWCox / 2L)(Vdata-(Vld+VSS)-(Vref-Vld-VSS)) 2

[0131] =(μWCox / 2L)(Vdata-(Vref-Vth)-Vth) 2

[0132] =(μWCox / 2L)(Vdata-Vref) 2

[0133] It can be seen that the threshold voltage compensation phase and the data signal Data writing phase are performed separately, and the output current (i.e., the current of the light-emitting device) is not affected by the voltage of the first power signal VDD and the threshold voltage Vth, but is only related to Vdata and Vref. The first reset signal Vref has a smaller current than the first power signal VDD, and the IR Drop (voltage drop) risk is small.

[0134] In other embodiments of the present disclosure, at least a portion of the other transistors except the driving transistor T5 may be P-type transistors, whose channel parts may be made of polysilicon. These transistors may be turned on at a low level and turned off at a high level.

[0135] The following describes the film layer of the driving backplane BP based on the above-mentioned pixel circuit PC:

[0136] like Figure 2 and Figure 3 As shown, the driving backplane BP includes a substrate SU, a semiconductor layer SE and at least one source and drain layer, wherein:

[0137] The substrate SU can be made of glass, polyimide or other materials, and can play a bearing role. Meanwhile, the substrate SU can adopt a single-layer or multi-layer structure, which is not particularly limited here.

[0138] The semiconductor layer SE is disposed on one side of the substrate SU, and the channel portion of at least some transistors is located in the semiconductor layer SE. For example, each transistor is a metal oxide transistor, the material of the semiconductor layer SE is metal oxide, and the channel portion of each transistor is located in the semiconductor layer SE. Of course, if there are both metal oxide transistors and transistors with channel portions made of polysilicon or other materials, the number of semiconductor layers SE can be multiple layers, and channel portions made of different materials can be distributed in different semiconductor layers SE. This article only takes the example of transistors being metal oxide transistors for explanation.

[0139] The number of source and drain layers is at least one, for example, the number of source and drain layers is two. The source and drain layers are located on the side of the semiconductor layer SE away from the substrate SU, and the connection of at least part of the transistors and the transmission of signals can be achieved through the source and drain layers. Each source and drain layer can adopt a single-layer or multi-layer structure, and each layer can adopt a conductive material such as a metal or an alloy. For example, the source and drain layer may include three sub-layers stacked in sequence in a direction away from the substrate SU, wherein the material of the middle layer is aluminum, and the materials of the other two layers are titanium, thereby forming a titanium / aluminum / titanium structure.

[0140] Furthermore, the driving backplane BP may also include a gate layer, which may overlap with the semiconductor layer SE to form a transistor, and the region in the semiconductor layer SE that overlaps with the gate layer is the channel of the transistor, and the non-overlapping region may be conductive to form the first and second poles of the transistor, and the region in the gate layer that overlaps with the semiconductor layer SE is the gate of the transistor. For any transistor, it may adopt a top gate structure, that is, its gate is located between the substrate SU and the semiconductor layer SE; it may also adopt a bottom gate structure, that is, the gate is located on the side of the semiconductor layer SE away from the substrate SU; or it may also adopt a top gate + bottom gate structure, that is, it has two gates, which are respectively located between the substrate SU and the semiconductor layer SE and on the side of the semiconductor layer SE away from the substrate SU, and the two gates also overlap.

[0141] In some embodiments of the present disclosure, Figure 2 , Figure 3 , Figure 16-Figure 24 As shown, the channel parts of each transistor are located in the same semiconductor layer SE, and the driving backplane BP may further include a light shielding layer BSM, a first gate layer GA1 and a second gate layer GA2, wherein:

[0142] like Fig.21 As shown, the light shielding layer BSM is disposed on one side of the substrate SU, and the semiconductor layer SE is disposed on the side of the light shielding layer BSM away from the substrate SU. The light shielding layer BSM may include a plurality of light shielding portions BS, and the light shielding portions BS may overlap with the channel portion of the driving transistor T5, thereby shielding the driving transistor T5 from light on the side close to the substrate SU, thereby improving the stability of the driving transistor T5.

[0143] like Fig. 20As shown, the first gate layer GA1 can be arranged on the side of the light shielding layer BSM away from the substrate SU, the semiconductor layer SE is arranged on the side of the first gate layer GA1 away from the substrate SU, and the second gate layer GA2 is arranged on the side of the semiconductor layer SE away from the substrate SU. The source and drain layer is arranged on the side of the second gate layer GA2 away from the substrate SU.

[0144] like Fig.16 and Fig. 20 As shown, the shading portion BS can be reused as the first plate Cst1 of the storage capacitor Cst, and the first gate layer GA1 includes the second plate Cst2 of the storage capacitor Cst, and the first plate Cst1 and the second plate Cst2 overlap. At the same time, the first plate Cst1 and the second plate Cst2 both overlap with the channel portion of the driving transistor T5. Further, the orthographic projection of the second plate Cst2 on the substrate SU is located within the orthographic projection of the first plate Cst1 on the substrate SU, and the orthographic projection of the channel portion of the driving transistor T5 on the substrate SU is located within the orthographic projection of the shading portion BS on the substrate SU.

[0145] Further, such as Figure 16-Figure 23 As shown, the semiconductor layer SE may include a first semiconductor portion SE1 and a second semiconductor portion SE2 that are spaced apart along the row direction X, and the first semiconductor portion SE1 and the second semiconductor portion SE2 both extend along the column direction Y. The channel portions of the first reset transistor T2 and the write transistor T1 are located in the first semiconductor portion SE1 along the column direction Y; the channel portions of the light emitting control transistor T4, the driving transistor T5, and the second reset transistor T3 are located in the second semiconductor portion SE2 along the column direction Y, and the channel portion of the driving transistor T5 is located between the channel portions of the light emitting control transistor T4 and the second reset transistor T3. The channel portion of the driving transistor T5 protrudes toward both sides of the second semiconductor portion SE2 along the row direction X, so that the width-to-length ratio of the driving transistor T5 is increased, which is beneficial to increase the output current.

[0146] Each transistor can adopt a top gate + bottom gate structure, and the bottom gate and the top gate are connected to achieve equipotential, which is beneficial to improve the stability of the transistor and obtain a good SS (subthreshold swing). The bottom gate of each transistor can be located at the first gate layer GA1, and the top gate of each transistor can be located at the second gate layer GA2. For example:

[0147] like Fig. 22 and Fig.24 , in addition to the second electrode plate Cst2 of the storage capacitor Cst, the first gate layer GA1 also includes a first gate portion G1, a second gate portion G2, a third gate portion G3 and a fourth gate portion G4; the second gate layer GA2 may include a fifth gate portion G5, a sixth gate portion G6, a seventh gate portion G7, an eighth gate portion G8 and a ninth gate portion G9; wherein:

[0148] On the basis that both the first semiconductor portion SE1 and the second semiconductor portion SE2 extend along the column direction Y, the first to ninth gate portions G1 to G9 may extend along the row direction X, and the width in the column direction Y is smaller than the length in the row direction X.

[0149] like Figure 17-Figure 19 As shown, the first gate portion G1 and the fifth gate portion G5 may overlap with the channel portion of the first reset transistor T2, and the first gate portion G1 and the fifth gate portion G5 are connected. The second gate portion G2 and the sixth gate portion G6 may overlap with the channel portion of the write transistor T1, and the second gate portion G2 and the sixth gate portion G6 are connected. The third gate portion G3 and the seventh gate portion G7 may overlap with the channel portion of the light emission control transistor T4, and the third gate portion G3 and the seventh gate portion G7 are connected. The fourth gate portion G4 and the eighth gate portion G8 overlap with the channel portion of the second reset transistor T3, and the fourth gate portion G4 and the eighth gate portion G8 are connected. The ninth gate portion G9 overlaps with the channel portion of the drive transistor T5, and the length of the ninth gate portion G9 in the row direction X is greater than the width of the channel portion of the drive transistor T5 in the row direction X. The orthographic projection of the ninth gate portion G9 on the substrate SU is located within the orthographic projections of the second electrode plate Cst2 and the light shielding portion BS on the substrate SU, and the ninth gate portion G9 serves as the gate of the driving transistor T5.

[0150] like Figure 2 , Figure 10-12 , Fig.25 and Fig.26 As shown, the source-drain layer includes a first source-drain layer SD1 and a second source-drain layer SD2 distributed in a direction away from the substrate SU, the first source-drain layer SD1 is located on a side of the second source-drain layer SD2 away from the substrate SU, and the second source-drain layer SD2 is located on a side of the first source-drain layer SD1 away from the substrate SU. The first reset scan line GL2, the second reset scan line GL3, the write scan line GL1, the light-emitting control line EML, the first reset signal line VRL, the second reset signal line VIL, the first auxiliary power line VDLs and the second auxiliary power line VSLs mentioned above are located in the first source-drain layer SD1. The first power line VDL, the second power line VSL, the data line DAL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs are located in the second source-drain layer SD2.

[0151] Further, such as Fig.10 , 12 and Fig.25 As shown, the first source-drain layer SD1 may further include a first connection portion S1, a second connection portion S2 and a third connection portion S3, wherein:

[0152] The first connection portion S1 can be connected to the second electrode of the first reset transistor T2 and the gate of the driving transistor T5 through contact holes, respectively. For example, one end of the first connection portion S1 can be connected to the area between the channel portion of the first reset transistor T2 and the write transistor T1 in the first semiconductor portion SE1 through a contact hole, and the other end can be connected to the ninth gate portion G9 through a contact hole.

[0153] Further, such as Fig.12 , Fig.14 and Fig.16 As shown, the first connection portion S1 can extend along a straight line, a broken line or a curved trajectory, as long as it can play the aforementioned connection role; for example, the first connection portion S1 may include a first connection segment and a second connection segment, the first connection segment can extend along the row direction X, and be located between the first reset scan line GL2 and the ninth gate portion G9, the second connection segment can extend along the column direction Y, and be located between the first semiconductor portion SE1 and the second semiconductor portion SE2; one end of the first connection segment is connected to the first semiconductor portion SE1 between the channel portion of the first reset transistor T2 and the write transistor T1 through a contact hole, and the other end is connected to one end of the second connection segment, and the other end of the second connection segment is connected to the ninth gate portion G9 through a contact hole.

[0154] like Fig.12 , Fig.15 and Fig.16 As shown, the second connection portion S2 can be connected to the second electrode plate Cst2 and the first electrode of the driving transistor T5 through the contact hole. For example, the second connection portion S2 can extend along the row direction X and be located between the write scan line GL1 and the first connection portion S1, and the orthographic projection on the substrate SU is located between the ninth gate portion G9 and the orthographic projection of the write scan line GL1 on the substrate SU. At the same time, the orthographic projection of the second connection portion S2 on the substrate SU can be located within the orthographic projection of the second electrode plate Cst2 on the substrate SU. The second connection portion S2 is connected to the second semiconductor portion SE2 between the channel portion of the second electrode plate Cst2 and the driving transistor T5 and the second reset transistor T3 through the contact hole, respectively.

[0155] The third connection portion S3 can be connected to the first electrode of the write transistor T1 and the data line DAL through the contact hole, respectively, to realize the transmission of the data signal Data. For example, the third connection portion S3 is located between the second reset scan line GL3 and the second reset signal line VIL, and between the first semiconductor portion SE1 and the second semiconductor portion SE2. The third connection portion S3 is connected to one end of the first semiconductor portion SE1 through the contact hole, and the end is located on the side of the channel portion of the write transistor T1 away from the channel portion of the first reset transistor T2. The third connection portion S3 is also connected to the data line DAL through the contact hole.

[0156] Further, such as Fig.10 , Fig.11 and Fig.26 As shown, the second source-drain layer SD2 may further include a transition portion S4, which may be connected to the first electrode of the driving transistor T5 and the second electrode of the second reset transistor T3. For example, the transition portion S4 may be connected to the second connection portion S2 through a contact hole. At the same time, the transition portion S4 may also be connected to the first electrode ANO of the light-emitting device LD through a contact hole.

[0157] In addition, if Figure 2 As shown, the driving backplane BP may further include a buffer layer BUF of an insulating material, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a first planar layer PLN1 and a second planar layer PLN2, wherein:

[0158] The buffer layer BUF may be disposed on one side of the substrate SU and cover the light shielding layer BSM. The first gate layer GA1 is disposed on the surface of the buffer layer BUF away from the substrate SU; the first gate insulating layer GI1 covers the first gate layer GA1; the semiconductor layer SE is disposed on the surface of the first gate insulating layer GI1 away from the substrate SU; the second gate insulating layer GI2 covers the semiconductor layer SE; the second gate layer GA2 is disposed on the surface of the second gate insulating layer GI2 away from the substrate SU; the interlayer dielectric layer ILD covers the second gate layer GA2, and the interlayer dielectric layer may be a single-layer structure or a multi-layer structure, for example, the interlayer dielectric layer may include a plurality of sub-dielectric layers stacked in sequence; the first source and drain layer S D1 is arranged on the surface of the interlayer dielectric layer ILD away from the substrate SU; the first source and drain layer SD1 can be covered with a passivation layer, and then the passivation layer is covered with the first flat layer PLN1. Of course, the passivation layer can also be omitted, and the first source and drain layer SD1 can be directly covered with the first flat layer PLN1; the second source and drain layer SD2 is arranged on the surface of the first flat layer PLN1 away from the substrate SU; the second flat layer PLN2 covers the second source and drain layer SD2; the first electrode ANO of the light-emitting device LD is arranged on the surface of the second flat layer PLN2 away from the substrate SU, and can be separated by the pixel definition layer PDL.

[0159] Since there are metal oxide transistors in the pixel circuit PC, and metal oxide semiconductors are easily affected by light, resulting in problems such as threshold voltage shift and low photostability, the source and drain layers can be used to at least shield the metal oxide transistors to reduce the light irradiating the metal oxide transistors. Specifically, at least one source and drain layer can be overlapped with the channel portion of at least part of the metal oxide transistors to achieve a light shielding effect and improve the photostability of these transistors.

[0160] For multiple source and drain layers, the pattern of the source and drain layer closest to the semiconductor layer SE can be used for shielding to minimize the illumination of the transistor. However, considering the limitation of the pattern of the same source and drain layer itself, the space available for shielding is limited. Therefore, multiple source and drain layers can be used to shield different metal oxide transistors to reduce the limitation of the pattern of each source and drain layer and avoid problems such as short circuits. The following is an example of the first source and drain layer SD1 and the second source and drain layer SD2 shielding different metal oxide transistors respectively:

[0161] In some embodiments of the present disclosure, Fig.12 , Fig.16 and Fig.25 As shown, the first source-drain layer SD1 can be used to shield the channel portion of the write transistor T1 and the second reset transistor T3. For example:

[0162] The write scan line GL1 overlaps with the channel portion of the write transistor T1, and the second gate portion G2 and the sixth gate portion G6 are staggered in the row direction X. The write scan line GL1 overlaps with the second gate portion G2 and the sixth gate portion G6, and is connected to the second gate portion G2 and the sixth gate portion G6 through contact holes, respectively, and can simultaneously transmit the write scan signal Gate1 to the second gate portion G2 and the sixth gate portion G6, thereby realizing the connection between the second gate portion G2 and the sixth gate portion G6.

[0163] Furthermore, the boundary of the second gate portion G2 and the sixth gate portion G6 in the orthogonal projection of the substrate SU in the column direction Y can be located within the boundary of the write scan line GL1 in the orthogonal projection of the substrate SU in the column direction Y, ensuring that the channel of the write transistor T1 is completely blocked. For example, the write scan line GL1 has a write shielding portion GL11 that protrudes toward both sides along the column direction Y. The width of the write scan line GL1 can be partially increased through the write shielding portion GL11, so that the boundary of the second gate portion G2 and the sixth gate portion G6 in the orthogonal projection of the substrate SU in the column direction Y is located within the boundary of the write shielding portion GL11, thereby eliminating the need to increase the width of the write scan line GL1 as a whole.

[0164] The second reset scan line GL3 overlaps with the channel portion of the second reset transistor T3, the fourth gate portion G4 and the eighth gate portion G8 are staggered in the row direction X, the second reset scan overlaps with the fourth gate portion G4 and the eighth gate portion G8, and is connected to the fourth gate portion G4 and the eighth gate portion G8 through contact holes, respectively, and can simultaneously transmit the second reset scan signal Gate3 to the fourth gate portion G4 and the eighth gate portion G8, and also realizes the connection between the fourth gate portion G4 and the eighth gate portion G8.

[0165] Furthermore, the boundaries of the fourth gate portion G4 and the eighth gate portion G8 in the orthogonal projection of the substrate SU in the column direction Y are located within the boundaries of the second reset scan line GL3 in the orthogonal projection of the substrate SU in the column direction Y, ensuring that the channel of the second reset transistor T3 is completely blocked. For example, the second reset scan line GL3 has a first reset blocking portion GL31 protruding toward both sides along the column direction Y, and the width of the second reset scan line GL3 can be locally increased by the first reset blocking portion GL31, so that the boundaries of the second gate portion G2 and the sixth gate portion G6 in the orthogonal projection of the substrate SU in the column direction Y are located within the boundaries of the write blocking portion GL11 in the orthogonal projection of the substrate SU in the column direction Y, thereby eliminating the need to increase the width of the write scan line GL1 as a whole.

[0166] In the above embodiment, the write transistor T1 and the second reset transistor T3 are blocked by the write scan line GL1 and the second reset scan line GL3. Since the top gate and the bottom gate of the write transistor T1 and the second reset transistor T3 are connected and have the same potential, the write scan line GL1 and the second reset scan line GL3 that transmit signals to the gates of the two will not increase the capacitance at the blocked location.

[0167] In some embodiments of the present disclosure, Fig.11 , Fig.16 and Fig.26 As shown, the second source-drain layer SD2 can be used to shield the channel portions of the first reset transistor T2 and the light emission control transistor T4. For example:

[0168] like Fig.12 , Fig.13 and Fig.16 As shown, the first reset scan line GL2 overlaps with the first gate portion G1 and the fifth gate portion G5; the first gate portion G1 and the fifth gate portion G5 are staggered in the row direction X, the first reset scan line GL2 overlaps with the first gate portion G1 and the fifth gate portion G5, and is connected to the first gate portion G1 and the fifth gate portion G5 through contact holes, respectively, and can simultaneously transmit the first reset scan signal Gate2 to the first gate portion G1 and the fifth gate portion G5, and also realizes the connection between the first gate portion G1 and the fifth gate portion G5.

[0169] Further, the boundary of the first gate portion G1 and the fifth gate portion G5 in the orthogonal projection of the substrate SU in the column direction Y is located within the boundary of one of the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs in the orthogonal projection of the substrate SU in the column direction Y, ensuring that the channel of the first reset transistor T2 is completely blocked. For example, one of the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs has a second reset blocking portion V1 protruding toward both sides along the row direction X, and the width of one of the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs can be locally increased by the second reset blocking portion V1, so that the boundary of the first gate portion G1 and the fifth gate portion G5 in the orthogonal projection of the substrate SU in the column direction Y is located within the boundary of the second reset blocking portion V1 in the orthogonal projection of the substrate SU in the column direction Y, thereby eliminating the need to increase the width of one of the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs as a whole.

[0170] The light emitting control line EML overlaps with the channel portion of the light emitting control transistor T4. The third gate portion G3 and the seventh gate portion G7 are staggered in the row direction X. The light emitting control line EML overlaps with the third gate portion G3 and the seventh gate portion G7, and is connected to the third gate portion G3 and the seventh gate portion G7 through contact holes, respectively, and can simultaneously transmit the light emitting control signal EM to the third gate portion G3 and the seventh gate portion G7, and also realizes the connection between the third gate portion G3 and the seventh gate portion G7.

[0171] Further, the boundary of the third gate portion G3 and the seventh gate portion G7 in the orthogonal projection of the substrate SU in the column direction Y is located within the boundary of the first power line VDL in the orthogonal projection of the substrate SU in the column direction Y. Ensure that the channel of the light-emitting control transistor T4 is completely shielded. For example, the first power line VDL has a power shielding portion VDL1 protruding toward both sides along the row direction X, and the boundary of the third gate portion G3 and the seventh gate portion G7 in the orthogonal projection of the substrate SU in the column direction Y is located within the boundary of the power shielding portion VDL1 in the orthogonal projection of the substrate SU in the column direction Y. The power shielding portion VDL1 can be used to partially increase the width of the first power line VDL so as to shield the third gate portion G3 and the seventh gate portion G7 without increasing the width of the first power line VDL as a whole.

[0172] In some embodiments of the present disclosure, the first power line VDL and the second semiconductor portion SE2 both extend along the column direction Y, and the first power line VDL can be used to shield the second semiconductor portion SE2, so that the first power line VDL overlaps with the channel portions of the second reset transistor T3, the driving transistor T5 and the light emitting control transistor T4 at the same time.

[0173] Further, such as Fig.11 and Fig.28 As shown, the boundary of at least a portion of the second semiconductor portion SE2 in the orthographic projection of the substrate SU in the row direction X can be located within the boundary of the orthographic projection of the first power line VDL in the substrate SU in the row direction X, thereby increasing the shielding range and reducing the light irradiated to the second semiconductor portion SE2. For example, the boundary of at least a portion of the second semiconductor portion SE2 in the orthographic projection of the substrate SU in the row direction X is taken as the first boundary, and the boundary of the orthographic projection of the first power line VDL in the substrate SU in the row direction X is taken as the second boundary. The first boundary is located inside the second boundary, and the distance L between the first boundary and the second boundary is less than 2μm. Furthermore, the distance L between the first boundary and the second boundary can be made less than 1μm, thereby ensuring the shielding effect while avoiding the width of the first power line VDL being too large and interfering with other wiring. Of course, the first boundary and the second boundary can also overlap, as long as the first boundary is not located outside the first boundary.

[0174] The first boundary mentioned above may at least include a portion of the second semiconductor portion SE2 between the channel portion of the light emission control transistor T4 and the channel portion of the driving transistor T5, and a portion between the channel portion of the driving transistor T5 and the channel portion of the second reset transistor T3, the boundary of the positive projection on the substrate SU. In order to ensure the width-to-length ratio of the channel of the driving transistor T5, the boundary of the positive projection of the channel portion of the driving transistor T5 on the substrate SU in the row direction X may be located outside the boundary of the positive projection of the first power line VDL on the substrate SU in the row direction X.

[0175] The channel portion of the driving transistor T5 can be shielded by the first source-drain layer SD1, but the first source-drain layer SD1 is close to the driving transistor T5, and it is easy to generate a large parasitic capacitance. Therefore, the second source-drain layer SD2 can be used for setting, for example, so that the positive projection of the channel portion of the driving transistor T5 on the substrate SU is located within the positive projection of the first power line VDL on the substrate SU. Specifically, it can be achieved by increasing the overall or partial line width of the first power line VDL. However, in order to avoid a short circuit between the first power line VDL and the data line DAL, the channel portion of the driving transistor T5 can also be shielded by the first electrode ANO, thereby reducing light exposure. Of course, the first electrode ANO is not limited to shielding only the driving transistor T5, and can also shield other metal oxide transistors. The following is an example of shielding the driving transistor T5:

[0176] In some embodiments of the present disclosure, Fig.10 and Fig.16As shown, a first electrode ANO can be overlapped with at least a channel portion of a driving transistor T5, and further, the orthographic projection of the channel portion on the substrate SU can be within the orthographic projection of the first electrode ANO on the substrate SU, so that light shielding is performed by the first electrode ANO. The first electrode ANO can adopt a single-layer or multi-layer structure, and its material can include metals or alloys such as aluminum and titanium, as long as it can shield light and conduct electricity.

[0177] Further, in some embodiments of the present disclosure, Fig.10 and Fig. 27 As shown, the first electrode ANO may include an electrode body A1 and a connection extension A2 connected to the edge of the electrode body A1, and a connection extension A2 is connected to the first electrode of a driving transistor T5 through a contact hole. The boundary of the positive projection of the pixel opening PH on the substrate SU may be located within the boundary of the electrode body A1 of the first electrode ANO exposed by the pixel opening PH, and the electrode body A1 in the pixel opening PH is stacked with the light-emitting layer to form a light-emitting device, while the pixel definition layer PDL is stacked on the first electrode ANO in the area outside the pixel opening PH. By connecting the connection extension A2 to the contact hole, the electrode body A1 can be kept flat, in particular, the electrode body A1 in the pixel opening PH can be kept flat without connecting the contact hole, thereby preventing the contact hole from affecting the light emission of the light-emitting device.

[0178] In some embodiments of the present disclosure, Fig.10 and Fig. 27 As shown, the channel portion of the driving transistor T5 can be shielded by increasing the area of ​​the first electrode ANO, but the number of first electrodes ANO is large and the space is limited. Therefore, the channel portion of the driving transistor T5 can be shielded by partially extending the first electrode ANO outward to increase the area. Specifically, at least a portion of the first electrode ANO may also include a shielding extension portion A3 connected to the edge of the electrode body A1, and the shielding extension portion A3 may overlap with the channel portion of the driving transistor T5. For example, the orthographic projection of at least a portion of the channel portion of the driving transistor T5 on the substrate SU can be located within the orthographic projection of the shielding extension portion A3 on the substrate SU, thereby improving the shading effect.

[0179] Furthermore, at least a portion of the first electrode ANO can overlap with the channel portions of multiple driving transistors T5 at the same time, that is, one first electrode ANO can block the channel portions of multiple driving transistors T5 at the same time. For one first electrode ANO and the channel portions of multiple driving transistors T5 blocked by it, the blocking extension A3 can block part of the channel portion, the electrode body A1 can also block part of the channel portion, and the connecting extension A2 can also block part of the channel portion, that is, any area of ​​the first electrode ANO can block the channel portion.

[0180] In some embodiments of the present disclosure, the light-emitting device may include a first light-emitting device, a second light-emitting device, and a third light-emitting device having different light-emitting colors. The area of ​​the first electrode ANO of the first light-emitting device is larger than the area of ​​the first electrode ANO of the second light-emitting device and the third light-emitting device. For example, the first light-emitting device may emit blue light, the second light-emitting device may emit red light, and the third light-emitting device may emit green light. The first electrode ANO of the first light-emitting device may overlap with the channel portion of the driving transistor T5 to achieve shielding. At the same time, the second light-emitting device and the third light-emitting device may be distributed along the row direction X, and the second light-emitting device and the third light-emitting device may be distributed as a whole with the first light-emitting device along the column direction Y. The first electrode ANO of a first light-emitting device LD1 may simultaneously shield the channel portions of the driving transistor T5 of 2, 3 or more pixel circuits PC distributed along the row direction X.

[0181] In other embodiments of the present disclosure, Fig.16 and Fig.30 As shown, the first electrodes ANO of the first light-emitting device, the second light-emitting device and the third light-emitting device can be provided with a shielding extension A3, and the shielding extension A3 of the first electrode ANO of the first light-emitting device can shield the channel of the driving transistor T5; and the shielding extension A3 of the second light-emitting device can shield the channel of the writing transistor T1, and the shielding extension A3 of the third light-emitting device can shield the channel of the second reset transistor T3. Of course, the positions of the second light-emitting device and the third light-emitting device can be interchanged. Making full use of the first electrode ANO to shield the channel of the transistor can minimize the influence of light on the transistor.

[0182] It should be noted that, in the above embodiment, the first electrode ANO blocks the channel portion of the driving transistor T5, but this does not mean that the first electrode ANO only overlaps with the channel portion of the driving transistor T5, and the first electrode ANO may also overlap with the channel of other transistors. At the same time, the first electrode ANO that overlaps with the channel of the transistor is not limited to the first light-emitting device, but may also be the second light-emitting device and the third light-emitting device.

[0183] In some embodiments of the present disclosure, the second source-drain layer SD2 may be used to shield the channels of the write transistor T1 and the second reset transistor T3. Fig.29As shown, the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs can be provided with a first routing shielding portion B1 protruding along the row direction X, and the first routing shielding portion B1 at least partially overlaps with the channel of the write transistor T1, so that the first routing shielding portion B1 is used to shield the channel of the write transistor T1, thereby reducing the influence of light. At the same time, the first power line VDL can be provided with a second routing shielding portion B2 protruding along the row direction X, and the second routing shielding portion B2 at least partially overlaps with the channel of the second reset transistor T3, so that the second routing shielding portion B2 is used to shield the channel of the second reset transistor T3, thereby reducing the influence of light. Of course, the second power line VSL, the first auxiliary reset line VRLs, the second auxiliary reset line VILs and the first power line VDL can also be widened as a whole, as long as it does not cause a short circuit between the routings.

[0184] It should be noted that if Fig.10 , Fig.12 , Fig.29 and Fig.30 As shown, the second reset transistor T3 and the write transistor T1 can be shielded by the first reset shielding portion GL31 and the write shielding portion GL11 mentioned above, or by the above-mentioned shielding extension portion A3 and the first wiring shielding portion B1 and the second wiring shielding portion B2, that is, shielding by using the first source and drain layer SD1, the second source and drain layer SD2 and the first electrode ANO. The above-mentioned methods can be used simultaneously, that is, the first source and drain layer SD1, the second source and drain layer SD2 and the first electrode ANO are used for shielding at the same time; or a single layer can be used for shielding, or any two layers can be used in combination, as long as the second reset transistor T3 and the write transistor T1 can be shielded, for example, only one of the first source and drain layer SD1, the second source and drain layer SD2 and the first electrode ANO is used for shielding; or, by shielding the first source and drain layer SD1 and the second source and drain layer SD2, the first electrode ANO may not have the shielding extension A3; or, by shielding the first source and drain layer SD1 and the first electrode ANO, the second source and drain layer SD2 may not have the first routing shielding portion B1 and the second routing shielding portion B2; in addition, the second reset transistor T3 and the write transistor T1 may also be shielded by different film layers, for example, the second reset transistor T3 is shielded by the shielding extension A3 and the first reset shielding portion GL31, while the write transistor T1 can be shielded by the write shielding portion GL11 and the first routing shielding portion B1. The shielding methods for the second reset transistor T3 and the write transistor T1 are not listed one by one here.

[0185] In addition, compared with the first source and drain layer SD1, the second source and drain layer SD2 and the first electrode ANO are farther away from the second gate layer GA2, so that the parasitic capacitance between the first wiring shielding portion B1, the second wiring shielding portion B2 and the shielding extension portion A3 and the second gate layer GA2 is smaller. However, in order to improve the shading effect, the boundaries of the orthographic projections of the first wiring shielding portion B1, the second wiring shielding portion B2 and the shielding extension portion A3 on the substrate SU can be at least partially located outside the boundaries of the orthographic projections of the channels of the transistors they shield on the substrate SU, and the distance between the boundaries is not less than 2μm, for example, 2μm~5um, so as to ensure the shading effect while avoiding interference with other structures.

[0186] The present disclosure also provides a display device, which may include a display panel of any of the above embodiments. The display panel is a display panel of any of the above embodiments, and its specific structure and beneficial effects can be referred to the embodiments of the display panel above, which will not be repeated here. The display device of the present disclosure can be an electronic device such as a mobile phone, a tablet computer, a television, or a wearable device with an image display function such as a smart watch, a virtual reality device, an augmented reality device, or other electronic devices with a display function such as a vehicle-mounted display device, which will not be listed one by one here.

[0187] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that: include: A driving backplane, comprising a plurality of pixel circuits arranged in an array along row and column directions, wherein the pixel circuits comprise a plurality of transistors, and the transistors in any of the pixel circuits comprise a driving transistor; the driving transistor and at least some of the other transistors in any of the pixel circuits are metal oxide transistors; the driving backplane comprises a substrate, a semiconductor layer and at least one source-drain layer arranged in a direction away from the substrate; the channel portions of at least some of the transistors are located in the semiconductor layer; the source-drain layer overlaps with the channel portions of at least some of the metal oxide transistors; The light emitting device is arranged on one side of the driving backplane and comprises a first electrode, a light emitting layer and a second electrode distributed in a direction away from the driving backplane; the first electrode of the driving transistor is connected to the first electrode of the light emitting device.

2. The display panel according to claim 1, characterized in that: The pixel circuit further includes a storage capacitor, and the transistor of the pixel circuit further includes a first reset circuit, a second reset circuit, a write circuit and a light emitting control circuit; The first reset circuit is connected to the gate of the driving transistor and is used to transmit a first reset signal in response to a first reset scan signal; the second reset circuit is connected to the first electrode of the driving transistor and is used to transmit a second reset signal in response to a second reset scan signal; the write circuit is connected to the gate of the driving transistor and is used to transmit a data signal in response to a write scan signal; the light-emitting control circuit is used to receive a first power supply signal and is connected to the second electrode of the driving transistor, and is used to be turned on in response to a light-emitting control signal; the storage capacitor is connected to the gate and the first electrode of the driving transistor.

3. The display panel according to claim 2, characterized in that: The driving backplane further includes a first power line and a data line extending in the column direction, and a first reset scan line, a second reset scan line, a write scan line, a light emitting control line, a first reset signal line, and a second reset signal line extending in the row direction; The first reset circuit includes a first reset transistor, the second reset circuit includes a second reset transistor, the write circuit includes a write transistor, and the light emitting control circuit includes a light emitting control transistor; each of the transistors in the pixel circuit is a metal oxide transistor; The first reset scan line is connected to the gate of the first reset transistor and is used to transmit the first reset scan signal; The first reset signal line is connected to the gate of the driving transistor through the first reset transistor, and is used for transmitting the first reset signal; The second reset scan line is connected to the gate of the second reset transistor and is used for transmitting the second reset scan signal; The second reset signal line is connected to the first electrode of the driving transistor through the second reset transistor, and is used for transmitting the second reset signal; The first power line is connected to the second electrode of the driving transistor through the light emitting control transistor, and is used to transmit the first power signal; The write scan line is connected to the gate of the write transistor for transmitting the write scan signal; the data line is connected to the gate of the drive transistor through the write transistor for transmitting the data signal; The light emitting control line is connected to the gate of the light emitting control transistor and is used for transmitting the light emitting control signal.

4. The display panel according to claim 3, characterized in that: The driving backplane further comprises a second power line extending in the column direction and a first auxiliary power line and a second auxiliary power line extending in the row direction; The first auxiliary power line and the first power line are located in different layers and are connected through a contact hole; The second power line and the second auxiliary power line are located in different layers and are connected through a contact hole; the second power line is connected to the second electrode for transmitting a second power signal.

5. The display panel according to claim 4, characterized in that: The driving backplane further includes a first auxiliary reset line extending along the column direction. The first auxiliary reset line and the first reset signal line are located in different layers and are connected through a contact hole.

6. The display panel according to claim 5, characterized in that: The driving backplane further includes a second auxiliary reset line extending along the column direction, wherein the second auxiliary reset line and the second reset signal line are located in different layers and are connected through a contact hole.

7. The display panel according to claim 6, characterized in that: One of the data lines is connected to a write transistor of a column of the pixel circuit; one of the first power lines is connected to a light emitting control transistor of a column of the pixel circuit; The data lines and the first power lines connected to the same column of pixel circuits are defined as a column line group, and between two adjacent column line groups there is provided the second power line, one of the first auxiliary reset line and the second auxiliary reset line.

8. The display panel according to claim 5, characterized in that: A row of the pixel circuits is simultaneously connected to a first reset scan line, a second reset scan line, a write scan line, a light emitting control line, a first reset signal line, and a second reset signal line; The first reset scan line, the second reset scan line, the write scan line, the light emission control line, the first reset signal line and the second reset signal line connected to the pixel circuits in the same row are defined as a row line group; A first auxiliary power line and a second auxiliary power line are disposed between two adjacent row line groups.

9. The display panel according to claim 6, characterized in that: The source-drain layer comprises a first source-drain layer and a second source-drain layer distributed in a direction away from the substrate; Channel portions of the write transistor and the second reset transistor overlap with the first source-drain layer; channel portions of the first reset transistor and the light emission control transistor overlap with the second source-drain layer.

10. The display panel according to claim 9, characterized in that: The semiconductor layer includes a first semiconductor portion and a second semiconductor portion spaced apart along the row direction, and the first semiconductor portion and the second semiconductor portion extend along the row direction; The channel portions of the first reset transistor and the write transistor are located in the first semiconductor portion along the column direction; The channel portions of the light emission control transistor, the drive transistor and the second reset transistor are located in the second semiconductor portion along the column direction; A channel portion of the write transistor overlaps with one of the write scan lines; a channel portion of the second reset transistor overlaps with one of the second reset scan lines; The first power line overlaps with channel portions of the second reset transistor, the drive transistor, and the light emission control transistor.

11. The display panel according to claim 10, characterized in that: At least a portion of the second semiconductor portion has a boundary of an orthographic projection of the substrate in the row direction located within a boundary of an orthographic projection of the first power line in the row direction.

12. The display panel according to claim 11, characterized in that: The boundary of at least a portion of the second semiconductor portion in the row direction of the orthographic projection of the substrate is taken as a first boundary, and the boundary of the first power line in the row direction of the orthographic projection of the substrate is taken as a second boundary; The first boundary is located inside the second boundary, and a distance between the first boundary and the second boundary is less than 2 μm.

13. The display panel according to claim 9, characterized in that: The first reset scan line, the second reset scan line, the write scan line, the light emitting control line, the first reset signal line, the second reset signal line, the first auxiliary power line and the second auxiliary power line are located in the first source-drain layer; The first power line, the second power line, the data line, the first auxiliary reset line and the second auxiliary reset line are located in the second source-drain layer.

14. The display panel according to claim 13, characterized in that: The driving backplane also includes: A light shielding layer is provided on one side of the substrate and includes a light shielding portion; the semiconductor layer is provided on a side of the light shielding layer away from the substrate, the light shielding portion overlaps with the channel portion of the driving transistor, and the light shielding portion is reused as a first plate of the storage capacitor; A first gate layer is provided on a side of the light shielding layer away from the substrate and includes a second electrode plate of the storage capacitor; the semiconductor layer is provided on a side of the first gate layer away from the substrate, and the first electrode plate overlaps with a channel portion of the driving transistor; The second gate layer is arranged on a side of the semiconductor layer away from the substrate and overlaps with the channel portion of the driving transistor; the first source and drain layer is arranged on a side of the second gate layer away from the substrate.

15. The display panel according to claim 14, characterized in that: The first gate layer further includes a first gate portion, a second gate portion, a third gate portion and a fourth gate portion; the second gate layer includes a fifth gate portion, a sixth gate portion, a seventh gate portion, an eighth gate portion and a ninth gate portion; The first gate portion and the fifth gate portion overlap with the channel portion of the first reset transistor, and the first gate portion and the fifth gate portion are connected; The second gate portion and the sixth gate portion overlap with the channel portion of the write transistor, and the second gate portion and the sixth gate portion are connected; The third gate portion and the seventh gate portion overlap with the channel portion of the light emission control transistor, and the third gate portion and the seventh gate portion are connected; The fourth gate portion and the eighth gate portion overlap with the channel portion of the second reset transistor, and the fourth gate portion and the eighth gate portion are connected; The ninth gate portion overlaps with a channel portion of the driving transistor.

16. The display panel according to claim 15, characterized in that: The boundary of the first gate portion and the fifth gate portion in the column direction of the orthogonal projection of the substrate is located within the boundary of the orthogonal projection of one of the second power line, the first auxiliary reset line and the second auxiliary reset line in the column direction of the substrate; and the first gate portion and the fifth gate portion are connected to the first reset scan line; The boundary between the orthographic projection of the third gate portion and the seventh gate portion in the column direction of the substrate is located within the boundary of the orthographic projection of the first power line in the column direction of the substrate; and the third gate portion and the seventh gate portion are connected to the light emitting control line; The boundary of the orthogonal projection of the second gate portion and the sixth gate portion in the column direction of the substrate is located within the boundary of the orthogonal projection of the write scan line in the column direction of the substrate; and the second gate portion and the sixth gate portion are connected to the first reset scan line; The boundary of the fourth gate portion and the eighth gate portion in the column direction of the orthographic projection of the substrate is located within the boundary of the orthographic projection of the substrate in the column direction; and the fourth gate portion and the eighth gate portion are connected to the second reset scan line.

17. The display panel according to any one of claims 2 to 16, characterized in that: A first electrode at least overlaps with a channel portion of the driving transistor.

18. The display panel according to claim 17, characterized in that: The first electrode comprises an electrode body and an extension portion connected to an edge of the electrode body, wherein the extension portion is connected to a first electrode of the driving transistor; At least a portion of the first electrode further includes an extension portion connected to an edge of the electrode body, and the extension portion overlaps with a channel portion of the driving transistor; The display panel further includes: The pixel definition layer is arranged on the same side of the driving backplane as the light-emitting device and has a pixel opening exposing each of the first electrodes; the boundary of the positive projection of the pixel opening on the substrate is located within the boundary of the electrode body of the exposed first electrode.

19. The display panel according to claim 17, characterized in that: At least a portion of the first electrode overlaps with channel portions of a plurality of the driving transistors at the same time.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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