Multi-level task synchronization method based on three-level cache distribution of processor and related device

Abstract

The invention provides a multi-level task synchronization method based on three-level cache distribution of a processor and a related device. The multi-level task synchronization method comprises the steps of determining a core needing task synchronization and a three-level cache needing task synchronization in each three-level cache of the processor; according to the number of the cores needing task synchronization and the number of the third-level caches, a first-level synchronizer and a second-level synchronizer are initialized respectively; and performing task synchronization among the cores and among the three-level caches by using the first-level synchronizer and the second-level synchronizer respectively until all the three-level caches needing task synchronization are synchronized, and then completing the synchronization of the cores in each three-level cache. By optimizing the hierarchical structure and task distribution of the three-level cache of the processor, the synchronization efficiency among multiple cores and the system performance are remarkably improved. By means of the multi-level synchronizer mechanism, synchronization time delay and resource consumption are effectively reduced, and stability and reliability of the system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of inter-core synchronization of multi-core processors, and in particular relates to a multi-level task synchronization method and related devices based on processor three-level cache distribution. Background Art

[0002] Electromagnetic transient simulation is a complex computational process, which requires extremely high computing power and data processing capabilities, especially when dealing with large-scale power grid models. In order to meet this demand, large power grid models are usually split into multiple subnets, each of which is responsible for simulation operations by one or more processor cores. However, this split method also brings problems with task synchronization and data consistency.

[0003] In the multi-core simulation process, each processor core is responsible for processing different subnets, but these subnets need to maintain data consistency and synchronization. Especially in electromagnetic transient simulation, the interaction and synchronization between subnets are the key to ensuring the accuracy of simulation results. Therefore, how to efficiently achieve task synchronization between multiple cores has become an urgent problem to be solved.

[0004] In processor architectures with multiple L3 caches, the task synchronization mechanism faces cache consistency operations triggered by shared read and write of data across the L3 caches, which may indeed lead to large performance losses, especially for complex applications such as electromagnetic transient simulation that need to run efficiently. In order to meet this challenge, in addition to traditional synchronization primitives such as mutexes and reader-writer locks, a more efficient task synchronization mechanism is also needed to meet the needs of applications such as electromagnetic transient simulation. Summary of the invention

[0005] In view of this, the present invention provides a multi-level task synchronization method and related devices based on processor three-level cache distribution, aiming to utilize the hierarchical structure and distribution characteristics of the processor three-level cache to achieve efficient synchronization between multiple cores by optimizing task allocation and cache management.

[0006] In order to achieve the above object, the technical solution provided by the present invention is as follows:

[0007] In a first aspect, the present invention provides a multi-level task synchronization method based on processor three-level cache distribution, comprising the following steps:

[0008] Determine the core that needs to perform task synchronization and the third-level cache that needs to perform task synchronization in each third-level cache of the processor;

[0009] Initialize the first-level synchronizer and the second-level synchronizer respectively according to the number of cores and the number of third-level caches that need to perform task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the core and the third-level cache respectively.

[0010] The first-level synchronizer and the second-level synchronizer are used to synchronize tasks between cores and between the third-level caches respectively. After all the third-level caches that need to synchronize tasks have completed synchronization, the cores in each third-level cache complete synchronization.

[0011] Furthermore, the core within each L3 cache of the processor is a L1 communication domain, and all L3 caches are L2 communication domains;

[0012] After determining the cores and the three-level caches that need to be synchronized in each three-level cache of the processor, it also includes:

[0013] Each core that needs to synchronize tasks in the first-level communication domain is required to hold a first-level synchronizer corresponding to its third-level cache;

[0014] Each L3 cache that needs to synchronize tasks in the L2 communication domain holds a global L2 synchronizer.

[0015] Furthermore, the first-level synchronizer and the second-level synchronizer are used to synchronize tasks between cores and between the third-level caches, including:

[0016] Using the second-level synchronizer, task synchronization between the third-level caches is started in the second-level communication domain;

[0017] Repeat the synchronization between the three-level caches according to the number of the three-level caches that need to be synchronized and the number of synchronizations in the second-level communication domain until the synchronization task of the second-level communication domain is completed;

[0018] Use the first-level synchronizer to synchronize tasks between cores in the first-level communication domain;

[0019] The inter-core task synchronization is repeated according to the number of cores that need to perform task synchronization and the number of synchronizations in the primary communication domain until the synchronization task of the primary communication domain is completed.

[0020] Further, the primary synchronizer and the secondary synchronizer each include: an expected synchronization quantity, a synchronization counter, and an upper synchronizer;

[0021] In the first-level synchronizer, the expected number of synchronizations is the number of cores in the third-level cache that need to synchronize tasks. The initial value of the synchronization counter is the expected number of synchronizations and the value of the synchronization counter is reduced by 1 each time synchronization is performed. The upper-level synchronizer is the second-level synchronizer.

[0022] In the secondary synchronizer, the expected number of synchronizations is the number of all the third-level caches that need to perform task synchronization, the initial count value of the synchronization counter is the expected number of synchronizations, and the upper synchronizer is empty.

[0023] Furthermore, the second-level synchronizer is used to synchronize tasks between the three-level caches until all the three-level caches that need to synchronize tasks have completed synchronization, including:

[0024] Each secondary synchronizer performs a synchronization and obtains the decremented synchronization counter value;

[0025] Determine whether the value of the synchronous counter after decrement is equal to zero;

[0026] If it is zero, execute the following steps:

[0027] Set the synchronization counter value to the expected number of synchronizations;

[0028] If it is not equal to zero, perform the following steps:

[0029] Busy waiting for set time;

[0030] Determine whether the synchronization counter value is equal to the expected synchronization number;

[0031] If not, the synchronization is continued using the secondary synchronizer until the synchronization counter value is equal to zero;

[0032] If yes, the synchronization is terminated and the first set synchronization status code is returned.

[0033] Furthermore, a first-level synchronizer is used to synchronize tasks between cores until all cores that need to synchronize tasks have completed synchronization, including:

[0034] Each first-level synchronizer performs a synchronization and obtains the decremented synchronization counter value;

[0035] Determine whether the value of the synchronous counter after decrement is equal to zero;

[0036] If it is zero, execute the following steps:

[0037] Wait for the secondary synchronizer to complete synchronization;

[0038] Set the synchronization counter value to the expected synchronization number, end the synchronization and return the second set synchronization status code;

[0039] If it is not equal to zero, perform the following steps:

[0040] Busy waiting for set time;

[0041] Determine whether the synchronization counter value is equal to the expected synchronization number;

[0042] If not, the synchronization is continued using the secondary synchronizer;

[0043] If yes, the synchronization is terminated and the first set synchronization status code is returned.

[0044] Furthermore, the synchronous counter is decremented by an atomic minus-1 operation.

[0045] In a second aspect, the present invention provides a multi-level task synchronization device based on processor three-level cache distribution, comprising:

[0046] A synchronization acquisition module, used to determine the cores and the third-level caches that need to be synchronized with the tasks in each third-level cache of the processor;

[0047] An initialization module is used to initialize the first-level synchronizer and the second-level synchronizer according to the number of cores and the number of third-level caches that need to perform task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the core and the third-level cache respectively;

[0048] The synchronous execution module is used to synchronize tasks between cores and between L3 caches using the L1 synchronizer and L2 synchronizer respectively, until all L3 caches that need to synchronize tasks have completed synchronization, and then the cores in each L3 cache complete synchronization.

[0049] In a third aspect, the present invention provides a computer device, the device comprising a processor and a memory:

[0050] The memory is used to store the computer program and send the instructions of the computer program to the processor;

[0051] The processor executes a multi-level task synchronization method based on processor three-level cache distribution as described in the first aspect according to the instructions of the computer program.

[0052] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, a multi-level task synchronization method based on a processor three-level cache distribution as in the first aspect is implemented.

[0053] In summary, the present invention provides a multi-level task synchronization method and related device based on the distribution of processor three-level cache, including determining the cores that need to perform task synchronization and the three-level caches that need to perform task synchronization in each three-level cache of the processor; initializing the first-level synchronizer and the second-level synchronizer respectively according to the number of cores and the number of three-level caches that need to perform task synchronization, and the first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the core and the three-level cache respectively; using the first-level synchronizer and the second-level synchronizer to perform task synchronization between cores and between three-level caches respectively, until all three-level caches that need to perform task synchronization have completed synchronization, and then the cores in each three-level cache complete synchronization. The present invention significantly improves the synchronization efficiency and system performance between multiple cores by optimizing the hierarchical structure and task allocation of the processor's three-level cache. Utilizing the multi-level synchronizer mechanism, the present invention effectively reduces synchronization delay and resource consumption, and improves the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 A flowchart of a multi-level task synchronization method based on processor three-level cache distribution provided by an embodiment of the present invention;

[0056] Figure 2 A schematic diagram of the relationship between a synchronous core and a synchronous three-level cache provided in an embodiment of the present invention;

[0057] Figure 3 A schematic diagram of synchronizer initialization provided by an embodiment of the present invention;

[0058] Figure 4 A flowchart of synchronization performed by a synchronizer provided in an embodiment of the present invention;

[0059] Figure 5 A block diagram of a multi-level task synchronization device based on processor three-level cache distribution provided by an embodiment of the present invention;

[0060] Figure 6 A block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] See also Figure 1 The present invention provides a multi-level task synchronization method based on processor three-level cache distribution, comprising the following steps:

[0063] S11: Determine the core that needs to perform task synchronization and the third-level cache that needs to perform task synchronization in each third-level cache of the processor.

[0064] It should be noted that the third-level cache (L3 Cache) is a type of processor cache, located between the CPU and the main memory. It is used to store frequently accessed data to reduce the number of times the processor accesses the main memory and increase data processing speed.

[0065] A core is an independent processing unit of the third-level cache in a multi-core processor that can execute tasks independently.

[0066] This step aims to identify all cores and L3 caches in the processor that need task synchronization. For each set of cores corresponding to the L3 cache, analyze and determine the number of cores that need task synchronization; then, based on these analysis results, count the total number of L3 caches that need task synchronization in the entire system, which can reduce unnecessary synchronization operations and improve efficiency.

[0067] See also Figure 2 , Figure 2 The relationship between the synchronous core and the synchronous L3 cache is shown. The numbers of synchronous cores of different L3 caches are 3, 4 and 0 respectively, so the number of synchronous L3 caches is 2.

[0068] S12: Initializing the first-level synchronizer and the second-level synchronizer respectively according to the number of cores and the number of third-level caches that need to perform task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the cores and the third-level cache respectively.

[0069] It should be noted that the first-level synchronizer is used for the synchronization mechanism between cores to ensure that multiple cores can coordinate and execute tasks. The second-level synchronizer is used for the synchronization mechanism between the three-level caches to ensure data consistency in different cache areas.

[0070] This step configures the L1 and L2 synchronizers according to the number of cores and L3 caches that need to be synchronized. The L1 synchronizer is responsible for synchronization between cores, while the L2 synchronizer is responsible for synchronization between L3 caches. This design allows the system to be optimized at different levels to adapt to different synchronization requirements.

[0071] S13: Use the first-level synchronizer and the second-level synchronizer to perform task synchronization between cores and between the third-level caches respectively, until all the third-level caches that need to perform task synchronization have completed synchronization, and then the cores in each third-level cache complete synchronization.

[0072] It should be noted that this step uses the first-level synchronizer to ensure synchronization between cores, and the second-level synchronizer to ensure synchronization between the three-level caches. This process will continue until all the three-level caches that need to be synchronized have completed synchronization. Once the cache synchronization is completed, the cores in each three-level cache will complete the synchronization between them.

[0073] This step implements a hierarchical synchronization strategy, which is to synchronize at the cache level first and then at the core level. This hierarchical synchronization strategy can reduce direct communication between cores and reduce synchronization latency, while ensuring data consistency and system stability.

[0074] This embodiment provides a multi-level task synchronization method based on processor three-level cache distribution, which proposes a multi-level synchronizer mechanism to reduce synchronization delay and resource consumption. The multi-level synchronizer includes a first-level synchronizer and a second-level synchronizer, which are responsible for synchronization between cores and between three-level caches respectively. The introduction of this mechanism allows synchronization operations to be performed at different levels, thereby improving synchronization efficiency.

[0075] The cooperation of the first-level synchronizer and the second-level synchronizer is the key to achieving efficient synchronization. The first-level synchronizer ensures synchronization between cores, while the second-level synchronizer ensures synchronization between the three-level caches. This hierarchical synchronization strategy allows the system to synchronize at the cache level first, which can reduce direct communication between cores and reduce synchronization latency. Once the cache-level synchronization is completed, the core-level synchronization will follow up to ensure that each core in the three-level cache can complete the synchronization.

[0076] Through the above optimization and multi-level synchronizer mechanism, the method proposed in this embodiment significantly improves the synchronization efficiency between multiple cores. The improvement of synchronization efficiency directly leads to the improvement of system performance, because synchronization operation is one of the key bottlenecks in multi-core processors. By reducing synchronization delay and resource consumption, the system can perform multi-tasking more efficiently, thereby improving the overall system performance and reliability.

[0077] In one embodiment, the core in each L3 cache of the processor is a L1 communication domain, and all L3 caches are L2 communication domains; after determining the core that needs to perform task synchronization and the L3 cache that needs to perform task synchronization in each L3 cache of the processor, the method further includes:

[0078] Each core that needs to synchronize tasks in the first-level communication domain is required to hold a first-level synchronizer corresponding to its third-level cache;

[0079] Each L3 cache that needs to synchronize tasks in the L2 communication domain holds a global L2 synchronizer.

[0080] In this embodiment, the cores in each L3 cache are defined as a level 1 communication domain, and all cores in the same L3 cache need to communicate and synchronize with each other. All L3 caches are defined as a level 2 communication domain, and different L3 caches need to communicate and synchronize with each other.

[0081] Each core that needs to synchronize tasks will hold a first-level synchronizer corresponding to its third-level cache. That is, in a third-level cache, if there are two cores that need to synchronize, then the two cores will each hold a first-level synchronizer for synchronization between them.

[0082] Each L3 cache that needs task synchronization will hold a global L2 synchronizer. That is, among all L3 caches, if there are three L3 caches that need synchronization, then these three L3 caches will each hold a L2 synchronizer for synchronization between them.

[0083] In the first-level communication domain, that is, in each L3 cache, the cores holding the first-level synchronizers will use these synchronizers to coordinate the task synchronization between them. This ensures that the cores in the same L3 cache can execute tasks in a coordinated manner. In the second-level communication domain, that is, between all L3 caches, the L3 cache holding the global second-level synchronizer will use these synchronizers to coordinate the task synchronization between them. This ensures data consistency and task coordination between different L3 caches.

[0084] This embodiment defines communication domains at different levels, organizes the cores in the same L3 cache into a L1 communication domain, improves the synchronization efficiency in the L1 communication domain, organizes the L3 cache into objects into a L2 communication domain, and reduces the number of synchronizations across the L3 cache. A dedicated synchronizer is also allocated to each core and L3 cache that needs to be synchronized, thereby achieving high efficiency and stability of task synchronization in a multi-core processor.

[0085] Based on the setting of the communication domain in the above embodiment, in a further embodiment, the first-level synchronizer and the second-level synchronizer are used to perform task synchronization between cores and between the third-level caches, respectively, including:

[0086] S21: Start task synchronization between the three-level caches in the second-level communication domain using the second-level synchronizer.

[0087] S22: Repeat the synchronization between the three-level caches according to the number of the three-level caches that need to perform task synchronization and the number of synchronizations in the secondary communication domain until the synchronization task of the secondary communication domain is completed;

[0088] S23: Use the first-level synchronizer to synchronize tasks between cores in the first-level communication domain;

[0089] S24: Repeat the inter-core task synchronization according to the number of cores that need to perform task synchronization and the number of synchronizations in the primary communication domain until the synchronization task of the primary communication domain is completed.

[0090] This embodiment implements synchronization operations at different levels by using the first-level synchronizer and the second-level synchronizer in a hierarchical manner. First, synchronization is performed between the three-level caches to ensure data consistency in different cache areas, and then synchronization is performed between the cores to ensure data consistency in different cores in the same cache. This method not only improves synchronization efficiency, but also ensures the stability and reliability of the system, which has important practical significance for parallel task processing in multi-core processors.

[0091] In one embodiment, the primary synchronizer and the secondary synchronizer each include: an expected synchronization quantity, a synchronization counter, and an upper synchronizer;

[0092] In the first-level synchronizer, the expected number of synchronizations is the number of cores in the third-level cache that need to synchronize tasks. The initial value of the synchronization counter is the expected number of synchronizations and the value of the synchronization counter is reduced by 1 each time synchronization is performed. The upper-level synchronizer is the second-level synchronizer.

[0093] In the secondary synchronizer, the expected number of synchronizations is the number of all the third-level caches that need to perform task synchronization, the initial count value of the synchronization counter is the expected number of synchronizations, and the upper synchronizer is empty.

[0094] It should be noted that each synchronizer includes an expected synchronization quantity N, a synchronization counter C, and a previous-level synchronizer S.

[0095] like Figure 3 As shown, a global secondary synchronizer S2 is set, and each third-level cache holds the global secondary synchronizer S2. The expected synchronization number N of the secondary synchronizer S2 is the total number of third-level caches that need to perform task synchronization in the entire system determined by the analysis in step S11. The synchronization counter C is equal to the expected synchronization number N, and the previous level synchronizer is set to empty.

[0096] A first-level synchronizer S1 is set in each three-level cache, and each core in the three-level cache holds the first-level synchronizer S1 set in its respective three-level cache. The synchronization number of the first-level synchronizer S1 is the number of cores in the three-level cache that need to perform task synchronization determined by analysis in step S11. The synchronization counter C is equal to the expected synchronization number N, and the previous-level synchronizer is set to the second-level synchronizer S2.

[0097] Based on the design of the synchronizer in the above embodiment, in a further embodiment, a synchronizer execution process is proposed. Figure 4 As shown, including:

[0098] 1) When each synchronizer performs a synchronization, the synchronization counter C is atomically decremented by 1 and the decremented counter value C' is obtained;

[0099] Regardless of whether it is a primary synchronizer or a secondary synchronizer, each synchronizer performs a synchronization operation and atomically decrements 1 after the operation to obtain the updated synchronization counter value.

[0100] 2) Determine the value of C';

[0101] Check if the synchronization counter is equal to zero to determine if all components (L3 cache or core) that need to be synchronized have completed synchronization.

[0102] 3) If C' is equal to 0, it means that all synchronous cores have completed synchronization, and execute steps 5) and 6);

[0103] 4) If C' is not equal to 0, it means that some cores have not completed synchronization, and execute steps 7), 8), 9), and 10);

[0104] 5) If the previous level synchronizer is set, you need to execute the synchronization of the previous level synchronizer until the previous level synchronizer completes the synchronization;

[0105] 6) Set the counter C to the synchronization number N, end the synchronization and return the synchronization status code 1;

[0106] For the secondary synchronizer, the synchronization counter is directly reset to the expected number of synchronizations, and the synchronization is ended, and a success status code is returned.

[0107] For a first-level synchronizer, it is necessary to wait for the synchronization of its previous-level synchronizer (second-level synchronizer) to be completed before resetting the synchronization counter to the expected number of synchronizations, ending the synchronization and returning a success status code.

[0108] 7) Busy waiting for a number of microseconds;

[0109] 8) Determine the value of counter C;

[0110] 9) If the value of counter C is not equal to the synchronization number N, it means that a core has not completed synchronization, and repeat step 1);

[0111] 10) If the value of counter C is equal to the number of synchronizations N, it means that all cores have completed synchronization, and the synchronization ends and returns the synchronization status code 0.

[0112] Both the primary synchronizer and the secondary synchronizer perform synchronization according to the above process.

[0113] This embodiment proposes a hierarchical synchronization mechanism, in which the first-level synchronizer is responsible for synchronization between cores, and the second-level synchronizer is responsible for synchronization between third-level caches. Each synchronizer will perform a synchronization operation and determine whether the synchronization is completed based on the value of the synchronization counter. If it is not completed, it will perform busy waiting and repeat synchronization until all components are synchronized.

[0114] In one embodiment, the decrement operation of the synchronization counter is performed in an atomic minus 1 manner to ensure the security and consistency of the synchronization operation in a multi-core environment.

[0115] Based on the same inventive concept, the embodiment of the present application also provides a multi-level task synchronization device based on the processor three-level cache distribution for implementing the above-mentioned multi-level task synchronization method based on the processor three-level cache distribution. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above-mentioned method, so the specific limitations in the embodiment of the multi-level task synchronization device based on the processor three-level cache distribution provided below can be referred to the above limitations on the multi-level task synchronization method based on the processor three-level cache distribution, and will not be repeated here.

[0116] See also Figure 5 The embodiment of the present invention further provides a multi-level task synchronization device based on processor three-level cache distribution, comprising:

[0117] A synchronization acquisition module, used to determine the core that needs to perform task synchronization and the third-level cache that needs to perform task synchronization in each third-level cache of the processor;

[0118] An initialization module is used to initialize the first-level synchronizer and the second-level synchronizer according to the number of cores and the number of third-level caches that need to perform task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the core and the third-level cache respectively;

[0119] The synchronous execution module is used to synchronize tasks between cores and between L3 caches using the L1 synchronizer and L2 synchronizer respectively, until all L3 caches that need to synchronize tasks have completed synchronization, and then the cores in each L3 cache complete synchronization.

[0120] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0121] Reference Figure 6 An embodiment of the present invention also provides a computer device, including: a memory and a processor and a computer program stored in the memory. When the computer program is executed on the processor, a multi-level task synchronization method based on the processor three-level cache distribution as described in any one of the above methods is implemented.

[0122] The computer device may be a desktop computer, a notebook, a PDA, a cloud server or other computing device. The computer device may include, but is not limited to, a processor and a memory. Those skilled in the art will understand that Figure 6 It is only an example of a computer device and does not constitute a limitation of the computer device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0123] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0124] In some embodiments, the memory may be an internal storage unit of the computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory may also be an external storage device of the computer device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device. Further, the memory may include both an internal storage unit and an external storage device of the computer device. The memory is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory may also be used to temporarily store data that has been output or is to be output.

[0125] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program implements a multi-level task synchronization method based on processor three-level cache distribution as described in any one of the above methods.

[0126] In this embodiment, if the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, USB flash drive, mobile hard disk, disk or optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0127] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0128] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0129] In the embodiments disclosed in the present application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0130] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-level task synchronization method based on processor three-level cache distribution, characterized in that: The steps include: Determine the core that needs to perform task synchronization and the third-level cache that needs to perform task synchronization in each third-level cache of the processor; Initializing the first-level synchronizer and the second-level synchronizer respectively according to the number of the cores and the number of the third-level caches that need to perform task synchronization, and the first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the cores and the third-level cache respectively; The first-level synchronizer and the second-level synchronizer are used to perform task synchronization between cores and between third-level caches respectively, until all the third-level caches that need to perform task synchronization have completed synchronization, and then the core in each third-level cache completes synchronization.

2. The multi-level task synchronization method based on processor three-level cache distribution according to claim 1 is characterized in that: The core in each L3 cache of the processor is a L1 communication domain, and all L3 caches are L2 communication domains; After determining the cores and the three-level caches that need to be synchronized in each three-level cache of the processor, it also includes: Each of the cores in the primary communication domain that needs to perform task synchronization holds the primary synchronizer corresponding to the corresponding third-level cache; Each of the third-level caches that needs to perform task synchronization in the second-level communication domain is made to hold the global second-level synchronizer.

3. The multi-level task synchronization method based on processor three-level cache distribution according to claim 2 is characterized in that: The first-level synchronizer and the second-level synchronizer are used respectively to synchronize tasks between cores and between third-level caches, including: Using the secondary synchronizer to start task synchronization between the third-level caches in the secondary communication domain; Repeat the synchronization between the three-level caches according to the number of the three-level caches that need to perform task synchronization and the number of synchronizations in the secondary communication domain until the synchronization task of the secondary communication domain is completed; Using the first-level synchronizer to perform inter-core task synchronization in the first-level communication domain; The inter-core task synchronization is repeated according to the number of the cores that need to perform task synchronization and the number of synchronizations in the primary communication domain until the synchronization task of the primary communication domain is completed.

4. The multi-level task synchronization method based on processor three-level cache distribution according to claim 1 is characterized in that: The first-level synchronizer and the second-level synchronizer each include: an expected synchronization quantity, a synchronization counter and an upper-level synchronizer; In the first-level synchronizer, the expected synchronization number is the number of cores in the third-level cache that need to perform task synchronization, the initial value of the synchronization counter is the expected synchronization number, and the value of the synchronization counter is reduced by 1 each time synchronization is performed, and the upper-level synchronizer is the second-level synchronizer; In the secondary synchronizer, the expected synchronization number is the number of all third-level caches that need to perform task synchronization, the initial count value of the synchronization counter is the expected synchronization number, and the upper-level synchronizer is empty.

5. The multi-level task synchronization method based on processor three-level cache distribution according to claim 4 is characterized in that: The second-level synchronizer is used to perform task synchronization among the three-level caches until all the three-level caches that need to perform task synchronization have completed synchronization, including: Each of the secondary synchronizers performs synchronization once and obtains a decremented synchronization counter value; Determining whether the value of the synchronization counter after decrement is equal to zero; If it is zero, execute the following steps: Setting the synchronization counter value to the expected synchronization number; If it is not equal to zero, perform the following steps: Busy waiting for set time; Determining whether the synchronization counter value is equal to the expected synchronization quantity; If not, continue to perform synchronization using the secondary synchronizer until the synchronization counter value is equal to zero; If yes, the synchronization is terminated and the first set synchronization status code is returned.

6. The multi-level task synchronization method based on processor three-level cache distribution according to claim 5 is characterized in that: Performing task synchronization among cores using the first-level synchronizer until all cores that need to perform task synchronization complete synchronization, including: Each of the first-level synchronizers performs synchronization once and obtains a decremented synchronization counter value; Determining whether the value of the synchronization counter after decrement is equal to zero; If it is zero, execute the following steps: Waiting for the secondary synchronizer to complete synchronization; Setting the synchronization counter value to the expected synchronization quantity, ending the synchronization and returning a second set synchronization status code; If it is not equal to zero, perform the following steps: Busy waiting for set time; Determining whether the synchronization counter value is equal to the expected synchronization quantity; If not, continue to perform synchronization using the secondary synchronizer; If yes, the synchronization is terminated and the first setting synchronization status code is returned.

7. The multi-level task synchronization method based on processor three-level cache distribution according to claim 4 is characterized in that: The synchronous counter is decremented by using an atomic minus-1 operation.

8. A multi-level task synchronization device based on processor three-level cache distribution, characterized in that: include: A synchronization acquisition module, used to determine the cores and the third-level caches that need to be synchronized with the tasks in each third-level cache of the processor; An initialization module, used to initialize the first-level synchronizer and the second-level synchronizer respectively according to the number of the cores and the number of the third-level caches that need to perform task synchronization, and the first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the cores and the third-level cache respectively; The synchronous execution module is used to use the first-level synchronizer and the second-level synchronizer to perform task synchronization between cores and between third-level caches respectively, until all the third-level caches that need to perform task synchronization have completed synchronization, and then the core in each third-level cache completes synchronization.

9. A computer device, characterized in that: The device comprises a processor and a memory: The memory is used to store a computer program and send instructions of the computer program to the processor; The processor executes a multi-level task synchronization method based on processor three-level cache distribution according to any one of claims 1 to 7 according to the instructions of the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the multi-level task synchronization method based on processor three-level cache distribution according to any one of claims 1 to 7 is implemented.

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