Chip and method for chip authentication

Abstract

An authentication method executed by a chip includes: receiving an authentication request from a debugger; in response to the authentication request being an offline authentication request, performing offline authentication based on an authentication credential, the authentication credential including access control information of the chip and a user seal generated based on the user information; enabling access of the debugger to the resource of the chip based on the access control information, where the step of performing the offline authentication comprises: sending an offline challenge value to the debugger, where the offline challenge value is generated by the chip based on the chip identifier; receiving a second signature corresponding to the offline challenge value from the debugger; the second signature is validated based on the offline challenge value using a user seal included in the authentication credential as an offline authentication public key.

Description

Technical Field

[0001] Some example embodiments relate to a method for chip authentication, and more particularly, to a method for authenticating secure debugging of a chip. Background Art

[0002] Many integrated circuits or chips have debugging interfaces to facilitate development and maintenance. A debugger can be connected to the chip's debugging interface and can run debugging software tools to obtain the chip's code and data, control the execution of code, and access and modify hardware resources such as registers, memory, or input / output (I / O). However, the debugging interface can represent a security risk that can be used to attack the chip's software and hardware. Summary of the invention

[0003] This Summary is provided to introduce in simplified form a selection of concepts that are further described in the Detailed Description. This Summary is not intended to identify key features or / and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0004] According to an example embodiment of the present disclosure, an authentication method performed by a chip includes: receiving an authentication request from a debugger; in response to the authentication request being an offline authentication request, performing offline authentication based on authentication credentials and a first signature, wherein the authentication credentials include access control information of the chip and a user seal generated based on user information; enabling the debugger to access resources of the chip based on the access control information, wherein the step of performing offline authentication includes: sending a challenge value to the debugger, wherein the offline challenge value is generated by the chip based on a chip identifier; receiving a second signature corresponding to the offline challenge value from the debugger; and verifying the second signature based on the offline challenge value using the user seal included in the authentication credentials as an offline authentication public key.

[0005] The step of performing offline authentication may further include: after receiving the offline authentication request, verifying the authentication credentials; and sending an offline challenge value to the debugger in response to the verification of the authentication credentials.

[0006] The step of verifying the authentication credentials may include: splicing the periodic tag with the authentication credentials to form a first splicing result, and using a pre-installed online authentication public key to verify that the first signature corresponds to the hash value of the first splicing result.

[0007] The authentication credential may also include a first validity period parameter and a second validity period parameter, wherein, in response to at least one of a single power-on time of the chip being greater than or equal to the first validity period parameter or an offline authentication count value being greater than or equal to the second validity period parameter, the debugger's access rights to the chip's resources are disabled.

[0008] The authentication method may further include: in response to the online authentication being performed, the offline authentication count value is cleared to zero, wherein in response to the offline authentication being performed, the offline authentication count value is increased by 1.

[0009] The authentication method may further include: sending the verification result to the debugger.

[0010] According to an example embodiment of the present disclosure, a method for authenticating a chip includes: receiving, by the chip, an authentication request from a debugger; in response to the authentication request being an online authentication request, performing online authentication, and enabling the debugger to access resources of the chip based on the online authentication, wherein the step of performing online authentication includes: sending an online challenge value from the chip to the debugger, wherein the online challenge value is generated based on a chip identifier; receiving, by the chip from the debugger, an authentication credential and a first signature generated by a server; verifying, by the chip, the first signature using a pre-installed online authentication public key; in response to the verification of the first signature, storing, by the chip, the authentication credential and the first signature in an off-chip memory, and storing the online challenge value as a periodic tag in an on-chip memory.

[0011] The authentication credential may be generated by the server based on an online challenge value and user information, and the authentication credential may include a user seal generated as a public key based on the user information and a salt value, wherein the first signature is generated by the server using an online authentication private key to sign the concatenation result of the online challenge value and the authentication credential.

[0012] The step of verifying the first signature may include: the chip splices the online challenge value with the received authentication credentials to form a first splicing result (M2); the chip uses a pre-installed online authentication public key to verify that the first signature corresponds to the hash value of the first splicing result.

[0013] The authentication credential may further include a first validity period parameter and a second validity period parameter, wherein, in response to at least one of the chip single power-on time being greater than or equal to the first validity period parameter or the offline authentication count value being greater than or equal to the second validity period parameter, the debugger's access rights to the chip's resources are disabled.

[0014] In response to online authentication being performed, the offline authentication count value is cleared to zero; in response to offline authentication being performed, the offline authentication count value is increased by 1.

[0015] The method for authenticating a chip may further include: the chip sending a verification result to a debugger.

[0016] According to an example embodiment of the present disclosure, a chip includes: an on-chip memory; an authentication unit, configured to: receive an authentication request from a debugger, and in response to the authentication request being an offline authentication request, perform offline authentication based on authentication credentials generated through online authentication, wherein the authentication credentials include access control information of the chip and a user seal generated based on user information; and a global access controller, configured to: after the authentication is passed, enable the debugger's access rights to the chip's resources based on the access control information, wherein, in order to perform offline authentication, the authentication unit is configured to: send an offline challenge value to the debugger, wherein the offline challenge value is generated based on a chip identifier, receive a second signature corresponding to the offline challenge value from the debugger, and verify the second signature based on the offline challenge value using the user seal included in the authentication credentials as an offline authentication public key.

[0017] In order to perform offline authentication, the authentication unit may be further configured to: verify the authentication credentials after receiving the offline authentication request; and send an offline challenge value to the debugger in response to the verification of the authentication credentials.

[0018] In order to verify the authentication credentials, the authentication unit can be configured to: splice the periodic label generated by online authentication with the authentication credentials to form a first splicing result, and use a pre-installed online authentication public key to verify whether the first signature corresponds to the hash value of the first splicing result, wherein the first signature is generated by the server in the online authentication.

[0019] The authentication unit may be further configured to: in response to the authentication request being an online authentication request, perform online authentication, wherein when the online authentication passes, save the authentication credential and the first signature corresponding to the authentication credential.

[0020] In order to perform online authentication, the authentication unit can be configured to: send an online challenge value to the debugger, where the online challenge value is generated based on the chip identifier; receive an authentication credential and a first signature generated by a server from the debugger; verify the first signature using a pre-installed online authentication public key; in response to the verification of the first signature passing, store the authentication credential and the first signature in an off-chip memory, and store the online challenge value as a periodic tag in an on-chip memory; and send the verification result to the debugger.

[0021] The authentication credentials can be generated by the server based on user information, wherein the first signature is generated by the server using the online authentication private key to sign the concatenation result of the online challenge value and the authentication credentials, wherein the user seal is a public key generated by the server based on user information and salt value.

[0022] In order to verify the first signature, the authentication unit can be configured to: splice the online challenge value with the received authentication credentials to form a first splicing result; and use a pre-installed online authentication public key to verify whether the first signature corresponds to the hash value of the first splicing result.

[0023] The authentication credential may further include a first validity period parameter and a second validity period parameter, wherein, in response to the chip single power-on time being greater than or equal to the first validity period parameter and / or the offline authentication count value being greater than or equal to the second validity period parameter, access rights to resources within the chip are disabled.

[0024] The method and system for chip authentication according to some example embodiments conceived by the present invention can realize online / offline dual-mode authentication without relying on agents and local databases, and can realize user identity-based authentication and authorization, revocation of access rights, and defense against replay attacks in both online and offline scenarios.

[0025] Additional aspects and / or advantages of the inventive concepts will be set forth in part in the description which follows and, in part, will be obvious from the description, and / or may be learned by practice of various exemplary embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings.

[0027] Figure 1 is a diagram illustrating an example of a chip authentication system.

[0028] Figure 2 is a diagram illustrating an example of a proxy mode for debug authentication of a chip.

[0029] Figure 3 is a diagram of a dual mode authentication method according to an exemplary embodiment of the present disclosure.

[0030] Figure 4 is a diagram of a dual mode authentication system according to an example embodiment of the present disclosure.

[0031] Figure 5 is a flowchart of an online authentication method according to an exemplary embodiment of the present disclosure.

[0032] Figure 6 is a diagram illustrating an example of authentication credentials according to an example embodiment of the present disclosure.

[0033] Figure 7 is a diagram of an online authentication method according to an exemplary embodiment of the present disclosure.

[0034] Figure 8 is a diagram illustrating an example of generating authentication credentials according to an example embodiment of the present disclosure.

[0035] Fig. 9 is a diagram illustrating an example of signing an authentication credential according to an example embodiment of the present disclosure.

[0036] Fig.10 is a diagram illustrating an example of verifying authentication credentials according to an example embodiment of the present disclosure.

[0037] Fig.11 is a flow chart of an offline authentication method according to an example embodiment of the present disclosure.

[0038] Fig.12 is a flowchart of an offline authentication method according to another example embodiment of the present disclosure.

[0039] Fig.13 is a diagram of an offline authentication method according to an exemplary embodiment of the present disclosure.

[0040] Fig.14 is a diagram illustrating the operation of a debugger during offline authentication according to an example embodiment of the present disclosure.

[0041] Fig.15 is a diagram illustrating the operation of a chip during offline authentication according to an example embodiment of the present disclosure.

[0042] Fig.16 is a diagram illustrating an example of a chip according to an example embodiment of the present disclosure.

[0043] Fig.17 is a diagram illustrating an example of logic of an expiration detector according to an example embodiment of the present disclosure.

[0044] Fig.18 is a diagram illustrating an example of an authentication loop according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following detailed description is provided to help the reader obtain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be clear. For example, except for the operations that must occur in a specific order, the order of operations described herein is only an example and is not limited to those orders set forth herein, but can be changed as will be clear after understanding the disclosure of the present application. In addition, for greater clarity and simplicity, the description of features known in the art may be omitted.

[0046] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein have been provided to illustrate only some of the many possible ways to implement the methods, devices, and / or systems described herein that will be clear after understanding the disclosure of the present application.

[0047] The structural or functional description of the examples disclosed here below is intended only for the purpose of describing the examples, and the examples may be implemented in various forms. The examples are not intended to be limiting, but various modifications, equivalents, and substitutes may also be included within the scope of the claims.

[0048] Although the terms "first" or "second" are used to explain various components, the components are not limited to the terms. These terms should only be used to distinguish one component from another component. For example, within the scope of the rights according to the concept of the present disclosure, a "first" component may be referred to as a "second" component, or similarly, a "second" component may be referred to as a "first" component.

[0049] It will be understood that when a component is referred to as being “connected to” another component, the component may be directly connected or coupled to the other component or intervening components may be present.

[0050] As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It should also be understood that when the terms "include" and / or "comprising" are used in this specification, it indicates the presence of stated features, integers, steps, operations, elements, components or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0051] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the examples belong. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0052] Hereinafter, examples will be described in detail with reference to the accompanying drawings. Regarding reference numerals assigned to elements in the drawings, it should be noted that the same elements will be denoted by the same reference numerals and redundant descriptions thereof may be omitted or simplified.

[0053] Figure 1 is a diagram illustrating an example of a chip authentication system.

[0054] Reference Figure 1, the chip authentication system may at least include a server (or authentication server), a debugger (or debugging device), and a chip. Users can interact with the chip authentication system. The server can store information such as user identifiers (user IDs), passwords, chip identifiers (chip IDs), keys, and access rights. The server can directly determine whether the user has access to chip resources. The server is remotely deployed and held by a trusted party (e.g., a chip manufacturer). The debugger may represent all the equipment and corresponding software tools used to debug the chip. The user of the debugger is the user, and the object of debugging is the chip. There may be resources in the chip that are to be prevented from access. The debugger can be connected to the server through the public Internet. The debugger can be connected to the user through a debugging interface and a cable.

[0055] The debugging authentication of the chip may include an offline authentication mode, an online authentication mode and a proxy mode.

[0056] The offline authentication mode can be performed by both the debugger and the chip as the debugging target. The chip can determine the legitimacy of the debugger by verifying whether it holds a certain key (for example, a password or a private key). For a legitimate debugger, the chip grants access to the debugging interface. Offline authentication is simple to implement and low cost, but it may be difficult to implement fine-grained permission allocation, and it is impossible to assign different access rights to different users. For example, the chip can store a limited amount of user information and permission information, and may not have the ability to dynamically update and maintain it.

[0057] The online authentication mode may introduce a third role, in which the server may be responsible for authentication and authorization. The server may keep the user information or user credentials of the user who may be called the debugger, the chip information (chip ID, etc.) and the corresponding access rights. The user information or user credentials may include, for example, a user ID or password. The server may assign different permissions to different debuggers or users to achieve fine-grained debugging permission control. For example, the access rights of the chip may be refined to a specific processor core, a specific memory area, a specific bus, and a specific input and output (I / O).

[0058] Although online authentication can be used, the debugger or debugging device may need to access a server for each online authentication. However, in some practical application scenarios, access to the server may not be available. For example, for information confidentiality considerations, the debugger or debugging device and the target chip may be in an environment with an internal network and / or no network that may not be able to access an external server, which limits the practical application of the online method.

[0059] Proxy mode can reduce the online mode's reliance on remote servers. Figure 2 is a diagram illustrating an example of a proxy mode for debug authentication of a chip.

[0060] A proxy that can access the external network can be set up in the debugging environment. The proxy can connect to the remote authentication server and save the obtained authorization information to a local database. When performing authorization, the authorization information saved in the local database can be provided to the chip without establishing a connection to the remote authentication server.

[0061] The traditional proxy mode may not support user-oriented authorization in offline scenarios. Since the authorization information stored in the local database is not associated with the user, anyone who can use the debugging environment to debug the chip in offline scenarios can obtain the same debugging permissions.

[0062] The traditional proxy model may not be able to revoke authorization. In the traditional proxy model, once the remote authentication server sends authorization information to the local agent, the local database can permanently retain this information, and from then on, it is out of the control of the remote server and can arbitrarily grant access to the debugger. Therefore, in the traditional proxy model, the authorization of the chip may have no validity period and may not be revoked.

[0063] The traditional proxy mode may not be able to resist the replay attack on the authorization information in the offline scenario. A replay attack is when the attacker uses the previous authorization information records to deceive the debugging target (chip).

[0064] In addition, the traditional proxy model may also use agents and databases as third parties and may not support true offline scenarios, which limits the application scenarios of the traditional proxy model.

[0065] In order to make chip debugging safer and support a variety of debugging environments, an embodiment of the present invention may provide a user-oriented online-offline chip authentication method.

[0066] Figure 3 is a diagram of a dual mode authentication method according to an exemplary embodiment of the present disclosure.

[0067] When the chip is in an unauthenticated state, online authentication may be performed first, and authentication credentials may be generated. The authentication credentials may be sent to the chip. The authentication credentials may be used as a basis for authenticating and authorizing the user in offline authentication. Thereafter, offline authentication may be performed in subsequent authentications. For example, an initial online authentication may be performed to generate authentication credentials, which may be used in subsequent offline authentications.

[0068] Reference Figure 3In step 100, an authentication request may be received from a debugger. In one example, a user may input user information and an authentication mode to the debugger. The user information may include a user ID and / or a password. However, the user information is not limited thereto and may include additional information. The authentication mode may include an online mode or an offline mode. In step 100, the debugger may send an authentication request to the chip based on the authentication mode received from the user.

[0069] In step S200, the authentication request may be parsed to determine the mode indicated by the user. For example, the authentication request may be designated as an online authentication mode or an offline authentication mode.

[0070] In the case where it is determined in step S200 that the authentication request is an online authentication request, in step S300, online authentication may be performed. Specifically, the online authentication protocol may be performed by the server, the debugger, and the chip. The online authentication protocol may use the server to authenticate the user and the chip to authenticate the server. In online authentication, the server may generate an authentication credential License and a cycle tag Cycle Tag. The server may send the authentication credential License and the cycle tag CycleTag to the chip as data for authenticating and authorizing the user in offline authentication, wherein the authentication credential includes the user's access rights, term (or validity period parameter), and user seal.

[0071] In the case where it is determined in step S200 that the authentication request is an offline authentication request, in step S400, offline authentication may be performed based on the authentication credentials generated by the online authentication previously performed in step S300. In the offline authentication process in step S400, the offline authentication protocol may be executed by both the debugger and the chip. The server may not be included in the offline authentication process in step S400. The chip can implement authentication and authorization of the user in an offline state according to the authentication credentials. The chip can implement authentication and authorization of the user in an offline state according to the authentication credentials, and fine-grained access permission allocation in offline scenarios can be implemented. The chip can implement authentication and authorization of the user in an offline state according to the authentication credentials, and can defend against replay attacks on authorization through periodic tags.

[0072] In step S500, the chip may determine whether the online / offline authentication performed in step S300 or S400 is successful. In response to successful authentication, in step S600, the chip may enable access rights to the resources within the chip based on the access control information. Otherwise, in response to failed authentication, the chip may disable access rights to the resources within the chip.

[0073] In one example, in response to the online authentication being successful, the chip may save the authentication credentials and the signature corresponding to the authentication credentials, and may clear the count CNT of the offline authentication counter to 0. In another example, in response to the offline authentication being successful, the chip may increase the count CNT of the offline authentication counter by 1 for the authorization expiration and revocation mechanism in the offline mode.

[0074] Figure 4 is a diagram of a dual mode authentication system according to an example embodiment of the present disclosure.

[0075] In the online authentication scenario 400, the server 405 may first authenticate the user. When the user authentication is successful, the server 405 may send the authentication credentials to the debugger 410. Thereafter, the chip 415 may authenticate the server 405 and may store the authentication credentials after the authentication is successful.

[0076] In the offline scenario 401, the chip can authenticate the user based on the authentication credentials to implement user-oriented authorization.

[0077] Regardless of online authentication or offline authentication, when the authentication is successful, the authentication unit may send parameters for detecting expiration, and may revoke authorization when the access right is detected to have expired. The authentication unit may be a module in the chip responsible for authentication. The parameters for detecting expiration may include, for example, a single power-on time of the chip and an offline authentication count.

[0078] Figure 5 is a flowchart of an online authentication method according to an exemplary embodiment of the present disclosure. Figure 5 The flowchart in corresponds to Figure 3 Step S300 in .

[0079] Reference Figure 5 When receiving an online authentication request from a debugger, the chip may send an online challenge value to the debugger at step S310. In one example, the online challenge value may be a value generated based on the chip ID.

[0080] The debugger may forward the online challenge value and user information (e.g., user ID and password) to the server. The server may generate an authentication credential based on the user information, and may sign the concatenation result of the authentication credential and the online challenge value using the online authentication private key to form a first signature. The server may forward the authentication credential and the first signature to the debugger.

[0081] In step S320 , the chip may receive an authentication credential (or authentication data) and a first signature from the debugger.

[0082] In step S330 , the chip may verify the first signature using a pre-installed online authentication public key.

[0083] In step S340 , in response to the first signature being verified successfully, the chip may store the authentication credential and the first signature.

[0084] In step S350, the chip may send the verification result to the debugger. When the online authentication is passed, the chip may enable access to the corresponding resources inside the chip according to the access rights. For example, the chip may update the user's access rights to access one or more resources of the chip.

[0085] Figure 6 is a diagram illustrating an example of authentication credentials according to an example embodiment of the present disclosure.

[0086] Reference Figure 6 , the authentication credentials may include the access control information of the chip and the user seal. The authentication credentials may also include data for performing a salting function. For example, the authentication credentials may include: access rights, validity period parameters (T and N), salt value (Salt) data, and a user seal. For example, the access control information of the chip may include access rights and validity period parameters (T and N). In another example, the access control information of the chip may include access rights, validity period parameters (T and N), and salt value (Salt) data. Figure 6 The arrangement of authentication credentials shown in is exemplary, and the parts of the authentication credentials may be arranged in any order.

[0087] The access rights may indicate that the server can determine the access rights of the user to the hardware resources of the chip by retrieving the permission control policy based on the user information (e.g., user ID) and chip information (e.g., chip ID) involved in the authentication. The chip will enable or disable debugging access to the corresponding hardware resources based on the access rights. The corresponding hardware resources may include, but are not limited to, processors, memory, I / O, and peripherals.

[0088] The validity period parameters may include T and N, wherein the first validity period parameter T may represent the allowed single power-on time of the chip, and the second validity period parameter N may represent the number of offline authentications that may be allowed. The validity period parameters T and N may be used to implement the revocation of authorization. The first validity period parameter T and the second validity period parameter N may be configured by the server as an authorization policy and stored in the database of the server.

[0089] The server may generate a random number and concatenate the random number with the current chip ID to generate a salt value. The salt value may include data that can be used as an additional input. For example, the salt value may include random data that can be used as an additional input. The salt value may be used to generate a key for offline authentication and may be used to defend against rainbow table attacks. The server may not need to store the salt value.

[0090] The user seal can be a public key. The user seal can be generated by the server based on the user information. The user seal can be generated by the server based on the user information to verify the signature. The user seal can correspond the authorized access rights to the user identity, so that the user identity can be verified to match the corresponding authorization during offline authentication, thereby realizing object-oriented offline authentication.

[0091] Figure 7 is a diagram of an online authentication method according to an exemplary embodiment of the present disclosure.

[0092] Online authentication can be performed using chip 415, which includes a pre-installed online authentication public key, or a hash value of the public key. This operation can be performed during the chip production stage. Server 405 can keep a private key corresponding to the public key.

[0093] Reference Figure 7 In step 701, the debugger 410 may receive user information and authentication mode Auth_Mode from the user. The user information may include a user ID and a password, but this is only an example and the present disclosure is not limited thereto. In response to the authentication mode being the online mode, the debugger 410 may determine that the user selects online authentication.

[0094] In step 702, debugger 410 may establish a secure channel with server 405 through a secure transmission protocol (eg, TLS or SSH). In step 703, debugger 410 may send an online authentication request to chip 415.

[0095] In step 704 , the chip 415 may generate a random number Nonce. The chip 415 may concatenate the random number Nonce with the chip ID to generate an online challenge value Challenge, and may send the Challenge to the debugger 410 .

[0096] In step 705, the debugger 410 may generate a request message by concatenating Challenge with the user ID and password, and may send the request message to the server 405. Since a secure channel has been established between the debugger 410 and the server 405, the user's password will not be leaked.

[0097] In step 706, the server 405 may authenticate the user according to the registered user information in its database, may generate an authentication credential (or authentication data) and its signature, and may send the authentication credential and its signature together to the debugger.

[0098] In step 707, the debugger 410 may receive the authentication credentials and their signatures from the server 405. In step 708, the debugger 410 may obtain the salt value from the authentication credentials and save it for generating key materials during offline authentication. In step 709, the debugger 410 may send the authentication credentials and their signatures to the chip 415.

[0099] In step 710 , the chip 415 may verify the received authentication credentials using the online authentication public key.

[0100] If the verification is successful, then in step 711, the chip 415 can save the received authentication credentials and signature to the off-chip memory for offline authentication. In step 712, the chip 415 can save the Challenge in step 704 to the on-chip memory as a cycle tag Cycle Tag to defend against replay attacks during offline authentication. In step 713, the chip 415 can feed back the authentication result to the debugger 410, and the online authentication can end. If the verification is successful, the chip 415 can enable the access rights of the corresponding resources according to the access right information.

[0101] Figure 8 is a diagram illustrating an example of generating authentication credentials according to an example embodiment of the present disclosure. Figure 8 The operations in can correspond to Figure 7 The part of generating authentication credentials in step 706 in .

[0102] Reference Figure 8 When receiving user information (eg, user ID and password, etc.) from the debugger, the server may query the database for access rights to the chip and validity period parameters (T and N) corresponding to the user ID.

[0103] The server may generate a random number Nonce, and may concatenate the random number Nonce with the current chip ID to generate a salt value Salt. That is, the salt value Salt may be written as Salt=Nonce||Chip ID.

[0104] In addition, the server can use the user information to generate a user seal. In one example, the server can generate key material (Key material) based on the currently authenticated user ID, password, and generated salt value through a password-based key derivation algorithm (e.g., Password-Based Key Derivation Function 2, PBKDF2). The server can generate a pair of public and private keys based on the key material and the signature algorithm as an offline authentication public key (offline-pk) and an offline authentication private key (offline-sk). The offline authentication public key can be saved in the authentication credential as the seal of the user, and the offline authentication private key can be destroyed by the server.

[0105] Fig. 9 is a diagram illustrating an example of signing an authentication credential according to an example embodiment of the present disclosure. Fig. 9 The operations in can correspond to Figure 7 The part of generating the signature in step 706 in .

[0106] Reference Fig. 9 , the server can cascade the generated authentication credentials and the online challenge value Challenge received from the chip to obtain the cascade result M1. The cascade result can be written as M1 = Challenge || License. The server can sign the hash value of M1 using the online authentication private key (online-sk), as shown below:

[0107] Signature=Sign(online-sk,Hash(M1)).

[0108] Fig.10 is a diagram illustrating an example of verifying authentication credentials according to an example embodiment of the present disclosure. Fig.10 The operations in can correspond to Figure 7 Step 710 in .

[0109] Reference Fig.10 The chip can compare the online challenge value Challenge with the received authentication credentials (License received ) to obtain the cascade result M2. The cascade result M2 can be written as M2 = Challenge || License received The chip can then verify the received signature using the pre-installed online authentication public key. received ) is the signature of the hash value of M2, as shown below:

[0110] Result=Verify(online-pk,Hash(M2),Signature received ).

[0111] Fig.11 is a flow chart of an offline authentication method according to an example embodiment of the present disclosure. Fig.11 The flowchart in corresponds to Figure 3 Step S400 in .

[0112] The execution of offline authentication may require the following conditions to be met: (1) the chip can be pre-installed with the online authentication public key; (2) the chip can be loaded with the periodic label and authentication credential license that can be generated during online authentication. loaded and its signature loaded ; (3) The debugger can load the salt value Salt stored in the online authentication process. If these conditions are not met, the offline authentication will fail and the user may not be able to obtain debugging permissions.

[0113] Reference Fig.11In step S420, the chip may send an offline challenge value to the debugger. In one example, the offline challenge value may be a value generated based on the chip ID.

[0114] The debugger can derive a user private key (user-sk) through user information (eg, user ID and password) and a salt value Salt, and can use the user private key to sign the received offline challenge value to generate a second signature.

[0115] In step S430 , the chip may receive a second signature corresponding to the offline challenge value from the debugger.

[0116] In step S440 , the chip may use the user seal included in the authentication credential as the offline authentication public key and the offline challenge value to verify the second signature.

[0117] In step S450, the chip may send the verification result to the debugger. For example, the debugger that has received the verification result may run a debugging software tool, which may obtain code and data from chip 415, control the operation of the code, and access or modify the resources of chip 415. When the offline authentication passes, chip 415 enables access rights to the corresponding resources inside the chip according to the access rights.

[0118] Fig.12 is a flowchart of an offline authentication method according to another example embodiment of the present disclosure. Fig.12 The flowchart in corresponds to Figure 3 Step S400 in .

[0119] Reference Fig.11 and Fig.12 , Fig.12 Steps S420 to S450 may be performed with Fig.11 Steps S420 to S450 in are the same, and repeated descriptions may be omitted or simplified.

[0120] In order to prohibit or prevent malicious users from modifying the authentication credentials stored in the off-chip memory before offline authentication, and to prohibit or defend against replay attacks, the authentication credentials loaded into the chip may be verified in step S410 after receiving the offline authentication request. In response to the authentication credentials being verified, an offline challenge value may be sent to the debugger in step S420. Fig.15 Describes in detail the operations that are performed to validate authentication credentials.

[0121] Fig.13 is a diagram of an offline authentication method according to an exemplary embodiment of the present disclosure. Fig.14 is a diagram illustrating the operation of a debugger during offline authentication according to an example embodiment of the present disclosure. Fig.15is a diagram illustrating the operation of a chip during offline authentication according to an example embodiment of the present disclosure.

[0122] Reference Fig.13 In step 1301, the debugger may receive user information and authentication mode Auth_Mode from the user. The user information may include a user ID and a password, but this is only an example and the present disclosure is not limited thereto. In response to the authentication mode being an offline mode, the debugger may determine that the user selects offline authentication.

[0123] In step 1302 , the debugger may send an offline authentication request to the chip.

[0124] In steps 1303 to 1304, the chip can use the pre-installed online authentication public key to authenticate the authentication credentials (License loaded ) for verification. Steps 1303 to 1304 may correspond to Fig.12 Step S410 in .

[0125] Reference Fig.15 The chip can read the cycle tag Cycle Tag from the on-chip memory, and can cascade the cycle tag Cycle Tag with the loaded authentication credentials to obtain a cascade result M3, where the cascade result M3 can be written as M3 = Cycle Tag||License loaded .

[0126] The chip can use the online authentication public key to verify the loaded signature loaded Whether it corresponds to the hash value of M3, as shown below:

[0127] Result=Verify(online-pk,Hash(M3),Signature loaded )

[0128] Return to reference Fig.13 If the verification is successful, then in step 1305, the chip can generate a random number Nonce, concatenate the random number Nonce with the chip ID to generate an offline challenge value Challenge, and send the offline challenge value Challenge to the debugger. If the verification is not successful, the offline authentication will fail.

[0129] In steps 1306 and 1307 , the debugger may sign the received offline challenge value Challenge.

[0130] Reference Fig.14, the debugger can use the user ID, password, and pre-stored salt value Salt to generate key material through a password-based key derivation algorithm (for example, PBKDF2), and then generate a user private key (user-sk) based on the key material and the signature algorithm, and use the private key to sign the received Challenge, as shown below:

[0131] Signature=Sign(user-sk,Challenge)

[0132] After signing, the debugger can destroy the private key. For example, by destroying the private key, the risk of leaking the private key can be reduced or eliminated.

[0133] Return to reference Fig.13 In step 1308, the debugger may send the signature to the chip.

[0134] In step 1309, the chip uses the user seal in the loaded authentication credentials as the offline authentication public key (offline-pk) to verify the received signature as follows:

[0135] Result=Verify(offline-pk,Challenge,Signature)

[0136] If the authentication credential belongs to the current user and the password is correct, the user private key user-sk derived from the user identity information (or user credentials) in step 1306 is equal to the offline authentication private key offline-sk, which is paired with the user seal in the authentication credential (i.e., the offline authentication public key offline-pk), and the signature verification will pass. Other user IDs or incorrect passwords will cause the derived user private key user-sk to not match the offline authentication public key offline-pk, resulting in the signature being unable to be verified and the authentication failing.

[0137] In step 1310, the chip may send the authentication result to the debugger, and the offline authentication is completed.

[0138] Fig.16 is a diagram illustrating an example of a chip according to an example embodiment of the present disclosure.

[0139] Reference Fig.16 According to an example embodiment of the present disclosure, the chip 415 may include: an on-chip memory 1601, an authentication unit 1602, a cryptographic engine 1603, an expiration detector 1604, and a global access controller 1605. In addition, the chip 415 may also include other modules, for example, a fine-grained access controller 1606, but the present disclosure is not limited thereto.

[0140] The debug access authorization revocation mechanism may be implemented by a logic circuit inside chip 415 .

[0141] Reference Fig.16 , between the debug interface 1607 and the resource 1608, two levels of access controllers may be provided. The resource 1608 may be a protected hardware resource. The first level of access controller may be implemented as a global access controller 1605. The global access controller 1605 may be equivalent to the main switch of the debug interface 1607. The global access controller 1605 is controlled by the expiration detector 1604. When it is detected that the debug access authorization has expired, the global access controller 1605 may disconnect the path between the debug interface 1607 and the resource 1608 in the chip 415. At this time, regardless of the authentication result, the resource 1608 in the chip 415 cannot be accessed through the debug interface 1607. If the debug access authorization has not expired, the global access controller 1605 may connect the path between the debug interface 1607 and the resource 1608 in the chip 415, and the debugger outside the chip 415 may be connected to the second level of access controller to implement fine-grained access control. For example, the second level of access controller may be implemented by a fine-grained access controller 1606.

[0142] On-chip memory 1601 (e.g., on-chip NVM) can be used to store cycle tags Cycle Tag and offline authentication count CNT. On-chip memory 1601 can allow debug authentication logic in chip 415 to access, and its pins can be unavailable to the outside. Cycle tags Cycle Tag and offline authentication count CNT can only occupy a small memory space inside chip 415. For example, the cycle tag can be set to 16 to 32 bytes, and the offline authentication count can be set to 1 to 2 bytes.

[0143] The authentication unit 1602 may be an entity in the chip 415 that performs online or offline authentication. The authentication unit 1602 may provide access rights information to the second-level access controller. The authentication unit 1602 may provide parameters to the expiration detector 1604. The authentication unit 1602 may trigger the expiration detector 1604 to update these parameters. These parameters may include the upper limit T of the single power-on time of the chip 415, the upper limit N of the cumulative number of offline authentications, and the offline authentication count CNT. T and N may be extracted by the authentication unit 1602 from the authentication credentials loaded and verified from the off-chip memory when performing offline authentication. The parameter CNT may be obtained by the authentication unit 1602 after completing the offline authentication by loading 1601 from the on-chip memory and performing a self-addition operation.

[0144] The cryptography engine may be used to perform signing and verification operations in chip 415. In some examples, the cryptography engine may be part of attestation unit 1602.

[0145] The expiration detector 1604 can check and determine in real time whether the debug access authorization has expired based on the input validity period parameters T and N, the system clock, and the offline authentication count CNT, and can output an enable signal or a disable signal to the global access controller 1605 to connect or disconnect the connection between the debug interface 1607 and the resources within the chip 415.

[0146] The authentication credentials and their signatures generated during online authentication may be stored in an off-chip memory (eg, an off-chip NVM) to save memory resources within the chip 415 .

[0147] The debugger can be implemented by an apparatus, a unit, a module, a device or other components. For example, the debugger can be a general-purpose computer or a special-purpose computer. The debugger can be directly connected to the chip, or connected to the chip via another device or component (for example, a card reader or a printed circuit board). The debugger can be a device different from the chip 415, so that the debugger can be arranged outside the chip 415. The debugger arranged outside the chip 415 can be different from the component of the chip 415, for example, it can be disconnected from the chip 415. For example, the debugger arranged outside the chip 415 can rely on the debug interface 1607 to access the chip 415.

[0148] Fig.17 is a diagram illustrating an example of logic of an expiration detector according to an example embodiment of the present disclosure.

[0149] Reference Fig.17 , timer 1701 can generate timing according to the input system clock signal Clock, and output a real-time count based on the timing. For example, if the timing is set to 5s, the count output by timer 1701 increases by 1 every 5s. Each time the chip is powered on, timer 1701 can start counting from 0 without saving the count value during power-off.

[0150] The configurator 1702 can be equivalent to a trigger, and its input data and trigger signal can all come from the authentication unit. The three parameters (T, N, and CNT) output by the configurator can be sent to two comparators Comparator-1 1703 and Comparator-2 1704. If the chip is in an unauthenticated state after power-on, the configurator 1702 outputs T=0, N=0, and CNT=0 by default. At this time, until the chip completes the authentication, t>=T will be satisfied. Therefore, the expiration detector 1604 can output a high level to the global access controller 1605 to disconnect the debug interface 1607. When the chip passes a successful authentication, the authentication unit 1602 can send T, N, and CNT as parameters to the configurator 1702, and send a trigger signal Trigger to the configurator 1702, so that the configurator 1702 selects the data to the output port.

[0151] Comparator-1 1703 and Comparator-2 1704 compare the two input data P and Q. The comparison rule of Comparator-1 1703 is: when P is greater than or equal to Q, it outputs a high level (i.e., 1), otherwise it outputs a low level (i.e., 0). The comparison rule of Comparator-2 1704 is: when P is greater than Q, it outputs a high level (i.e., 1), otherwise it outputs a low level (i.e., 0). OR gate OR 1705 can perform a logical OR operation on the output signals of the two comparators, and can generate a control signal of the first-level access controller (i.e., implemented by the global access controller).

[0152] An example of implementing revocation of debug access authorization according to an example embodiment of the present disclosure is described below.

[0153] Assume that a user needs to debug a solid-state drive (SSD) master control chip that uses the online-offline authentication method described in the present disclosure.

[0154] During the first debugging, the user selected the online mode. Optionally, the online mode can be the default mode for the first debugging. After the online authentication is successful, the authentication credentials can be obtained from the authentication server through the chip. The values ​​of the validity period parameters T and N can be 480 minutes and 50 times respectively, and the offline authentication count CNT stored in the chip can be 0. Assuming that the timing unit of the timer Timer is set to 1 minute, based on the validity period parameter T=480, it can be seen that: regardless of online authentication or offline authentication, the user can debug for a maximum of 480 minutes. If it times out, the user will no longer be able to access the debugging interface. In addition, based on the validity period parameter N=50, it can be seen that: the user can perform up to 50 offline authentications until online authentication is required to obtain a new configuration.

[0155] In the second debugging, the user selected the offline mode. After the offline authentication is passed, the offline authentication count CNT can be increased by 1. Since the offline authentication count CNT is less than 50, the expiration detector can output a low-level signal to the global access controller during the chip single power-on time t from 0 to 479 minutes, which means that the user can perform debugging work for up to about 8 hours. The user can turn off the chip power after debugging for 4 hours.

[0156] In the third debugging, the user can continue to select offline mode. After the offline authentication is passed, the offline authentication count CNT can be increased to 2. When the chip power-on time exceeds 8 hours, the chip single power-on time t accumulates to 480 minutes. At this time, the expiration detector detects the expiration event and triggers the global access controller to disconnect the debug interface from the chip resources. The user may want to continue debugging, so the user can restart the chip and perform a new offline authentication. The offline authentication count CNT can be increased to 3. The user can then obtain 8 hours of continuous debugging time.

[0157] Similarly, when the user has completed 50 offline authentications, when he performs offline authentication again, the offline authentication count CNT becomes 51, which is greater than N, triggering an expiration event. The expiration detector triggers the global controller to disconnect the debug interface from the chip resources. The user may want to continue debugging, so the user restarts the chip for offline authentication. Although the authentication is successful, the offline authentication count CNT becomes 52, triggering an expiration event, and the debug interface is disconnected from the chip resources.

[0158] In order to continue debugging, it can be assumed that the user applies to the superior (for example, the server administrator) for more debugging time and times. After approval, it can be assumed that the user has obtained temporary permission to connect to the external network. After completing the online authentication, the chip obtains new authentication credentials from the authentication server, where the values ​​of T and N can be set to 600 minutes and 80 times respectively, which means that each user debugging (online or offline) can last up to 10 hours, and a total of 80 offline authentications can be performed. Since the offline authentication count CNT is cleared during online authentication, the user can then debug normally through offline authentication.

[0159] Fig.18 is a diagram illustrating an example of an authentication loop according to an example embodiment of the present disclosure.

[0160] According to an example embodiment of the present disclosure, the chip may experience different states during the authentication process. The states in the authentication process may include: unauthenticated state, online authentication state, offline authentication state, or expired state. All state transition processes between different online states may be referred to as an authentication cycle.

[0161] Reference Fig.18The unauthenticated state refers to the state where the chip has not been debugged or authenticated after power-on or has not successfully passed the debug authentication. In the unauthenticated state, if the chip receives an online authentication request, it can enter the online authentication state of the next authentication cycle; if the chip receives an offline authentication request, it can enter the offline authentication state of this authentication cycle. After triggering an expiration event, the online authentication state and the offline authentication state can be transferred to the expired state of their respective authentication cycles. In any state, restarting the chip can enter the unauthenticated state of the authentication cycle to which it belongs.

[0162] According to an example embodiment of the present disclosure, the cycle tags of different authentication cycles may be different from each other, which can ensure that the authentication credentials of different authentication cycles cannot be used interchangeably, thereby effectively defending against replay attacks.

[0163] Even if the user ID and password do not change with the authentication cycle, the user seals of the same user in different authentication cycles can be different. For example, the user seals of a user in different authentication cycles can be different, because a new salt value Salt is generated for each authentication cycle, so that the final derived offline authentication public key (i.e., user seal) and offline authentication private key can be different due to the authentication cycle, thereby improving security. Even if the debugger leaks the offline authentication private key, the private key is only valid for the current authentication cycle and will become invalid in the next authentication cycle. For example, the private key can be used only for the current authentication cycle and can become invalid in the next authentication cycle.

[0164] According to the authentication method of the example embodiment of the present disclosure, authentication based on user identity can be implemented. During online authentication, the server can issue access authorization to authenticated users. The server can generate a user seal based on the user ID and password. The server can use the user seal and access authorization to generate authentication credentials together. The authentication credentials are stored in the external memory of the chip to save memory resources inside the chip. In subsequent offline authentication, the chip can use the previously stored authentication credentials to authenticate and authorize the user. Even if a user who has not passed the authentication can use the debugging environment (for example, can log in to the debugging host or the computer room server normally), he cannot obtain authorization.

[0165] According to the authentication method of the example embodiment of the present disclosure, a validity period can be assigned to the authorized access rights, and the access rights can be revoked based on the validity period. The authorized access rights can form authentication credentials together with their validity period parameters and can be saved on the target chip, which can be responsible for detecting whether the access rights have expired and deciding whether to revoke the access rights. The validity period parameters can be associated with the single power-on time t of the chip and the number of offline authentications CNT. When any one of t≥T and CNT>N is satisfied, the access rights can be judged as expired, which makes the scheme of malicious users bypassing the validity period by keeping the chip powered on or resetting the timer invalid. Only by re-performing online authentication can the expired status be cleared and the authentication and authorization functions be restored. For example, only by performing online authentication again can the expired status be cleared and the authentication and authorization functions be restored.

[0166] The authentication method according to the exemplary embodiment of the present disclosure can effectively defend against replay attacks. Since the authorization information in different authentication cycles can be attached with different cycle tags, the chip can judge the authorization information of all historical authentication cycles as invalid, thereby resisting replay attacks. In addition, since the user seals of different authentication cycles can be different, the system can therefore have higher security.

[0167] In one example, a malicious user (or attacker) tampers with the stored authentication credentials before offline authentication in an attempt to change their own permissions. According to an example embodiment of the present disclosure, during offline authentication, the chip will verify the signature of the authentication credentials with a pre-installed online authentication public key (online-pk). Therefore, the authentication credentials tampered by the attacker will cause the signature verification to fail. In addition, the attacker cannot forge a signature for the authentication credentials that he tampered with because the attacker cannot obtain the online authentication private key on the server.

[0168] In one example, a malicious user tampers with the stored authentication credentials after the offline authentication is passed, attempting to change his or her own permissions. According to the example embodiments of the present disclosure, since the tampering behavior occurs after the user passes the offline authentication, it will not be detected by the signature verification operation temporarily. However, at this time, the tampered authentication credentials may be in a stored state and have not been loaded into the system. Only after re-authentication can the stored authentication credentials be loaded into the system, and this step may include detecting that the authentication credentials have been tampered with.

[0169] In one example, a malicious user can back up the authentication credentials and their signatures in the chip after a certain authentication is passed, and then write the backed-up authentication credentials and their signatures into the chip at some point in the future in an attempt to restore his or her rights on the chip. According to the example embodiments of the present disclosure, since each authentication cycle can use a cycle tag to uniquely mark the authentication credentials and participate in the verification of the authentication credential signature, even if the online authentication public key remains unchanged, the historical authentication credentials still cannot pass the current authentication.

[0170] The authentication method according to the example embodiment of the present disclosure occupies limited chip resources. Although some logic units may be deployed on the chip and occupy some chip internal and external memory space, resource usage can be low. For example, the main resource overhead of the authentication method according to the example embodiment of the present disclosure may come from the cryptographic calculations during authentication, while the chip may only involve the verification of the signature. Therefore, the cryptographic engine built into the chip can be used directly to perform cryptographic calculations without the need for additional circuits. Other logics in the authentication method according to the example embodiment of the present disclosure and the expiration detector can be implemented only by simple logic gate circuits. In addition, the authentication credentials can be stored in the off-chip memory of the chip without occupying the chip's own resources. Although the cycle tag Cycle Tag and the offline authentication count CNT can be stored in the on-chip memory, both are very small.

[0171] The devices, units, modules and other components described herein are implemented by hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, or any other electronic components. These and other hardware components can be configured to perform the operations described in this application. In other examples, one or more hardware components in the hardware components that perform the operations described in this application can be implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer may be comprised of one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices. These processing elements may be configured to respond to and execute instructions in a defined manner to achieve desired results. In one example, a processor or computer may include or may be connected to one or more memories storing instructions or software executable by the processor or computer. Hardware components implemented by a processor or computer may execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) for performing the operations described in this application. The hardware components may also access, manipulate, process, create, and store data in response to the execution of the instructions or software. For simplicity, the singular term "processor" or "computer" may be used in the description of the examples described in this application, but in other examples, plural terms may be used. Processor or computer can be used, or processor or computer can include multiple processing elements, or multiple types of processing elements, or both.For example, a single hardware component, or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller.One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or another processor and another controller.One or more processors, or a processor and a controller can implement a single hardware component, or two or more hardware components.Hardware components can have any one or more of different processing configurations, and examples of different processing configurations include: a single processor, an independent processor, a parallel processor, a single instruction single data (SISD) multiprocessing, a single instruction multiple data (SIMD) multiprocessing, multiple instructions single data (MISD) multiprocessing or multiple instructions multiple data (MIMD) multiprocessing.

[0172] The method of performing the operations described in this application is performed by computing hardware (e.g., by one or more processors or computers), which is implemented as execution instructions or software described herein to perform the operations described in this application. For example, a single operation, or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller may perform a single operation, or two or more operations.

[0173] Instructions or software for controlling a processor or computer to implement hardware components and perform the methods described herein may be written as a computer program, code segment, instruction, or any combination thereof to individually or collectively instruct or configure a processor or computer to operate as a machine or special-purpose computer to perform operations performed by the hardware components and methods described above. In one example, the instructions and / or software may include machine code (such as machine code generated by a compiler) directly executed by a processor or computer. In another example, the instructions or software include high-level code executed by a processor or computer using an interpreter. A person of ordinary skill in the art or a programmer may easily write instructions and / or software based on the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions in the specification, and the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions in the specification disclose algorithms for performing operations performed by the hardware components and methods described herein.

[0174] Instructions or software for controlling a processor or computer to implement hardware components and perform the methods described herein, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-RLTH, BD-R E, at least one of a Blu-ray or optical disk storage device, a hard disk drive (HDD), a solid-state drive (SSD), a flash memory, a card memory (such as a multimedia card or a micro card (for example, Secure Digital (SD) or Extreme Digital (XD))), a magnetic tape, a floppy disk, a magneto-optical data storage device, an optical data storage device, a hard disk, a solid-state disk, and any other device, any other device can be configured to store instructions or software and any associated data, data files and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files and data structures to a processor or computer so that the processor or computer can execute the instructions.

[0175] Although various example embodiments have been described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. An authentication method performed by a chip, the authentication method comprising: Receive an authentication request from a debugger; In response to the authentication request being an offline authentication request, performing offline authentication based on the authentication credential, wherein the authentication credential includes access control information of the chip and a user seal generated based on the user information; Enable debugger access to chip resources based on access control information, The steps of performing offline authentication include: sending an offline challenge value to a debugger, wherein the offline challenge value is generated by the chip based on the chip identifier; receiving, from the debugger, a second signature corresponding to the offline challenge value; The second signature is verified based on the offline challenge value using the user seal included in the authentication credential as the offline authentication public key.

2. The authentication method according to claim 1, in, The steps for performing offline authentication also include: After receiving the offline authentication request, verify the authentication credentials; In response to verification of the authentication credentials, an offline challenge value is sent to the debugger.

3. The authentication method according to claim 2, in, The steps to verify the authentication credentials include: Concatenate the periodic tag with the authentication credential to form a first concatenation result, Use the pre-installed online authentication public key to verify that the first signature corresponds to the hash value of the first concatenation result.

4. A method for authenticating a chip, comprising: The chip receives an authentication request from the debugger; In response to the authentication request being an online authentication request, performing online authentication, Based on online authentication, the debugger is enabled to access the chip resources. The steps of performing online authentication include: sending an online challenge value from the chip to the debugger, wherein the online challenge value is generated based on the chip identifier; receiving, by the chip from the debugger, an authentication credential and a first signature generated by the server; The chip verifies the first signature using a pre-installed online authentication public key; In response to verification of the first signature, the chip stores the authentication credential and the first signature in an off-chip memory, and stores the online challenge value as a cycle tag in an on-chip memory.

5. The method according to claim 4, in, The authentication credential is generated by the server based on the online challenge value and the user information, and the authentication credential includes a user seal as a public key generated based on the user information and the salt value. The first signature is generated by the server using the online authentication private key to sign the concatenation result of the online challenge value and the authentication credential.

6. A chip, comprising: On-chip memory; an authentication unit configured to: receive an authentication request from a debugger, and in response to the authentication request being an offline authentication request, perform offline authentication based on an authentication credential generated through online authentication, wherein the authentication credential includes access control information of the chip and a user seal generated based on user information; and The global access controller is configured to: enable the debugger to access the chip resources based on the access control information after authentication, In order to perform offline authentication, the authentication unit is configured as follows: sending an offline challenge value to a debugger, wherein the offline challenge value is generated based on the chip identifier, receiving from the debugger a second signature corresponding to the offline challenge value, The second signature is verified based on the offline challenge value using the user seal included in the authentication credential as the offline authentication public key.

7. The chip according to claim 6, wherein: To perform offline authentication, the authentication unit is also configured to: After receiving the offline authentication request, verify the authentication credentials; In response to verification of the authentication credentials, an offline challenge value is sent to the debugger.

8. The chip according to claim 7, wherein: To verify the authentication credentials, the authentication unit is configured to: The periodic label generated by online authentication is spliced ​​with the authentication credential to form a first splicing result. Use the pre-installed online authentication public key to verify whether the first signature corresponds to the hash value of the first concatenation result, The first signature is generated by the server during online authentication.

9. The chip according to claim 8, wherein: The authentication unit is also configured to: In response to the authentication request being an online authentication request, performing online authentication, When the online authentication is passed, the authentication credential and the first signature corresponding to the authentication credential are saved.

10. The chip according to claim 9, wherein: To perform online authentication, the authentication unit is configured to: Sending an online challenge value to the debugger, where the online challenge value is generated based on the chip identifier; receiving, from the debugger, authentication credentials and a first signature generated by the server; Verifying the first signature using a pre-installed online certification public key; In response to the first signature being verified successfully, the authentication credential and the first signature are stored in an off-chip memory, and the online challenge value is stored as a period tag in an on-chip memory; Send verification results to the debugger.

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