A double-sided TFT pixel driving circuit with improved aperture ratio
By setting the first sub-circuit and the second sub-circuit on the upper substrate and the lower substrate in the double-sided TFT pixel driving circuit, respectively, to overlap in the light output direction, the problem of low opening rate of the traditional pixel driving circuit is solved, and a higher opening rate and lower GOA driving difficulty is achieved.
Patent Information
- Application Number
- CN202411594531.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-09
- Publication Date
- 2025-04-04
AI Technical Summary
The conventional pixel driving circuit that can realize pre-storing of pixel voltages has a problem of low opening rate.
By providing a first sub-circuit and a second sub-circuit for driving adjacent sub-pixels on the upper substrate and the lower substrate, respectively, such that they overlap in the light exit direction of the pixel driving circuit, so that each two adjacent sub-pixels are affected only by one sub-circuit.
It greatly improves the pixel opening rate, reduces the computing power load of the peripheral GOA circuit, simplifies the difficulty of GOA driving, and is conducive to the implementation of high resolution and high refresh.
Smart Images
Figure CN119763462A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of pixel driving technology, and in particular to a double-sided TFT pixel driving circuit capable of improving aperture ratio. Background Art
[0002] Field sequential or color sequential display driving technology uses the residual effect of human visual pause to directly mix the RGB three-color light source to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other.
[0003] Under the field sequential technology route, the traditional pixel driving circuit capable of pre-storing pixel voltage needs to set up a pre-storage capacitor and its corresponding transistor for controlling charge sharing. Since the pre-storage capacitor needs to ensure the voltage accuracy of the final pixel capacitor, the capacitance of the pre-storage capacitor needs to be set larger, which has a significant impact on the aperture ratio of the pixel driving circuit, ultimately resulting in the aperture ratio of the traditional pixel driving circuit capable of pre-storing pixel voltage being much smaller than the traditional 1T2C pixel driving circuit.
[0004] In summary, the conventional pixel driving circuit capable of implementing pixel voltage pre-storage has the problem of low aperture ratio. Summary of the invention
[0005] In view of this, the present invention provides a double-sided TFT pixel driving circuit with improved aperture ratio, which solves the problem of low aperture ratio existing in the traditional pixel driving circuit capable of pre-storing pixel voltage by improving the circuit structure and driving timing.
[0006] To solve the above problems, the technical solution of the present invention is to adopt a double-sided TFT pixel driving circuit with improved aperture ratio, wherein the minimum repeating circuit unit of the pixel driving circuit includes: a first sub-circuit arranged on an upper substrate and a second sub-circuit arranged on a lower substrate, wherein the upper substrate and the lower substrate are both array substrates; the first sub-circuit and the second sub-circuit are respectively used to drive adjacent sub-pixels; the first sub-circuit and the second sub-circuit overlap in the light emitting direction of the pixel driving circuit.
[0007] Optionally, the first sub-circuit is configured as: arranged on an upper substrate, including a first transistor and a second transistor, wherein the first source and drain of the first transistor are coupled to a first data signal line, the second source and drain are coupled to a first pre-storage capacitor and a first source and drain of the second transistor, and the gate is coupled to a first control signal line; the second source and drain of the second transistor are coupled to a first pixel capacitor and a first holding capacitor, and the gate is coupled to a first transfer signal line.
[0008] Optionally, the second sub-circuit is configured as: arranged on the lower substrate, including a third transistor and a fourth transistor, wherein the first source and drain of the third transistor are coupled to the second data signal line, the second source and drain are coupled to the second pre-storage capacitor, and the gate is coupled to the second control signal line; the second source and drain of the fourth transistor are coupled to the second pixel capacitor and the second holding capacitor, and the gate is coupled to the second transfer signal line.
[0009] Optionally, one end of the first pre-storage capacitor, the first pixel capacitor and the first holding capacitor away from the transistor is coupled to a first common signal line.
[0010] Optionally, one end of the second pre-storage capacitor, the second pixel capacitor and the second holding capacitor away from the transistor is coupled to the second common signal line.
[0011] Optionally, the driving timing of the pixel driving circuit is configured as follows: in the backlight-on stage of the Nth frame, the first control signal and the second control signal synchronously jump to a high potential, the first transistor and the third transistor are synchronously turned on, the first data signal line stores the first data signal containing the grayscale voltage to the first pre-storage capacitor through the first transistor, and the second data signal line stores the second data signal containing the grayscale voltage to the second pre-storage capacitor through the third transistor, and the first control signal and the second control signal synchronously jump back to a low potential; in the backlight-off stage of the Nth frame, the first transfer signal and the second transfer signal synchronously jump to a high potential, the second transistor and the fourth transistor are turned on, the first pre-storage capacitor transmits the first data signal containing the grayscale voltage to the first pixel capacitor through the second transistor, and after the second pre-storage capacitor transmits the second data signal containing the grayscale voltage to the second pixel capacitor through the fourth transistor, the first transfer signal and the second transfer signal jump back to a low potential, entering the backlight-on stage of the N+1th frame.
[0012] Optionally, in the positive polarity frame: in the backlight-on stage, the first common signal and the second common signal are configured to 0; in the backlight-off stage, after the first transfer signal and the second transfer signal jump back to a low potential, the first common signal and the second common signal jump to Vop-max, wherein Vop-max is the driving voltage required for the maximum grayscale of the pixel.
[0013] Optionally, in the negative polarity frame: in the backlight-on stage, the first common signal and the second common signal are configured as Vop-max; in the backlight-off stage, after the first transfer signal and the second transfer signal jump back to a low potential, the first common signal and the second common signal jump to 0.
[0014] Optionally, the first sub-circuit can also be configured as: arranged on an upper substrate, including a first transistor, a second transistor and a fifth transistor, wherein the first source and drain of the first transistor are coupled to the first data signal line, the second source and drain are coupled to the first pre-storage capacitor and the first source and drain of the second transistor, and the gate is coupled to the first control signal line; the second source and drain of the second transistor are coupled to the first pixel capacitor and the first holding capacitor, and the gate is coupled to the first transfer signal line; the first source and drain of the fifth transistor are coupled to the first pixel capacitor and the first holding capacitor, the gate is coupled to the first reset signal line, and the second source and drain are coupled to the first common signal line.
[0015] Optionally, the second sub-circuit can also be configured as: arranged on the lower substrate, including a third transistor, a fourth transistor and a sixth transistor, wherein the first source and drain of the third transistor are coupled to the second data signal line, the second source and drain are coupled to the second pre-storage capacitor, and the gate is coupled to the second control signal line; the second source and drain of the fourth transistor are coupled to the second pixel capacitor and the second holding capacitor, and the gate is coupled to the second transfer signal line; the first source and drain of the sixth transistor are coupled to the second pixel capacitor and the second holding capacitor, the gate is coupled to the second reset signal line, and the second source and drain are coupled to the second common signal line.
[0016] The primary improvement of the present invention is to provide a double-sided TFT pixel driving circuit with improved aperture ratio, by arranging the first sub-circuit and the second sub-circuit for driving adjacent sub-pixels on the upper substrate and the lower substrate respectively, so that the first sub-circuit and the second sub-circuit overlap in the light emitting direction of the pixel driving circuit (the vertical observation direction of the substrate), so that the aperture ratio of every two adjacent sub-pixels in the light emitting direction of the pixel driving circuit is only affected by one sub-circuit, which greatly improves the pixel aperture ratio and solves the problem of low aperture ratio existing in the traditional pixel driving circuit capable of realizing pixel voltage pre-storage.
[0017] And because the first control signal of the first sub-circuit and the second control signal of the second sub-circuit can be configured to jump synchronously, the computing power load of the peripheral GOA circuit required by the present invention is half of that of the traditional pixel driving circuit, which reduces the difficulty of GOA driving and is conducive to the realization of high resolution and high refresh. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 is a simplified circuit diagram of a pixel driving circuit according to Embodiment 1 of the present invention; Figure 2 is a simplified structural cross-sectional view of a pixel driving circuit according to Embodiment 1 of the present invention; Figure 3 is a simplified driving timing diagram of the pixel driving circuit of embodiment 1 of the present invention; Figure 4 is a schematic diagram of pixel combination of the pixel driving circuit in the TN / VA mode according to the embodiment 1 of the present invention; Figure 5 is a schematic diagram of pixel combination of the pixel driving circuit in the IPS / FFS mode according to the embodiment 1 of the present invention; Figure 6 is a simplified circuit diagram of a pixel driving circuit according to Embodiment 2 of the present invention; Figure 7 3 is a circuit diagram of a pixel driving circuit according to Embodiment 3 of the present invention. DETAILED DESCRIPTION
[0019] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0022] The following embodiments of the technical solution of the present application will be described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.
[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.
[0024] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.
[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0026] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship. Example 1
[0027] Specifically, Figure 1 As shown, a double-sided TFT pixel driving circuit with improved aperture ratio, the minimum repeating circuit unit of the pixel driving circuit includes: a first sub-circuit arranged on an upper substrate and a second sub-circuit arranged on a lower substrate.
[0028] Specifically, the upper substrate and the lower substrate are both array substrates.
[0029] Specifically, as shown in the simplified circuit structure Figure 2 As shown, the first sub-circuit and the second sub-circuit are respectively used to drive adjacent sub-pixels, and the first sub-circuit and the second sub-circuit overlap in the light emitting direction of the pixel driving circuit. The present invention arranges the first sub-circuit and the second sub-circuit for driving adjacent sub-pixels on the upper substrate and the lower substrate respectively, so that the first sub-circuit and the second sub-circuit overlap in the light emitting direction of the pixel driving circuit (the vertical observation direction of the substrate), so that the aperture ratio of every two adjacent sub-pixels in the light emitting direction of the pixel driving circuit is affected by only one sub-circuit, which greatly improves the pixel aperture ratio and solves the problem of low aperture ratio in the traditional pixel driving circuit capable of realizing pixel voltage pre-storage.
[0030] Furthermore, the first subcircuit and the second subcircuit can drive sub-pixels of adjacent columns or adjacent rows, respectively. When the first subcircuit and the second subcircuit drive sub-pixels of adjacent columns, respectively, since the first control signal of the first subcircuit and the second control signal of the second subcircuit can be configured to jump synchronously, the computing power load of the peripheral GOA circuit required by the present invention is half of that of the traditional pixel driving circuit, which reduces the difficulty of GOA driving and is conducive to the realization of high resolution and high refresh.
[0031] Further, the first sub-circuit is configured as: arranged on an upper substrate, including a first transistor T1 and a second transistor T2, wherein the first source and drain of the first transistor T1 are coupled to the first data signal line Data1, the second source and drain are coupled to the first pre-storage capacitor C1 and the first source and drain of the second transistor T2, and the gate is coupled to the first control signal line Scan1; the second source and drain of the second transistor T2 are coupled to the first pixel capacitor Clc1 and the first holding capacitor C2, and the gate is coupled to the first transfer signal line Tran1.
[0032] Further, the second sub-circuit is configured as: arranged on the lower substrate, including a third transistor T3 and a fourth transistor T4, wherein the first source and drain of the third transistor T3 are coupled to the second data signal line Data2, the second source and drain are coupled to the second pre-storage capacitor C3, and the gate is coupled to the second control signal line Scan2; the second source and drain of the fourth transistor T4 are coupled to the second pixel capacitor Clc2 and the second holding capacitor C4, and the gate is coupled to the second transfer signal line Tran2.
[0033] Furthermore, the first pre-storage capacitor C1, the first pixel capacitor Clc1 and the first holding capacitor C2 are coupled to the first common signal line Com1 at one end away from the transistor. The second pre-storage capacitor C3, the second pixel capacitor Clc2 and the second holding capacitor C4 are coupled to the second common signal line Com2 at one end away from the transistor.
[0034] Furthermore, Figure 3 As shown, the driving timing of the pixel driving circuit is configured as follows: In the backlight-on stage of the Nth frame, the first control signal and the second control signal synchronously jump to a high potential, the first transistor T1 and the third transistor T3 are synchronously turned on, the first data signal line data1 stores the first data signal including the grayscale voltage to the first pre-storage capacitor C1 through the first transistor T1, the second data signal line data2 stores the second data signal including the grayscale voltage to the second pre-storage capacitor C3 through the third transistor T3, and the first control signal and the second control signal synchronously jump back to a low potential; In the backlight off stage of the Nth frame, the first transfer signal and the second transfer signal synchronously jump to a high potential, the second transistor T2 and the fourth transistor T4 are turned on, the first pre-storage capacitor C1 transmits the first data signal containing the grayscale voltage to the first pixel capacitor Clc1 through the second transistor T2, and the second pre-storage capacitor C3 transmits the second data signal containing the grayscale voltage to the second pixel capacitor C3 through the fourth transistor T4. Then, the first transfer signal and the second transfer signal jump back to a low potential, and enter the backlight on stage of the N+1th frame.
[0035] It should be noted here that the driving timings of the first sub-circuit and the second transfer signal sub-circuit in this embodiment can be independent of each other (for example, the first control signal and the second control signal can jump independently, and the same applies to the transfer signal). The above driving timing is only to show a preferred implementation method that can reduce the difficulty of GOA driving. The present invention does not specifically limit the driving timing of the pixel driving circuit.
[0036] It should be noted here that, in this embodiment, the high potential is defined as a potential that can ensure that the N-type MOS tube is turned on after writing.
[0037] It should be noted here that if Figure 4 and Figure 5 As shown, the pixel driving circuit claimed in the present invention can be used for panels of various modes, such as TN / VA / IPS / FFS.
[0038] Furthermore, in order to reduce the Data range, the common signal can be further configured as follows by reducing the charge transfer amount: in the positive polarity frame, during the backlight-on stage, the first common signal and the second common signal are configured to 0, and during the backlight-off stage, after the first transfer signal and the second transfer signal jump back to a low potential, the first common signal and the second common signal jump to Vop-max, wherein Vop-max is the driving voltage required for the maximum grayscale of the pixel; in the negative polarity frame, during the backlight-on stage, the first common signal and the second common signal are configured to Vop-max, and during the backlight-off stage, after the first transfer signal and the second transfer signal jump back to a low potential, the first common signal and the second common signal jump to 0. Example 2
[0039] Specifically, Figure 6 As shown, this embodiment provides a double-sided TFT pixel driving circuit with improved aperture ratio, wherein the minimum repeating circuit unit of the pixel driving circuit comprises: a first sub-circuit arranged on the upper substrate and a second sub-circuit arranged on the lower substrate.
[0040] Further, the first sub-circuit can also be configured as: arranged on an upper substrate, including a first transistor T1, a second transistor T2 and a fifth transistor T5, wherein the first source and drain of the first transistor T1 are coupled to the first data signal line Data1, the second source and drain are coupled to the first pre-storage capacitor C1 and the first source and drain of the second transistor T2, and the gate is coupled to the first control signal line Scan1; the second source and drain of the second transistor T2 are coupled to the first pixel capacitor Clc1 and the first holding capacitor C2, and the gate is coupled to the first transfer signal line Tran1; the first source and drain of the fifth transistor T5 are coupled to the first pixel capacitor Clc1 and the first holding capacitor C2, the gate is coupled to the first reset signal line Reset1, and the second source and drain are coupled to the first common signal line Com1.
[0041] Further, the second sub-circuit is configured as: arranged on the lower substrate, including a third transistor T3, a fourth transistor T4 and a sixth transistor T6, wherein the first source and drain of the third transistor T3 are coupled to the second data signal line Data2, the second source and drain are coupled to the second pre-storage capacitor C3, and the gate is coupled to the second control signal line Scan2; the second source and drain of the fourth transistor T4 are coupled to the second pixel capacitor Clc2 and the second holding capacitor C4, and the gate is coupled to the second transfer signal line Tran2; the first source and drain of the sixth transistor T6 are coupled to the second pixel capacitor Clc2 and the second holding capacitor C4, the gate is coupled to the second reset signal line Reset2, and the second source and drain are coupled to the second common signal line Com2.
[0042] Specifically, the driving timing of the pixel driving circuit claimed in this embodiment is substantially the same as the driving timing of Embodiment 1, and only the reset signal needs to be configured to jump before the transfer signal jumps, so it will not be described in detail.
[0043] It should be noted that the purpose of illustrating the pixel driving circuit claimed for protection in Example 2 in the present application is to illustrate that the pixel driving circuit claimed for protection in the present application is applicable to various types of sub-circuits, and other first sub-circuits and second sub-circuits with adaptively changed structures are within the protection scope of the present application. Example 3
[0044] Specifically, Figure 7 As shown, a double-sided TFT pixel driving circuit with improved aperture ratio, the minimum repeating circuit unit of the pixel driving circuit includes: a first sub-circuit arranged on an upper substrate, a second sub-circuit arranged on a lower substrate, and a third sub-circuit arranged on the upper substrate or the lower substrate.
[0045] Specifically, the first subcircuit and the second subcircuit overlap in the light emitting direction of the pixel driving circuit. The present invention arranges the first subcircuit and the second subcircuit for driving adjacent sub-pixels on the upper substrate and the lower substrate respectively, so that the first subcircuit and the second subcircuit overlap in the light emitting direction of the pixel driving circuit (the vertical observation direction of the substrate), so that the aperture ratio of every three adjacent sub-pixels in the light emitting direction of the pixel driving circuit is affected by only two subcircuits.
[0046] It should be noted that, although the aperture ratio of the pixel driving circuit in this embodiment is significantly improved compared with the conventional pixel driving circuit capable of pre-storing pixel voltage, it is lower than the aperture ratio of the pixel driving circuit in Embodiment 1. The purpose of illustrating the pixel driving circuit in Embodiment 3 in this application is to illustrate that the minimum repeating unit of the pixel driving circuit can be not only two sub-circuits, but also N sub-circuits, where N≥2. Therefore, the technical solutions of arranging the complete sub-circuits corresponding to adjacent sub-pixels on the upper and lower substrates respectively to improve the aperture ratio should all fall within the protection scope required by this application.
[0047] It should be noted here that in each embodiment of the present application, the backlight emits R, G, and B three-color lights frame by frame, and the visual persistence effect of the human eye is used to display a color image, wherein the order of the R, G, and B backlights can be swapped.
[0048] The above is a double-sided TFT pixel driving circuit for improving the aperture ratio provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
[0049] Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly implemented with a software module executed by a hardware or processor, or a combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.
Claims
1. A double-sided TFT pixel driving circuit for improving aperture ratio, characterized in that: The minimum repeating circuit unit of the pixel driving circuit comprises: a first sub-circuit arranged on the upper substrate and a second sub-circuit arranged on the lower substrate, wherein: The upper substrate and the lower substrate are both array substrates; The first sub-circuit and the second sub-circuit are respectively used to drive adjacent sub-pixels; The first sub-circuit and the second sub-circuit overlap in the light emitting direction of the pixel driving circuit.
2. The pixel driving circuit according to claim 1, characterized in that: The first sub-circuit is configured as follows: disposed on an upper substrate, comprising a first transistor (T1) and a second transistor (T2), wherein: The first source and drain of the first transistor (T1) are coupled to the first data signal line (Data1), the second source and drain are coupled to the first pre-storage capacitor (C1) and the first source and drain of the second transistor (T2), and the gate is coupled to the first control signal line (Scan1); The second source and drain of the second transistor (T2) are coupled to the first pixel capacitor (Clc1) and the first holding capacitor (C2), and the gate is coupled to the first transfer signal line (Tran1).
3. The pixel driving circuit according to claim 2, characterized in that: The second sub-circuit is configured as follows: disposed on the lower substrate, including a third transistor (T3) and a fourth transistor (T4), wherein: The first source and drain of the third transistor (T3) are coupled to the second data signal line (Data2), the second source and drain are coupled to the second pre-storage capacitor (C3), and the gate is coupled to the second control signal line (Scan2); The second source and drain of the fourth transistor (T4) are coupled to the second pixel capacitor (Clc2) and the second holding capacitor (C4), and the gate is coupled to the second transfer signal line (Tran2).
4. The pixel driving circuit according to claim 3, characterized in that: The first pre-storage capacitor (C1), the first pixel capacitor (Clc1) and the first holding capacitor (C2) are coupled to a first common signal line (Com1) at one end away from the transistor.
5. The pixel driving circuit according to claim 4, characterized in that: The second pre-storage capacitor (C3), the second pixel capacitor (Clc2) and the second holding capacitor (C4) are coupled to the second common signal line (Com2) at one end away from the transistor.
6. The pixel driving circuit according to claim 5, characterized in that: The driving timing of the pixel driving circuit is configured as follows: In the backlight-on stage of the Nth frame, the first control signal and the second control signal are synchronously changed to a high potential, the first transistor (T1) and the third transistor (T3) are synchronously turned on, the first data signal line (data1) stores the first data signal containing the grayscale voltage to the first pre-storage capacitor (C1) through the first transistor (T1), the second data signal line (data2) stores the second data signal containing the grayscale voltage to the second pre-storage capacitor (C3) through the third transistor (T3), and the first control signal and the second control signal are synchronously changed back to a low potential; In the backlight off stage of the Nth frame, the first transfer signal and the second transfer signal synchronously jump to a high potential, the second transistor (T2) and the fourth transistor (T4) are turned on, the first pre-storage capacitor (C1) transmits the first data signal containing the grayscale voltage to the first pixel capacitor (Clc1) through the second transistor (T2), and the second pre-storage capacitor (C3) transmits the second data signal containing the grayscale voltage to the second pixel capacitor (C3) through the fourth transistor (T4), and then the first transfer signal and the second transfer signal jump back to a low potential, entering the backlight on stage of the N+1th frame.
7. The pixel driving circuit according to claim 6, characterized in that: In positive polarity frame: In the backlight on stage, the first common signal and the second common signal are configured to be 0; In the backlight off stage, after the first transfer signal and the second transfer signal jump back to a low potential, the first common signal and the second common signal jump to Vop-max, where Vop-max is the driving voltage required for the maximum grayscale of the pixel.
8. The pixel driving circuit according to claim 3, characterized in that: In negative polarity frame: In the backlight-on stage, the first common signal and the second common signal are configured as Vop-max; In the backlight off stage, after the first transfer signal and the second transfer signal jump back to a low potential, the first common signal and the second common signal jump to 0.
9. The pixel driving circuit according to claim 1, characterized in that: The first sub-circuit is configured as follows: disposed on an upper substrate, comprising a first transistor (T1), a second transistor (T2) and a fifth transistor (T5), wherein: The first source and drain of the first transistor (T1) are coupled to the first data signal line (Data1), the second source and drain are coupled to the first pre-storage capacitor (C1) and the first source and drain of the second transistor (T2), and the gate is coupled to the first control signal line (Scan1); The second source and drain of the second transistor (T2) are coupled to the first pixel capacitor (Clc1) and the first holding capacitor (C2), and the gate is coupled to the first transfer signal line (Tran1); the first source and drain of the fifth transistor (T5) are coupled to the first pixel capacitor (Clc1) and the first holding capacitor (C2), the gate is coupled to the first reset signal line (Reset1), and the second source and drain are coupled to the first common signal line (Com1).
10. The pixel driving circuit according to claim 9, characterized in that: The second sub-circuit is configured as follows: disposed on the lower substrate, including a third transistor (T3), a fourth transistor (T4) and a sixth transistor (T6), wherein: The first source and drain of the third transistor (T3) are coupled to the second data signal line (Data2), the second source and drain are coupled to the second pre-storage capacitor (C3), and the gate is coupled to the second control signal line (Scan2); The second source and drain of the fourth transistor (T4) are coupled to the second pixel capacitor (Clc2) and the second holding capacitor (C4), and the gate is coupled to the second transfer signal line (Tran2); the first source and drain of the sixth transistor (T6) are coupled to the second pixel capacitor (Clc2) and the second holding capacitor (C4), the gate is coupled to the second reset signal line (Reset2), and the second source and drain are coupled to the second common signal line (Com2).