Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, belongs to the technical field of design and display, and aims to optimize the layout design of the display panel and achieve higher PPI. The display panel comprises: a circuit unit comprising M pixel circuits arranged along a first direction, M being an integer greater than or equal to 2; the data line comprises a first data line and a second data line, and the pixel circuit is electrically connected with the first data line and the second data line; wherein the data lines which are adjacent in the first direction and are not spaced by the pixel circuits at most comprise M-1 first data lines which are electrically connected with the same circuit unit, and / or at most comprise M-1 second data lines which are electrically connected with the same circuit unit; or at least one pixel circuit is provided with the first data line and the second data line which are electrically connected with the circuit unit where the pixel circuit is located on the two opposite sides in the first direction.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] To improve display effects, currently, display panels can be driven by combining pulse amplitude modulation (Pulse Amplitude Modulation, PAM) and pulse width modulation (Pulse Width Modulation, PWM).

[0003] However, the pixel circuit structure in this type of display panel is complex and the number of connected signal lines is also large, which limits the PPI of the display panel. In order to pursue a higher PPI, layout optimization of the display panel becomes particularly important. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device, which can optimize the layout design of the display panel to achieve a higher PPI.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0006] A circuit unit, comprising M pixel circuits arranged along a first direction, where M is an integer greater than or equal to 2;

[0007] Data lines, including a first data line and a second data line, the pixel circuits being electrically connected to the first data line and the second data line respectively;

[0008] Among the data lines adjacent to each other in the first direction and not separated by the pixel circuit, at most M-1 of the first data lines are electrically connected to the same circuit unit, and / or at most M-1 of the second data lines are electrically connected to the same circuit unit;

[0009] Alternatively, at least one of the pixel circuits is provided with the first data line and the second data line electrically connected to the circuit unit in which the pixel circuit is located on two opposite sides in the first direction.

[0010] In a second aspect, based on the same inventive concept, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0011] The technical solution provided by the embodiment of the present invention has the following beneficial effects:

[0012] Regarding “among the data lines adjacent to each other in the first direction and without pixel circuits spaced apart, at most M-1 first data lines electrically connected to the same circuit unit are included, and / or, at most M-1 second data lines electrically connected to the same circuit unit are included”:

[0013] The data lines that are adjacent to each other in the first direction and have no pixel circuits between them are defined as a data line group.

[0014] In the embodiment of the present invention, the display panel includes a data line group A', which includes at most M-1 first data lines electrically connected to the same circuit unit and / or at most M-1 second data lines electrically connected to the same circuit unit.

[0015] Under this arrangement, above the circuit unit, at most only M-1 first connection lines corresponding to M-1 pixel circuits need to turn toward the left to be electrically connected to the first data line at the data line group A', and the first connection lines corresponding to the remaining pixel circuits turn toward the right to be electrically connected to the first data line, so that at most only M-1 first connection lines will overlap in the second direction, and the M first connection lines will only occupy a vertical height of (M-1)×(k1+k2) above the circuit unit at most. And / or, below the circuit unit, at most only M-1 second connection lines corresponding to M-1 pixel circuits need to turn toward the right to be electrically connected to the second data line at the data line group A', and the second connection lines corresponding to the remaining pixel circuits turn toward the left to be electrically connected to the second data line, so that at most only M-1 second connection lines will overlap in the second direction, and the M second connection lines will only occupy a vertical height of (M-1)×(k3+k4) below the circuit unit at most.

[0016] The upper part and the lower part of the circuit unit may be understood as two opposite sides of the circuit unit in the second direction.

[0017] k1 is the line width of the first connecting line, k2 is the avoidance distance between the first connecting line and other lines in the second direction, which can also be understood as the spacing between two adjacent first connecting lines in the second direction y. k3 is the line width of the second connecting line, k4 is the avoidance distance between the second connecting line and other lines in the second direction, which can also be understood as the spacing between two adjacent second connecting lines in the second direction.

[0018] Regarding “at least one pixel circuit is provided with a first data line and a second data line electrically connected to the circuit unit in which the pixel circuit is located on two opposite sides in the first direction”:

[0019] In an embodiment of the present invention, at least one pixel circuit is provided with a first data line and a second data line electrically connected to its circuit unit on one side in the first direction, and the pixel circuit is also provided with a first data line and a second data line electrically connected to its circuit unit on the other side in the first direction.

[0020] This means that the M first data lines connected to the circuit unit are dispersedly arranged on two opposite sides of at least one pixel circuit, and the M second data lines connected to the circuit unit are also dispersedly arranged on two opposite sides of at least one pixel circuit.

[0021] Among the M first data lines connected to the circuit unit, some of the first connection lines turn toward the left to be electrically connected to the first data line, and some of the first connection lines turn toward the right to be electrically connected to the first data line. Among the M second data lines connected to the circuit unit, some of the second connection lines turn toward the right to be electrically connected to the second data line, and some of the second connection lines turn toward the left to be electrically connected to the second data line.

[0022] This means that above the circuit unit, at most only the M-1 first connection lines corresponding to the M-1 pixel circuits will overlap in the second direction, and the M first connection lines will occupy at most (M-1)×(k1+k2) vertical height above the circuit unit. Below the circuit unit, at most only the M-1 second connection lines corresponding to the M-1 pixel circuits will overlap with each other in the second direction, and the M second connection lines will occupy at most (M-1)×(k3+k4) vertical height below the circuit unit.

[0023] As can be seen from the above, by adopting the technical solution provided in the embodiment of the present invention, at least k1+k2 of the vertical height can be saved above the circuit unit, and / or at least k3+k4 of the vertical height can be saved below the circuit unit. The vertical height of the pixel in the embodiment of the present invention is at least k1+k2+k3+k4 less than the vertical height of the pixel in the related art. The saved layout space can be used to set more pixels, thereby effectively improving the PPI of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0025] Figure 1 A schematic diagram of a structure of a display panel in the related art;

[0026] Figure 2A A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0027] Figure 2B Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0028] Figure 3A A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0029] Figure 3B A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0030] Figure 4A A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0031] Figure 4B A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0032] Figure 5A A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0033] Figure 5B A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0034] Fig. 6A A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0035] Figure 6B A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0036] Figure 7 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0037] Figure 8 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0038] Fig. 9 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0039] Fig.10 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0040] Fig.11 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0041] Fig.12 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0042] Fig.13 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0043] Fig.14 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0044] Fig.15 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0045] Fig.16 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0046] Fig.17 A schematic diagram of a circuit structure of a first electrostatic protection circuit provided by an embodiment of the present invention;

[0047] Fig.18 A schematic diagram of a circuit structure of a second electrostatic protection circuit provided by an embodiment of the present invention;

[0048] Fig.19 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention;

[0049] Fig. 20 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0053] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0054] As described in the background art, current display panels can be driven by a driving method that combines PAM and PWM.

[0055] like Figure 1 As shown, Figure 1This is a structural schematic diagram of a display panel in the related technology. The data line Data in this type of display panel includes a first data line Data1 and a second data line Data2. One of the first data line Data1 and the second data line Data2 is used to transmit the PAM data voltage required for PAM driving, and the other is used to transmit the PWM data voltage required for PWM driving.

[0056] The pixel circuit 01 is electrically connected to the first data line Data1 through the first connection line 03 , and is electrically connected to the second data line Data2 through the second connection line 04 .

[0057] In the related art, the first data line Data1 connected to the M pixel circuits 01 in the circuit unit 02 is usually set on one side of the circuit unit 02 in the first direction x, and the first data line Data1 connected to the M pixel circuits 01 in the circuit unit 02 is set on the other side of the circuit unit 02 in the first direction x, where M is an integer greater than or equal to 2.

[0058] However, the inventors found during the research process that based on this arrangement of the data lines Data, the circuit unit 02 requires a larger wiring space on both sides of the circuit unit 02 in the second direction y, resulting in a larger vertical height of the pixel.

[0059] The following description is made by taking the example that the first data line Data1 connected to the M pixel circuits 01 in the circuit unit 02 is located on the left side of the circuit unit 02 and the second data line Data2 connected to the M pixel circuits 01 is located on the right side of the circuit unit 02 .

[0060] Under this arrangement, in the circuit unit 02, the M first connection lines 03 corresponding to the M pixel circuits 01 need to turn to the left above the circuit unit 02 to connect with the first data line Data1, which will cause the M first connection lines 03 to overlap each other in the second direction y, resulting in the M first connection lines 03 occupying at least M×(k1+k2) vertical heights above the circuit unit 02. Among them, k1 is the line width of the first connection line 03, and k2 is the avoidance distance between the first connection line 03 and other wirings in the second direction y, which can also be understood as the spacing between two adjacent first connection lines 03 in the second direction y.

[0061] Similarly, in the circuit unit 02, the M second connection lines 04 corresponding to the M pixel circuits 01 need to turn to the right below the circuit unit 02 to connect with the second data line Data2, which will cause the M second connection lines 04 to overlap each other in the second direction y, resulting in the M second connection lines 04 occupying at least M×(k3+k4) vertical height below the circuit unit 02. Among them, k3 is the line width of the second connection line 04, and k4 is the avoidance distance between the second connection line 04 and other wirings in the second direction y, which can also be understood as the spacing between two adjacent second connection lines 04 in the second direction y. Among them, k3 and k1 can be equal or unequal, and k4 and k2 can be equal or unequal.

[0062] Furthermore, the vertical height H of the pixel is relatively large, which is not conducive to the optimization of PPI.

[0063] In this regard, an embodiment of the present invention provides a display panel, which may be a light emitting diode (LED) display panel or other types of display panels, for example, a micro LED display panel.

[0064] like Figure 2A to Figure 6B As shown, Figure 2A A schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 2B Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 3A A schematic diagram of another structure of a display panel provided in an embodiment of the present invention is shown in FIG. Figure 3B This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 4A This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 4B This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 5A This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 5B This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig. 6A This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 6B This is another structural schematic diagram of a display panel provided by an embodiment of the present invention.

[0065] The display panel includes a circuit unit 1 , and the circuit unit 1 includes M pixel circuits 2 arranged along a first direction x, where M is an integer greater than or equal to 2.

[0066] The display panel further includes data lines Data, the data lines Data include first data lines Data1 and second data lines Data2, and the pixel circuits 2 are electrically connected to the first data lines Data1 and the second data lines Data2, respectively. More specifically, the pixel circuits 2 are electrically connected to the first data lines Data1 through the first connection lines 3, and are electrically connected to the second data lines Data2 through the second connection lines 4.

[0067] Among them, the data lines Data adjacent to each other in the first direction x and not separated by pixel circuits 2 include at most M-1 first data lines Data1 electrically connected to the same circuit unit 1, and / or include at most M-1 second data lines Data2 electrically connected to the same circuit unit 1.

[0068] Alternatively, at least one pixel circuit 2 is provided with a first data line Data1 and a second data line Data2 electrically connected to the circuit unit 1 where the pixel circuit 2 is located on two opposite sides in the first direction x.

[0069] Regarding “among the data lines Data that are adjacent in the first direction x and not separated by pixel circuits 2, at most M-1 first data lines Data1 electrically connected to the same circuit unit 1, and / or at most M-1 second data lines Data2 electrically connected to the same circuit unit 1”:

[0070] The data lines Data that are adjacent to each other in the first direction x and do not separate the pixel circuits 2 are defined as a data line group.

[0071] In the related art, see Figure 1 The display panel includes a data line group A, the data line group A includes M first data lines Data1 electrically connected to the same circuit unit 1, and includes M second data lines Data2 electrically connected to the same circuit unit 1.

[0072] This arrangement makes it possible for the M first connection lines 03 to overlap with each other above the circuit unit 02 along the second direction y, occupying at least a longitudinal height of M×(k1+k2), and for the M second connection lines 04 to overlap with each other below the circuit unit 02, occupying at least a longitudinal height of M×(k3+k4).

[0073] In the embodiment of the present invention, see Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B The display panel includes a data line group A', the data line group A' includes at most M-1 first data lines Data1 electrically connected to the same circuit unit 1, and / or, includes at most M-1 second data lines Data2 electrically connected to the same circuit unit 1.

[0074] Under this arrangement, above the circuit unit 1, at most only the M-1 first connection lines 3 corresponding to the M-1 pixel circuits 2 need to turn toward the left to the data line group A' to be electrically connected to the first data line Data1, and the first connection lines 3 corresponding to the remaining pixel circuits 2 turn toward the right to be electrically connected to the first data line Data1. In this way, at most only the M-1 first connection lines 3 will overlap in the second direction y, and the M first connection lines 3 will only occupy a longitudinal height of at most (M-1)×(k1+k2) above the circuit unit 1. And / or, below the circuit unit 1, at most only the M-1 second connection lines 4 corresponding to the M-1 pixel circuits 2 need to turn toward the right to the data line group A' to be electrically connected to the second data line Data2, and the second connection lines 4 corresponding to the remaining pixel circuits 2 turn toward the left to be electrically connected to the second data line Data2. In this way, at most only the M-1 second connection lines 4 will overlap in the second direction y, and the M second connection lines 4 will only occupy a longitudinal height of (M-1)×(k3+k4) below the circuit unit 1 at most. Among them, k1, k2, k3 and k4 are Figure 2A and Figure 2B Marked in.

[0075] The upper side and the lower side of the circuit unit 1 may be understood as two opposite sides of the circuit unit 1 in the second direction y.

[0076] Regarding “at least one pixel circuit 2 is provided with a first data line Data1 and a second data line Data2 electrically connected to the circuit unit 1 in which the pixel circuit 2 is located on two opposite sides in the first direction x”:

[0077] First, it should be noted that the pixel circuit 2 includes a first side and a second side that are opposite to each other in the first direction x. The above features can be understood as, for at least one pixel circuit 2, a first data line Data1 and a second data line Data2 electrically connected to the circuit unit 1 in which the pixel circuit 2 is located are simultaneously disposed in the first side region of the pixel circuit 2, and these first data lines Data1 and the second data lines Data2 may be adjacent to or not adjacent to the pixel circuit 2 on this side, and a first data line Data1 and a second data line Data2 electrically connected to the circuit unit 1 in which the pixel circuit 2 is located are also simultaneously disposed in the second side region of the pixel circuit 2, and these first data lines Data1 and the second data lines Data2 may be adjacent to or not adjacent to the pixel circuit 2 on this side.

[0078] In the related art, see again Figure 1 On one side of the pixel circuit 2 in the first direction x, only the first data line Data1 electrically connected to the circuit unit 1 in which the pixel circuit 2 is located is provided, or only the second data line Data2 electrically connected to the circuit unit 1 in which the pixel circuit 2 is located is provided.

[0079] This arrangement makes it possible for the M first connection lines 03 to overlap with each other above the circuit unit 02 along the second direction y, occupying at least a longitudinal height of M×(k1+k2), and for the M second connection lines 04 to overlap with each other below the circuit unit 02, occupying at least a longitudinal height of M×(k3+k4).

[0080] In the embodiment of the present invention, at least one pixel circuit 2 is provided with a first data line Data1 and a second data line Data2 electrically connected to the circuit unit 1 in which it is located on one side in the first direction x, and the pixel circuit 2 is also provided with a first data line Data1 and a second data line Data2 electrically connected to the circuit unit 1 in which it is located on the other side in the first direction x.

[0081] This means that the M first data lines Data1 connected to the circuit unit 1 are dispersedly arranged on two opposite sides of at least one pixel circuit 2 , and the M second data lines Data2 connected to the circuit unit 1 are also dispersedly arranged on two opposite sides of at least one pixel circuit 2 .

[0082] Among the M first data lines Data1 connected to the circuit unit 1, some of the first connection lines 3 turn toward the left to be electrically connected to the first data line Data1, and some of the first connection lines 3 turn toward the right to be electrically connected to the first data line Data1. Among the M second data lines Data2 connected to the circuit unit 1, some of the second connection lines 4 turn toward the right to be electrically connected to the second data line Data2, and some of the second connection lines 4 turn toward the left to be electrically connected to the second data line Data2.

[0083] This means that above the circuit unit 1, at most only the M-1 first connection lines 3 corresponding to the M-1 pixel circuits 2 will overlap in the second direction y, and the M first connection lines 3 will occupy at most (M-1)×(k1+k2) vertical height above the circuit unit 1. Below the circuit unit 1, at most only the M-1 second connection lines 4 corresponding to the M-1 pixel circuits 2 will overlap with each other in the second direction y, and the M second connection lines 4 will occupy at most (M-1)×(k3+k4) vertical height below the circuit unit 1.

[0084] It can be seen from the above that by adopting the technical solution provided by the embodiment of the present invention, at least a vertical height of k1+k2 can be saved above the circuit unit 1, and / or at least a vertical height of k3+k4 can be saved below the circuit unit 1. Figure 1 and Figure 2AThe vertical height H' of the pixel in the embodiment of the present invention is at least k1+k2+k3+k4 less than the vertical height H of the pixel in the related art. The saved layout space can be used to set more pixels, thereby effectively improving the PPI of the display panel.

[0085] Moreover, the vertical height of the pixel is compressed, which can reduce the risk of metal circuit damage when laser cutting is required at the edge of the display panel during the manufacturing process. Or in a narrow-frame display panel, the pixel circuit at the edge needs to be designed to be inward, and the vertical height of the pixel is compressed, which can also increase the design flexibility of the frame width.

[0086] In one possible implementation, see Figure 2A to Figure 6B , along the first direction x, there is no other circuit unit 1 between the data line Data and the circuit unit 1 electrically connected thereto. In other words, the data line Data connected to the pixel circuit 2 in the circuit unit 1 is either located between adjacent pixel circuits 2 in the circuit unit 1, or is located on one side of the circuit unit 1 in the first direction x and adjacent to the circuit unit 1.

[0087] This arrangement can make the pixel circuit 2 and the data line Data connected thereto closer to each other, thereby reducing the connection distance between the two and further reducing signal attenuation.

[0088] In one possible implementation, see Figure 2A to Figure 4B In the circuit unit 1, the first data line Data1 electrically connected to at most M-1 pixel circuits 2 is located on the same side of the circuit unit 1 in the first direction x, and may be further adjacent to the circuit unit 1; the second data line Data2 electrically connected to at most M-1 pixel circuits 2 is located on the same side of the circuit unit 1 in the first direction x, and may be further adjacent to the circuit unit 1.

[0089] by Figure 2A and Figure 2B For example, M=2. In the circuit unit 1, the first data line Data1 connected to two pixel circuits 2 and the second data line Data2 connected to one pixel circuit 2 are located on the left side of the circuit unit 1, and the first data line Data1 connected to one pixel circuit 2 and the second data line Data2 connected to two pixel circuits 2 are located on the right side of the circuit unit 1.

[0090] Based on this arrangement, among the M first connection lines 3 connected to the circuit unit 1, at most only M-1 first connection lines 3 need to turn toward the same side to connect to the first data line Data1, and the vertical height above the circuit unit 1 can be compressed by at least k1+k2. Among the M second connection lines 4 connected to the circuit unit 1, at most only M-1 second connection lines 4 need to turn toward the same side to connect to the second data line Data2, and the vertical height below the circuit unit 1 can be compressed by at least k3+k4.

[0091] In one possible implementation, see Figure 2A to Figure 5B , two data lines Data electrically connected to at least one pixel circuit 2 are located on the same side of the pixel circuit 2 in the first direction x, and may further be adjacent to the pixel circuit 2 .

[0092] Therefore, under the premise of compressing the vertical height of the pixel, the distance between at least part of the pixel circuit 2 and the two data lines Data connected thereto is made equal, and the load difference between the first connection line 3 and the second connection line 4 is small.

[0093] With respect to the above design that “the two data lines Data electrically connected to at least one pixel circuit 2 are located on the same side of the pixel circuit 2 in the first direction x”, in a feasible implementation manner, see Figure 2A to Figure 6B , the pixel circuit 2 includes a first pixel circuit 2 -R, a second pixel circuit 2 -G and a third pixel circuit 2 -B.

[0094] The first pixel circuit 2 -R may be electrically connected to a red light emitting device, the second pixel circuit 2 -G may be electrically connected to a green light emitting device, and the third pixel circuit 2 -B may be electrically connected to a blue light emitting device.

[0095] For ease of distinction, in the accompanying drawings of the embodiments of the present invention, the first data lines connected to the first pixel circuit 2-R, the second pixel circuit 2-G, and the third pixel circuit 2-B are respectively labeled with the accompanying drawings markings Data1-R, Data1-G, and Data1-B, and the second data lines connected to the first pixel circuit 2-R, the second pixel circuit 2-G, and the third pixel circuit 2-B are respectively labeled with the accompanying drawings markings Data2-R, Data2-G, and Data2-B.

[0096] The circuit unit 1 includes a first pixel circuit 2 -R, a second pixel circuit 2 -G, and a third pixel circuit 2 -B arranged along a first direction x.

[0097] Among them, the two data lines Data electrically connected to the first pixel circuit 2-R are located on a side of the first pixel circuit 2-R away from the second pixel circuit 2-G, and may be further adjacent to the first pixel circuit 2-R. And / or, the two data lines Data electrically connected to the third pixel circuit 2-B are located on a side of the third pixel circuit 2-B away from the second pixel circuit 2-G, and may be further adjacent to the third pixel circuit 2-B.

[0098] The first pixel circuit 2 -R and the third pixel circuit 2 -B are pixel circuits on the outer sides of the circuit unit 1 . The first pixel circuit 2 -R and the third pixel circuit 2 -B are both closer to one side of the circuit unit 1 and farther from the other side.

[0099] Based on the above arrangement, the first pixel circuit 2-R and the two data lines Data connected thereto are relatively close, and the third pixel circuit 2-B and the two data lines Data connected thereto are relatively close, and the connection wiring between the two pixel circuits and the data lines is relatively convenient, the connection distance is relatively short, and the signal voltage drop is relatively small.

[0100] Further, see Figure 3A and Figure 3B , the two data lines Data electrically connected to the second pixel circuit 2 -G are located at the same side of the circuit unit 1 in the first direction x.

[0101] For example, the first data line Data1-G and the second data line Data2-G are located on a side of the first pixel circuit 2-R away from the second pixel circuit 2-G. Alternatively, the first data line Data1-G and the second data line Data2-G are located on a side of the third pixel circuit 2-B away from the second pixel circuit 2-G.

[0102] contrast Figure 1 and Figure 3B In this arrangement, the data lines Data are evenly distributed in the intervals between the circuit units 1, and 2M data lines Data are evenly distributed in each interval, and the distribution pattern of the data lines is consistent with the distribution pattern of the data lines in the related art. This panel structure can only adjust the connection relationship between the 2M data lines Data in the intervals and the pixel circuits 2 in the circuit units 1 based on the original panel, without additional adjustment for the spacing between the circuit units 1 and the spacing between adjacent pixel circuits 2 in the circuit units 1.

[0103] Further, see Figure 3A and Figure 3BTo avoid the connection distance between the second pixel circuit 2-G and the data line Data being too long, the two data lines Data connected to the second pixel circuit 2-G may be located between the two data lines Data connected to the first pixel circuit 2-R and the first pixel circuit 2-R, or between the two data lines Data connected to the third pixel circuit 2-B and the third pixel circuit 2-B.

[0104] With respect to the above design that “the two data lines Data electrically connected to at least one pixel circuit 2 are located on the same side of the pixel circuit 2 in the first direction x”, in another feasible implementation, see Figure 4A and Figure 4B The pixel circuit 2 includes a first side and a second side in the first direction x. Two data lines Data electrically connected to the pixel circuit 2 are located on the first side of the pixel circuit 2, and no other pixel circuit 2 is spaced between the data lines Data and the pixel circuit 2 connected thereto.

[0105] For example, the first data line Data1-R and the second data line Data2-R are located on a side of the first pixel circuit 2-R away from the second pixel circuit 2-G, and are adjacent to the first pixel circuit 2-R. The first data line Data1-G and the second data line Data2-G are located between the first pixel circuit 2-R and the second pixel circuit 2-G. The first data line Data1-B and the second data line Data2-B are located on a side of the third pixel circuit 2-B away from the second pixel circuit 2-G, and are adjacent to the third pixel circuit 2-B.

[0106] Based on this arrangement, on the one hand, the three first connecting lines 3 connected to the circuit unit 1 have no overlap in the second direction y, and compared with the related art, the longitudinal height of 2×(k1+k2) can be compressed above the circuit unit 1. The three second connecting lines 4 connected to the circuit unit 1 also have no overlap in the second direction y, and compared with the related art, the longitudinal height of 2×(k3+k4) can be compressed below the circuit unit 1, thereby compressing the longitudinal height of the pixel to a smaller size and achieving a higher PPI.

[0107] On the other hand, each pixel circuit 2 and the two data lines Data connected thereto are very close to each other, and the corresponding connection distances are relatively small.

[0108] Among them, the first data line Data1 corresponding to each pixel circuit 2 is closer to the pixel circuit 2 connected thereto, or the second data line Data corresponding to each pixel circuit 2 is closer to the pixel circuit 2 connected thereto, so that the wiring of the connection lines corresponding to different pixel circuits 2 is more regular.

[0109] In one possible implementation, see Figure 2A , Figure 2B , Figure 5A to Figure 6B , two data lines Data electrically connected to at least one pixel circuit 2 are respectively located at two opposite sides of the pixel circuit 2 in the first direction x.

[0110] In other words, for at least part of the pixel circuit 2, a data line Data electrically connected to the pixel circuit 2 is respectively arranged in the area on both sides of the pixel circuit 2 in the first direction x. The two data lines Data may be adjacent to the pixel circuit 2 on both sides of the pixel circuit 2 or may not be adjacent to each other, so as to realize flexible arrangement of the data lines Data.

[0111] With respect to the above-mentioned design that “the two data lines Data electrically connected to at least one pixel circuit 2 are respectively located on two opposite sides of the pixel circuit 2 in the first direction x”, in a feasible implementation manner, see Figure 2A , Figure 2B , Figure 5A to Figure 6B , the pixel circuit 2 includes a first pixel circuit 2 -R, a second pixel circuit 2 -G and a third pixel circuit 2 -B.

[0112] The circuit unit 1 includes a first pixel circuit 2 -R, a second pixel circuit 2 -G, and a third pixel circuit 2 -B arranged along a first direction x.

[0113] The two data lines Data electrically connected to the second pixel circuit 2-G are respectively located on opposite sides of the second pixel circuit 2-G in the first direction x. The first data line Data1-G may be adjacent to or not adjacent to the second pixel circuit 2-G on one side of the second pixel circuit 2-G, and the second data line Data2-G may be adjacent to or not adjacent to the second pixel circuit 2-G on one side of the second pixel circuit 2-G.

[0114] The second pixel circuit 2-G is the pixel circuit 2 in the middle of the circuit unit 1. By adjusting the position of the data line Data connected to it, the number of the first connection lines 3 overlapping in the second direction y and the number of the second connection lines 4 overlapping in the second direction y can be changed more directly. Figure 5A and Figure 5B When the two data lines Data connected to the second pixel circuit 2-G are located on both sides of the second pixel circuit 2-G and are adjacent to the second pixel circuit 2-G, it can be achieved that the three first connection lines 3 have no overlap in the second direction y, and the three second connection lines 4 have no overlap in the second direction y, and the vertical height of the pixel can be compressed to a smaller size.

[0115] With respect to the above-mentioned design that “the two data lines Data electrically connected to at least one pixel circuit 2 are respectively located on two opposite sides of the pixel circuit 2 in the first direction x”, in a feasible implementation manner, see Fig. 6A and Figure 6BThe two data lines Data electrically connected to the pixel circuit 2 are located at opposite sides of the pixel circuit 2 in the first direction x, and no other pixel circuit 2 is spaced between the data line Data and the pixel circuit 2 connected thereto.

[0116] That is, the first data line Data1-R and the second data line Data2-R are respectively located at two opposite sides of the first pixel circuit 2-R in the first direction x and are respectively adjacent to the first pixel circuit 2-R. The first data line Data1-G and the second data line Data2-G are respectively located at two opposite sides of the second pixel circuit 2-G in the first direction x and are respectively adjacent to the second pixel circuit 2-G. The first data line Data1-B and the second data line Data2-B are respectively located at two opposite sides of the third pixel circuit 2-B in the first direction x and are respectively adjacent to the third pixel circuit 2-B.

[0117] Under this arrangement, on the one hand, above the circuit unit 1, the three first connecting lines 3 connected to the circuit unit 1 have no overlap in the second direction y, and compared with the related art, 2×(k1+k2) of the longitudinal height can be saved. Below the circuit unit 1, the three second connecting lines 4 connected to the circuit unit 1 have no overlap in the second direction y, and compared with the related art, 2×(k3+k4) of the longitudinal height can be saved, and the longitudinal height of the pixel can be compressed to a smaller size.

[0118] On the other hand, each pixel circuit 2 and the two data lines Data connected thereto are very close to each other, so the connection and wiring are convenient, the connection distance is short, and the voltage drop is small.

[0119] On the other hand, under this arrangement, two data lines Data are disposed between two adjacent pixel circuits 2 in the first direction x, and the overall distribution of the data lines Data is more uniform.

[0120] In one possible implementation, see Figure 2A , Figure 2B , Figure 5A and Figure 5B , the pixel circuit 2 includes a first pixel circuit 2 -R, a second pixel circuit 2 -G and a third pixel circuit 2 -B.

[0121] The circuit unit 1 includes a first pixel circuit 2 -R, a second pixel circuit 2 -G, and a third pixel circuit 2 -B arranged along a first direction x.

[0122] The two data lines Data electrically connected to the first pixel circuit 2-R are located on a side of the first pixel circuit 2-R away from the second pixel circuit 2-G, and the two data lines Data electrically connected to the third pixel circuit 2-B are located on a side of the third pixel circuit 2-B away from the second pixel circuit 2-G. The two data lines Data electrically connected to the second pixel circuit 2-G are located on opposite sides of the second pixel circuit 2-G in the first direction x.

[0123] Based on the above data line Data arrangement:

[0124] Above the circuit unit 1, the first connection line 3 corresponding to the first pixel circuit 2-R and the third pixel circuit 2-B turns toward different sides to connect to the first data line Data1. The first connection line 3 corresponding to the second pixel circuit 2-G is either Figure 2A and Figure 2B As shown, only the first connection line 3 corresponding to the first pixel circuit 2-R (or the first connection line 3 corresponding to the third pixel circuit 2-B) overlaps in the second direction y, so that a longitudinal height of k1+k2 is saved above the circuit unit 1, or as shown in FIG. Figure 5A As shown in FIG. B , the first connection lines 3 corresponding to the first pixel circuit 2 -R and the third pixel circuit 2 -B do not overlap in the second direction y, so that a vertical height of 2×(k1+k2) is saved above the circuit unit 1 .

[0125] Below the circuit unit 1, the second connection line 4 corresponding to the first pixel circuit 2-R and the third pixel circuit 2-B turns toward different sides to connect to the second data line Data2. The second connection line 4 corresponding to the second pixel circuit 2-G is either Figure 2A and Figure 2B As shown, only the second connection line 4 corresponding to the first pixel circuit 2-R (or the second connection line 4 corresponding to the third pixel circuit 2-B) overlaps in the second direction y, so that a longitudinal height of k3+k4 is saved below the circuit unit 1, or as shown in FIG. Figure 5A As shown in FIG. B , the second connection lines 4 corresponding to the first pixel circuit 2 -R and the third pixel circuit 2 -B do not overlap in the second direction y, so that a vertical height of 2×(k3+k4) is saved above the circuit unit 1 .

[0126] Based on the above solution, in a feasible implementation mode, see Figure 5A and Figure 5B For the two data lines Data electrically connected to the second pixel circuit 2-G, one is located between the first pixel circuit 2-R and the second pixel circuit 2-G, and the other is located between the second pixel circuit 2-G and the third pixel circuit 2-B.

[0127] For example, the first data line Data1-G is located between the first pixel circuit 2-R and the second pixel circuit 2-G, and the second data line Data2-G is located between the second pixel circuit 2-G and the third pixel circuit 2-B. Alternatively, the second data line Data2-G is located between the first pixel circuit 2-R and the second pixel circuit 2-G, and the first data line Data1-G is located between the second pixel circuit 2-G and the third pixel circuit 2-B.

[0128] In this arrangement, above the circuit unit 1, the three first connection lines 3 corresponding to the three pixel circuits 2 do not overlap in the second direction y, and below the circuit unit 1, the three second connection lines 4 corresponding to the three pixel circuits 2 do not overlap in the second direction y. Compared with the related art, the pixels can be compressed by a vertical height of 2×(k1+k2)+2×(k3+k4).

[0129] Or, in another possible implementation, see Figure 2A and Figure 2B , and Figure 7 and Figure 8 As shown, Figure 7 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 8 Another structural schematic diagram of the display panel provided in an embodiment of the present invention, for the two data lines Data electrically connected to the second pixel circuit 2-G, one is located on the side of the first pixel circuit 2-R away from the second pixel circuit 2-G, and the other is located on the side of the third pixel circuit 2-B away from the second pixel circuit 2-G.

[0130] For example, the first data line Data1-G is located at a side of the first pixel circuit 2-R away from the second pixel circuit 2-G, and the second data line Data2-G is located at a side of the third pixel circuit 2-B away from the second pixel circuit 2-G. Alternatively, the second data line Data2-G is located at a side of the first pixel circuit 2-R away from the second pixel circuit 2-G, and the first data line Data1-G is located at a side of the third pixel circuit 2-B away from the second pixel circuit 2-G.

[0131] Based on this arrangement, above the circuit unit 1, the first connection line 3 corresponding to the second pixel circuit 2-G only overlaps with the first connection line 3 corresponding to the first pixel circuit 2-R (or the third pixel circuit 2-B) in the second direction y, and below the circuit unit 1, the second connection line 4 corresponding to the second pixel circuit 2-G only overlaps with the second connection line 4 corresponding to the third pixel circuit 2-B (or the first pixel circuit 2-R) in the second direction y. Compared with the related art, the pixels can be compressed by the vertical height of k1+k2+k3+k4.

[0132] Further, see Figure 8 For the two data lines Data electrically connected to the second pixel circuit 2-G, one of them is located between the two data lines Data electrically connected to the first pixel circuit 2-R, and the other is located between the two data lines Data electrically connected to the third pixel circuit 2-B.

[0133] For example, the first data line Data1-G is located between the first data line Data1-R and the second data line Data2-R, and the second data line Data2-G is located between the first data line Data1-B and the second data line Data2-B. Alternatively, the second data line Data2-G is located between the first data line Data1-R and the second data line Data2-R, and the first data line Data1-G is located between the first data line Data1-B and the second data line Data2-B.

[0134] Under the premise of compressing the vertical height of the pixel, this arrangement can shorten the connection distance between the second pixel circuit 2-G and the corresponding data line Data, thereby reducing the connection distance and the voltage drop.

[0135] Alternatively, see Figure 2A For the two data lines Data electrically connected to the second pixel circuit 2-G, one is located between the first pixel circuit 2-R and the two data lines Data electrically connected thereto, and the other is located between the third pixel circuit 2-B and the two data lines Data electrically connected thereto.

[0136] For example, the first data line Data1-G is located between the first pixel circuit 2-R and the first data line Data1-R and the second data line Data2-R, and the second data line Data2-G is located between the third pixel circuit 2-B and the first data line Data1-B and the second data line Data2-B. Alternatively, the second data line Data2-G is located between the first pixel circuit 2-R and the first data line Data1-R and the second data line Data2-R, and the first data line Data1-G is located between the third pixel circuit 2-B and the first data line Data1-B and the second data line Data2-B.

[0137] Under the premise of compressing the vertical height of the pixel, this arrangement makes the connection distance between the second pixel circuit 2-G and the corresponding data line Data smaller. The smaller the connection distance, the smaller the corresponding signal voltage drop.

[0138] Or, see Figure 7For the two data lines Data electrically connected to the second pixel circuit 2-G, one of them is located on the side of the two data lines Data electrically connected to the first pixel circuit 2-R away from the first pixel circuit 2-R, and the other is located on the side of the two data lines Data electrically connected to the third pixel circuit 2-B away from the third pixel circuit 2-B.

[0139] For example, the first data line Data1-G is located at a side of the first data line Data1-R and the second data line Data2-R away from the first pixel circuit 2-R, and the second data line Data2-G is located at a side of the first data line Data1-B and the second data line Data2-B away from the third pixel circuit 2-B. Alternatively, the second data line Data2-G is located at a side of the first data line Data1-R and the second data line Data2-R away from the first pixel circuit 2-R, and the first data line Data1-G is located at a side of the first data line Data1-B and the second data line Data2-B away from the third pixel circuit 2-B.

[0140] Combined with the above analysis, this arrangement can save the vertical height of k1+k2 above the circuit unit 1 and the vertical height of k3+k4 below the circuit unit 1, thereby optimizing the layout design.

[0141] When the two data lines Data electrically connected to the first pixel circuit 2-R are located on the side of the first pixel circuit 2-R away from the second pixel circuit 2-G, the two data lines Data electrically connected to the third pixel circuit 2-B are located on the side of the third pixel circuit 2-B away from the second pixel circuit 2-G, and the two data lines Data electrically connected to the second pixel circuit 2-G are respectively located on the opposite sides of the second pixel circuit 2-G in the first direction x, in a feasible implementation manner, as Fig. 9 As shown, Fig. 9 This is another structural diagram of a display panel provided by an embodiment of the present invention, in which the pixel circuit 2 includes a pulse amplitude modulation module 5 and a pulse width modulation module 6. The first data line Data1 is electrically connected to the pulse amplitude modulation module 5 through the first connection line 3, and the second data line Data2 is electrically connected to the pulse width modulation module 6 through the second connection line 4.

[0142] The first connection line 3 includes a first portion 7, which extends at least along the first direction x and whose end is electrically connected to the first data line Data1 through a first via hole 8. The second connection line 4 includes a second portion 9, which extends at least along the first direction x and whose end is electrically connected to the second data line Data2 through a second via hole 10.

[0143] The first portion 7 and the second portion 9 corresponding to the pixel circuit 2 are respectively located at two opposite sides of the pixel circuit 2 in a second direction y, and the second direction y intersects with the first direction x.

[0144] The first portion 7 corresponding to the second pixel circuit 2-G and the first portion 7 corresponding to the first pixel circuit 2-R are located on the same side of the circuit unit 1 in the second direction y and overlap along the second direction y. The second portion 9 corresponding to the second pixel circuit 2-G and the first portion 7 corresponding to the third pixel circuit 2-B are located on the same side of the circuit unit 1 in the second direction y and overlap along the second direction y.

[0145] For example, the first portion 7 corresponding to the first pixel circuit 2 -R is located above the circuit unit 1 , and the first portion 7 corresponding to the third pixel circuit 2 -B is located below the circuit unit 1 .

[0146] The first data line Data1-G is located on a side of the first pixel circuit 2-R away from the second pixel circuit 2-G. The first connection lines 3 corresponding to the first pixel circuit 2-R and the second pixel circuit 2-G both turn from the top of the circuit unit 1 toward the left to be electrically connected to the first data line Data1, so that the first portion 7 corresponding to the second pixel circuit 2-G and the first portion 7 corresponding to the first pixel circuit 2-R are both located above the circuit unit 1 and overlap along the second direction y.

[0147] The second data line Data2-G is located on the side of the third pixel circuit 2-B away from the second pixel circuit 2-G. The second connection line 4 corresponding to the second pixel circuit 2-G turns toward the right side below the circuit unit 1 to be electrically connected to the second data line Data2, and the first connection line 3 corresponding to the third pixel circuit 2-B also turns toward the right side below the circuit unit 1 to be electrically connected to the first data line Data1, so that the second part 9 corresponding to the second pixel circuit 2-G and the first part 7 corresponding to the third pixel circuit 2-B are located below the circuit unit 1 and overlap along the second direction y.

[0148] Based on the above structure, the first data line Data1 and the first connection line 3 transmit the PAM data voltage required for PAM driving, and the second data line Data2 and the second connection line 4 transmit the PWM data voltage required for PWM driving. Usually, the PAM data voltage required for the same color sub-pixel at different gray scales is the same, so the first data line Data1 and the first connection line 3 transmit a constant voltage signal.

[0149] With the above design, the first connecting line 3 corresponding to the second pixel circuit 2-G is adjacent to the first connecting line 3 corresponding to the first pixel circuit 2-R, and the second connecting line 4 corresponding to the second pixel circuit 2-G is adjacent to the first connecting line 3 corresponding to the third pixel circuit 2-B, thereby reducing interference with the connecting line corresponding to the second pixel circuit 2-G.

[0150] In one structure, see Fig. 9, the positions of the pulse amplitude modulation module 5 and the pulse width modulation module 6 in the third pixel circuit 2-B can be swapped, that is, the pulse amplitude modulation module 5 in the third pixel circuit 2-B points to the direction of the pulse width modulation module 6, which is opposite to the direction in which the pulse amplitude modulation module 5 in the first pixel circuit 2-R and the second pixel circuit 2-G points to the pulse width modulation module 6, thereby making it easier to implement the above technical solution.

[0151] When the two data lines Data electrically connected to the first pixel circuit 2-R are located on the side of the first pixel circuit 2-R away from the second pixel circuit 2-G, the two data lines Data electrically connected to the third pixel circuit 2-B are located on the side of the third pixel circuit 2-B away from the second pixel circuit 2-G, and the two data lines Data electrically connected to the second pixel circuit 2-G are respectively located on the opposite sides of the second pixel circuit 2-G in the first direction x, in a feasible implementation manner, as Fig.10 As shown, Fig.10 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. The pixel circuit 2 includes a pulse amplitude modulation module 5 and a pulse width modulation module 6. The first data line Data1 is electrically connected to the pulse amplitude modulation module 5, and the second data line Data2 is electrically connected to the pulse width modulation module 6.

[0152] For the two data lines Data electrically connected to the second pixel circuit 2 -G, one is adjacent to the first data line Data1 electrically connected to the first pixel circuit 2 -R, and the other is adjacent to the first data line Data1 electrically connected to the third pixel circuit 2 -B.

[0153] For example, see Fig.10 The first data line Data1-R is located on a side of the first data line Data1-R away from the second data line Data2-R and is adjacent to the first data line Data1-R, and the second data line Data2-R is located on a side of the first data line Data1-B away from the second data line Data2-B and is adjacent to the first data line Data1-B.

[0154] As mentioned above, a constant voltage signal is transmitted when the first data line Data1 is electrically connected to the pulse amplitude modulation module 5. Therefore, the two data lines Data connected to the second pixel circuit 2-G are respectively adjacent to the first data lines Data1 corresponding to the first pixel circuit 2-R and the third pixel circuit 2-B, so that the mutual interference between the data lines Data can be reduced.

[0155] When the two data lines Data electrically connected to the first pixel circuit 2-R are located on the side of the first pixel circuit 2-R away from the second pixel circuit 2-G, the two data lines Data electrically connected to the third pixel circuit 2-B are located on the side of the third pixel circuit 2-B away from the second pixel circuit 2-G, and the two data lines Data electrically connected to the second pixel circuit 2-G are respectively located on the opposite sides of the second pixel circuit 2-G in the first direction x, in a feasible implementation manner, as Fig.11 As shown, Fig.11 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. The pixel circuit 2 is electrically connected to the first data line Data1 through the first connection line 3 and is electrically connected to the second data line Data2 through the second connection line 4.

[0156] The first connection line 3 includes a first portion 7, which extends at least along the first direction x and whose end is electrically connected to the first data line Data1 through a first via hole 8. The second connection line 4 includes a second portion 9, which extends at least along the first direction x and whose end is electrically connected to the second data line Data2 through a second via hole 10.

[0157] The first part 7 and the second part 9 corresponding to the second pixel circuit 2 -G are located on the same side of the circuit unit 1 in the second direction y, and the second direction y intersects with the first direction x.

[0158] For example, see Fig.11 The first part 7 and the second part 9 corresponding to the second pixel circuit 2-G are both located above the circuit unit 1. After the second connecting line 4 corresponding to the second pixel circuit 2-G is led out from under the circuit unit 1, it can extend upward between the second pixel circuit 2-G and the third pixel circuit 2-B to the top of the circuit unit 1, and then turn to the right to be electrically connected to the second data line Data2.

[0159] This structure can further compress some layout space below (or above) the circuit unit 1, and the vertical height of the pixel is smaller, so that more pixels can be set in a limited space to achieve a higher PPI.

[0160] In a possible implementation, Fig.12 As shown, Fig.12 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention, in which the pixel circuit 2 is electrically connected to the data line Data via the connecting line 11 .

[0161] At least part of the data lines Data include a first line segment 12 and a second line segment 13. In a direction perpendicular to the plane of the display panel, the first line segment 12 overlaps with the connection line 11 connected to other data lines Data, and the second line segment 13 does not overlap with the connection line 11 connected to other data lines Data.

[0162] The connection line 11 includes a first connection line 3 and a second connection line 4, and the first line segment 12 overlaps with the connection line 11 connected to other data lines Data, which means that the first line segment 12 overlaps with the first connection line 3 or the second connection line 4 connected to other data lines Data.

[0163] The above configuration is to perform necking processing on the data line Data. By reducing the line width of the first line segment 12, the overlapping area between the first line segment 12 and the connection line 11 connected to other data lines Data can be reduced, thereby reducing coupling.

[0164] In a possible implementation, Fig.13 As shown, Fig.13 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention, in which the pixel circuit 2 is electrically connected to the data line Data via the connecting line 11 .

[0165] The connecting line 11 includes a first sub-portion 14 and a second sub-portion 15 which are connected to each other. At least a portion of the first sub-portion 14 extends along a first direction x, and the second sub-portion 15 protrudes from the first sub-portion 14 along a second direction y. In a direction perpendicular to the plane where the display panel is located, the second sub-portion 15 overlaps with the data line Data connected thereto, and the second direction y intersects with the first direction x.

[0166] The connecting line 11 includes a first sub-connecting line 16 and a second sub-connecting line 17, the first sub-portions 14 in the first sub-connecting line 16 and the second sub-connecting line 17 are located on the same side of the circuit unit 1 in the second direction y, and, along the second direction y, the second sub-portion 15 in the first sub-connecting line 16 overlaps with the first sub-portion 14 in the second sub-connecting line 17.

[0167] The second sub-portion 15 in the first sub-connection line 16 protrudes from the first sub-portion 14 in a direction away from the second sub-connection line 17 .

[0168] The second sub-portion 15 is provided in the connection line 11, so that the overlapping area between the connection line 11 and the data line Data connected thereto can be increased, and at least two vias can be provided at the end of the connection line 11 to connect to the data line Data, thereby improving the connection reliability between the pixel circuit 2 and the data line Data.

[0169] For the first sub-connecting line 16 and the second sub-connecting line 17, if the second sub-portion 15 in the first sub-connecting line 16 protrudes from the first sub-portion 14 in the direction close to the second sub-connecting line 17, then the interval between the first sub-portions 14 in the first sub-connecting line 16 and the second sub-connecting line 17 in the second direction y needs to be larger to make room to accommodate the second sub-portion 15 of the first sub-connecting line 16. In the embodiment of the present invention, the second sub-portion 15 in the first sub-connection line 16 is protruded from the first sub-portion 14 in a direction away from the second sub-connection line 17. With this arrangement, the first sub-portion 14 in the first sub-connection line 16 and the second sub-connection line 17 does not need to accommodate the second sub-portion 15 in the interval in the second direction y. The released space can be used to compress the spacing between the first sub-portions 14 in the first sub-connection line 16 and the second sub-connection line 17 to reduce the longitudinal height of the pixel, or can also be used to increase the width of the first sub-portion 14 in the first sub-connection line 16 or the second sub-connection line 17 to balance the load of the first sub-connection line 16 and the second sub-connection line 17.

[0170] For example, Fig.14 As shown, Fig.14 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention, in which the length of the first sub-portion 14 in the first sub-connection line 16 is greater than the length of the first sub-portion 14 in the second sub-connection line 17, and the width of the first sub-portion 14 in the first sub-connection line 16 in the second direction y is greater than the width of the first sub-portion 14 in the second sub-connection line 17 in the second direction y. Alternatively, the length of the first sub-portion 14 in the second sub-connection line 17 is greater than the length of the first sub-portion 14 in the first sub-connection line 16, and the width of the first sub-portion 14 in the second sub-connection line 17 in the second direction y is greater than the width of the first sub-portion 14 in the first sub-connection line 16 in the second direction y, so as to balance the loads of the first sub-connection line 16 and the second sub-connection line 17.

[0171] Furthermore, if Fig.15 As shown, Fig.15 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention, in which the second sub-portion 15 in the second sub-connection line 17 points to the direction of the first sub-portion 14, which is opposite to the direction in which the second sub-portion 15 in the first sub-connection line 16 points to the first sub-portion 14. That is, the first sub-connection line 16 and the second sub-portion 15 in the second sub-connection line 17 are away from each other, so that the second sub-portion 15 in the second sub-connection line 17 can be prevented from overlapping with the first sub-connection line 16 in the first direction x, thereby reducing the coupling between the two connection lines.

[0172] In a possible implementation, Figure 16 to Figure 18 As shown, Fig.16 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.17A schematic diagram of a circuit structure of a first electrostatic protection circuit 18 provided in an embodiment of the present invention, Fig.18 This is a schematic diagram of a circuit structure of a second electrostatic protection circuit 19 provided in an embodiment of the present invention. The display panel also includes a first electrostatic protection circuit 18 and a second electrostatic protection circuit 19 .

[0173] The first static electricity protection circuit 18 is electrically connected to the first data line Data1, the first high potential signal line VGH1 and the first low potential signal line VGL1, respectively. The second static electricity protection circuit 19 is electrically connected to the second data line Data2, the second high potential signal line VGH2 and the second low potential signal line VGL2, respectively.

[0174] The first high potential signal line VGH1 and the second high potential signal line VGH2 provide different voltages, and / or the first low potential signal line VGL1 and the second low potential signal line VGL2 provide different voltages.

[0175] In one structure, the first electrostatic protection circuit 18 includes a first switch 20 and a second switch 21. The control end and the first end of the first switch 20 are electrically connected to the first high potential signal line VGH1, and the second end is electrically connected to the first data line Data1. The control end and the first end of the second switch 21 are electrically connected to the first data line Data1, and the second end is electrically connected to the first low potential signal line VGL1. When static electricity causes the voltage on the first data line Data1 to be abnormal, when the voltage is too high, the first switch 20 is turned on, and the static electricity is conducted away via the first high potential signal line VGH1. When the voltage is too low, the second switch 21 is turned on, and the static electricity is conducted away via the first low potential signal line VGL1, thereby realizing electrostatic protection for the first data line Data1.

[0176] The second electrostatic protection circuit 19 includes a third switch 22 and a fourth switch 23. The control end and the first end of the third switch 22 are electrically connected to the second high potential signal line VGH2, and the second end is electrically connected to the second data line Data2. The control end and the first end of the fourth switch 23 are electrically connected to the second data line Data2, and the second end is electrically connected to the second low potential signal line VGL2. When static electricity causes the voltage on the second data line Data2 to be abnormal, when the voltage is too high, the third switch 22 is turned on, and the static electricity is conducted away via the second high potential signal line VGH2. When the voltage is too low, the fourth switch 23 is turned on, and the static electricity is conducted away via the second low potential signal line VGL2.

[0177] In the pixel circuit 2 structure combining PAM and PWM drive, the pulse width modulation module 6 needs to charge the gate of the driving tube in the pulse amplitude modulation module 5, so usually, the PWM data voltage is higher than the PAM data voltage. For example, the voltage range of the PWM data voltage is 0 to 5V, and the voltage range of the PAM data voltage is -5V to 0V. For this reason, when designing an electrostatic protection circuit for the first data line Data1 and the second data line Data2, the high-level voltage and low-level voltage received by the two electrostatic protection circuits can be differentiated to make them more compatible with the voltage range on the connected data line Data, thereby providing better electrostatic protection for the connected data line Data.

[0178] Exemplarily, the first data line Data1 is used to provide a PAM data voltage, and the voltages provided by the first high potential signal line VGH1 and the first low potential signal line VGL1 are respectively designed to be +3 V and -12 V. The second data line Data2 is used to provide a PWM data voltage, and the voltages provided by the second high potential signal line VGH2 and the second low potential signal line VGL2 are respectively designed to be +8 V and -7 V.

[0179] Below Fig.19 Taking the pixel circuit 2 shown as an example, the circuit structure of the pixel circuit 2 is schematically described.

[0180] like Fig.19 As shown, Fig.19 This is a circuit structure diagram of a pixel circuit 2 provided in an embodiment of the present invention. The pixel circuit 2 includes a pulse width modulation module 6 and a pulse amplitude modulation module 5. The first data line Data1 is electrically connected to the pulse amplitude modulation module 5, and the second data line Data2 is electrically connected to the pulse width modulation module 6.

[0181] The pulse width modulation module 6 may include:

[0182] The first driving transistor M1.

[0183] The first gate reset transistor M2 has a gate electrically connected to the first scanning line PWM-S1, a first electrode electrically connected to the first reset signal line PWM-REF, and a second electrode electrically connected to the gate of the first driving transistor M1.

[0184] The first data writing transistor M3 has a gate electrically connected to the second scanning line PWM-S2, a first electrode electrically connected to the second data line Data2, and a second electrode electrically connected to the first electrode of the first driving transistor M1.

[0185] The first compensation transistor M4 has a gate electrically connected to the second scanning line PWM-S2, a first electrode electrically connected to the second electrode of the first driving transistor M1, and a second electrode electrically connected to the gate of the first driving transistor M1.

[0186] The first capacitor C1 has a first plate electrically connected to the sweep signal line SWEEP, and a second plate electrically connected to the gate of the first driving transistor M1.

[0187] The first light emission control transistor M5 has a gate electrically connected to the first light emission control signal line PWM-EM, a first electrode electrically connected to the first fixed potential signal line PWM-vdd, and a second electrode electrically connected to the first electrode of the first driving transistor M1.

[0188] The second light emitting control transistor M6 has a gate electrically connected to the first light emitting control signal line PWM-EM, and a first electrode electrically connected to the second electrode of the first driving transistor M1.

[0189] The pulse amplitude modulation module 5 may include:

[0190] The second driving transistor M7 has a gate electrically connected to the second electrode of the second light emitting control transistor M6.

[0191] The second gate reset transistor M8 has a gate electrically connected to the third scan line PAM-S1, a first electrode electrically connected to the second reset signal line PAM-REF, and a second electrode electrically connected to the gate of the second driving transistor M7.

[0192] The second data writing transistor M9 has a gate electrically connected to the fourth scanning line PAM-S2, a first electrode electrically connected to the first data line Data1, and a second electrode electrically connected to the first electrode of the second driving transistor M7.

[0193] The second compensation transistor M10 has a gate electrically connected to the fourth scan line PAM-S2, a first electrode electrically connected to the second electrode of the second driving transistor M7, and a second electrode electrically connected to the gate of the second driving transistor M7.

[0194] The anode reset transistor M11 has a gate electrically connected to the fourth scan line PAM-S2, a first electrode electrically connected to the second reset signal line PAM-REF, and a second electrode electrically connected to the light emitting element D.

[0195] The third light emission control transistor M12 has a gate electrically connected to the second light emission control transistor PAM-EM, a first electrode electrically connected to the second fixed potential signal line PAM-vdd, and a second electrode electrically connected to the first electrode of the second driving transistor M7.

[0196] The fourth light emitting control transistor M13 has a gate electrically connected to the second light emitting control transistor PAM-EM, a first electrode electrically connected to the second electrode of the second driving transistor M7, and a second electrode electrically connected to the light emitting element D.

[0197] The second capacitor C2 has a first plate electrically connected to the second fixed potential signal line PAM-vdd, and a second plate electrically connected to the gate of the second driving transistor M7.

[0198] It should be noted that Fig.19 This is only an illustration of a circuit structure of the pixel circuit 2 . In other optional embodiments of the present invention, the pixel circuit 2 may also adopt other circuit structures.

[0199] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig. 20 As shown, Fig. 20 1 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. Of course, Fig. 20 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0200] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0201] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: A circuit unit, comprising M pixel circuits arranged along a first direction, where M is an integer greater than or equal to 2; Data lines, including a first data line and a second data line, the pixel circuits being electrically connected to the first data line and the second data line respectively; Among the data lines adjacent to each other in the first direction and not separated by the pixel circuit, at most M-1 of the first data lines are electrically connected to the same circuit unit, and / or at most M-1 of the second data lines are electrically connected to the same circuit unit; Alternatively, at least one of the pixel circuits is provided with the first data line and the second data line electrically connected to the circuit unit in which the pixel circuit is located on two opposite sides in the first direction.

2. The display panel according to claim 1, characterized in that: Along the first direction, no other circuit units are spaced between the data line and the circuit unit electrically connected thereto.

3. The display panel according to claim 1, characterized in that: In the circuit unit, at most M-1 of the first data lines electrically connected to the pixel circuits are located on the same side of the circuit unit in the first direction, and at most M-1 of the second data lines electrically connected to the pixel circuits are located on the same side of the circuit unit in the first direction.

4. The display panel according to claim 1, characterized in that: The two data lines electrically connected to at least one pixel circuit are located on the same side of the pixel circuit in the first direction.

5. The display panel according to claim 4, characterized in that: The pixel circuit includes a first pixel circuit, a second pixel circuit and a third pixel circuit; The circuit unit includes the first pixel circuit, the second pixel circuit and the third pixel circuit arranged along the first direction; The two data lines electrically connected to the first pixel circuit are located on a side of the first pixel circuit away from the second pixel circuit, and / or the two data lines electrically connected to the third pixel circuit are located on a side of the third pixel circuit away from the second pixel circuit.

6. The display panel according to claim 5, characterized in that: The two data lines electrically connected to the second pixel circuit are located at the same side of the circuit unit in the first direction.

7. The display panel according to claim 4, characterized in that: The pixel circuit includes a first side and a second side in the first direction; The two data lines electrically connected to the pixel circuit are located on the first side of the pixel circuit, and no other pixel circuit is interposed between the data lines and the pixel circuit connected thereto.

8. The display panel according to claim 1, characterized in that: The two data lines electrically connected to at least one pixel circuit are respectively located at two opposite sides of the pixel circuit in the first direction.

9. The display panel according to claim 8, characterized in that: The pixel circuit includes a first pixel circuit, a second pixel circuit and a third pixel circuit; The circuit unit includes the first pixel circuit, the second pixel circuit and the third pixel circuit arranged along the first direction; The two data lines electrically connected to the second pixel circuit are respectively located at two opposite sides of the second pixel circuit in the first direction.

10. The display panel according to claim 8, characterized in that: The two data lines electrically connected to the pixel circuit are located at two opposite sides of the pixel circuit in the first direction, and no other pixel circuit is interposed between the data line and the pixel circuit connected thereto.

11. The display panel according to claim 1, characterized in that: The pixel circuit includes a first pixel circuit, a second pixel circuit and a third pixel circuit; The circuit unit includes the first pixel circuit, the second pixel circuit and the third pixel circuit arranged along the first direction; Wherein, the two data lines electrically connected to the first pixel circuit are located on a side of the first pixel circuit away from the second pixel circuit, and the two data lines electrically connected to the third pixel circuit are located on a side of the third pixel circuit away from the second pixel circuit; The two data lines electrically connected to the second pixel circuit are respectively located at two opposite sides of the second pixel circuit in the first direction.

12. The display panel according to claim 11, characterized in that: For the two data lines electrically connected to the second pixel circuit, one is located between the first pixel circuit and the second pixel circuit, and the other is located between the second pixel circuit and the third pixel circuit.

13. The display panel according to claim 11, characterized in that: For the two data lines electrically connected to the second pixel circuit, one is located on a side of the first pixel circuit away from the second pixel circuit, and the other is located on a side of the third pixel circuit away from the second pixel circuit.

14. The display panel according to claim 13, characterized in that: For the two data lines electrically connected to the second pixel circuit, one of them is located between the two data lines electrically connected to the first pixel circuit, and the other is located between the two data lines electrically connected to the third pixel circuit.

15. The display panel according to claim 13, characterized in that: For the two data lines electrically connected to the second pixel circuit, one is located between the first pixel circuit and the two data lines electrically connected thereto, and the other is located between the third pixel circuit and the two data lines electrically connected thereto.

16. The display panel according to claim 13, characterized in that: For the two data lines electrically connected to the second pixel circuit, one of them is located on the side of the two data lines electrically connected to the first pixel circuit away from the first pixel circuit, and the other is located on the side of the two data lines electrically connected to the third pixel circuit away from the third pixel circuit.

17. The display panel according to claim 13, characterized in that: The pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module, the first data line is electrically connected to the pulse amplitude modulation module through a first connecting line, and the second data line is electrically connected to the pulse width modulation module through a second connecting line; The first connection line includes a first portion, the first portion extends at least along the first direction and an end portion thereof is electrically connected to the first data line through a first via hole, and the second connection line includes a second portion, the second portion extends at least along the first direction and an end portion thereof is electrically connected to the second data line through a second via hole; The first part and the second part corresponding to the pixel circuit are respectively located at two opposite sides of the pixel circuit in a second direction, and the second direction intersects with the first direction; Wherein, the first portion corresponding to the second pixel circuit and the first portion corresponding to the first pixel circuit are located on the same side of the circuit unit in the second direction and overlap along the second direction; The second portion corresponding to the second pixel circuit and the first portion corresponding to the third pixel circuit are located at the same side of the circuit unit in the second direction and overlap along the second direction.

18. The display panel according to claim 13, characterized in that: The pixel circuit comprises a pulse amplitude modulation module and a pulse width modulation module, the first data line is electrically connected to the pulse amplitude modulation module, and the second data line is electrically connected to the pulse width modulation module; For the two data lines electrically connected to the second pixel circuit, one is adjacent to the first data line electrically connected to the first pixel circuit, and the other is adjacent to the first data line electrically connected to the third pixel circuit.

19. The display panel according to claim 13, characterized in that: The pixel circuit is electrically connected to the first data line through a first connection line, and is electrically connected to the second data line through a second connection line; The first connection line includes a first portion, the first portion extends at least along the first direction and an end portion thereof is electrically connected to the first data line through a first via hole, and the second connection line includes a second portion, the second portion extends at least along the first direction and an end portion thereof is electrically connected to the second data line through a second via hole; The first part and the second part corresponding to the second pixel circuit are located on the same side of the circuit unit in a second direction, and the second direction intersects with the first direction.

20. The display panel according to claim 1, characterized in that: The pixel circuit is electrically connected to the data line via a connecting line; At least part of the data lines include a first line segment and a second line segment. In a direction perpendicular to the plane where the display panel is located, the first line segment overlaps with the connection line connected to other data lines, and the line width of the first line segment is smaller than the line width of the second line segment.

21. The display panel according to claim 1, characterized in that: The pixel circuit is electrically connected to the data line via a connecting line; The connecting line includes a first sub-portion and a second sub-portion that are connected, wherein at least a portion of the first sub-portion extends along the first direction, and the second sub-portion protrudes from the first sub-portion along the second direction, and in a direction perpendicular to the plane where the display panel is located, the second sub-portion overlaps with the data line connected thereto, and the second direction intersects with the first direction; The connection line includes a first sub-connection line and a second sub-connection line, the first sub-portions in the first sub-connection line and the second sub-connection line are located on the same side of the circuit unit in the second direction, and the second sub-portion in the first sub-connection line overlaps the first sub-portion in the second sub-connection line along the second direction; The second sub-portion in the first sub-connection line protrudes from the first sub-portion along a direction away from the second sub-connection line.

22. The display panel according to claim 21, characterized in that: The direction in which the second sub-portion in the second sub-connection line points to the first sub-portion is opposite to the direction in which the second sub-portion in the first sub-connection line points to the first sub-portion.

23. The display panel according to claim 21, characterized in that: The length of the first sub-portion in the second sub-connection line is greater than the length of the first sub-portion in the first sub-connection line, and the width of the first sub-portion in the second direction in the second sub-connection line is greater than the width of the first sub-portion in the first sub-connection line in the second direction; Alternatively, the length of the first sub-portion in the first sub-connection line is greater than the length of the first sub-portion in the second sub-connection line, and the width of the first sub-portion in the first sub-connection line in the second direction is greater than the width of the first sub-portion in the second sub-connection line in the second direction.

24. The display panel according to claim 1, characterized in that: The display panel further includes a first electrostatic protection circuit and a second electrostatic protection circuit; The first electrostatic protection circuit is electrically connected to the first data line, the first high potential signal line and the first low potential signal line respectively, and the second electrostatic protection circuit is electrically connected to the second data line, the second high potential signal line and the second low potential signal line respectively; The first high potential signal line and the second high potential signal line provide different voltages, and / or the first low potential signal line and the second low potential signal line provide different voltages.

25. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 24.

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