Pixel driving circuit

Abstract

The present invention discloses a pixel driving circuit, including compensation, light-emitting, reset and test circuits. The first transistor of the compensation circuit is coupled between the system high voltage and the second node, and the control end is coupled to the first node; the second transistor thereof is coupled between the first node and the second node, and the control end receives the first scanning signal; the capacitor thereof is coupled between the first node and the third node. The third transistor of the light-emitting circuit is coupled between the second node and the fourth node, and the control end receives the light-emitting control signal, and the light-emitting element thereof is coupled between the fourth node and the system low voltage. The fourth transistor of the reset circuit is coupled between the third node and the fourth node, and the control end receives the second scanning signal. The fifth transistor of the test circuit is coupled between the fourth node and the data voltage, and the control end receives the test signal.

Description

Technical Field

[0001] The present disclosure relates to a pixel driving circuit. Background Art

[0002] In the design of high-transmittance display panels, the pixel driving circuit currently used requires more transistors and capacitors to achieve functions such as reset, threshold voltage compensation, data writing and light emission, resulting in a complex circuit layout and difficulty in meeting the high-transmittance requirements of the display panel. Summary of the invention

[0003] Therefore, the embodiment of the present disclosure provides a pixel driving circuit, including a compensation circuit, a light emitting circuit, a reset circuit and a test circuit. The compensation circuit includes a first transistor, a second transistor and a capacitor. The first end of the first transistor receives a system high voltage, the control end thereof is coupled to the first node, and the second end thereof is coupled to the second node. The first end of the second transistor is coupled to the first node, the control end thereof receives a first scan signal, and the second end thereof is coupled to the second node. The first end of the capacitor is coupled to the first node, and the second end thereof is coupled to the third node. The light emitting circuit is coupled to the compensation circuit, and includes a third transistor and a light emitting element. The first end of the third transistor is coupled to the second node, the control end thereof receives a light emitting control signal, and the second end thereof is coupled to the fourth node. The first end of the light emitting element is coupled to the fourth node, and the second end thereof receives a system low voltage. The reset circuit is coupled to the compensation circuit and the light emitting circuit, and includes a fourth transistor. The first end of the fourth transistor is coupled to the third node, the control end thereof receives a second scan signal, and the second end thereof is coupled to the fourth node. The test circuit is coupled to the reset circuit and the light emitting circuit, and includes a fifth transistor. A first terminal of the fifth transistor is coupled to the fourth node, a control terminal thereof receives a test signal, and a second terminal thereof receives a data voltage.

[0004] According to an embodiment of the present disclosure, in a driving sequence, the data voltage includes a first voltage level and a second voltage level, and the first voltage level is used to reset the potentials of the first node, the second node, the third node and the fourth node in the pixel driving circuit, and the second voltage level is used to determine the grayscale of the pixel driving circuit.

[0005] According to an embodiment of the present disclosure, the first voltage level and the second voltage level are lower than the system low voltage.

[0006] According to an embodiment of the present disclosure, when the system low voltage is a negative voltage, the first voltage level and the second voltage level are negative voltages; when the system low voltage is a positive voltage, the first voltage level is a negative voltage or a positive voltage, and the second voltage level is a negative voltage or a positive voltage.

[0007] According to an embodiment of the present disclosure, during a reset period of the pixel driving circuit, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are turned on to reset the first node, the third node and the fourth node to a first voltage level.

[0008] According to an embodiment of the present disclosure, during the compensation period of the pixel driving circuit, the third transistor is turned off and the first transistor, the second transistor, the fourth transistor and the fifth transistor are turned on so that the first node changes from the first voltage level to the system high voltage plus the threshold voltage of the first transistor, and the third node is maintained at the first voltage level.

[0009] According to an embodiment of the present disclosure, during the data writing period of the pixel driving circuit, the second transistor and the third transistor are turned off and the first transistor, the fourth transistor and the fifth transistor are turned on to write the second voltage level to the third node, and the first node is a floating voltage.

[0010] According to an embodiment of the present disclosure, during the light emitting period of the pixel driving circuit, the second transistor, the fourth transistor and the fifth transistor are turned off and the first transistor and the third transistor are turned on to generate a driving current from a system high voltage through the first transistor, the third transistor and the light emitting element to a system low voltage.

[0011] According to an embodiment of the present disclosure, the driving current is expressed as: driving current = K (second voltage level - first voltage level) 2 , where K is the process parameter of the first transistor.

[0012] According to an embodiment of the present disclosure, during the test period of the pixel driving circuit, the test circuit is further configured to turn on the fifth transistor according to a test signal to test whether the compensation circuit, the light emitting circuit and the reset circuit operate normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To make the above and other features, advantages and embodiments of the present invention more understandable, the accompanying drawings are described as follows:

[0014] Figure 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the present invention;

[0015] Figure 2 A timing waveform diagram of each supply signal of the pixel driving circuit according to an embodiment of the present invention; and

[0016] Figures 3 to 6 FIG. 4 is a schematic diagram illustrating the operating principle of a pixel driving circuit according to an embodiment of the present invention.

[0017] Wherein, the reference numerals are:

[0018] 100: Pixel driving circuit

[0019] 110: Compensation circuit

[0020] 120: Light-emitting circuit

[0021] 130: Reset circuit

[0022] 140: Test Circuit

[0023] AT: Test signal

[0024] C1: Capacitor

[0025] Data: Data voltage

[0026] EM: Lighting control signal

[0027] I D :Drive current

[0028] LED: Light Emitting Element

[0029] N1: First Node

[0030] N2: Second node

[0031] N3: The third node

[0032] N4: The fourth node

[0033] Q1: The first transistor

[0034] Q2: Second transistor

[0035] Q3: The third transistor

[0036] Q4: The fourth transistor

[0037] Q5: The fifth transistor

[0038] S1: first scanning signal

[0039] S2: Second scanning signal

[0040] T1: Reset period

[0041] T2: Compensation period

[0042] T3: Data writing period

[0043] T4: Luminous period

[0044] VDD: system high voltage

[0045] Vn: First voltage level

[0046] Vd: Second voltage level

[0047] VSS: System low voltage DETAILED DESCRIPTION

[0048] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. The embodiments of the components and configurations described below are provided as examples only and are not intended to be limiting. In addition, for the purpose of simplicity and clarity, the disclosure repeats reference symbols and / or numbers in each example, which in itself does not limit the relationship between the various embodiments and / or components discussed.

[0049] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of a pixel driving circuit 100 according to an embodiment of the present invention. The pixel driving circuit 100 includes a compensation circuit 110, a light emitting circuit 120, a reset circuit 130 and a test circuit 140.

[0050] The compensation circuit 110 includes a first transistor Q1, a second transistor Q2, and a capacitor C1, and is configured to provide a threshold voltage V th The compensation is performed so that the light-emitting circuit 120 can generate a threshold voltage V that is independent of the system high voltage VDD and the first transistor Q1. th The driving current I D , to avoid driving current I D The error occurs, resulting in a variation in the brightness of the light emitting element LED of the light emitting circuit 120 .

[0051] A first end of the first transistor Q1 receives the system high voltage VDD, a control end thereof is coupled to the first node N1, and a second end thereof is coupled to the second node N2. A first end of the second transistor Q2 is coupled to the first node N1, a control end thereof receives the first scan signal S1, and a second end thereof is coupled to the second node N2. A first end of the capacitor C1 is coupled to the first node N1, and a second end thereof is coupled to the third node N3.

[0052] The light emitting circuit 120 is coupled to the compensation circuit 110 and includes a third transistor Q3 and a light emitting element LED. A first end of the third transistor Q3 is coupled to the second node N2, a control end thereof receives a light emitting control signal EM, and a second end thereof is coupled to a fourth node N4. A first end of the light emitting element LED is coupled to the fourth node N4, and a second end thereof receives a system low voltage VSS.

[0053] The reset circuit 130 is coupled to the compensation circuit 110 and the light emitting circuit 120 and includes a fourth transistor Q4. A first terminal of the fourth transistor Q4 is coupled to the third node N3, a control terminal thereof receives the second scan signal S2, and a second terminal thereof is coupled to the fourth node N4.

[0054] The test circuit 140 is coupled to the reset circuit 130 and the light emitting circuit 120 and includes a fifth transistor Q5. A first terminal of the fifth transistor Q5 is coupled to the fourth node N4, a control terminal thereof receives a test signal AT, and a second terminal thereof receives a data voltage Data.

[0055] Please refer to Figure 2 , Figure 2 is a timing waveform diagram of each supply signal of the pixel driving circuit 100 according to an embodiment of the present invention, and is combined with Figures 3 to 6 The schematic diagram of the operation principle of the pixel driving circuit 100 shown here can help better understand the present invention. The driving timing of the pixel driving circuit 100 includes a reset period T1, a compensation period T2, a data writing period T3 and a light emitting period T4, which correspond to Figures 3 to 6 The circuit shown operates.

[0056] exist Figures 3 to 6 In the figure, the crossed transistors represent a non-conducting state, the uncrossed transistors represent a conducting state, and in each driving timing, the data voltage Data includes a first voltage level Vn and a second voltage level Vd. In the embodiment of the present invention, the first voltage level Vn and the second voltage level Vd are both lower than the system low voltage VSS. When the system low voltage VSS supplied to the pixel driving circuit 100 is a negative voltage, the first voltage level Vn and the second voltage level Vd are both negative voltages. When the system low voltage VSS supplied to the pixel driving circuit 100 is a positive voltage, the first voltage level Vn and the second voltage level Vd may be a negative voltage or a positive voltage.

[0057] During the reset period T1, the first scan signal S1, the second scan signal S2, the light emitting control signal EM and the test signal AT are all at a low logic level. Figure 3 As shown, the second transistor Q2, the third transistor Q3, the fourth transistor Q4 and the fifth transistor Q5 are turned on according to the low logic levels of the first scan signal S1, the second scan signal S2, the light emitting control signal EM and the test signal AT.

[0058] The first voltage level Vn of the data voltage Data is written to the third node N3 due to the conduction of the fourth transistor Q4 and the fifth transistor Q5, and is written to the first node N1 due to the conduction of the second transistor Q2 and the third transistor Q3. At this time, the control end and the second end of the first transistor Q1 are reset to the same potential and form a diode connection. It is worth noting that since the first voltage level Vn is less than the system low voltage VSS, the light-emitting element LED cannot be illuminated due to the reverse bias at its two ends. At this point, the reset period T1 completes the reset of the voltages of each node in the pixel driving circuit 100.

[0059] During the compensation period T2, the first scan signal S1, the second scan signal S2 and the test signal AT are at a low logic level, and the light emitting control signal EM is at a high logic level. Figure 4 As shown, the second transistor Q2, the fourth transistor Q4 and the fifth transistor Q5 are turned on according to the low logic level of the first scan signal S1, the second scan signal S2 and the test signal AT, and the third transistor Q3 is turned off according to the high logic level of the light emitting control signal EM.

[0060] The fourth transistor Q4 and the fifth transistor Q5 are continuously turned on so that the third node N3 is maintained at the first voltage level Vn of the data voltage Data. The second transistor Q2 is continuously turned on and the third transistor Q3 is turned off so that the first node N1 changes from the first voltage level Vn to the system high voltage VDD plus the threshold voltage V of the first transistor Q1. th (i.e. VDD+V th ). In this case, the threshold voltage V of the first transistor Q1 th is stored in the control terminal of the first transistor Q1 to complete the threshold voltage V th compensation.

[0061] During the data writing period T3, the first scan signal S1 and the light emitting control signal EM are at a high logic level, while the second scan signal S2 and the test signal AT are at a low logic level. Figure 5 As shown, the fourth transistor Q4 and the fifth transistor Q5 are turned on according to the low logic level of the second scan signal S2 and the test signal AT, and the second transistor Q2 and the third transistor Q3 are turned off according to the high logic level of the first scan signal S1 and the light emitting control signal EM.

[0062] The second voltage level Vd of the data voltage Data is written to the third node N3 due to the conduction of the fourth transistor Q4 and the fifth transistor Q5. The first node N1 is a floating voltage due to the turn-off of the second transistor Q2 and the third transistor Q3. At this time, the potential of the first node N1 is affected by the capacitive coupling effect of the capacitor C1 and changes to the potential of the first node N1 at the previous time point plus the potential change of the third node N3, that is, from (VDD+V th ) changes to (VDD+V th )+(Vd-Vn). It is worth noting that since the second voltage level Vd that determines the gray scale is also lower than the system low voltage VSS, the light emitting element LED cannot be lit due to the reverse bias at its two ends.

[0063] During the light-emitting period T4, the first scan signal S1, the second scan signal S2 and the test signal AT are at a high logic level, and the light-emitting control signal EM is at a low logic level. Figure 6As shown, the first transistor Q1 is maintained in the on state, the third transistor Q3 is turned on according to the low logic level of the light emitting control signal EM, and the second transistor Q2, the fourth transistor Q4 and the fifth transistor Q5 are turned off according to the high logic levels of the first scanning signal S1, the second scanning signal S2 and the test signal AT.

[0064] The second transistor Q2, the fourth transistor Q4 and the fifth transistor Q5 are turned off so that the first node N1 and the third node N3 are maintained at the same potential as the previous time point, and based on the potential of each node, the driving current I D It can be expressed as:

[0065] Drive Circuit I D =K(second voltage level V d -First voltage level V n ) 2 ,

[0066] K depends on the process parameters of the first transistor Q1 , which parameters include carrier mobility, gate width, gate length, and unit capacitance of the gate oxide layer.

[0067] By the driving current I D It can be found from the expression that the system high voltage VDD and the critical voltage V of the first transistor Q1 th Capable of self-driving current I D That is, the driving current I generated by the pixel driving circuit 100 is D Regardless of the system high voltage VDD and the threshold voltage V of the first transistor Q1 th In this way, the influence of threshold voltage shift caused by process variation or long-term operation can be improved, and the driving current I D It is also less likely to cause errors due to voltage drops in the paths of the system high voltage VDD and the system low voltage VSS.

[0068] In the embodiment of the present invention, before the pixel driving circuit 100 actually operates, it also includes a test period (not shown) to test whether the functions of the compensation circuit 110, the light emitting circuit 120 and the reset circuit 130 are normal through the test circuit 140. For example, the test circuit 140 can be used as an array test circuit to ensure that the functions of the capacitor C1 and the first to fifth transistors Q1-Q5 in the compensation circuit 110, the light emitting circuit 120 and the reset circuit 130 are normal through pre-testing.

[0069] In summary, the present invention proposes a pixel driving circuit that simplifies its wiring design by reducing the number of components therein (including only five transistors and one capacitor), which not only effectively improves the transmittance of the display panel, but also simultaneously takes into account the reset, threshold voltage compensation, data writing and light-emitting functions of the pixel driving circuit.

[0070] Although the present invention has been disclosed as above in various embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A pixel driving circuit, characterized in that: Include: A compensation circuit comprising: a first transistor, a first terminal of which receives a system high voltage, a control terminal of which is coupled to a first node, and a second terminal of which is coupled to a second node; a second transistor, a first terminal of which is coupled to the first node, a control terminal of which receives a first scan signal, and a second terminal of which is coupled to the second node; as well as a capacitor, a first end of which is coupled to the first node, and a second end of which is coupled to a third node; A light emitting circuit is coupled to the compensation circuit and comprises: a third transistor, a first terminal of which is coupled to the second node, a control terminal of which receives a light-emitting control signal, and a second terminal of which is coupled to a fourth node; and a light emitting element, a first end of which is coupled to the fourth node, and a second end of which receives a system low voltage; A reset circuit is coupled to the compensation circuit and the light emitting circuit and comprises: a fourth transistor, a first terminal of which is coupled to the third node, a control terminal of which receives a second scan signal, and a second terminal of which is coupled to the fourth node; and A test circuit is coupled to the reset circuit and the light emitting circuit and comprises: A fifth transistor has a first terminal coupled to the fourth node, a control terminal receiving a test signal, and a second terminal receiving a data voltage.

2. The pixel driving circuit according to claim 1, characterized in that: In a driving timing of the pixel driving circuit, the data voltage includes a first voltage level and a second voltage level, and the first voltage level is used to reset the potentials of the first node, the second node, the third node and the fourth node in the pixel driving circuit, and the second voltage level is used to determine the grayscale of the pixel driving circuit.

3. The pixel driving circuit according to claim 2, characterized in that: The first voltage level and the second voltage level are lower than the system low voltage.

4. The pixel driving circuit according to claim 3, characterized in that: When the system low voltage is a negative voltage, the first voltage level and the second voltage level are negative voltages; when the system low voltage is a positive voltage, the first voltage level is a negative voltage or a positive voltage, and the second voltage level is a negative voltage or a positive voltage.

5. The pixel driving circuit according to claim 2, wherein: During a reset period of the pixel driving circuit, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are turned on to reset the first node, the third node and the fourth node to the first voltage level.

6. The pixel driving circuit according to claim 5, characterized in that: During a compensation period of the pixel driving circuit, the third transistor is turned off and the first transistor, the second transistor, the fourth transistor and the fifth transistor are turned on so that the first node changes from the first voltage level to the system high voltage plus a critical voltage of the first transistor, and the third node is maintained at the first voltage level.

7. The pixel driving circuit according to claim 6, characterized in that: During a data writing period of the pixel driving circuit, the second transistor and the third transistor are turned off and the first transistor, the fourth transistor and the fifth transistor are turned on so that the third node is written to the second voltage level, and the first node is a floating voltage.

8. The pixel driving circuit according to claim 7, characterized in that: During a light-emitting period of the pixel driving circuit, the second transistor, the fourth transistor and the fifth transistor are turned off and the first transistor and the third transistor are turned on to generate a driving current from the system high voltage flowing through the first transistor, the third transistor and the light-emitting element to the system low voltage.

9. The pixel driving circuit according to claim 8, characterized in that: The expression of the driving current is: The driving current = K (the second voltage level - the first voltage level) 2 , Wherein K is the process parameter of the first transistor.

10. The pixel driving circuit according to claim 1, wherein: During a test period of the pixel driving circuit, the test circuit is further configured to turn on the fifth transistor according to the test signal to test whether the compensation circuit, the light emitting circuit and the reset circuit operate normally.

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