Control circuit, control method, display screen and terminal equipment

Abstract

The invention provides a control circuit, a control method, a display screen and terminal equipment. In a plurality of rows of cascaded driving circuits in the control circuit, except for a first number of rows of driving circuits with a previous cascading sequence and a second number of rows of driving circuits with a later cascading sequence, each row of driving circuits is electrically connected with a pixel circuit; in the Nth row driving circuit, a first signal generating circuit outputs a first driving signal according to row transmission signals output by the (N + Y2) th row driving circuit and the (N-X4) th row driving circuit, and a second signal generating circuit outputs a second driving signal according to row transmission signals output by the (N-X1) th row driving circuit and the (N-X2) th row driving circuit, the third signal generating circuit outputs a third driving signal according to the row transmission signals output by the (N-X2) th row driving circuit, the (N-X3) th row driving circuit, the Nth row driving circuit and the (N + Y1) th row driving circuit; the corresponding pixel circuit controls the light-emitting device to work based on at least part of the first driving signal, the second driving signal, the third driving signal and the row transmission signals output by the Nth row driving circuit and the (N-X1) th row driving circuit respectively. According to the scheme, the frame of the display screen can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of display screens, and in particular to a control circuit, a control method, a display screen and a terminal device. Background Art

[0002] Organic Light Emitting Diode (OLED) displays have the characteristics of self-luminescence, low driving voltage, fast response, and good color purity, and have occupied a dominant position in the display field. In recent years, in order to reduce manufacturing costs, narrow borders have become an inevitable trend for display panels.

[0003] At present, the display panel basically adopts two circuits, GOA (Gate driver on array) and EOA (Emission driver on array), to provide the required driving signal to the pixel circuit to drive the OLED to emit light and realize display. In the above manner, it is necessary to provide the GOA and EOA with various signals such as clock signals and control signals required by each. Since different signals need to be routed separately and there are two circuits, GOA and EOA, the circuit and signal routing occupy a large display panel space, which is very unfavorable to reduce the border of the display panel. Summary of the invention

[0004] In view of the above problems, various aspects of the present application provide a control circuit, a control method, a display screen and a terminal device, so as to achieve the purpose of effectively reducing the border of the display panel in the display screen by only using the GOA circuit to drive the corresponding OLED to emit light.

[0005] In one embodiment of the present application, a control circuit is provided. The control circuit includes: a plurality of row cascaded drive circuits and a plurality of pixel circuits, each row drive circuit outputs a row transmission signal according to a received clock signal, and the low levels in the row transmission signals output by two adjacent row drive circuits are continuous in time; except for the first number of row drive circuits in the front cascade sequence and the second number of row drive circuits in the back cascade sequence, each row drive circuit is electrically connected to a corresponding pixel circuit, and each row drive circuit includes a first signal generating circuit, a second signal generating circuit and a third signal generating circuit; wherein,

[0006] In the Nth row driving circuit:

[0007] The first signal generating circuit is used to output a first driving signal according to the row transmission signals output by the N+Y2th row driving circuit and the N-X4th row driving circuit;

[0008] The second signal generating circuit is used to output a second driving signal according to the row transmission signals output by the N-X1th row driving circuit and the N-X2th row driving circuit;

[0009] The third signal generating circuit is used to output a third driving signal according to the row transmission signals output by the N-X2 row driving circuit, the N-X3 row driving circuit, the N row driving circuit and the N+Y1 row driving circuit;

[0010] a pixel circuit electrically connected to the N-th row driving circuit, configured to control the operation of the corresponding light-emitting device based on the first driving signal, the second driving signal, the third driving signal, and at least part of the row transmission signals outputted by the N-th row driving circuit and the N-X1-th row driving circuit;

[0011] Among them, the first number is greater than or equal to 4, the second number is greater than or equal to 2, N, X4, X3, X2, X1, Y1 and Y2 are all natural numbers greater than zero, X4 is greater than X3, X3 is greater than X2, X2 is greater than X1, Y2 is greater than Y1, and N is greater than the first number and less than the difference between the total number of rows of the driving circuit and the second number.

[0012] In another embodiment of the present application, a control method is provided, which is applicable to an N-row driving circuit and a pixel circuit electrically connected to the N-row driving circuit, wherein the N-row driving circuit is one of the multiple rows of cascaded driving circuits in the control circuit provided in the first embodiment of the present application. Specifically, the control method includes:

[0013] receiving row transmission signals outputted by the N-X4 row driving circuit, the N-X3 row driving circuit, the N-X2 row driving circuit, the N-X1 row driving circuit, the N row driving circuit, the N+Y1 row driving circuit and the N+Y2 row driving circuit respectively among the plurality of row driving circuits; wherein the row transmission signals include a low level, and the low levels in the row transmission signals outputted by two adjacent row driving circuits are continuous in time;

[0014] Generate a first driving signal according to the row transmission signals output by the N+Y2th row driving circuit and the N-X4th row driving circuit;

[0015] Generate a second driving signal according to the row transmission signals output by the N-X1th row driving circuit and the N-X2th row driving circuit;

[0016] Generate a third driving signal according to the row transmission signals output by the N-X2 row driving circuit, the N-X3 row driving circuit, the N row driving circuit and the N+Y1 row driving circuit;

[0017] Based on the first drive signal, the second drive signal, the third drive signal, and at least part of the row transmission signals output by the Nth row drive circuit and the N-X1th row drive circuit, the corresponding light-emitting devices are controlled to operate.

[0018] In another embodiment of the present application, a display screen is further provided. The display screen includes: a display panel, and a control circuit provided in other embodiments of the present application. The control circuit is arranged in the space of the display panel, and the steps in the control method provided in other embodiments of the present application can be implemented through the Nth row drive circuit included in the control circuit and the pixel circuit electrically connected to the Nth row drive circuit.

[0019] In another embodiment of the present application, a terminal device is provided, which includes: a housing and a display screen provided in other embodiments of the present application, wherein the display screen is mounted on the housing.

[0020] The technical solutions provided by the embodiments of the present application include a plurality of row cascaded drive circuits and a plurality of pixel circuits in the control circuit, each row drive circuit outputs a row transmission signal according to the received clock signal, and the row transmission signals output by two adjacent row drive circuits are continuous in time; except for the first number of row drive circuits in the front cascade sequence and the second number of row drive circuits in the back cascade sequence, each row drive circuit is electrically connected to a corresponding pixel circuit, and each row drive circuit includes a first signal generating circuit, a second signal generating circuit and a third signal generating circuit. Among them, in the Nth row drive circuit: the first signal generating circuit is used to output the first drive signal according to the row transmission signal output by the N+Y2th row drive circuit and the N-X4th row drive circuit; the second signal generating circuit is used to output the second drive signal according to the row transmission signal output by the N-X1th row drive circuit and the N-X2th row drive circuit; the third signal generating circuit is used to output the third drive signal according to the row transmission signal output by the N-X2th row drive circuit, the N-X3th row drive circuit, the Nth row drive circuit and the N+Y1th row drive circuit. The above-mentioned output drive signals and at least part of the row transmission signals output by the N-row drive circuit and the N-X1-row drive circuit respectively will be input into the pixel circuit electrically connected to the N-row drive circuit, so that the pixel circuit controls the corresponding light-emitting device to operate based on the received signals. It can be seen that the N-row drive circuit in the present scheme can generate the drive signals required for the pixel circuit to control the light-emitting device to operate based on the row transmission signals output by multiple rows of other drive circuits, without the need to rely on other circuits such as EOA and Nscan GOA to generate them. This helps to reduce the border size of the display panel in the display screen and further promote the development of narrow borders of display screens. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 A schematic diagram of the structure of a display panel provided by an exemplary embodiment of the present application;

[0023] Figure 2 A schematic diagram of a control circuit provided by an exemplary embodiment of the present application;

[0024] Figure 3 This is a waveform diagram of row transmission signals output by adjacent N-4th row to N+4th row driving circuits in an exemplary control circuit of the present application;

[0025] Figure 4 A schematic diagram of the structure of an N-th row driving circuit in a control circuit is provided for an exemplary embodiment of the present application;

[0026] Figure 5a A waveform diagram of a first driving signal EM(N), a second driving signal S1N, a third driving signal S2N, a row transmission signal GOUT(N) and another signal SP2 output by an N-th row driving circuit is provided for an exemplary embodiment of the present application;

[0027] Figure 5b A waveform diagram of a first driving signal EM(N) and a pulse width modulation signal PWM provided by an exemplary embodiment of the present application;

[0028] Figures 6a to 6c A schematic diagram of the structure of a pixel circuit provided for an exemplary embodiment of the present application;

[0029] Figure 7 A structural schematic diagram of a control method provided by an exemplary embodiment of the present application;

[0030] Figure 8 A schematic diagram of the structure of a terminal device provided for an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0031] With the development of optical technology and semiconductor technology, OLED displays have taken a leading position in the display field due to their self-luminescence, low driving voltage, fast response, good color purity, low energy consumption, and high contrast. In recent years, narrow borders have become an inevitable trend for display panels to reduce manufacturing costs.

[0032] At present, the OLED display driver in the display panel adopts two circuit architectures, GOA and EOA, to provide the required signals to the pixel circuit to drive the OLED to emit light to realize display, wherein the signals required by the pixel circuit to drive the OLED to emit light include but are not limited to the enable (EM) signal, the GOUT signal outputted from the output end of the GOA circuit (hereinafter referred to as the line transmission signal), etc. For example, see Figure 1 The structural diagram of the display panel P shown on the left side of the figure shows that the display panel P includes: a display area AA and a non-display area outside the display area AA. The non-display area is used to lay out circuits such as GOA and EOA, and to lay out corresponding signal routing lines for different signals that need to be provided for circuits such as GOA and EOA. The width of the signal routing lines is related to the degree to which the display panel can achieve a narrow frame effect. For the above-mentioned two circuits of GOA and EOA, the signals that need to be provided by DDIC (Display Driver Integrated Circuit) include but are not limited to: GCK (or SCK, a clock signal provided for the GOA circuit), ECK (a clock signal provided for the EOA circuit), GSTV (Gate Start Virtical, a light-emitting start signal for each frame provided for the GOA circuit), ESTV (Emission Start Virtical, a light-emitting start signal for each frame provided for the EOA circuit), and the like. In addition, since some pixel circuits may be composed of NMOS tubes (i.e., N-type MOS tubes) and some may be composed of PMOS tubes (i.e., P-type MOS tubes), and the circuits composed of NMOS tubes require Nscan signals (scan signals) to control the on and off of the NMOS tubes in the circuits, it is sometimes necessary to arrange Nscan GOA circuits in the non-display area to provide the pixel circuits with the Nscan signals required to drive the OLED to emit light.

[0033] It can be seen from the above content that when the OLED display drive is realized by the traditional method described above, due to the existence of two circuits, GOA and EOA, and the need to separately route different signals for the two circuits, this causes the circuits and signal routing to occupy a larger Panel space, especially the EOA circuit and the signal routing for ECK and other signals required for the EOA circuit occupy a larger Panel space, so that the non-display area of ​​the display panel occupies a relatively large area, which is extremely unfavorable for reducing the border of the display panel, and thus becomes a bottleneck in the development of narrow borders.

[0034] In view of the above problems, the basic design idea of ​​the present application to realize OLED display driving is: adding corresponding signal generating circuits in the GOA circuit, and using these added signal generating circuits to use the GOUT signals output by the original output terminals of the adjacent multiple rows of GOA circuits to generate various signals required for the pixel circuit to drive the OLED to emit light, so as to achieve the purpose of no longer needing the EOA circuit and the Nscan GOA circuit, thereby effectively reducing the border of the display panel. For example, see Figure 1 For the display panel P' shown on the right, the present application solution only requires the GOA circuit to be arranged in the display panel P' space, without the need to arrange the EOA circuit and the Nscan GOA circuit. In addition, in order to enable the OLED to switch between DC mode (direct current dimming mode) and PWM mode (pulse width modulation dimming mode) at will, the present application also improves the pixel circuit. Specifically, a transistor (PMOS) for accessing the pulse width modulation signal is added to the pixel circuit. Based on the above basic design ideas, the embodiments of the present application provide a control circuit, a control method, a display screen and a terminal device.

[0035] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0036] In the embodiments of the present application, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar phases with substantially the same functions and effects. For example, the first signal generating circuit and the second signal generating circuit are only used to distinguish different signal generating circuits, and the order thereof is not limited. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0037] It should be noted that the words "exemplary" or "for example" in this application are used to indicate examples, illustrations or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in this application should be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way. In addition, "at least one" in this application refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, B exists alone, wherein A and B can be singular or plural, etc. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and c can represent: a, b, c, a, b and c, a and b, a and c, b and c.

[0038] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0039] Figure 2 This is a schematic diagram of the structure of a control circuit provided by an exemplary embodiment of the present application. The control circuit is used to control the working state of the light-emitting device in the display panel, such as controlling the light-emitting device to work to emit light. Figure 2 As shown, the control circuit includes: a display driving circuit 1 and a plurality of pixel circuits 2. The above-mentioned pixel circuit 2 is the smallest circuit unit of the display panel, and a pixel circuit is equivalent to a sub-pixel (or sub-pixel) in the display panel. Each pixel circuit 2 is electrically connected to a corresponding light-emitting device 3. The light-emitting device may also be referred to as a pixel in the field of display screen technology. Specifically, the light-emitting device may be, but is not limited to, an OLED, an LCD (Liquid Crystal Display), etc. Preferably, in this embodiment, the light-emitting device is an OLED.

[0040] The control circuit is arranged in the space of the display panel in the display screen. The display panel includes a display area AA and a non-display area located around the display area. Specifically, a plurality of pixel circuits in the control circuit are arranged in the display area AA, and the display driving circuit 1 is arranged in the non-display area.

[0041] The display driving circuit 1 includes a plurality of rows of cascaded driving circuits 11, and the driving circuit 11 is a GOA circuit. Each row of driving circuits 11 outputs a row transmission signal according to the received clock signal. In the present embodiment, the row transmission signal is recorded as GOUT(*), and * indicates the row number of the driving circuit outputting the row transmission signal. For example, GOUT(N) indicates the row transmission signal output by the Nth row driving circuit. The clock signal received by each row of driving circuits includes a first clock signal (GCK1) and a second clock signal (GCK2), wherein the first clock signal is composed of a periodic alternation of high levels, and the second clock signal is composed of a periodic alternation of low levels. Specifically, when the first clock signal is at a high level, the second clock signal is at a low level. Also, the row transmission signal output by each row of driving circuits includes a valid low level, and the low levels in the row transmission signals output by two adjacent rows of driving circuits are continuous in time.

[0042] In addition, except for the first number of row drive circuits in the front cascade sequence and the second number of row drive circuits in the back cascade sequence, each row drive circuit is electrically connected to a corresponding pixel circuit, and the pixel circuit controls the operation of the corresponding light-emitting device according to various signals received from the drive circuit. For details of the various signals that the pixel circuit can receive from the row drive circuit, please refer to the relevant content below. The above-mentioned first number is greater than or equal to 4, and the second number is greater than or equal to 2. The specific values ​​of the first number and the second number can be determined according to actual needs. For example, see Figure 5a If the high level holding time of the first driving signal EM(N) described later is required to be the shortest, such as 8 seconds, then both the first number and the second number can be 4.

[0043] From the above content, the control circuit mentioned above includes: a plurality of row cascaded driving circuits and a plurality of pixel circuits. Cascade means that a plurality of row driving circuits are arranged and connected together in a certain order along the vertical direction.

[0044] It should be supplemented here that the first number of row driving circuits in the front of the above-mentioned cascade sequence and the second number of row driving circuits in the back of the cascade sequence are additionally provided dummy (false load) circuits, which are not used to electrically connect the pixel circuits, and only need to ensure that the corresponding row transmission signals can be output to provide the required row transmission signals for other row transmission circuits. Specifically, the first number of row driving circuits in the front of the above-mentioned cascade sequence can be arranged in the top space of the display panel, and the second number of row driving circuits in the back of the above-mentioned cascade sequence can be arranged in the bottom space of the display panel. For example, according to the cascade sequence of the driving circuits, different driving circuits are numbered from top to bottom in an ascending manner using row numbers, and the starting number of the row number is 1, wherein the 1st to 4th row driving circuits are arranged in the top space of the display panel, and the 1st to 4th row driving circuits are designed as dummy circuits. In addition, when each row driving circuit realizes the output of the row transmission signal, in addition to the need to use the clock signal, it may also need to be combined with other received signals, such as the following Figure 4 The GIN signal connected to an input terminal of the Nth row driving circuit shown in FIG. For the specific various signals that the driving circuit needs to combine to output the row transmission signal, please refer to the related content of the existing GOA circuit.

[0045] Figure 3 The waveform diagram of the row transmission signals output by the N-4th row to the N+4th row driving circuits in the multi-row driving circuits changing with time is shown.

[0046] Furthermore, except for the first number of row driving circuits in the front cascade sequence and the second number of row driving circuits in the back cascade sequence, each row driving circuit includes a first signal generating circuit, a second signal generating circuit and a third signal generating circuit. Of course, the first number of row driving circuits in the front cascade sequence and the second number of row driving circuits in the back cascade sequence can also include the above-mentioned signal generating circuits, but considering that in this embodiment, it is only necessary to ensure that the first number of row driving circuits in the front cascade sequence and the second number of row driving circuits in the back cascade sequence can output corresponding row transmission signals, therefore, in order to save costs, it is preferably designed that the other driving circuits except for the first number of row driving circuits in the front cascade sequence and the second number of row driving circuits in the back cascade sequence include the above-mentioned signal generating circuits.

[0047] Figure 4 1 shows a schematic diagram of the structure of the N-th row driving circuit, in which each transistor in the N-th row driving circuit is a P-type transistor (PMOS), and the P-type transistor is turned on at a low level. Figure 4 , in the Nth row driving circuit,

[0048] The first signal generating circuit 111 is used to output a first driving signal according to the row transmission signals (such as GOUT(N+4), GOUT(N-4)) output by the N+Y2-th row driving circuit and the N-X4-th row driving circuit;

[0049] The second signal generating circuit 112 is used to output a second driving signal according to the row transmission signals (such as GOUT(N-1), GOUT(N-2)) output by the N-X1-th row driving circuit and the N-X2-th row driving circuit;

[0050] The third signal generating circuit is used to output a third driving signal according to the row transmission signals (such as GOUT(N-2), GOUT(N-3), GOUT(N), GOUT(N+1)) output by the N-X2 row driving circuit, the N-X3 row driving circuit, the N row driving circuit and the N+Y1 row driving circuit;

[0051] The pixel circuit electrically connected to the N-th row driving circuit is used to control the operation of the corresponding light-emitting device based on at least part of the first driving signal, the second driving signal, the third driving signal, the row transmission signal output by the N-th row driving circuit and the row transmission signal output by the N-X1-th row driving circuit.

[0052] Among them, N, X4, X3, X2, X1, Y1 and Y2 are all natural numbers greater than zero, X4 is greater than X3, X3 is greater than X2, X2 is greater than X1, Y2 is greater than Y1, and N is greater than the first number and less than or equal to the difference between the total number of rows of the driving circuit and the second number.

[0053] Figure 4 The above EM(N), S1N and S2N shown in the figure represent the first drive signal, the second drive signal and the third drive signal respectively. The generation principle of the first drive signal, the second drive signal and the third drive signal will be described in detail below. And, Figure 4 The GOUT(N) shown in the figure represents the row transmission signal output by the N-th row driving circuit. GOUT(N) is generated by other circuits in the N-th row driving circuit except the first signal generating circuit, the second signal generating circuit and the third signal generating circuit. Specifically, GOUT(N) is a circuit composed of the nineteenth to twenty-sixth transistors (i.e., M19 to M26), the second capacitor C2 and the third capacitor C3, and is output according to the received first clock signal GCK1, the second clock signal GCK2 and other signals. For the specific electrical connection relationship between the nineteenth to twenty-sixth transistors, the second capacitor C2 and the third capacitor C3 and the generation principle of GOUT(N), please refer to Figure 4 and / or existing related content. In addition, Figure 4GOUT(N-4), GOUT(N-3), GOUT(N-2), GOUT(N-1), GOUT(N+1), and GOUT(N+4) shown respectively represent the row transmission signals output by the N+4th row driving circuit, the N-3th row driving circuit, the N-2th row driving circuit, the N-1th row driving circuit, the N+1th row driving circuit, and the N+4th row driving circuit. In this case, the values ​​of X4, X3, X2, X1, Y1, and Y2 are: X4=4, X3=3, X2=2, X1=1, Y1=1, Y2=4.

[0054] exist Figure 5a In the Figure 4 FIG. 4 is a waveform diagram showing the first driving signal EM(N), the second driving signal S1N, the third driving signal S2N and the row transmission signal GOUT(N) output by the Nth row driving circuit varying with time. Figure 5a SP2 in the figure represents the signal output by other circuits.

[0055] Further, see Figure 4 The first signal generating circuit 111 includes a first transistor M1, a second transistor M2 and a first capacitor C1. The gate g (gate) of the first transistor M1 is connected to the row transmission signal GOUT (N+4) output by the N+4 row driving circuit, the drain d (drain) is connected to the constant low voltage VHL, the source s (source) is connected to the drain d of the second transistor M2, and the first end of the first capacitor C1 to output the first driving signal EM (N). The gate of the second transistor M2 is connected to the row transmission signal GOUT (N-X4) output by the N-X4 row driving circuit, the source s is connected to the second end of the first capacitor C1 and connected to the constant high voltage VGH.

[0056] Combination Figures 3 to 5a The principle of the first signal generating circuit 111 outputting the first driving signal EM(N) is as follows:

[0057] Taking X4=4 and Y2=4 as an example, the line transmission signal GOUT(N-4) connected to the gate of the second transistor M2 is pulled down and is at a low level at time t-4, thereby turning on the second transistor M2. Since the source s of the second transistor M2 is connected to the constant high potential VGH and the drain d is used to output the first drive signal EM(N), the first drive signal EM(N) can be pulled high after the second transistor M2 is turned on, that is, the first drive signal EM(N) will be pulled high by GOUT(N-4) at time t-4. After the first drive signal EM(N) is pulled high, under the action of the first capacitor C1 connected in parallel with the second transistor M2, the voltage at the node F1 where the first capacitor C1 is electrically connected to the drain of the second transistor M2 will maintain a high level. In this way, even if the second transistor M2 is subsequently operated in a truncated state (off state) due to the change of the line transmission signal GOUT(N-4) from low to high (see the waveform of the line transmission signal GOUT(N-4) after time t-3), the first drive signal EM(N) will not fluctuate, and the first drive signal EM(N) will continue to maintain a high level state. Further, when it reaches time t+4, the line transmission signal Gout(N+4) connected to the first transistor M1 is pulled down and is at a low level, thereby turning on the first transistor M1. Since the drain d of the first transistor M1 is connected to a constant low potential and the source s is connected to the node F1 for outputting the first drive signal EM(N), the voltage at the node F1 will become a low level at this time, and accordingly, the first drive signal EM(N) output from the node F1 will be pulled down and become a low level.

[0058] As can be seen from the above, by using the row transmission signal GOUT(N-4) output by the N-4th row driving circuit and the row transmission signal GOUT(N+4) output by the N+4th row driving circuit, the first signal generating circuit 111 composed of the second transistor M2, the first transistor M1 and the first capacitor C1 can output the following: Figure 5a The first drive signal EM(N) shown in FIG. 1 maintains a high level during a time period between time t-4 and time t+4.

[0059] The second signal generating circuit 112 includes a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is connected to the row transmission signal GOUT(N-X1) output by the N-X1 row driving circuit, the drain d is connected to the constant low voltage potential VGL, and the source s and the drain d of the fourth transistor M4 are connected to a common node to output the second driving signal S1N. The gate of the fourth transistor M4 is connected to the row transmission signal GOUT(N-X2) output by the N-X2 row driving circuit, and the source s is connected to the constant high voltage potential VGH.

[0060] Combination Figures 3 to 5aThe principle of the second signal generating circuit 112 outputting the second driving signal S1N is as follows:

[0061] Taking X1=1 and X2=2 as an example, the row signal GOUT(N-2) connected to the gate of the fourth transistor M4 is pulled down and is at a low level at time t-2, thereby turning on the fourth transistor M4. Since the source s of the fourth transistor M4 is connected to the constant high potential VGH, the drain d and the source s of the third transistor M3 share the node F2 to output the second drive signal S1N, the voltage at the node F2 becomes a high level after the fourth transistor M2 is turned on, thereby causing the second drive signal S1N to be pulled high, that is, at this time t-2, the second drive signal S1N will be pulled high by the row signal GOUT(N-2). Further, when reaching time t-1, since the row signal Gout(N-1) connected to the third transistor M3 is pulled down and is at a low level, the third transistor M3 will be turned on. Since the drain d of the third transistor M3 is connected to the constant low potential VGL and the source s is connected to the node F2 for outputting the second drive signal S1N, the voltage at the node F2 will become low level at this time, and accordingly, the second drive signal S1N output from the node F2 will be pulled low. After time t, the third transistor M3 works in the cut-off state because the line transmission signal GOUT(N-1) changes from low to high, so the voltage at the node F2 will remain at a low level, and accordingly, the second drive signal S1N will also remain in a pulled-down state.

[0062] As can be seen from the above, by using the row transmission signal GOUT(N-2) output by the N-2 row driving circuit and the row transmission signal GOUT(N-1) output by the N-1 row driving circuit, the second signal generating circuit 112 composed of the third transistor M3 and the fourth transistor M4 can output the following: Figure 5a The second driving signal S1N shown in FIG. 1 maintains a high level during a time period between time t-2 and time t-1.

[0063] The third signal generating circuit 113 comprises a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8. The gates of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are connected to the row transmission signal GOUT(N-X2) output by the N-X2 row driving circuit, the row transmission signal GOUT(N-X3) output by the N-X3 row driving circuit, the row transmission signal GOUT(N+Y1) output by the N+Y1 row driving circuit and the row transmission signal GOUT(N) output by the N row driving circuit, respectively. Moreover, the source s of the fifth transistor M5, the drain d of the sixth transistor M6, the source s of the seventh transistor M7 and the drain d of the eighth transistor M8 are connected to a node F3 to output the third driving signal S2N, the drain d of the fifth transistor M5 and the drain d of the seventh transistor M7 are connected to the constant low potential VGL, and the source s of the sixth transistor M6 and the source s of the eighth transistor are connected to the constant high potential VGH.

[0064] Combination Figures 3 to 5a The principle of the third signal generating circuit 113 outputting the third driving signal S2N is as follows:

[0065] Taking X2=2, X3=3, and Y1=1 as an example, the row signal GOUT(N-3) connected to the gate of the sixth transistor M6 is pulled down and is at a low level at time t-3, thereby turning on the sixth transistor M6. Since the source s of the sixth transistor M6 is connected to the constant high potential VGH and the drain d is connected to the node F3 to output the second drive signal S2N, the voltage at the node F3 becomes a high level after the sixth transistor M6 is turned on, thereby causing the third drive signal S2N to be pulled high, that is, at this time t-3, the third drive signal S2N will be pulled high by the row signal GOUT(N-3). When reaching time t-2, since the row signal Gout(N-2) connected to the third transistor M5 is pulled down and is at a low level, the fifth transistor M5 will be turned on. Since the drain d of the fifth transistor M5 is connected to the constant low potential VGL and the source s is connected to the node F3 for outputting the second drive signal S1N, the voltage at the node F3 becomes low level at this time, and accordingly, the third drive signal S2N output from the node F3 is pulled low. At time t-1, the fifth transistor M5 works in the cut-off state because the line transmission signal GOUT(N-2) changes from low to high, so the voltage at the node F3 remains at a low level, and accordingly, the third drive signal S2N also remains in a pulled-down state.

[0066] Further, when the time t is reached, the row signal GOUT(N) connected to the gate of the eighth transistor M8 is pulled down and is at a low level, so that the eighth transistor M8 is turned on. Since the source s of the eighth transistor M8 is connected to the constant high potential VGH and the drain d is connected to the node F3 to output the second drive signal S2N, the voltage at the node F3 becomes high again after the eighth transistor M8 is turned on, thereby causing the third drive signal S2N to be pulled up again, that is, at the time t, the third drive signal S2N will be pulled up by the row signal GOUT(N). When the time t+1 is reached, since the row signal Gout(N+1) connected to the seventh transistor M7 is pulled down and is at a low level, the seventh transistor M7 will be turned on. Since the drain d of the seventh transistor M7 is connected to the constant low potential VGL and the source s is connected to the node F3 for outputting the third drive signal S2N, the voltage at the node F3 will become low at this time, and accordingly, the third drive signal S2N output from the node F3 will be pulled down. At time t+2, the seventh transistor M7 works in the cutoff state because the line transmission signal GOUT(N+1) changes from low to high. Therefore, the voltage at the node F3 remains at a low level. Accordingly, the third driving signal S2N also remains in a pulled-down state.

[0067] As can be seen from the above, by using the row signal GOUT(N-2) output by the N-2 row driving circuit, the row signal GOUT(N-3) output by the N-3 row driving circuit, the row signal GOUT(N+1) output by the N+1 row driving circuit and the row signal GOUT(N) output by the N row driving circuit, the third signal generating circuit 113 composed of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 can output the following: Figure 5a The third driving signal S2N shown in FIG. 1 maintains a high level in a time period between time t-3 and time t-2, and in a time period between time t and time t+1.

[0068] At least part of the first drive signal EM(N), the second drive signal S1N, the third drive signal S2N and the row signal GOUT(N) output by the Nth row drive circuit, and the row signal GOUT(N-1) output by the N-X1th row will be used as the input of the pixel circuit electrically connected to the Nth row drive circuit, so that the pixel circuit controls the corresponding light-emitting device to work using the signals received. Which signals are used as the input of the pixel circuit is related to the type of transistors in the pixel circuit, which will be described in detail below.

[0069] It should be noted here that the above combination Figure 4In the described example, the row transmission signals connected to the gates of the first transistor M1 to the eighth transistor M8 are only schematic. Of course, other values ​​can be set for X4, X3, X2, X1, Y1 and Y2 according to actual needs, so that the gates of the first transistor M1 to the eighth transistor M8 can be connected to the row transmission signals output by other row driving circuits, so as to control the order of the middle and high level outputs of the first drive signal EM(N), the second drive signal S1N and the third drive signal S2N and the time width occupied by the high level. For example, the second transistor M2 can be connected to the row transmission signal GOUT(N-6) output by the N-6 row driving circuit and the first transistor M1 can be connected to the row transmission signal GOUT(N+6) output by the N+6 row driving circuit, so that the output first drive signal EM(N) is at a high level in the time period between t-6 and t+6.

[0070] Figure 6a to Figure 6b The schematic diagrams of the structures of several types of pixel circuits are shown, among which: Figure 6a The pixel circuit shown is implemented using LTPO 8T1C. Figure 6b The pixel circuit shown in is implemented using LTPO 7T1C. Figure 6c The pixel circuit shown is implemented using LTPS 7T1C. Figure 6a As shown, the pixel circuit electrically connected to the Nth row driving circuit includes:

[0071] A first sub-circuit 21, electrically connected to the light emitting device 3, and used for receiving the first driving signal;

[0072] A second sub-circuit 22, used for receiving the second driving signal or the row transmission signal output by the N-X1th row driving circuit;

[0073] A third sub-circuit 23, wherein a first terminal a31 is electrically connected to the first sub-circuit, a second terminal a32 is electrically connected to the second sub-circuit, and a third terminal is used to receive the third driving signal or the row transmission signal output by the Nth row driving circuit;

[0074] The fourth sub-circuit 24 has one end electrically connected to the first sub-circuit for receiving the row transmission signal output by the Nth row driving circuit.

[0075] Specifically, the first sub-circuit 21 at least includes: a first circuit unit 211, a ninth transistor M9 and a second circuit unit 212.

[0076] The first end of the first circuit unit 211 is connected to the power supply voltage VDD of the pixel circuit, the second end is connected to one end of the fourth sub-circuit and the source s of the ninth transistor M9 as a node, and the third end is used to connect to the first drive signal. In specific implementation, the first circuit unit 211 includes at least the tenth transistor M10, and the gate of the tenth transistor M10 is also the third end of the first circuit unit 211, which is used to connect to the first drive signal EM(N). Furthermore, in some other embodiments, the first circuit unit 211 may also include a twelfth transistor M12, and the gate of the twelfth transistor M12 is used to connect to the pulse width modulation signal. The electrical connection method of the twelfth transistor M12 is as follows:

[0077] See Figure 6a In the pixel circuit shown in the upper part, the source s of the twelfth transistor M12 is connected to the supply voltage VDD, and the drain d is electrically connected to the source s of the ninth transistor M9 through the tenth transistor M10. In this electrical connection mode, the first end and the second end of the first circuit unit 211 mentioned above refer to the source s of the twelfth transistor M12 and the drain d of the tenth transistor M10, respectively. Or

[0078] See Figure 6a In the pixel circuit shown in the lower middle part, the twelfth transistor M12 is electrically connected between the ninth transistor M9 and the tenth transistor M10. In this electrical connection mode, the first end and the second end of the first circuit unit 211 are the source s of the tenth transistor M10 and the drain d of the twelfth transistor M12, respectively.

[0079] The first end of the second circuit unit 212 is electrically connected to the light emitting device 3, the second end is in common with the first end a31 of the third sub-circuit 23 and the drain d of the ninth transistor M9, and the third end is used to access the first drive signal EM(N). Similar to the first circuit unit, in a specific implementation, the second circuit unit 212 includes at least an eleventh transistor M11, and the gate of the eleventh transistor M11 is also the third end of the second circuit unit 212, which is used to access the first drive signal EM(N). Furthermore, in some other embodiments, the second circuit unit 212 may also include a thirteenth transistor M13, and the gate of the thirteenth transistor M13 is used to access the pulse width modulation signal. The electrical connection method of the thirteenth transistor M13 is as follows:

[0080] See Figure 6a In the pixel circuit shown in the upper part, the thirteenth transistor M13 is electrically connected between the eleventh transistor M11 and the light emitting device 3. In this electrical connection mode, the first end and the second end of the second circuit unit 212 mentioned above refer to the source s of the eleventh transistor M11 and the drain d of the thirteenth transistor M13, respectively.

[0081] See Figure 6a In the pixel circuit shown in the lower middle part, the thirteenth transistor M13 is electrically connected between the eleventh transistor M11 and the ninth transistor M9. In this electrical connection mode, the first end and the second end of the second circuit unit 212 are the source s of the thirteenth transistor M13 and the drain d of the eleventh transistor M11, respectively.

[0082] The twelfth transistor M12 and / or the thirteenth transistor M13 described above can be used to switch the working mode of the light emitting device. The working modes include a DC dimming mode and a pulse width modulation dimming mode. The switching of the working modes will be described in detail below.

[0083] As can be seen from the above, in this embodiment, the first sub-circuit 21 may be constructed in the following forms:

[0084] ① It is composed of a tenth transistor M10, a ninth transistor M9, and an eleventh transistor M11 which are electrically connected in sequence from top to bottom.

[0085] ② It is composed of a twelfth transistor M12, a tenth transistor M10, a ninth transistor M9, and an eleventh transistor M11 which are electrically connected in sequence from top to bottom.

[0086] ③ It is composed of a tenth transistor M10, a twelfth transistor M12, a ninth transistor M9, and an eleventh transistor M11 which are electrically connected in sequence from top to bottom.

[0087] ④ It is composed of a tenth transistor M10, a ninth transistor M9, an eleventh transistor M11, and a thirteenth transistor M13 which are electrically connected in sequence from top to bottom.

[0088] ⑤ It is composed of a tenth transistor M10, a ninth transistor M9, a thirteenth transistor M13, and an eleventh transistor M11 which are electrically connected in sequence from top to bottom.

[0089] ⑥ It is composed of a twelfth transistor M12, a tenth transistor M10, a ninth transistor M9, an eleventh transistor M11 and a thirteenth transistor M13 which are electrically connected in sequence from top to bottom.

[0090] ⑦ It is composed of a tenth transistor M10, a twelfth transistor M12, a ninth transistor M9, an eleventh transistor M11 and a thirteenth transistor M13 which are electrically connected in sequence from top to bottom.

[0091] ⑧ It is composed of a twelfth transistor M12, a tenth transistor M10, a ninth transistor M9, a thirteenth transistor M13 and an eleventh transistor M11 which are electrically connected in sequence from top to bottom.

[0092] ⑨ is composed of a tenth transistor M10, a twelfth transistor M12, a ninth transistor M9, a thirteenth transistor M13 and an eleventh transistor M11 which are electrically connected in sequence from top to bottom.

[0093] In order to realize the switching of different dimming modes for the light-emitting device 3 and ensure the balance of the voltage across the source and drain of the ninth transistor M9, in the present embodiment, preferably, the structure of the first sub-circuit 21 is as any one of the above forms ⑥ to ⑨, that is, the first sub-circuit 21 preferably includes a twelfth transistor M12 and a thirteenth transistor M13.

[0094] Figure 6a The first subcircuit 21 in the pixel circuit shown in the upper part is configured as described in ⑥ above, and the first subcircuit 21 in the pixel circuit shown in the lower part is configured as described in ⑨ above. Other configurations of the first subcircuit 21 are not shown in the figure.

[0095] In addition, the gate of the ninth transistor M9 in the first sub-circuit 21 is electrically connected to the second terminal a32 of the third sub-circuit 23 and the first terminal a21 of the first sub-circuit 21. Furthermore, each transistor in the first sub-circuit 21 is a P-type transistor (PMOS).

[0096] Furthermore, the first sub-circuit 21 further includes at least one of a fourteenth transistor M14 and a fifteenth transistor M15, which is used to implement a reset function. The specific implementation description of the reset function will be introduced below. The drain d of the fourteenth transistor M14 is in common with the source s of the ninth transistor M9, the second end of the first circuit unit 211 and one end of the fourth sub-circuit 24. The drain of the fifteenth transistor M15 is in common with the first end of the second circuit unit 212 and the anode of the light-emitting device 3.

[0097] Figure 6a An example is shown in which the first sub-circuit 21 includes a fourteenth transistor M14 and a fifteenth transistor M15 . Figure 6b and Figure 6c An example in which the first sub-circuit 21 includes a fifteenth transistor M15 is shown in FIG.

[0098] The signals connected to the second sub-circuit 22 and the third sub-circuit 23 are related to the types of transistors therein. Specifically,

[0099] If the transistors in the second subcircuit 22 and the third subcircuit 23 are both first-type transistors, the second subcircuit 22 is used to access the second drive signal S1N, and the third subcircuit 23 is used to access the third drive signal S2N. The first-type transistors are N-type transistors. Figure 6a or Figure 6bAs shown, the second sub-circuit 22 includes a sixteenth transistor M16, and the third sub-circuit 23 includes a seventeenth transistor M17, and both the sixteenth transistor M16 and the seventeenth transistor M17 are N-type transistors, and the N-type transistors are turned on at a high level, thereby connecting the gate of the sixteenth transistor M16 to the second drive signal S1N, and connecting the gate of the seventeenth transistor M17 to the third drive signal S2N.

[0100] If the transistors in the second subcircuit 22 and the third subcircuit 23 are both second-type transistors, the second subcircuit 22 is used to access the row transmission signal GOUT(N-X1) output by the N-X1 row driving circuit, and the third subcircuit 23 is used to access the row transmission signal GOUT(N) output by the N-row driving circuit. The second-type transistors are P-type transistors. Figure 6c As shown, the second sub-circuit 22 includes a sixteenth transistor M16, and the third sub-circuit 23 includes a seventeenth transistor M17, and both the sixteenth transistor M16 and the seventeenth transistor M17 are P-type transistors, and the P-type transistors are turned on at a low level. Therefore, the gate of the sixteenth transistor M16 is connected to the row signal GOUT(N-X1), and the gate of the seventeenth transistor M17 is connected to the row signal GOUT(N).

[0101] The fourth sub-circuit 24 includes an eighteenth transistor M18. The eighteenth transistor M18 is a P-type transistor, and its gate is used to receive the row transmission signal GOUT(N) output by the Nth row driving circuit.

[0102] It should be noted that, in addition to the transistors described above, the pixel circuit may also include other components, such as Figure 6a or Figure 6b or Figure 6c As shown, a fourth capacitor C4 may also be included, one end of which is connected to the power supply voltage of the pixel circuit, and the other end of which is electrically connected to the gate of the ninth transistor M9, the second end a32 of the third sub-circuit 23, and the first end a21 of the second sub-circuit 22. The function of the fourth capacitor C4 will be described in detail below. As for other specific components that may be included in the pixel circuit and their corresponding functions, please refer to the existing relevant content.

[0103] Combine the following Figure 6a The pixel circuit shown in the upper middle part introduces the principle that the pixel circuit uses the received signals to control the operation of the corresponding light-emitting device.

[0104] Combination Figure 5aThe first drive signal EM(N), the second drive signal S1N, the third drive signal S2N shown in the figure are the row transmission signal GOUT(N) output by the Nth row drive circuit, and some other input signals required by the pixel circuit, such as the signal SP2, which are signal waveforms that change with time. Since the pixel circuit needs to turn off the tenth transistor M10 and the eleventh transistor M11 before each new control to cut off the current from the power supply voltage VDD to the light-emitting device (such as OLED), so that the light-emitting device stops working (that is, turns off and stops emitting light), the first drive signal EM(N) connected to the tenth transistor M10 and the eleventh transistor M11 needs to be pulled up from low to high. During the time period when the first drive signal EM(N) is pulled high (the time period between t-4 and t+4), the tenth transistor M10 and the eleventh transistor M11 remain turned off, and during this time period, the pixel circuit is configured based on other connected signals so that the pixel circuit meets the preconditions required to control the light-emitting device to work and emit light. The specific configuration process is as follows:

[0105] See Figure 5a After the first drive signal EM(N) is pulled high at time t-4, when time t-3 is reached, the third drive signal S2N connected to the seventeenth transistor M17 is pulled high, so that the seventeenth transistor M17 is turned on, and the signal SP2 connected to the fourteenth transistor M14 is pulled low at the same time, so that the fourteenth transistor M14 is turned on, so that the third initial voltage signal Vinit3 is written to the node F5 through the fourteenth transistor M14, the ninth transistor M9 and the seventeenth transistor M17, that is, the voltage at the node F5 is Vinit3 at this time. Afterwards, when time t-2 is reached, the third drive signal S2N is pulled low, the signal SP2 is pulled high, and the fourteenth transistor M14 and the seventeenth transistor M17 are both turned off. In addition, at time t-2, since the second drive signal S1N is pulled high, the sixteenth transistor M16 is turned on, so that the first initial voltage signal is written to the node F5 through the sixteenth transistor M16, which is equivalent to the third initial voltage signal Vinit3 previously written to the node F5 being replaced by the current first initial voltage signal Vinit1, and the voltage at the node F5 at this time is Vinit1. After the first initial voltage signal Vinit1 is written, at time t-1, the second drive signal S1N is pulled low, so that the sixteenth transistor M16 is turned off. Since after the first initial voltage signal Vinit1 is written to the node F5, the node F5 is a negative voltage, so the ninth transistor is continuously turned on.

[0106] Further, at the next time t, the row transmission signal GOUT(N) output by the Nth row driving circuit is pulled low, and the third driving signal S2N is pulled high again, so that the eighteenth transistor M18 and the seventeenth transistor M17 are turned on at the same time, and the display data signal VData The 18th transistor M18, the 9th transistor M9 and the 17th transistor M17 are used to write to the node F5. After writing, because the line transmission signal GOUT(N) is pulled high and the third driving signal S2N is pulled low at time t+1, the 18th transistor M18 and the 17th transistor M17 are turned off. At this time, the voltage at the node F5 is V Data , the V Data will be stored in the fourth capacitor C4 to maintain stability. In other words, the voltage at F5 remains at V Data It is unchanged, and the size of this VData determines the conduction degree of the ninth transistor M9. It should be supplemented here that there is a certain time interval between the first drive signal S1N being pulled low at time t-1, and the line transmission signal GOUT(N) being pulled low and the third drive signal S2N being pulled high at time t. Of course, there may be no certain time interval, but in order to achieve a better control effect, a certain time interval is preferably selected.

[0107] Further, at the time t+2, the signal SP2 is pulled low again, so that the fourteenth transistor M14 and the fifteenth transistor M15 are both turned on, and the third initial signal Vinit3 is written to the node F4 through the fourteenth transistor M14, and the second initial signal Vinit2 is written to the node F6 through the fifteenth transistor M15. The above further writing action is actually an anode reset to make the potentials of the nodes F4 and F5 return to an initial state before controlling the operation of the light-emitting device. Afterwards, at the time t+3, the signal SP2 is pulled high, so that the fourteenth transistor M14 and the fifteenth transistor M15 are turned off. At this point, the pixel circuit is ready for the preconditions required to control the operation of the light-emitting device.

[0108] Next is to control the light emitting device to emit light. The process of controlling the light emitting device is as follows:

[0109] Continue to see Figure 5a , when the time t+4 is reached, the first driving signal EM(N) is pulled low, so that the tenth transistor M10 and the eleventh transistor M11 are both turned on. If the twelfth transistor M12 and the thirteenth transistor M13 are not electrically connected in the pixel circuit, a vertical DC path will be formed from the power supply voltage VDD to the light-emitting device 3, so that the light-emitting device 3 always works in the DC dimming mode (DC mode).

[0110] In order to switch the working mode of the light emitting device, the present embodiment further electrically connects the twelfth transistor M12 and the thirteenth transistor M13 in the pixel circuit, and the gates of the twelfth transistor M12 and the thirteenth transistor M13 are both connected to a low-level pulse width modulation signal. Figure 5b, when the pulse width modulation signal (PWM) is kept at a low level for a long time in the time period between t+4 and T1, the twelfth transistor M12 and the thirteenth transistor M13 are both in the on state in the time period. Since the tenth transistor M10, the ninth transistor M9 and the eleventh transistor M11 are also in the on state at this time, a vertical DC path is formed between the power supply voltage VDD and the light emitting device 3, and the light emitting device 3 works in the DC dimming mode. After reaching the time T1, if the pulse width modulation signal changes to a low-level periodically alternating signal, the twelfth transistor M12 and the thirteenth transistor M13 are both intermittently turned on, so that the light emitting device works in the "on--off--on--off" and other working modes, that is, it works in the pulse width modulation dimming mode (PWM mode).

[0111] As can be seen from the above, this solution can control the operation of the light-emitting device to switch arbitrarily between the DC mode and the PWM mode by adding the twelfth transistor M12 and the thirteenth transistor M13 in the pixel circuit and connecting the corresponding pulse width modulation signals to them.

[0112] It is generally supplemented here that the transistor described in the context of this application may more specifically refer to a thin film transistor (TFT for short). TFT is a field effect transistor.

[0113] In summary, the control circuit provided in this embodiment includes a plurality of cascaded drive circuits and a plurality of pixel circuits, each row of drive circuits outputs a row transmission signal according to a received clock signal, and the row transmission signals output by two adjacent row drive circuits are continuous in time; except for the first number of row drive circuits in the front cascade sequence and the second number of rows in the back cascade sequence, each row of drive circuits is electrically connected to a corresponding pixel circuit, and each row of drive circuits includes a first signal generating circuit, a second signal generating circuit and a third signal generating circuit. Among them, in the Nth row drive circuit: the first signal generating circuit is used to output a first drive signal according to the row transmission signal output by the N+Y2th row drive circuit and the N-X4th row drive circuit; the second signal generating circuit is used to output a second drive signal according to the row transmission signal output by the N-X1th row drive circuit and the N-X2th row drive circuit; the third signal generating circuit is used to output a third drive signal according to the row transmission signal output by the N-X2th row drive circuit, the N-X3th row drive circuit, the Nth row drive circuit and the N+Y1th row drive circuit. The above-mentioned output drive signals and at least part of the row transmission signals output by the N-row drive circuit and the N-X1-row drive circuit will be input into the pixel circuit electrically connected to the N-row drive circuit, so that the pixel circuit controls the corresponding light-emitting device to operate based on the received signals. It can be seen that the N-row drive circuit in this scheme can generate the drive signals required for the pixel circuit to control the light-emitting device to operate based on the row transmission signals output by multiple rows of other drive circuits (the multiple rows of other drive circuits can be adjacent or spaced by one or more rows, etc.), without the need to rely on other circuits such as EOA and Nscan GOA to generate them. This helps to reduce the border size of the display panel and further promote the development of narrow borders of display screens.

[0114] Based on the above content, the present application also provides an embodiment of a control method. Figure 7 The flowchart of the control method provided in the embodiment of the present application is shown. The control method is applicable to the N-row driving circuit and the pixel circuit electrically connected to the N-row driving circuit. The N-row driving circuit is one of the multiple row cascaded driving circuits in the control circuit provided in other embodiments of the present application. Figure 7 The control method comprises the following steps:

[0115] 101. Receive row transmission signals outputted by the N-X4 row driving circuit, the N-X3 row driving circuit, the N-X2 row driving circuit, the N-X1 row driving circuit, the N row driving circuit, the N+Y1 row driving circuit and the N+Y2 row driving circuit, respectively, among the plurality of row driving circuits; wherein the row transmission signals include a low level, and the low level levels in the row transmission signals outputted by two adjacent row driving circuits are continuous in time;

[0116] 102. Generate a first driving signal according to the row transmission signals output by the N+Y2th row driving circuit and the N-X4th row driving circuit;

[0117] 103. Generate a second driving signal according to the row transmission signals output by the N-X1th row driving circuit and the N-X2th row driving circuit;

[0118] 104. Generate a third driving signal according to the row transmission signals output by the N-X2 row driving circuit, the N-X3 row driving circuit, the N row driving circuit, and the N+Y1 row driving circuit;

[0119] 105. Control the operation of corresponding light-emitting devices based on at least part of the first drive signal, the second drive signal, the third drive signal, and row transmission signals output by the Nth row drive circuit and the N-X1th row drive circuit.

[0120] The above 101-104 are executed by the Nth row driving circuit, and the above 105 is executed by the pixel circuit electrically connected to the Nth row driving circuit. For the specific implementation description of 101-104, please refer to the relevant content in other embodiments above, and will not be described in detail here.

[0121] In an implementable solution, the above 105 “controlling the operation of the corresponding light emitting device based on at least part of the row transmission signals output by the Nth row driving circuit and the N-X1th row driving circuit” may specifically include:

[0122] 1051. Based on the first drive signal, the second drive signal, the third drive signal, and at least part of the row transmission signals output by the N-th row drive circuit and the N-X1-th row drive circuit, configure the pixel circuit electrically connected to the N-th row drive circuit so that the pixel circuit meets the preconditions required for controlling the operation of the light-emitting device;

[0123] 1052. After the configuration is completed, the first driving signal is at a low level, and the light-emitting device works.

[0124] In a specific implementation, the pixel circuit includes a first subcircuit electrically connected to the light-emitting device, the first subcircuit includes a first circuit unit, a ninth transistor, and a second circuit unit electrically connected in series, wherein one end of the second circuit unit is electrically connected to the light-emitting device. Accordingly, the pixel circuit satisfies the preconditions required to control the operation of the light-emitting device, including:

[0125] The ninth transistor is turned on, and at least the tenth transistor included in the first circuit unit and at least the eleventh transistor included in the second circuit unit are turned off; wherein the degree of conduction of the ninth transistor is controlled according to the voltage at the node where the ninth transistor is electrically connected to the second sub-circuit in the pixel circuit;

[0126] The source of the ninth transistor and / or the anode of the light emitting device is reset to a reset voltage value.

[0127] Combination Figure 6a In the structural schematic diagram of the pixel circuit shown above, the source s of the ninth transistor described here is reset to the reset voltage value, which means that the voltage at the node F4 returns to Vinit3; and the anode of the light-emitting device is reset to the reset voltage value, which means that the voltage at the node F6 returns to Vinit2.

[0128] When implementing the configuration of the pixel circuit, the signals used for configuration are largely related to the types of transistors in the second subcircuit and the third subcircuit included in the pixel circuit. Specifically, the pixel circuit also includes the second subcircuit and the third subcircuit, the first end of the third subcircuit is electrically connected to the first subcircuit, and the second end is electrically connected to one end of the second subcircuit; and accordingly, the above 1051 "based on the first drive signal, the second drive signal, the third drive signal, at least part of the row transmission signals output by the Nth row drive circuit and the N-X1th row drive circuit, the pixel circuit electrically connected to the Nth row drive circuit is configured" may specifically include:

[0129] 10511. When the transistors in the second sub-circuit and the third sub-circuit are all first-type transistors, the pixel circuit is configured based on the first drive signal, the second drive signal, the third drive signal, and the row transmission signal output by the Nth row drive circuit;

[0130] 10512. When the transistor types in the second sub-circuit and the third sub-circuit are both second-type transistors, the pixel circuit is configured based on the first drive signal and the row transmission signals output by the Nth row drive circuit and the N-X1th row drive circuit respectively.

[0131] For the specific implementation description of the above steps 10511 to 10512, please refer to the relevant content in other embodiments above.

[0132] Furthermore, a specific implementation scheme of “the first driving signal is at a low level and the light emitting device works” in the above 1052 may include:

[0133] 10521. When the first driving signal is at a low level, the tenth transistor and the eleventh transistor are both turned on, and the first sub-circuit forms a DC path, so that the light-emitting device operates in a DC dimming mode.

[0134] Further, the first circuit unit further includes a twelfth transistor and / or the second circuit further includes a thirteenth transistor; and the above step 1052 may further include the following steps:

[0135] 10522. When the twelfth transistor and / or the thirteenth transistor is intermittently turned on, the light-emitting device is switched to operate in a pulse width modulation dimming mode.

[0136] For the specific implementation description of each step described above in this embodiment, please refer to the relevant content in other embodiments above. In addition to the above steps, other steps may be included in the embodiment of the present application. For the other steps that may be included and their specific implementation description, please refer to the relevant content in other embodiments above. And, for the specific structural description of the pixel circuit and the driving circuit, please refer to the relevant content in other embodiments.

[0137] The control circuit provided in the present application can be arranged in a display screen in practice. Therefore, another embodiment of the present application provides a display screen. The display screen includes a display panel and a control circuit as provided in an embodiment of the present application, the control circuit is arranged in the space of the display panel, and the steps in the control method provided in other embodiments of the present application can be implemented through the N-th row driving circuit included in the control circuit and the pixel circuit electrically connected to the N-th row driving circuit.

[0138] During specific implementation, for detailed description of the control circuit, please refer to the relevant contents in other embodiments above. Also, the above-mentioned display screen may include an LCD (Liquid Crystal Display) display screen or an OLED (Organic Light-Emitting Diode) display screen for displaying the interface of the terminal system or various applications. And if the display panel included in the above-mentioned display screen is a touch panel (TP), the display screen can be implemented as a touch screen to receive input signals from the user. The touch panel may include one or more touch sensors to sense touch, slide and gestures on the touch panel. The touch sensor can not only sense the boundary of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0139] The display screen can be mounted on the housing of the terminal device. Thus, another embodiment of the present application provides a terminal device, which can be a mobile phone, a tablet computer, a PDA (Personal Digital Assistant), a netbook, a desktop computer, a virtual reality device (AR / VR device), a car computer, a wearable device (such as a smart bracelet), a smart home device, and other electronic devices.

[0140] Figure 8 The structure diagram of the terminal device provided in the embodiment of the present application is shown. Figure 8 The terminal device 4 includes: a housing (not shown in the figure) and a display screen 41 provided in other embodiments of the present application, and the display screen is installed on the housing.

[0141] For detailed description of the display screen 41, please refer to the relevant contents of other embodiments above.

[0142] In addition to the above, the terminal device 4 may also include other components, such as a control device 42, a camera 43, a memory 44, a communication component 45, a power component 46, and an audio component 47, etc. Figure 8 The following only schematically shows some components of the terminal device, which does not mean that the terminal device only includes Figure 8 Components shown.

[0143] The control device 42 includes a processor. The processor is coupled to the memory 44 and is used to execute the computer program in the memory 44 to implement the steps or functions of the control method provided in other embodiments of the present application through the N-th row driving circuit and the pixel circuit electrically connected to the N-th row driving circuit included in the control circuit provided in other embodiments of the present application.

[0144] The memory 44 is used to store computer programs and can be configured to store various other data to support operations on the terminal device. Examples of such data include instructions for any application or method used to operate on the terminal device. The memory 44 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0145] The camera 43 is used to capture still images or videos.

[0146] The above-mentioned communication component 45 is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G and other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0147] The power supply assembly 46 provides power to various components of the device where the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device where the power supply assembly is located.

[0148] The above-mentioned audio component 47 can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC), and when the device where the audio component is located is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in a memory or sent via a communication component. In some embodiments, the audio component also includes a speaker for outputting an audio signal.

[0149] Accordingly, an embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed, each step in the above method embodiment can be implemented.

[0150] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media that include computer-usable program code. Computer-usable storage media include, but are not limited to, disk storage, CD-ROM, optical storage, etc.

[0151] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0152] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0153] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0154] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0155] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0156] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0157] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0158] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A control circuit, characterized in that: include: A plurality of row cascaded drive circuits and a plurality of pixel circuits, each row drive circuit outputs a row transmission signal according to a received clock signal, and the low levels of the row transmission signals output by two adjacent row drive circuits are continuous in time; except for the first number of row drive circuits in the front cascade sequence and the second number of row drive circuits in the back cascade sequence, each row drive circuit is electrically connected to the corresponding pixel circuit, and each row drive circuit includes a first signal generating circuit, a second signal generating circuit and a third signal generating circuit; wherein, In the Nth row driving circuit: The first signal generating circuit is used to output a first driving signal according to the row transmission signals output by the N+Y2th row driving circuit and the N-X4th row driving circuit; The second signal generating circuit is used to output a second driving signal according to the row transmission signals output by the N-X1th row driving circuit and the N-X2th row driving circuit; The third signal generating circuit is used to output a third driving signal according to the row transmission signals output by the N-X2 row driving circuit, the N-X3 row driving circuit, the N row driving circuit and the N+Y1 row driving circuit; a pixel circuit electrically connected to the N-th row driving circuit, configured to control the operation of the corresponding light-emitting device based on at least part of the first driving signal, the second driving signal, the third driving signal, and the row transmission signals output by the N-th row driving circuit and the N-X1-th row driving circuit; Among them, the first number is greater than or equal to 4, the second number is greater than or equal to 2, N, X4, X3, X2, X1, Y1 and Y2 are all natural numbers greater than zero, X4 is greater than X3, X3 is greater than X2, X2 is greater than X1, Y2 is greater than Y1, and N is greater than the first number and less than or equal to the difference between the total number of rows of the driving circuit and the second number.

2. The control circuit according to claim 1, characterized in that: The first signal generating circuit includes a first transistor, a second transistor and a first capacitor; the gate of the first transistor is connected to the row transmission signal output by the N+Y2 row driving circuit, the drain is connected to a constant voltage low potential, the source is connected to the drain of the second transistor, and the first end of the first capacitor to output the first driving signal; the gate of the second transistor is connected to the row transmission signal output by the N-X4 row driving circuit, the source is connected to the second end of the first capacitor and connected to a constant voltage high potential; The second signal generating circuit includes a third transistor and a fourth transistor; the gate of the third transistor is connected to the row transmission signal output by the N-X1 row driving circuit, the drain is connected to a constant voltage low potential, and the source and the drain of the fourth transistor share a common node to output the second driving signal; the gate of the fourth transistor is connected to the row transmission signal output by the N-X2 row driving circuit, and the source is connected to a constant voltage high potential; The third signal generating circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; the gates of the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are respectively connected to the row transmission signals output by the N-X2 row driving circuit, the N-X3 row driving circuit, the N+Y1 row driving circuit and the N row driving circuit; and the source of the fifth transistor, the drain of the sixth transistor, the source of the seventh transistor and the drain of the eighth transistor are connected to a common node to output the third driving signal; the drain of the fifth transistor and the drain of the seventh transistor are both connected to a constant low voltage potential, and the source of the sixth transistor and the source of the eighth transistor are both connected to a constant high voltage potential.

3. The control circuit according to claim 1 or 2, characterized in that: The pixel circuit electrically connected to the Nth row driving circuit comprises: A first sub-circuit, electrically connected to the light-emitting device, and configured to receive the first driving signal; A second sub-circuit, used for receiving the second driving signal or the row transmission signal output by the N-X1th row driving circuit; A third sub-circuit, a first end of which is electrically connected to the first sub-circuit, a second end of which is electrically connected to one end of the second sub-circuit, and a third end of which is used to receive the third driving signal or the row transmission signal output by the Nth row driving circuit; A fourth sub-circuit, one end of which is electrically connected to the first sub-circuit, is used to receive the row transmission signal output by the Nth row driving circuit.

4. The control circuit according to claim 3, characterized in that: The first sub-circuit at least comprises: A first circuit unit, a ninth transistor and a second circuit unit; wherein, The first end of the first circuit unit is connected to the power supply voltage of the pixel circuit, the second end is connected to a common node with one end of the fourth sub-circuit and the source of the ninth transistor, and the third end is used to connect to the first driving signal; The first end of the second circuit unit is electrically connected to the light emitting device, the second end is a common node with the first end of the third sub-circuit and the drain of the ninth transistor, and the third end is used to receive the first driving signal; A gate of the ninth transistor is electrically connected to the second end of the third sub-circuit and one end of the second sub-circuit.

5. The control circuit according to claim 4, characterized in that: The first circuit unit includes at least a tenth transistor, and the second circuit unit includes at least an eleventh transistor; gates of the tenth transistor and the eleventh transistor are both connected to the first driving signal.

6. The control circuit according to claim 5, characterized in that: The first circuit unit further includes a twelfth transistor and / or the second circuit unit further includes a thirteenth transistor, which are used to switch the working mode of the light emitting device, and the working mode includes a DC dimming mode and a pulse width modulation dimming mode; wherein, The source of the twelfth transistor is connected to the supply voltage, and the drain is electrically connected to the source of the ninth transistor through the tenth transistor; or the twelfth transistor is electrically connected between the ninth transistor and the tenth transistor; The thirteenth transistor is electrically connected between the eleventh transistor and the light emitting device, or the thirteenth transistor is electrically connected between the eleventh transistor and the ninth transistor; The gates of the twelfth transistor and the thirteenth transistor are both connected to the pulse width modulation signal.

7. The control circuit according to claim 4, characterized in that: The first sub-circuit further includes at least one of a fourteenth transistor and a fifteenth transistor, for implementing a reset function; The drain of the fourteenth transistor shares a common node with the source of the ninth transistor, the second end of the first circuit unit and one end of the fourth sub-circuit; The drain of the fifteenth transistor shares a common node with the first end of the second circuit unit and the anode of the light emitting device.

8. The control circuit according to any one of claims 4 to 7, characterized in that: When the transistors in the second sub-circuit and the third sub-circuit are both first-type transistors, the second sub-circuit is used to access the second drive signal; and the third sub-circuit is used to access the third drive signal; When the transistors in the second subcircuit and the third subcircuit are both second type transistors, the second subcircuit is used to access the row transmission signal output by the N-X1th row driving circuit, and the third subcircuit is used to access the row transmission signal output by the Nth row driving circuit.

9. A control method, characterized in that: Applicable to an N-row driving circuit and a pixel circuit electrically connected to the N-row driving circuit, wherein the N-row driving circuit is one of a plurality of row cascaded driving circuits in a control circuit as described in any one of claims 1 to 8; the method comprising: receiving row transmission signals outputted by the N-X4 row driving circuit, the N-X3 row driving circuit, the N-X2 row driving circuit, the N-X1 row driving circuit, the N row driving circuit, the N+Y1 row driving circuit and the N+Y2 row driving circuit respectively among the plurality of row driving circuits; wherein the row transmission signals include a low level, and the low levels in the row transmission signals outputted by two adjacent row driving circuits are continuous in time; Generate a first driving signal according to the row transmission signals output by the N+Y2th row driving circuit and the N-X4th row driving circuit; Generate a second driving signal according to the row transmission signals output by the N-X1th row driving circuit and the N-X2th row driving circuit; Generate a third driving signal according to the row transmission signals output by the N-X2 row driving circuit, the N-X3 row driving circuit, the N row driving circuit and the N+Y1 row driving circuit; Based on the first drive signal, the second drive signal, the third drive signal, and at least part of the row transmission signals output by the Nth row drive circuit and the N-X1th row drive circuit, the corresponding light-emitting devices are controlled to operate.

10. The method according to claim 9, characterized in that Based on the first drive signal, the second drive signal, the third drive signal, and at least part of the row transmission signals output by the Nth row drive circuit and the N-X1th row drive circuit, controlling the corresponding light emitting devices to operate includes: Based on the first drive signal, the second drive signal, the third drive signal, and at least part of the row transmission signals output by the N-th row drive circuit and the N-X1-th row drive circuit, a pixel circuit electrically connected to the N-th row drive circuit is configured so that the pixel circuit meets the preconditions required for controlling the operation of the light-emitting device; After the configuration is completed, the first driving signal is at a low level and the light emitting device works.

11. The method according to claim 10, characterized in that The pixel circuit includes a first subcircuit electrically connected to the light emitting device, the first subcircuit includes a first circuit unit, a ninth transistor and a second circuit unit electrically connected in series, wherein one end of the second circuit unit is electrically connected to the light emitting device; The pixel circuit meets the preconditions required for controlling the operation of the light-emitting device, including: The ninth transistor is turned on, and at least the tenth transistor included in the first circuit unit and at least the eleventh transistor included in the second circuit unit are turned off; wherein the degree of conduction of the ninth transistor is controlled according to the voltage at the node where the ninth transistor is electrically connected to the second sub-circuit in the pixel circuit; The source of the ninth transistor and / or the anode of the light emitting device is reset to a reset voltage value.

12. The method according to claim 11, characterized in that The first driving signal is at a low level, and the light emitting device works, including: When the first driving signal is at a low level, the tenth transistor and the eleventh transistor are both turned on, and the first sub-circuit forms a DC path, so that the light-emitting device operates in a DC dimming mode.

13. The method according to claim 12, characterized in that The first circuit unit further includes a twelfth transistor and / or the second circuit unit further includes a thirteenth transistor; When the twelfth transistor and / or the thirteenth transistor is intermittently turned on, the light emitting device is switched to operate in a pulse width modulation dimming mode.

14. The method according to any one of claims 11 to 13, characterized in that The pixel circuit further includes a second sub-circuit and a third sub-circuit, wherein a first end of the third sub-circuit is electrically connected to the first sub-circuit, and a second end of the third sub-circuit is electrically connected to one end of the second sub-circuit; and Based on the first drive signal, the second drive signal, the third drive signal, and at least part of the row transmission signals output by the N-th row drive circuit and the N-X1-th row drive circuit, a pixel circuit electrically connected to the N-th row drive circuit is configured, including: When the transistors in the second sub-circuit and the third sub-circuit are all first-type transistors, the pixel circuit is configured based on the first drive signal, the second drive signal, the third drive signal and the row transmission signal output by the Nth row drive circuit; When the transistor types in the second sub-circuit and the third sub-circuit are both second-type transistors, the pixel circuit is configured based on the first driving signal and the row transmission signals output by the Nth row driving circuit and the N-X1th row driving circuit.

15. A display screen, characterized in that: include: Display panel; The control circuit described in any one of claims 1 to 8 above is arranged in the space of the display panel, and the steps of the control method described in any one of claims 9 to 14 above can be implemented through the N-th row driving circuit included in the control circuit and the pixel circuit electrically connected to the N-th row driving circuit.

16. A terminal device, characterized in that: include: A housing and a display screen as claimed in claim 15, wherein the display screen is mounted on the housing.

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