Pixel circuit, driving method of pixel circuit and display panel

Abstract

The invention discloses a pixel circuit, a driving method of the pixel circuit and a display panel. The pixel circuit comprises a driving module, the driving module and a first power supply end are connected to a first node, and the driving module and a light-emitting module are connected to a second node; the unloading module and a second control end of the driving module are connected to a fourth node, a control end of the unloading module is connected with a second scanning line, and the unloading module is used for transmitting data voltage to the fourth node; the compensation module is connected with the first control end of the driving module, the control end of the compensation module is connected with a third scanning line, and the compensation module is used for compensating and storing the threshold voltage of the driving module; wherein a second scanning signal transmitted by the second scanning line and a third scanning signal transmitted by the third scanning line are global control signals. According to the technical scheme provided by the invention, the narrow-frame display panel is realized.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a pixel circuit, a driving method of the pixel circuit, and a display panel. Background Art

[0002] With the development of display technology, people have higher and higher requirements on display panels. Existing display panels have the problem of wide left and right borders. Summary of the invention

[0003] Embodiments of the present invention provide a pixel circuit, a driving method of the pixel circuit and a display panel to solve the problem of wide left and right borders of the display panel.

[0004] In order to achieve the above technical problems, the present invention adopts the following technical solutions:

[0005] An embodiment of the present invention provides a pixel circuit, including:

[0006] A driving module, the driving module is connected to the first power supply terminal at a first node, and is connected to the light emitting module at a second node;

[0007] A transfer module, wherein the transfer module and the second control end of the driving module are connected to the fourth node, and the control end of the transfer module is connected to the second scanning line for transmitting a data voltage to the fourth node;

[0008] A compensation module, the compensation module is connected to the first control terminal of the driving module, the control terminal of the compensation module is connected to the third scanning line, and is used to compensate and store the threshold voltage of the driving module;

[0009] The second scanning signal transmitted by the second scanning line and the third scanning signal transmitted by the third scanning line are both global control signals.

[0010] Optionally, the pixel circuit further includes:

[0011] A data writing module, wherein the data writing module and the transfer module are connected to the third node, and a control end of the data writing module is connected to the first scanning line for transmitting a data voltage to the third node;

[0012] The first scanning signal transmitted by the first scanning line is a line-by-line scanning signal.

[0013] Optionally, the pixel circuit further includes:

[0014] A first storage module, the first storage module is connected between the third node and the first power supply terminal, and the first storage module is used to store data voltage;

[0015] Optionally, the data writing module includes a first switching tube, and the first storage module includes a first capacitor; the first electrode of the first switching tube is connected to the data line, the second electrode of the first switching tube and the first end of the first capacitor are connected to a third node, the control electrode of the first switching tube is connected to the first scanning line, and the second end of the first capacitor is connected to the first power supply end.

[0016] Optionally, the pixel circuit further includes:

[0017] The second storage module, the transfer module and the second control end of the driving module and the second storage module are connected to the fourth node, and the second storage module is connected between the second node and the fourth node;

[0018] Optionally, the transfer module includes a second switching tube, and the second storage module includes a second capacitor; the first electrode of the second switching tube is connected to the third node, the second electrode of the second switching tube is connected to the second control end of the driving module and the first end of the second capacitor is connected to the fourth node, the second end of the second capacitor is connected to the second node, and the control electrode of the second switching tube is connected to the second scan line.

[0019] Optionally, the compensation module includes: a compensation unit, a reset unit and a third storage unit;

[0020] The compensation unit, the first control end of the driving module and the third storage unit are connected to the fifth node, the compensation unit is connected between the first node and the fifth node, and the control end of the compensation unit is connected to the third scan line;

[0021] The third storage unit, the reset unit and the second end of the driving module are connected to the second node, the reset unit is connected between the first initialization line and the second node, and the control end of the reset unit is connected to the third scanning line;

[0022] Optionally, the compensation unit includes a third switch tube, the reset unit includes a fourth switch tube, and the third storage unit includes a third capacitor;

[0023] A first electrode of the third switch tube is connected to the first node, a second electrode of the third switch tube and the first control terminal of the driving module and the first end of the third capacitor are connected to a fifth node, and a control electrode of the third switch tube is connected to the third scan line;

[0024] The second end of the third capacitor, the first electrode of the fourth switch tube and the second end of the driving module are connected to the second node, the second electrode of the fourth switch tube is connected to the first initialization line, and the control electrode of the fourth switch tube is connected to the third scan line.

[0025] Optionally, the pixel circuit further includes:

[0026] A first initialization module is connected between the second initialization line and the anode of the light emitting module, and a control end of the first initialization module is connected to the second scanning line;

[0027] A second initialization module, the second initialization module is connected between the first initialization line and the fourth node, and a control end of the second initialization module is connected to the third scanning line;

[0028] Optionally, the first initialization module includes a fifth switch tube; a first electrode of the fifth switch tube is connected to the second initialization line, a second electrode of the fifth switch tube is connected to the anode of the light emitting module, and a control electrode of the fifth switch tube is connected to the second scan line;

[0029] Optionally, the second initialization module includes a sixth switch tube, a first electrode of the sixth switch tube is connected to the first initialization line, a second electrode of the sixth switch tube is connected to the fourth node, and a control electrode of the sixth switch tube is connected to the third scan line.

[0030] Optionally, the pixel circuit further includes:

[0031] A first light-emitting control module is connected between the second end of the driving module and the anode of the light-emitting module, and a control end of the first light-emitting control module is connected to a first light-emitting control line; a first light-emitting control signal transmitted by the first light-emitting control line is a global control signal;

[0032] Optionally, the first light-emitting control module includes a seventh switch tube, a first electrode of the seventh switch tube is connected to the second end of the driving module, a second electrode of the seventh switch tube is connected to the anode of the light-emitting module, and a control electrode of the seventh switch tube is connected to the first light-emitting control line;

[0033] Optionally, the pixel circuit further includes: a second light emitting control module connected between the first power supply terminal and the first node, a control terminal of the second light emitting control module connected to a second light emitting control line; a second light emitting control signal transmitted by the second light emitting control line is a global control signal;

[0034] Optionally, the second light-emitting control module includes an eighth switch tube, a first electrode of the eighth switch tube is connected to the first power supply terminal, a second electrode of the eighth switch tube is connected to the first node, and a control electrode of the eighth switch tube is connected to the second light-emitting control line;

[0035] Optionally, the driving module includes a driving transistor, the light-emitting module includes an organic light-emitting diode, the first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor and the first end of the first light-emitting control module are connected to the second node, the second end of the first light-emitting control module is connected to the anode of the organic light-emitting diode, and the cathode of the organic light-emitting diode is connected to the second power supply end; the first control end of the driving transistor and the compensation module are connected to the fifth node, and the second control end of the driving transistor and the transfer module are connected to the fourth node.

[0036] According to a second aspect of the present invention, this embodiment provides a method for driving a pixel circuit, the method being performed by the pixel circuit provided in any item of the first aspect; the method comprising:

[0037] In the compensation stage, the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the third scanning signal, and store the threshold voltage of the driving module;

[0038] In the data writing stage, the transfer modules in all the pixel circuits simultaneously transmit the data voltage to the second control terminal of the driving module according to the second scanning signal;

[0039] Wherein, the second scanning signal and the third scanning signal are both global control signals.

[0040] Optionally, in the compensation stage, before the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the third scanning signal and store the threshold voltage of the driving module, the method further includes:

[0041] In the data pre-writing stage, the first storage module in each pixel circuit stores the data voltage row by row according to the first scanning signal; the first scanning signal is a row-by-row scanning signal;

[0042] Optionally, in the compensation stage, the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the third scanning signal and store the threshold voltage of the driving module, including:

[0043] In the compensation stage, the voltage difference across the second storage modules in all the pixel circuits is zero, and the third storage units of the compensation modules in all the pixel circuits simultaneously store the threshold voltage of the driving module;

[0044] Optionally, in the data writing stage, the transfer modules in all the pixel circuits simultaneously transmit the data voltage to the second control terminal of the driving module according to the second scanning signal, including:

[0045] In the data writing stage, the transfer modules in all the pixel circuits simultaneously transfer the data voltage temporarily stored in the first storage module to the second control terminal of the driving module according to the second scanning signal, and store it through the second storage module.

[0046] According to yet another aspect of the present invention, this embodiment provides a display panel, comprising the pixel circuit provided in any item of the first aspect.

[0047] The pixel circuit provided by the embodiment of the present invention includes a driving module, a transfer module and a compensation module. The threshold voltage of the driving module is compensated by the compensation module. Then, the data voltage is transmitted to the second control terminal of the driving module by the transfer module. By setting the second scanning signal transmitted by the second scanning line and the third scanning signal transmitted by the third scanning line to be global control signals, the compensation phase of the pixel circuits located in different rows is carried out simultaneously, so that the pixel circuits located in different rows can use a common GIP circuit to provide the timing signal required for the compensation phase. In this way, the compensation phase and the light-emitting phase of the pixel circuits of each row can use a common GIP circuit, which can not only improve the threshold voltage compensation effect of the driving module in the pixel circuit of the display panel, improve the brightness uniformity of the display panel, and improve the display effect of the display panel, but also reduce the number of GIP circuits that generate timing signals, thereby reducing the space occupied by the GIP circuit that provides the timing signal in the frame of the display panel, and reducing the width of the left and right frames of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.

[0049] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0050] Figure 2 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0051] Figure 3 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0052] Figure 4 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0053] Figure 5 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0054] Figure 6 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0055] Figure 7 is a schematic diagram of a driving timing of a pixel circuit provided by an embodiment of the present invention;

[0056] Figure 8is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present invention;

[0057] Fig. 9 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0059] Based on the above technical problems, this embodiment proposes the following solutions:

[0060] Figure 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 1 The pixel circuit 100 provided by the embodiment of the present invention includes a driving module 1, a transfer module 31 and a compensation module 4. The driving module 1 is connected to the first power supply terminal ELVDD at the first node N1, and the driving module 1 is connected to the light emitting module D1 at the second node N2; the transfer module 31 is connected to the second control terminal of the driving module 1 at the fourth node N4, and the control terminal of the transfer module 31 is connected to the second scan line SnC, which is used to transmit the data voltage to the second control terminal of the driving module 1; the compensation module 4 is connected to the first control terminal of the driving module 1, and the control terminal of the compensation module 4 is connected to the third scan line REC. The compensation module 4 is used to compensate for the threshold voltage Vth of the driving module 1 and store the threshold voltage Vth of the driving module 1; wherein the second scan signal transmitted by the second scan line SnC and the third scan signal transmitted by the third scan line REC are both global control signals.

[0061] Specifically, the first power supply terminal ELVDD can transmit a DC voltage, such as a first power supply voltage VDD. The first node N1 refers to a node where the first end of the driving module 1 is electrically connected to the first power supply terminal ELVDD. The light-emitting module D1 may include a light-emitting element, such as an organic light-emitting diode (OLED). The second node N2 refers to a node where the second end of the driving module 1 is electrically connected to the first end of the light-emitting module D1. The first end of the light-emitting module D1 is typically an anode. The driving module 1 may include a driving transistor. The driving current of the driving module 1 is used to drive the light-emitting module D1 to emit light. Exemplarily, the first end of the driving module may be a drain, and the second end of the driving module may be a source, without any limitation herein.

[0062] The first end of the transfer module 31 is connected to the data line. The data voltage is transmitted to the second control end of the driving module 1 through the transfer module 31. The control end of the transfer module 31 is connected to the second scan line SnC. Since the second scan signal transmitted by the second scan line SnC is a global control signal, the pixel circuits 100 in each row can simultaneously transfer the data voltage to the second control end of the driving module 1.

[0063] The threshold voltage of the driving module 1 is compensated by the compensation module 4. Since the control end of the compensation module 4 is connected to the third scan line REC. The third scan signal transmitted by the third scan line REC is a global control signal. At least two pixel circuits 100 located in different rows can perform threshold voltage compensation at the same time, and each compensation module 4 of at least two pixel circuits 100 located in different rows can share a gate drive (GIP) circuit, so that the number of GIP circuits of the display panel is reduced, thereby reducing the space occupied by the GIP circuit in the frame of the display panel, and further reducing the width of the left and right frames of the display panel.

[0064] After the compensation phase, the data writing phase is entered. In the data writing phase, the transfer module 3 can transmit the data voltage to the second control terminal of the driving module 1. At least two pixel circuits 100 located in different rows can simultaneously transmit the data voltage to the second control terminal. In the light-emitting phase, at least two pixel circuits 100 located in different rows can emit light at the same time. This arrangement allows at least two pixel circuits 100 located in different rows to be driven by the same timing signal during the data writing phase and the light-emitting phase. This arrangement reduces the number of GIP circuits that generate timing signals of the display panel, thereby reducing the space occupied by the GIP circuits that provide timing signals in the border of the display panel, thereby reducing the width of the left and right borders of the display panel.

[0065] The pixel circuit 100 provided in this embodiment includes a driving module 1, a transfer module 31 and a compensation module 4. The threshold voltage of the driving module 1 is compensated by the compensation module 4. Then, the data voltage is transmitted to the second control terminal of the driving module 1 by the transfer module 3. By setting the second scanning signal transmitted by the second scanning line SnC and the third scanning signal transmitted by the third scanning line REC to be global control signals, the compensation phase of at least two pixel circuits 100 located in different rows is carried out simultaneously, so that at least two pixel circuits 100 located in different rows can use a common GIP circuit to provide the timing signal required in the compensation phase. In this way, the compensation phase of the pixel circuits 100 of each row can use a common GIP circuit, which can not only improve the threshold voltage compensation effect of the driving module 1 in the pixel circuit 100 of the display panel, improve the brightness uniformity of the display panel, and improve the display effect of the display panel, but also reduce the number of GIP circuits that generate timing signals, thereby reducing the space occupied by the GIP circuit that provides the timing signal in the frame of the display panel, and reducing the width of the left and right frames of the display panel.

[0066] Optional, Figure 2 FIG. 1 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 2 The pixel circuit 100 may further include: a data writing module 21, the data writing module 21 and the transfer module 31 are connected to the third node N3, the control end of the data writing module 21 is connected to the first scanning line SnW, and is used to transmit the data voltage to the third node N3; the first scanning signal transmitted by the first scanning line SnW is a row-by-row scanning signal.

[0067] Specifically, the first scanning signal transmitted by the first scanning line SnW is a row-by-row scanning signal, so that the data pre-writing stage is performed row by row, so that the pixel circuits 100 located in different rows can write the data voltage row by row, so as to accurately write the data voltage into the pixel circuits 100 of the corresponding row. After the data pre-writing stage of the pixel circuits 100 of all rows is completed, the compensation stage of the pixel circuits 100 of each row is set to be performed simultaneously, so that the timing signal of the compensation module 4 of the pixel circuits 100 of each row can use a common GIP circuit, so that the pixel circuits 100 located in each row can be controlled by the same timing signal and compensated at the same time, thereby reducing the number of GIP circuits, thereby reducing the width of the display panel frame occupied by the GIP circuit, and thus realizing a narrow frame of the display panel.

[0068] The data writing phase of the pixel circuits 100 of each row is set to be carried out simultaneously, so that the timing signals of the transfer modules 3 of the pixel circuits 100 of each row can use a common GIP circuit, and the pixel circuits 100 located in each row can be controlled by the same timing signal and transmit the data voltage to the second control terminal at the same time, thereby reducing the number of GIP circuits, and then reducing the width of the display panel frame occupied by the GIP circuit, and further reducing the frame of the display panel. In addition, such a setting can not only take into account the good threshold voltage compensation effect of the driving transistor, but also make the writing efficiency of the data voltage higher.

[0069] The light-emitting modules D1 connected to the pixel circuits 100 of each row are arranged to emit light simultaneously, so that the timing signals of the light-emitting control modules of the pixel circuits 100 of each row can adopt a common GIP circuit, so that the pixel circuits 100 located in each row can drive the light-emitting modules D1 to emit light simultaneously under the control of the same light-emitting control signal, thereby reducing the number of GIP circuits, and further reducing the width of the display panel border occupied by the GIP circuits, thereby further reducing the border of the display panel.

[0070] Optional, continue to see Figure 2 The pixel circuit may further include: a first storage module 22; the first storage module 22 is connected between the third node N3 and the first power supply terminal ELVDD, and the first storage module 22 is used to store the data voltage VData.

[0071] Specifically, in the data pre-writing stage, the data writing module 21 is turned on according to the first scanning signal transmitted on the first scanning line SnW, so as to transmit the data voltage VData transmitted on the data line Data to the first storage module 22 through the turned-on data writing module 21. The first storage module 22 can temporarily store the data voltage VData transmitted on the data line Data.

[0072] Optional, Figure 3 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 3 On the basis of the above embodiment, the data writing module 21 includes a first switch tube T9, and the first storage module 22 includes a first capacitor C3; a first electrode of the first switch tube T9 is connected to the data line Data, a second electrode of the first switch tube T9 and a first end of the first capacitor C3 are connected to a third node N3, a control electrode of the first switch tube T9 is connected to the first scan line SnW, and a second end of the first capacitor C3 is connected to the first power supply end ELVDD.

[0073] Specifically, the first switch tube T9 may be an N-type switch tube or a P-type switch tube. When the control electrode of the first switch tube T9 is turned on according to the first scan signal transmitted on the first scan line SnW, the data voltage VData transmitted on the data line Data is transmitted to the first capacitor C3 through the turned-on first switch tube T9, and the data voltage VData is temporarily stored through the first capacitor C3.

[0074] It should be noted that Figure 3 The case where the first switch tube T9 is an N-type switch tube is exemplarily shown, and no limitation is made here.

[0075] Optionally, based on the above embodiment, continue to refer to Figure 2 The pixel circuit 100 may include: a second storage module 32; the transfer module 31 and the second control terminal of the driving module 1 and the second storage module 32 are connected to the fourth node N4, and the second storage module 32 is connected between the second node N2 and the fourth node N4.

[0076] Specifically, in the data writing stage, the transfer module 31 is turned on according to the second scan signal transmitted on the second scan line SnC, so as to transfer the data voltage VData temporarily stored on the first storage module 22 to the second control end of the driving module 1 through the turned-on transfer module 31. The second storage module 32 can store the data voltage VData. The data voltage VData is used to control the driving module 1 to turn on, thereby driving the light-emitting module D1 to emit light.

[0077] Optionally, based on the above embodiment, continue to refer to Figure 3 The transfer module 31 includes a second switch tube T2, and the second storage module 32 includes a second capacitor Cst1; the first electrode of the second switch tube T2 is connected to the third node N3, the second electrode of the second switch tube T2 and the second control end of the driving module 1 and the first end of the second capacitor Cst1 are connected to the fourth node N4, the second end of the second capacitor Cst1 is connected to the second node N2, and the control electrode of the second switch tube T2 is connected to the second scan line SnC.

[0078] Specifically, the second switch tube T2 may be an N-type switch tube or a P-type switch tube. When the control electrode of the second switch tube T2 is turned on according to the second scan signal transmitted on the second scan line SnC, the data voltage temporarily stored on the first storage module 22 is transmitted to the second control terminal of the driving module 1 through the turned-on second switch tube T2 and stored in the second capacitor Cst1.

[0079] It should be noted that Figure 3 The case where the second switch tube T2 is an N-type switch tube is exemplarily shown, and no limitation is made here.

[0080] Optionally, based on the above embodiment, continue to refer to Figure 2 The compensation module 4 may include: a compensation unit 41, a reset unit 42 and a third storage unit 44; the compensation unit 41 and the first control end of the driving module 1 and the third storage unit 44 are connected to the fifth node N5, the compensation unit 41 is connected between the first node N1 and the fifth node N5, and the control end of the compensation unit 41 is connected to the third scan line REC; the third storage unit 44 and the reset unit 42 and the second end of the driving module 1 are connected to the second node N2, the reset unit 42 is connected between the first initialization line Ini and the second node N2, and the control end of the reset unit 42 is connected to the third scan line REC.

[0081] Specifically, before the compensation phase, a reset phase may be performed. In the reset phase, the compensation unit 41 is turned on according to the third scan signal transmitted on the third scan line REC to connect the first node N1 and the fifth node N5 to the same potential. The reset unit 42 is turned on according to the third scan signal transmitted on the third scan line REC, and the potential of the second end of the driving module 1, that is, the second node N2, jumps to the first initialization voltage Vini transmitted on the first initialization line Ini, and the third storage unit 44 is reset.

[0082] In the compensation phase, the first power supply terminal ELVDD stops outputting the first power supply voltage VDD to the first node N1. The potential of the first control terminal of the driving module 1 gradually decreases from the first power supply voltage VDD, and the threshold voltage Vth of the driving module 1 is compensated, and the threshold voltage Vth is finally stored in the third storage unit 44. At this time, the voltage difference between the two ends of the second storage module 32 is zero, that is, the voltage difference between the second control terminal and the source of the driving module 1 is zero, so that the threshold voltage Vth of the driving module 1 is zero.

[0083] After the compensation phase, the data writing phase begins. In the data writing phase, the data voltage temporarily stored in the first storage module 22 is transferred to the second control terminal of the driving module 1 , ie, the fourth node N4 , and is stored through the second storage module 32 .

[0084] Optionally, based on the above embodiment, continue to refer to Figure 3 The compensation unit 41 includes a third switch tube T5, the reset unit 42 includes a fourth switch tube T4, and the third storage unit 44 includes a third capacitor Cst2; a first electrode of the third switch tube T5 is connected to the first node N1, a second electrode of the third switch tube T5 and the first control end of the driving module 1 and the first end of the third capacitor Cst2 are connected to the fifth node N5, and the control electrode of the third switch tube T5 is connected to the third scan line REC; a second end of the third capacitor Cst2 and the first electrode of the fourth switch tube T4 and the second end of the driving module 1 are connected to the second node N2, a second electrode of the fourth switch tube T4 is connected to the first initialization line Ini, and a control electrode of the fourth switch tube T4 is connected to the third scan line REC.

[0085] Specifically, the third switch tube T5 may be an N-type switch tube or a P-type switch tube. When the control electrode of the third switch tube T5 is turned on according to the third scan signal transmitted on the third scan line REC, the first node N1 and the fifth node N5 are connected at the same potential, so that the potential of the fifth node N5 is the first power supply voltage VDD. The fourth switch tube T4 may be an N-type switch tube or a P-type switch tube. When the control electrode of the fourth switch tube T4 is turned on according to the third scan signal transmitted on the third scan line REC, the potential of the second node N2 is the first initialization voltage Vini transmitted on the first initialization line Ini.

[0086] In the compensation phase, the first power terminal ELVDD stops outputting the first power voltage VDD to the first node N1. The potential of the first control terminal of the driving module 1 gradually decreases from the first power voltage VDD, the threshold voltage of the driving module 1 is compensated, and the threshold voltage of the driving module 1 is stored in the third capacitor Cst2.

[0087] It should be noted that Figure 3 The case where the third switch tube T5 , the fourth switch tube T4 , and the sixth switch tube T3 are all N-type switch tubes is exemplarily shown, and no limitation is made here.

[0088] Optional, Figure 4 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 4 Based on the above embodiment, the pixel circuit 100 may further include: a first initialization module 5 connected between the second initialization line Ref and the anode of the light emitting module D1, and a control end of the first initialization module 5 connected to the second scanning line SnC.

[0089] Specifically, in the initialization stage, when the first initialization module 5 is turned on according to the second scan signal transmitted on the second scan line SnC, the second initialization voltage Vref transmitted on the second initialization line Ref initializes the anode of the light emitting module D1. The first initialization module 5 initializes the anode of the light emitting module D1 in the initialization stage.

[0090] Optionally, based on the above embodiment, continue to refer to Figure 4 The first initialization module 5 includes a fifth switch tube T8; a first electrode of the fifth switch tube T8 is connected to the second initialization line Vref, a second electrode of the fifth switch tube T8 is connected to the anode of the light emitting module D1, and a control electrode of the fifth switch tube T8 is connected to the second scan line SnC.

[0091] Specifically, the fifth switch tube T8 can be an N-type switch tube or a P-type switch tube. In the initialization stage, when the fifth switch tube T8 is turned on according to the second scan signal transmitted on the second scan line SnC, the second initialization voltage Vref transmitted on the second initialization line Vref initializes the anode of the light-emitting module D1. The fifth switch tube T8 initializes the anode of the light-emitting module D1 in the initialization stage.

[0092] It should be noted that Figure 4 The case where the fifth switch tube T8 is an N-type switch tube is exemplarily shown, and no limitation is made here.

[0093] Optional, continue combining Figures 2 to 4 On the basis of the above embodiment, the pixel circuit 100 may further include: a second initialization module 43, the second initialization module 43 is connected between the first initialization line Ini and the fourth node N4, and the control end of the second initialization module 43 is connected to the third scan line REC.

[0094] Specifically, in the reset stage, the second initialization module 43 is turned on according to the third scan signal transmitted by the third scan line REC, and the first initialization voltage Vini transmitted by the first initialization line Ini resets the second control end of the driving module 1, that is, the fourth node N4. The potential of the second control end of the driving module 1 also jumps to the first initialization voltage Vini. Since the second storage module 32 is connected between the fourth node N4 and the second node N2, the potentials of both ends of the second storage module 32 are the first initialization voltage Vini, and the second storage module 32 is reset.

[0095] Optional, continue to see Figure 4 Based on the above embodiment, the second initialization module 43 may include a sixth switch tube T3, a first electrode of the sixth switch tube T3 is connected to the first initialization line Ini, a second electrode of the sixth switch tube T3 is connected to the fourth node N4, and a control electrode of the sixth switch tube T3 is connected to the third scan line REC.

[0096] Specifically, the sixth switch tube T3 may be an N-type switch tube or a P-type switch tube. In the reset stage, when the sixth switch tube T3 is turned on according to the third scan signal transmitted on the third scan line REC, the first initialization voltage Vini transmitted on the first initialization line Ini resets the fourth node N4. Since the fourth node N4 is connected to the second control terminal of the driving module 1, the sixth switch tube T3 resets the second control terminal of the driving module 1 in the reset stage. The second capacitor Cst1 and the third capacitor Cst2 are both reset.

[0097] Optionally, based on the above embodiment, continue to refer to Figure 4In the data pre-writing stage, the first storage module 22 stores the data voltage Vdata; in the compensation stage, the voltage difference between the two ends of the second storage module 32 is zero, and the voltage difference between the two ends of the third storage unit 44 is the threshold voltage Vth of the driving module 1. In the data writing stage, the data voltage Vdata temporarily stored in the first storage module 22 is transferred to the second control terminal of the driving module 1 and stored through the second storage module 32.

[0098] Specifically, in the data pre-writing stage, the first storage module 22 temporarily stores the data voltage Vdata. In the reset stage, the second storage module 32 is reset, and the voltage difference of the second storage module 32 is zero. In the compensation stage, the third storage unit 44 stores the threshold voltage of the driving module 1. In the data writing stage, the voltage value stored in the second storage module 32 is:

[0099] (Vdata-Vref)*C3 / (Cst1+C3).

[0100] Wherein, Vdata is the data voltage, Vref is the second initialization voltage, C3 is the capacitance of the first capacitor, and Cst1 is the capacitance of the second capacitor.

[0101] Optional, Figure 5 It is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 6 FIG. 1 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Figure 5 and Figure 6 On the basis of the above embodiment, the pixel circuit 100 may further include: a first light emitting control module 6 connected between the second end of the driving module 1 and the anode of the light emitting module D1, and a control end of the first light emitting control module 6 connected to a first light emitting control line EMC1. The first light emitting control signal transmitted by the first light emitting control line EMC1 is a global control signal.

[0102] It should be noted that the driving module 1 is a four-terminal device. The driving module 1 has a first control terminal and a second control terminal. The first control terminal can be a top gate TG, and the second control terminal can be a bottom gate BG. Alternatively, the first control terminal can be a bottom gate BG, and the second control terminal can be a top gate TG, which is not limited here.

[0103] Specifically, when the first light-emitting control module 6 is turned on according to the first light-emitting control signal EMC1 transmitted by the first light-emitting control line EMC1 connected to its control end, the first end of the light-emitting module D1 is connected to the second end of the driving module 1. In the light-emitting stage, the current flowing through the driving module 1 flows to the light-emitting module D1 through the turned-on first light-emitting control module 6, so as to drive the light-emitting module D1 to emit light.

[0104] By setting the first light-emitting control signal transmitted by the first light-emitting control line EMC1 as a global control signal, the light-emitting modules D1 connected to the pixel circuits 100 in each row can emit light at the same time, so that the timing signals of the light-emitting control modules of the pixel circuits 100 in each row can use a common GIP circuit, and the pixel circuits 100 located in each row can be controlled by the same light-emitting control signal to drive the light-emitting modules D1 to emit light at the same time, thereby reducing the number of GIP circuits, and further reducing the width of the display panel frame occupied by the GIP circuits, and further reducing the frame of the display panel.

[0105] Optional, continue combining Figure 5 and Figure 6 On the basis of the above embodiment, the first light-emitting control module 6 includes a seventh switch tube T7, a first electrode of the seventh switch tube T7 is connected to the second end of the driving module 1, a second electrode of the seventh switch tube T7 is connected to the anode of the light-emitting module D1, and a control electrode of the seventh switch tube T7 is connected to the first light-emitting control line EMC1.

[0106] Specifically, the seventh switch tube T7 may be an N-type switch tube or a P-type switch tube. When the seventh switch tube T7 is turned on according to the first light-emitting control signal EMC1 transmitted by the first light-emitting control line EMC1 connected to its control electrode, the first end of the light-emitting module D1 is connected to the second end of the driving module 1. In the light-emitting stage, the current flowing through the driving module 1 flows to the light-emitting module D1 through the turned-on seventh switch tube T7 to drive the light-emitting module D1 to emit light.

[0107] Optionally, based on the above embodiment, continue to combine Figure 5 and Figure 6 The pixel circuit 100 may further include: a second light emitting control module 7 connected between the first power supply terminal ELVDD and the first node N1, and a control terminal of the second light emitting control module 7 connected to a second light emitting control line EMC2. The second light emitting control signal transmitted by the second light emitting control line is a global control signal.

[0108] Specifically, when the second light-emitting control module 7 is turned on according to the second light-emitting control signal EMC2 transmitted by the second light-emitting control line EMC2 connected to the control end thereof, the first power supply terminal ELVDD is connected to the first end of the driving module 1. In the light-emitting stage, the current flowing through the driving module 1 flows to the light-emitting module D1 through the turned-on second light-emitting control module 7, so as to drive the light-emitting module D1 to emit light. The second light-emitting control signal transmitted by the second light-emitting control line is set as a global control signal, so as to facilitate the control of the light-emitting modules D1 connected to the pixel circuits 100 of each row to emit light at the same time, thereby reducing the number of GIP circuits, thereby reducing the width of the display panel frame occupied by the GIP circuits, and further reducing the frame of the display panel.

[0109] Optional, continue combining Figure 5and Figure 6 On the basis of the above embodiment, the second light emitting control module 7 includes an eighth switch tube T6, a first electrode of the eighth switch tube T6 is connected to the first power supply terminal ELVDD, a second electrode of the eighth switch tube T6 is connected to the first node N1, and a control electrode of the eighth switch tube T6 is connected to the second light emitting control line EMC2.

[0110] Specifically, the eighth switch tube T6 may be an N-type switch tube or a P-type switch tube. When the eighth switch tube T6 is turned on according to the second light-emitting control signal EMC2 transmitted by the second light-emitting control line EMC2 connected to its control end, the first power supply end ELVDD is connected to the first end of the driving module 1. In the light-emitting stage, the current flowing through the driving module 1 flows to the light-emitting module D1 through the turned-on eighth switch tube T6 to drive the light-emitting module D1 to emit light.

[0111] It should be noted that Figure 5 The case where the seventh switch tube T7 and the eighth switch tube T6 are N-type switch tubes is exemplarily shown, and no limitation is made here.

[0112] Optional, Figure 7 Schematic diagram of a driving timing of a pixel circuit provided by an embodiment of the present invention. Figures 5 to 7 On the basis of the above embodiment, the driving module 1 includes a driving transistor T1, the light emitting module D1 includes an organic light emitting diode, the first electrode of the driving transistor T1 is connected to the first node N1, the second electrode of the driving transistor T1 and the first end of the first light emitting control module 6 are connected to the second node N2, the second end of the first light emitting control module 6 is connected to the anode of the organic light emitting diode, and the cathode of the organic light emitting diode is connected to the second power supply terminal ELVSS; the first control end of the driving transistor T1 and the compensation module 4 are connected to the fifth node N5, and the second control end of the driving transistor T1 and the transfer module 3 are connected to the fourth node N4.

[0113] specific, exemplary, combined Figures 5 to 7 The working process of the pixel circuit 100 provided in this embodiment is as follows:

[0114] In the data pre-writing stage t1, the second scan line SnC is at a low level, the third scan line REC is at a low level, and the first scan line SnW is at a high level. The data signal is written into the first capacitor C3 of each pixel circuit 100 row by row until all rows complete the data pre-writing stage.

[0115] In the reset stage t2, the first light-emitting control signal EMC1 is at a low level, the seventh switch tube T7 is turned off, and the light-emitting module D1 does not emit light. The third scan line REC is set to a high level, and the sixth switch tube T3, the fourth switch tube T4 and the third switch tube T5 are all turned on. The first power supply terminal ELVDD inputs the first power supply voltage VDD to the first node N1. Since the third switch tube T5 is turned on, the potentials of the fifth node N5 and the first node N1 are both the first power supply voltage VDD. Since the sixth switch tube T3 and the fourth switch tube T4 are both turned on, the first initialization voltage Vini resets the fourth node N4 and the second node N2, so that the second capacitor Cst1 and the third capacitor Cs and the second switch tube T2 are reset.

[0116] In the compensation stage t3, the second light emitting control signal EMC2 is set to a low level, and the eighth switch tube T6 is turned off. The voltage of the first control terminal of the driving transistor T1, that is, the potential of the fifth node N5, starts to drop from the first power supply voltage VDD, and the threshold voltage Vth of the driving transistor T1 starts to be compensated. After the compensation is completed, the final threshold voltage Vth is stored in the third capacitor Cst2, and the voltage difference of the second capacitor Cst1 is zero.

[0117] In the data writing phase t4, the third scan line REC is set to a low level, and the sixth switch tube T3, the fourth switch tube T4 and the third switch tube T5 are all turned off. The first light-emitting control signal EMC1 is set to a high level, the second scan line SnC is set to a high level, and the second switch tube T2, the seventh switch tube T7 and the fifth switch tube T8 are all turned on. The potential of the anode of the light-emitting module D1 is the second initialization voltage Vref. Since the seventh switch tube T7 is turned on, the potential of the second node N2 is the second initialization voltage Vref. Since the second switch tube T2 is turned on, the data voltage stored in the first capacitor C3 is transmitted to the second control terminal of the driving transistor T1, and the data voltage is stored in the second capacitor Cst1. The voltage stored in the second capacitor Cst1 is:

[0118] (Vdata-Vref)*C3 / (Cst1+C3).

[0119] In the data writing phase t4, an initialization phase is also performed simultaneously, that is, when the fifth switch tube T8 is turned on, the second initialization voltage Vref is written into the anode of the light emitting module D1, and the anode of the light emitting module D1 is initialized to the second initialization voltage Vref. This arrangement effectively avoids the difference in luminous brightness caused by the difference in potential between the anodes of each light emitting module D1, thereby improving the luminous uniformity between each light emitting module D1.

[0120] In the light-emitting stage t5, the second scan line SnC is set to a low level, and the second switch tube T2 and the fifth switch tube T8 are both turned off. The third scan line REC continues to be at a low level, and the sixth switch tube T3, the fourth switch tube T4 and the third switch tube T5 are all turned off. The second light-emitting control signal EMC2 is set to a high level, and the eighth switch tube T6 is turned on. The first light-emitting control signal EMC1 remains at a high level, the seventh switch tube T7 continues to be turned on, and the light-emitting module D1 starts to light up. The light-emitting modules D1 located in different rows emit light at the same time.

[0121] In the light-emitting stage t5, the pixel circuits 100 of each row drive the light-emitting modules D1 of each row to light up at the same time, and then repeat the data pre-writing stage t1 of the next frame. Enter the writing and temporary storage of the data voltage VData row by row. After all rows of pixel circuits 100 have completed the writing and temporary storage of the data voltage VData, all rows of pixel circuits 100 simultaneously perform the reset stage t2, compensation stage t3, data writing stage t4 and reset of the light-emitting module D1 of the pixel circuit 100, and then all rows of pixel circuits 100 start to drive the light-emitting modules D1 of each row to light up at the same time, and enter the light-emitting stage t5. With this arrangement, only one set of GIP circuit driving is required, that is, only the scanning circuit of the first scanning line SnW is provided, which can greatly compress the width of the left and right borders of the display panel.

[0122] It should be noted that the figure exemplarily shows that the first scanning lines are SnW <1> 、SnW <2> 、……、SnW <n>.and Figure 5 When the pixel circuit in the embodiment cooperates with each other, each first scanning line SnW <1> 、SnW <2> 、……、SnW <n>The effective level signal is a high level, without any limitation.

[0123] Figure 8 1 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present invention. Figure 1 and Figure 8 The driving method of the pixel circuit provided in this embodiment is executed by the pixel circuit 100 proposed in any of the above embodiments. The driving method of the pixel circuit provided in this embodiment includes:

[0124] S101 . In a compensation stage, the compensation modules 4 in all pixel circuits 100 simultaneously compensate the threshold voltage of the driving module 1 according to the third scanning signal, and store the threshold voltage of the driving module 1 .

[0125] S102, in the data writing stage, the transfer modules 3 in all pixel circuits 100 simultaneously transmit data voltages to the second control terminal of the driving module 1 according to the second scanning signal; wherein the second scanning signal and the third scanning signal are both global control signals.

[0126] Optionally, based on the above embodiments, in the compensation stage, the compensation modules in all the pixel circuits simultaneously compensate for the threshold voltage of the driving module according to the third scanning signal, and before storing the threshold voltage of the driving module, it also includes: in the data pre-writing stage, the first storage module in each of the pixel circuits stores the data voltage row by row according to the first scanning signal; the first scanning signal is a row-by-row scanning signal.

[0127] Optionally, based on the above embodiments, in the compensation stage, the compensation modules in all the pixel circuits simultaneously compensate for the threshold voltage of the driving module according to the third scanning signal, and store the threshold voltage of the driving module, including: in the compensation stage, the voltage difference across the second storage module in all the pixel circuits is zero, and the third storage unit of the compensation module in all the pixel circuits simultaneously stores the threshold voltage of the driving module.

[0128] Optionally, based on the above embodiments, in the data writing stage, the transfer modules in all the pixel circuits simultaneously transmit the data voltage to the second control terminal of the driving module according to the second scanning signal, including: in the data writing stage, the transfer modules in all the pixel circuits simultaneously transfer the data voltage temporarily stored in the first storage module to the second control terminal of the driving module according to the second scanning signal, and store it through the second storage module.

[0129] The driving method of the pixel circuit 100 provided in this embodiment is arranged that in the compensation stage, the compensation modules 4 in all pixel circuits 100 simultaneously compensate the threshold voltage of the driving module 1 according to the third scanning signal and store the threshold voltage of the driving module 1. And in the data writing stage, the transfer modules 3 in all pixel circuits 100 simultaneously transmit the data voltage to the second control terminal of the driving module 1 according to the second scanning signal. Since the second scanning signal and the third scanning signal are both global control signals, the compensation stage of at least two pixel circuits 100 located in different rows is carried out simultaneously, so that at least two pixel circuits 100 located in different rows can use a common GIP circuit to provide the timing signal required for the compensation stage.

[0130] With such an arrangement, a common GIP circuit can be used in the compensation stage of at least two rows of pixel circuits 100, which can not only improve the threshold voltage compensation effect of the driving module 1 in the pixel circuit 100 of the display panel, improve the brightness uniformity of the display panel, and improve the display effect of the display panel, but also reduce the number of GIP circuits that generate timing signals, thereby reducing the space of the border of the display panel occupied by the GIP circuit that provides the timing signal, and reducing the width of the left and right borders of the display panel.

[0131] This embodiment provides a display panel. Fig. 9 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Fig. 9 The display panel 200 provided in this embodiment includes the pixel circuit 100 provided in any of the above embodiments, and has the beneficial effects of the pixel circuit 100 provided in any of the above embodiments, which will not be repeated here. The display panel 200 may include a display screen of a mobile terminal such as a mobile phone, a computer, or a wearable device.

[0132] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.< / n> < / n>

Claims

1. A pixel circuit, characterized in that: include: A driving module, wherein the driving module is connected to the first power supply terminal at a first node, and is connected to the light emitting module at a second node; A transfer module, wherein the transfer module and the second control end of the driving module are connected to a fourth node, and the control end of the transfer module is connected to the second scan line for transmitting a data voltage to the fourth node; A compensation module, the compensation module is connected to the first control terminal of the driving module, the control terminal of the compensation module is connected to the third scan line, and is used to compensate and store the threshold voltage of the driving module; The second scan signal transmitted by the second scan line and the third scan signal transmitted by the third scan line are both global control signals.

2. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: A data writing module, wherein the data writing module and the transfer module are connected to a third node, and a control end of the data writing module is connected to a first scanning line for transmitting a data voltage to the third node; The first scanning signal transmitted by the first scanning line is a line-by-line scanning signal.

3. The pixel circuit according to claim 2, characterized in that: The pixel circuit further includes: A first storage module, the first storage module is connected between the third node and the first power supply terminal, and the first storage module is used to store the data voltage; Preferably, the data writing module includes a first switching tube, and the first storage module includes a first capacitor; the first electrode of the first switching tube is connected to the data line, the second electrode of the first switching tube and the first end of the first capacitor are connected to a third node, the control electrode of the first switching tube is connected to the first scanning line, and the second end of the first capacitor is connected to the first power supply end.

4. The pixel circuit according to claim 2 or 3, characterized in that: The pixel circuit further includes: A second storage module, the transfer module and the second control end of the driving module and the second storage module are connected to a fourth node, and the second storage module is connected between the second node and the fourth node; Preferably, the transfer module includes a second switch tube, and the second storage module includes a second capacitor; the first electrode of the second switch tube is connected to the third node, the second electrode of the second switch tube is connected to the second control end of the driving module and the first end of the second capacitor is connected to the fourth node, the second end of the second capacitor is connected to the second node, and the control electrode of the second switch tube is connected to the second scan line.

5. The pixel circuit according to claim 1, characterized in that: The compensation module comprises: A compensation unit, a reset unit and a third storage unit; The compensation unit, the first control end of the driving module and the third storage unit are connected to a fifth node, the compensation unit is connected between the first node and the fifth node, and the control end of the compensation unit is connected to a third scan line; The third storage unit, the reset unit and the second end of the driving module are connected to a second node, the reset unit is connected between the first initialization line and the second node, and the control end of the reset unit is connected to a third scan line; Preferably, the compensation unit includes a third switch tube, the reset unit includes a fourth switch tube, and the third storage unit includes a third capacitor; The first electrode of the third switch tube is connected to the first node, the second electrode of the third switch tube and the first control end of the driving module and the first end of the third capacitor are connected to the fifth node, and the control electrode of the third switch tube is connected to the third scan line; The second end of the third capacitor, the first electrode of the fourth switch tube and the second end of the driving module are connected to the second node, the second electrode of the fourth switch tube is connected to the first initialization line, and the control electrode of the fourth switch tube is connected to the third scan line.

6. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: A first initialization module is connected between the second initialization line and the anode of the light emitting module, and a control end of the first initialization module is connected to the second scanning line; A second initialization module, wherein the second initialization module is connected between the first initialization line and the fourth node, and a control end of the second initialization module is connected to the third scan line; Preferably, the first initialization module includes a fifth switch tube; a first electrode of the fifth switch tube is connected to the second initialization line, a second electrode of the fifth switch tube is connected to the anode of the light emitting module, and a control electrode of the fifth switch tube is connected to the second scan line; Preferably, the second initialization module includes a sixth switch tube, a first electrode of the sixth switch tube is connected to the first initialization line, a second electrode of the sixth switch tube is connected to the fourth node, and a control electrode of the sixth switch tube is connected to the third scan line.

7. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: A first light-emitting control module is connected between the second end of the driving module and the anode of the light-emitting module, and a control end of the first light-emitting control module is connected to a first light-emitting control line; a first light-emitting control signal transmitted by the first light-emitting control line is a global control signal; Preferably, the first light-emitting control module includes a seventh switch tube, a first electrode of the seventh switch tube is connected to the second end of the driving module, a second electrode of the seventh switch tube is connected to the anode of the light-emitting module, and a control electrode of the seventh switch tube is connected to the first light-emitting control line; Preferably, the pixel circuit further comprises: a second light emitting control module connected between the first power supply terminal and the first node, a control terminal of the second light emitting control module connected to a second light emitting control line; a second light emitting control signal transmitted by the second light emitting control line is a global control signal; Preferably, the second light-emitting control module comprises an eighth switch tube, a first electrode of the eighth switch tube is connected to the first power supply end, a second electrode of the eighth switch tube is connected to the first node, and a control electrode of the eighth switch tube is connected to the second light-emitting control line; Preferably, the driving module includes a driving transistor, the light-emitting module includes an organic light-emitting diode, the first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor and the first end of the first light-emitting control module are connected to the second node, the second end of the first light-emitting control module is connected to the anode of the organic light-emitting diode, and the cathode of the organic light-emitting diode is connected to the second power supply end; the first control end of the driving transistor and the compensation module are connected to the fifth node, and the second control end of the driving transistor and the transfer module are connected to the fourth node.

8. A method for driving a pixel circuit, characterized in that: The method is performed by the pixel circuit according to any one of claims 1 to 7; the method comprises: In the compensation stage, the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the third scanning signal, and store the threshold voltage of the driving module; In the data writing stage, the transfer modules in all the pixel circuits simultaneously transmit the data voltage to the second control terminal of the driving module according to the second scanning signal; Wherein, the second scanning signal and the third scanning signal are both global control signals.

9. The driving method of the pixel circuit according to claim 8, characterized in that: In the compensation stage, before the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the third scanning signal and store the threshold voltage of the driving module, the method further includes: In the data pre-writing stage, the first storage module in each pixel circuit stores the data voltage row by row according to the first scanning signal; the first scanning signal is a row-by-row scanning signal; Preferably, in the compensation stage, the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the third scanning signal and store the threshold voltage of the driving module, including: In the compensation stage, the voltage difference across the second storage modules in all the pixel circuits is zero, and the third storage units of the compensation modules in all the pixel circuits simultaneously store the threshold voltage of the driving module; Preferably, in the data writing stage, the transfer modules in all the pixel circuits simultaneously transmit the data voltage to the second control terminal of the driving module according to the second scanning signal, including: In the data writing stage, the transfer modules in all the pixel circuits simultaneously transfer the data voltage temporarily stored in the first storage module to the second control terminal of the driving module according to the second scanning signal, and store it through the second storage module.

10. A display panel, characterized in that: The pixel circuit comprises the pixel circuit as claimed in any one of claims 1 to 7.

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