Display device

Abstract

The invention relates to a display device. The display device includes a substrate and a plurality of pixels on the substrate, where each pixel includes a light emitting element and a pixel circuit configured to control an amount of light emission flow to the light emitting element, and where the pixel circuit includes: a driving transistor having a first conductivity type; a first switching transistor having a second conductivity type and configured to be connected or disconnected between a gate and a drain of the driving transistor; a second switching transistor having a second conductivity type and configured to supply a reset voltage to a gate of the driving transistor; a storage capacitor including a gate electrode of the driving transistor, an interlayer insulating layer covering the gate electrode of the driving transistor, and an intermediate conductive layer disposed on the interlayer insulating layer; and an auxiliary capacitor including a capacitor electrode disposed under the driving transistor, a semiconductor layer of the driving transistor, and an insulating layer between the capacitor electrode and the semiconductor layer of the driving transistor.

Description

[0001] This application is a divisional application of the invention patent application with the application date of June 1, 2022, application number "202210617746.1", and invention name "Pixel circuit configured to control light-emitting element". Technical Field

[0002] The present invention relates to a display device. Background Art

[0003] Organic light-emitting diode (OLED) elements are current-driven self-luminous elements, so they do not require backlight. In addition, OLED elements have the advantages of achieving low power consumption, wide viewing angle and high contrast. They are expected to contribute to the development of flat panel display devices.

[0004] An active matrix (AM) OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. The transistor in the OLED display device is a thin film transistor (TFT); typically, a low temperature polysilicon (LTPS) TFT is used.

[0005] The threshold voltage and charge mobility of the TFTs vary. Since the drive transistors determine the light emission intensity of the OLED display device, variations in their electrical characteristics may cause problems. Therefore, a typical OLED display device includes an adjustment circuit for compensating for variations and offsets in the threshold voltage of the drive transistors.

[0006] OLED display devices may exhibit ghosting, a phenomenon known as image sticking. For example, when a full-screen image with a medium luminous level is displayed after displaying a black and white checkerboard pattern for a certain period of time, the OLED display device may display a ghost image of the checkerboard pattern with a different luminous level for a period of time.

[0007] This is caused by the hysteresis effect of the driving transistor. The hysteresis effect causes a phenomenon in which the leakage current in the field effect transistor flows differently when the gate-source voltage changes from a high voltage to a low voltage and when the gate-source voltage changes from a low voltage to a high voltage.

[0008] That is, different drain currents flow between pixels where the emission level changes from black level to intermediate level and pixels where the emission level changes from white level to intermediate level. For this reason, the OLED display device emits light of different intensities. This difference in drain current lasts for several frames, so the difference in the intensity of emitted light is visually recognized as a ghost. This behavior of drain current is called transient response of current caused by hysteresis effect. Summary of the invention

[0009] The ghost image caused by the image sticking after displaying the black and white checkerboard pattern can be a type in which the area displaying black becomes relatively dark or a type in which the area displaying black becomes relatively bright. The image sticking is caused by the current transient response caused by the hysteresis effect of the driving TFT and the compensation of the threshold voltage change of the driving TFT by the pixel circuit. Therefore, a technology for reducing the image sticking of the pixel circuit is needed.

[0010] One aspect of the present invention is a pixel circuit configured to control the light emission of a light emitting element, the pixel circuit comprising: a light emitting element; a driving transistor configured to control a driving current flowing to the light emitting element; a storage capacitor connected to the gate of the driving transistor and configured to store a control voltage of the driving transistor; a first switching transistor configured to connect or disconnect between the gate and the drain of the driving transistor; a second switching transistor connected between a data line and a source of the driving transistor, the second switching transistor configured to transfer a data signal voltage from the data line through the driving transistor and the first switching transistor to the storage capacitor; and an auxiliary capacitor connected to the second switching transistor, the auxiliary capacitor configured to store an auxiliary charge depending on the data signal voltage from the data line. During a first period when both the second switching transistor and the first switching transistor are turned on, the auxiliary capacitor maintains the auxiliary charge according to the data signal voltage from the data line. During a second period when the second switching transistor is turned off and the first switching transistor is turned on, the auxiliary charge is transferred from the auxiliary capacitor to the storage capacitor through the first switching transistor and the driving transistor. The capacitance of the auxiliary capacitor is equal to or greater than 1 / 2 of the capacitance of the storage capacitor.

[0011] Another aspect of the present invention is a pixel circuit configured to control the light emission of a light emitting element, the pixel circuit comprising: a light emitting element; a driving transistor configured to control a driving current flowing to the light emitting element; a storage capacitor connected to the gate of the driving transistor and configured to store a control voltage of the driving transistor; a first switching transistor configured to connect or disconnect between the gate and the drain of the driving transistor; a second switching transistor connected between a data line and a source of the driving transistor, the second switching transistor configured to transfer a data signal voltage from the data line to the storage capacitor through the driving transistor and the first switching transistor; and a first auxiliary capacitor and a second auxiliary capacitor connected to the second switching transistor, the first auxiliary capacitor and the second auxiliary capacitor configured to store auxiliary charges depending on the data signal voltage from the data line. The first auxiliary capacitor is connected between a power supply line configured to supply an anode current to the light emitting element and a node between the second switching transistor and the driving transistor. The second auxiliary capacitor is connected between a node between the second switching transistor and the driving transistor and an anode electrode of the light emitting element.

[0012] One aspect of the present invention reduces image sticking of a display device.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematically shows an example of a configuration of an OLED display device of a display apparatus;

[0015] Figure 2 A configuration example of a pixel circuit according to one embodiment of the present specification is shown;

[0016] Figure 3 Control within one frame period Figure 2 A timing diagram of signals of the pixel circuit shown;

[0017] Figure 4 Shows Figure 2 and Figure 3 Simulation results of the relationship between the Vth compensation period and image sticking in the pixel circuit shown;

[0018] Figure 5 Shows Figure 2 and Figure 3 Simulation results of the relationship between the total capacitance of the auxiliary capacitors in the pixel circuit shown and image sticking;

[0019] Figure 6 is shown from another angle Figure 2 and Figure 3 a graph of simulation results for the pixel circuit shown;

[0020] Figure 7 schematically shows a structural example of a pixel circuit when viewed in a stacking direction;

[0021] Figure 8 Schematically shows the Figure 7 The cross-sectional structure of the section line VIII-VIII';

[0022] Fig. 9 Schematically shows the Figure 7 The cross-sectional structure of the section line IX-IX';

[0023] Fig.10 is a plan view schematically showing a structural example of a pixel circuit excluding one transistor;

[0024] Fig.11 Another example of the circuit configuration of a pixel circuit is shown;

[0025] Fig.12It is schematically shown Fig.11 A plan view showing an example of a circuit structure of a pixel circuit shown;

[0026] Fig.13 Schematically shows the Fig.12 The cross-sectional structure of the section line XIII-XIII';

[0027] Fig.14 It is schematically shown from Fig.11 A plan view showing an example of a device structure of a pixel circuit in which one transistor is removed from the pixel circuit shown;

[0028] Fig.15 Another example of the circuit structure of the pixel circuit is shown;

[0029] Fig.16 It is schematically shown Fig.15 A plan view showing an example of a device structure of a pixel circuit shown;

[0030] Fig.17 Schematically shows the Fig.16 The cross-sectional structure of the section line XVII-XVII';

[0031] Fig.18 Schematically shows the Fig.16 The cross-sectional structure of the section line XVIII-XVIII';

[0032] Fig.19 Another example of the circuit structure of the pixel circuit is shown;

[0033] Fig. 20 It is schematically shown Fig.19 A plan view of an example of a device structure of a pixel circuit shown; and

[0034] Fig.21 Schematically shows the Fig. 20 Cross-sectional structure along section line XXI-XXI'. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Common elements in the drawings are denoted by the same reference numerals, and each element in the drawings may be exaggerated in size and / or shape for a clear understanding of the description.

[0036] Disclosed below are techniques for improving drive current control in electroluminescent display devices, and more specifically, techniques for reducing image sticking in electroluminescent display devices. Electroluminescent display devices are display devices that utilize light-emitting elements that emit light in response to a drive current, such as organic light-emitting diode (OLED) display devices.

[0037] Display the configuration of the device

[0038] Figure 1 A configuration example of an OLED display device 10 of a display apparatus is schematically shown. Figure 1 The horizontal direction is the X-axis direction, the vertical direction is the Y-axis direction, and the vertical direction is perpendicular to the X-axis direction. The OLED display device 10 includes a thin film transistor (TFT) substrate 100 on which an OLED element (organic light emitting element) is formed, a packaging substrate 200 for packaging the OLED element, and a bonding member 300 for bonding the TFT substrate 100 to the packaging substrate 200.

[0039] The space between the TFT substrate 100 and the encapsulation substrate 200 is filled with an inert gas such as dry nitrogen and sealed with an adhesive member 300. Instead of the encapsulation substrate 200, a structural encapsulation unit having a different structure, for example, a structural encapsulation unit using thin film encapsulation may be employed.

[0040] Scanning circuits 131 and 132, a driver IC 134, and a demultiplexer 136 are provided around the cathode electrode region 114 outside the display region 125 of the TFT substrate 100. The driver IC 134 is connected to an external device through a flexible printed circuit (FPC) 135. The scanning circuits 131 and 132 drive the scanning lines on the TFT substrate 100.

[0041] For example, the driver IC 134 is mounted with an anisotropic conductive film (ACF). The driver IC 134 supplies a power supply signal and a timing signal (control signal) to the scanning circuits 131 and 132 , and further supplies a data signal to the demultiplexer 136 .

[0042] The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer greater than 1). The demultiplexer 136 changes the output data line of the data signal from the driver IC 134 d times in each scanning period to drive d times the data lines of the output pin of the driver IC 134.

[0043] The display area 125 includes a plurality of OLED elements (pixels) and a plurality of pixel circuits for controlling the light emission of the plurality of pixels. In the example of a color OLED display device, each OLED element emits light of one color of red, blue and green. The plurality of pixel circuits constitute a pixel circuit array.

[0044] As will be described later, each pixel circuit includes a driving TFT (driving transistor) and a storage capacitor storing a signal voltage for determining a driving current of the driving TFT. The data signal transmitted by the data line is adjusted for the threshold voltage Vth of the driving TFT and stored in the storage capacitor. The voltage of the storage capacitor determines the gate voltage (Vgs) of the driving TFT. The adjusted control voltage in the storage capacitor changes the conductance of the driving TFT in an analog manner to supply a forward bias current corresponding to the light emission level to the OLED element.

[0045] The pixel circuit in one embodiment of the present specification also includes an auxiliary capacitor for storing an auxiliary voltage, which is used to adjust the voltage stored in the storage capacitor. After the data signal is written from the data line to the pixel circuit, the auxiliary capacitor supplies a potential to the storage capacitor to adjust the voltage stored in the storage capacitor. The auxiliary capacitor makes it possible to more appropriately adjust the control voltage stored in the storage capacitor relative to the threshold voltage Vth of the driving TFT.

[0046] Pixel circuit

[0047] Figure 2 1 shows an example of a configuration of a pixel circuit 400 in an embodiment of the present specification. The pixel circuit 400 includes a storage capacitor for storing a control voltage for controlling the amount of current of a driving transistor. The control voltage stored in the storage capacitor is also referred to as a driving voltage of the driving transistor. The storage capacitor stores the control voltage according to a data signal (its potential) sent from the driver IC 134 through a data line. The control voltage is a voltage after applying an adjustment (Vth compensation) to the threshold voltage Vth of the driving transistor to the data signal, and can be referred to as an adjusted data voltage.

[0048] The pixel circuit 400 also includes auxiliary capacitors Cd1 and Cd2 for storing auxiliary charges depending on the data signal supplied from the data line. The auxiliary voltage takes a value depending on the data signal and can be referred to as a data voltage. The auxiliary capacitor is located between the data line and the drive transistor in the pixel circuit. Each auxiliary capacitor supplies a charge depending on the auxiliary voltage to the storage capacitor through a diode-connected drive transistor. Therefore, Vth compensation is continuously applied to the control voltage maintained in the storage capacitor.

[0049] The pixel circuit 400 adjusts the data signal supplied from the driver IC 134 and uses the adjusted signal to control the light emission of the OLED element. The pixel circuit 400 includes eight transistors (TFTs) M1 to M8, each of which has a gate, a source, and a drain. The transistors M1 to M8 in this example are p-type TFTs, and the transistors other than the driving transistor M3 are switching transistors. The transistor M8 is optional.

[0050] The pixel circuit 400 further includes a storage capacitor Cst, a first auxiliary capacitor Cd1, and a second auxiliary capacitor Cd2. The storage capacitor Cst is connected between an anode power supply for supplying a power supply potential VDD and a gate (node ​​N1) of the driving transistor M3. The storage capacitor Cst stores a gate-source voltage (also referred to as a gate voltage or a control voltage) of the driving transistor M3.

[0051] One end of the auxiliary capacitor Cd1 is connected to a node N3 located between the source / drain of the switching transistor M2 and the source / drain of the driving transistor M3, and the other end is connected to a power line for transmitting the anode power supply potential VDD. The auxiliary capacitor Cd1 stores an auxiliary voltage between the source / drain of the switching transistor M2 and the anode power supply. The transistor M2 is a second switching transistor for switching between transmitting a data signal to the storage capacitor and stopping the transmission of the data signal.

[0052] One end of the auxiliary capacitor Cd2 is connected to the node N3 between the source / drain of the switching transistor M2 and the source / drain of the driving transistor M3, and the other end is connected to the anode of the OLED element E1. The auxiliary capacitor Cd2 stores an auxiliary voltage between the source / drain of the switching transistor M2 and the anode of the OLED element E1.

[0053] The transistor M3 is a driving transistor for controlling the amount of current flowing to the OLED element E1. The driving transistor M3 controls the amount of current supplied from the anode power supply to the OLED element E1 according to the voltage stored in the storage capacitor Cst. The cathode of the OLED element E1 is connected to the cathode power supply for supplying the cathode potential VEE.

[0054] The transistors M1 and M6 control whether the OLED element E1 is to emit light. The transistor M1 is connected from the source / drain to the anode power supply, and turns on / off the current supply to the driving transistor M3 connected to the other source / drain. The transistor M6 is connected from the source / drain to the drain of the driving transistor M3, and turns on / off the current supply to the OLED element E1 connected to the other source / drain. The transistors M1 and M6 are controlled by the light emission control signal Em input to their gates from the scanning circuit 131 or 132.

[0055] The transistor M7 operates to supply a reset potential to the anode of the OLED element E1. When the transistor M7 is turned on by the selection signal S2 input to the gate from the scanning circuit 131 or 132, it supplies a reset potential Vrst from the reset power supply to the anode of the OLED element E1. The reset potential may be a GND potential or a potential lower than the GND potential. The other end of the reset power supply is connected to GND.

[0056] The transistor M5 controls whether to supply a reset potential to the gate of the driving transistor M3. When the transistor M5 is turned on by the selection signal S1 input to the gate terminal from the scanning circuit 131 or 132, it supplies a reset potential Vrst to the gate of the transistor M3 from a reset power supply connected to the source / drain of the transistor M5. The other end of the reset power supply is connected to GND. The reset potential of the anode of the OLED element E1 may be different from the reset potential of the gate of the driving transistor M3.

[0057] The transistor M2 is a selection transistor for selecting the pixel circuit 400 to which the data signal is supplied. The gate voltage of the transistor M2 is controlled by the selection signal S2 supplied from the scanning circuit 131 or 132. When the selection transistor M2 is turned on, it supplies the data signal Vdata supplied from the driver IC 134 through the data line to the auxiliary capacitors Cd1 and Cd2.

[0058] In this example, the source and drain of transistor M2 are connected between the data line and the source (node ​​N2) of driving transistor M3. In addition, transistor M8 is connected between the source / drain (node ​​N3) of selection transistor M2 and the source (node ​​N2) of driving transistor M3. Transistor M8 is a third switching transistor. Transistor M4 is connected between the drain and gate of driving transistor M3. Transistor M4 is a first switching transistor.

[0059] The transistors M4 and M8 are controlled by the selection signal S3 supplied from the scanning circuit 131 or 132. The transistor M4 operates to compensate for the threshold voltage Vth of the driving transistor M3. The transistor M4 switches between the connection and disconnection of the gate and the drain of the driving transistor M3. When the transistor M4 is turned on, the driving transistor M3 is in a diode connection state. When the transistor M4 is turned off, the driving transistor M3 is in a normal state.

[0060] The data signal Vdata from the data line is supplied to the storage capacitor Cst through the transistors M2 and M8 in the on state, the driving transistor M3 in the diode connection state, and the transistor M4 in the on state. At the same time, Vth compensation is applied. During this period, the data signal Vdata from the data line is also supplied to the auxiliary capacitors Cd1 and Cd2 through the transistor M2 in the on state.

[0061] After the transistor M2 is turned off, the charge stored in the node N3 caused by the auxiliary voltage of the auxiliary capacitors Cd1 and Cd2 is transferred to the storage capacitor Cst through the transistor M8 in the on state, the driving transistor M3 in the diode connection state, and the transistor M4 in the on state. This charge transfer process further performs Vth compensation on the control voltage stored in the storage capacitor Cst.

[0062] The storage capacitor Cst stores the gate-source voltage of the driving transistor M3 to control the amount of current supplied from the driving transistor M3 to the OLED element E1. As described above, the storage capacitor Cst stores a voltage adjusted according to the threshold voltage Vth of the driving transistor M3.

[0063] As described above, after the transistor M2 is turned off, the control voltage of the storage capacitor Cst can continue to be Vth compensated by the auxiliary capacitors Cd1 and Cd2. Therefore, more appropriate Vth compensation can be performed, which effectively reduces image sticking.

[0064] Figure 2 The pixel circuit 400 in the example includes two auxiliary capacitors Cd1 and Cd2. This configuration increases the capacitance for storing auxiliary charge in the pixel circuit 400 to perform more effective Vth compensation. If another configuration example that can ensure the required capacitance is available, one of the two auxiliary capacitors Cd1 and Cd2 can be removed. When writing an auxiliary voltage to the auxiliary capacitor, one end of the capacitor is supplied with a data signal and the other end is supplied with a predetermined fixed potential. The fixed potential is not limited to a specific potential.

[0065] Figure 3 It is used to control the Figure 2 4 is a timing diagram of signals of the pixel circuit 400 shown. Figure 3 4 is a timing diagram for selecting the Nth pixel circuit row and writing the data signal Vdata into the pixel circuit 400. Specifically, Figure 3 The signals shown in FIG. 1 are a light emission control signal Em, a selection signal S1, a selection signal S2, a selection signal S3, and a data signal Vdata. The selection signal S2 may be common to the selection signal S1_N+1 of the (N+1)th row.

[0066] At time T1, the light emitting control signal Em changes from low to high. At time T1, transistors M1 and M6 are turned off. At time T1, the selection signals S1, S2 and S3 are high. According to these control signals, transistors M2, M4, M5, M7 and M8 are turned off. The states of these transistors are maintained until time T2 later than time T1. The potential of node N1 is the signal potential of the previous frame.

[0067] At time T2, the selection signal S1 changes from high to low. At time T2, the light emission control signal Em and the selection signals S2 and S3 are high. The transistor M5 is turned on in response to the change of the selection signal S1. The transistors M1, M2, M4 and M6 to M8 are turned off.

[0068] In response to the transistor M5 being turned on, the potential of the node N1 becomes the reset potential Vrst. The reset potential Vrst is supplied to the node N1 from time T2 to time T3. Since the node N1 is supplied with the reset potential every frame, the gate potential of the driving transistor M3 is the same potential every frame, so the hysteresis effect of the driving transistor M3 can be reduced.

[0069] At time T3, the selection signal S1 changes from low to high, and the selection signals S2 and S3 change from high to low. The light-emitting control signal Em is high. The transistor M5 is turned off in response to the change of the selection signal S1. The transistors M2 and M7 are turned on in response to the change of the selection signal S2. The transistors M4 and M8 are turned on in response to the change of the selection signal S3. The transistors M1 and M6 remain turned off.

[0070] In response to the transistor M7 being turned on, the reset potential Vrst is supplied to the anode of the OLED element E1 and one end of the auxiliary capacitor Cd2. Since the transistor M4 is turned on, the driving transistor M3 is diode-connected.

[0071] Since transistors M2 and M8 are turned on, the data signal Vdata from the data line is written into the storage capacitor Cst through transistors M2, M8, M3 and M4. The voltage to be written into the storage capacitor Cst is a voltage after adjusting the threshold voltage Vth of the driving transistor M3 for the data signal Vdata.

[0072] In addition, since the transistor M2 is turned on, the data signal Vdata from the data line is written into the auxiliary capacitors Cd1 and Cd2 through the transistor M2. The auxiliary capacitor Cd1 stores the voltage between the anode power supply potential (fixed potential) and the data signal, and the auxiliary capacitor Cd2 stores the voltage between the data signal and the reset power supply potential (fixed potential). In the period from time T3 to time T4, the data signal Vdata is written into the pixel circuit 400 and the Vth compensation of the data signal Vdata is performed.

[0073] At time T4, the selection signal S2 changes from low to high. At time T4, the light emitting control signal Em and the selection signal S1 are high, and the selection signal S3 is low. Transistors M2 and M7 are turned off in response to the change of the selection signal S2. Transistors M8 and M4 are turned on, and transistors M1, M2, and M5 to M7 are turned off.

[0074] Since transistors M8 and M4 are turned on, Vth compensation of the control signal stored in the storage capacitor Cst continues through the auxiliary voltage (data voltage) stored in the auxiliary capacitors Cd1 and Cd2. From time T4 to time T5, these states of the control signal and the transistors are maintained. In one example, the auxiliary capacitors Cd1 and Cd2 have the capacitance required to keep the node N3 at a potential substantially the same as the potential of the data signal Vdata during this period.

[0075] At time T5, the selection signal S3 changes from low to high. The time T5 coincides with the time when the selection signal S2 of the (N+m)th row (m is an integer greater than 1) changes from high to low. In response to this change in the selection signal S3, the transistors M4 and M8 are turned off. The other switching transistors remain turned off. At time T5, the Vth compensation of the control voltage in the storage capacitor Cst by the auxiliary capacitors Cd1 and Cd2 ends.

[0076] At time T6, the light emitting control signal Em changes from high to low, and the transistors M1 and M6 change from off to on. The selection signals S1, S2 and S3 are high, and the transistors M2, M4, M5, M7 and M8 remain off. The driving transistor M3 controls the driving current supplied to the OLED element E1 based on the adjusted data voltage stored in the storage capacitor Cst. This means that the OLED element E1 emits light.

[0077] The above-mentioned pixel circuit action enables Vth compensation to be applied in the period from time T3 to time T5. This period is longer than the period from time T3 to time T4, in which the selection signal S2 is low and the data signal is written from the data line to the pixel circuit. The Vth compensation period suitable for the display device can be determined by adjusting the time T5 when designing the circuit. The determined Vth compensation period is longer than the data writing period.

[0078] Figure 3 The data writing period in the example of is the period from time T3 to time T4. The Vth compensation period is the period from time T3 to time T5. The data writing period is the period during which the transistor M2 is turned on and the data signal is supplied from the data line to the pixel circuit. The Vth compensation period is the period during which the potential is supplied to the storage capacitor Cst through the driving transistor M3 in the diode connection state and Vth compensation is applied to the control voltage in the storage capacitor Cst.

[0079] Figure 3The data writing period in the example is included in the Vth compensation period. That is, in the period from time T3 to time T4, data writing and Vth compensation are performed simultaneously. However, in the subsequent period from time T4 to time T5, data writing is not performed and only Vth compensation using the auxiliary capacitor is performed. This configuration of the Vth compensation period including the data writing period can achieve more appropriate Vth compensation.

[0080] In another configuration example, the data writing period may end before the Vth compensation period without overlapping the period. Figure 3 In the timing diagram of , the data writing period may be the period from time T2 to time T3. This period is a reset period, in which the selection signal S1 is low and a reset potential is supplied to the gate of the driving transistor M3. Since the transistor M8 is turned off, the data signal from the data line is supplied to the auxiliary capacitors Cd1 and Cd2, but not to the storage capacitor Cst.

[0081] Auxiliary capacitor conditions

[0082] Below, an example of the conditions of the auxiliary capacitors Cd1 and Cd2 is described. During the Vth compensation period when the selection signal S3 is low, the potential of the node N2 is preferably maintained at the potential Vdata of the data signal. If the total auxiliary capacitance (Cd1+Cd2) of the auxiliary capacitors is small, the potential of the node N2 drops sharply so that the Vth compensation mechanism stops. Therefore, an auxiliary capacitor with a sufficiently large total auxiliary capacitance Cd is included in the pixel circuit to enhance the charge retention function of the node N2. As a result, the node N2 obtains a smaller potential change during the Vth compensation period to continue the Vth compensation.

[0083] Figure 4 Shows about Figure 2 and Figure 3 The simulation results of the relationship between the Vth compensation period and image sticking in the pixel circuit shown in FIG. Figure 4 In the curve graph, the horizontal axis represents the Vth compensation period, and the vertical axis represents the indication number of the intensity of image sticking. When the indication number takes a positive value, the image sticking is negative. When the indication number takes a negative value, the image sticking is positive. The farther the indication number is from 0, the stronger the image sticking is. The data writing period (1H period) is 4.2μs, and the capacitance of the storage capacitor Cst is 80fF. The data writing period is also called the horizontal selection period.

[0084] In the curve graph, different lines represent the simulation results of different total auxiliary capacitances Cd of two auxiliary capacitors Cd1 and Cd2. Line 421 represents the data of a pixel circuit with a total auxiliary capacitance of 0 for the auxiliary capacitance. Line 422 represents the data of a pixel circuit with a total auxiliary capacitance of 40 fF for the auxiliary capacitance. Line 423 represents the data of a pixel circuit with a total auxiliary capacitance of 80 fF for the auxiliary capacitor. Line 424 represents the data of a pixel circuit in which the total auxiliary capacitance of the auxiliary capacitor is 160 fF or 240 fF.

[0085] The image residual intensity index is defined as follows:

[0086] Image residual intensity index = 2.0 * (I1 - I2) / (I1 + I2),

[0087] where I1 represents the drain current when the emission level changes from black to the intermediate level, and I2 represents the drain current when the emission level changes from white to the intermediate level after a predetermined period of display of a black-and-white checkerboard pattern.

[0088] According to this definition, when I1 > I2 or the image residual intensity index takes a positive value, the current (brightness) of the pixel displaying black becomes higher than the current of the pixel displaying white. Therefore, the ghosting is a checkerboard pattern with a brightness opposite to the original black-and-white checkerboard pattern. Therefore, it is defined as negative image residual. When I1 < I2, the image residual is defined as positive image residual.

[0089] Figure 4 The range 430 in is the range in which the image residual intensity index takes values from -2.0E-03 to 2.0E-03. This range 430 is the range of negligible image residual obtained from the experimental results of the inventor. It is known that image residual depends on the bias history of the driving TFT, and the image residual intensity index increases almost proportionally to the stress time by displaying a black-and-white checkerboard pattern.

[0090] It is well known that when the brightness difference between adjacent regions is about ±1%, ghosting can be visually perceived. However, in these simulations, the stress time for displaying black and white is about 1 / 10 of the actual product test conditions, so the image residual intensity index takes a smaller value. The above range 430 is determined considering the differences in the display conditions and simulation conditions of the display panel.

[0091] As Figure 4 shown, when the total auxiliary capacitance Cd is greater than or equal to 40 fF, by appropriately determining the Vth compensation period, the image residual intensity can be included in the range 430. In addition, when the total auxiliary capacitance Cd is greater than or equal to 80 fF, the image residual intensity can be reduced to zero by appropriately determining the Vth compensation period.

[0092] Since the capacitance of the storage capacitor Cst is 80 fF as described above, by providing a total auxiliary capacitance greater than or equal to 1 / 2 of the capacitance of the storage capacitor, the image sticking intensity can be included in the range 430. In addition, by providing a total auxiliary capacitance greater than or equal to the capacitance of the storage capacitor, the image sticking intensity can be reduced to zero.

[0093] like Figure 4 As shown, when the value of Cd and the length of the compensation period are too large, the image sticking intensity indicator number drops too much in the negative direction. In order to appropriately reduce image sticking, it is very important to determine an appropriate compensation period. The compensation period is explained below.

[0094] Figure 5 Shows Figure 2 and Figure 3 The simulation results of the relationship between the total auxiliary capacitance and image sticking in the pixel circuit are shown. Figure 5 In the graph of , the horizontal axis represents the total auxiliary capacitance, and the vertical axis represents the image sticking intensity. The data writing period (1H period) is 4.2 μs, and the capacitance of the storage capacitor Cst is 80 fF.

[0095] Different lines in the graph represent simulation results for different Vth compensation periods. Line 441 represents the data of the pixel circuit when the Vth compensation period is 12.6 μs; Line 442 represents the data of the pixel circuit when the Vth compensation period is 21.0 μs. Line 443 represents the data of the pixel circuit when the Vth compensation period is 29.4 μs; Line 444 represents the data of the pixel circuit when the Vth compensation period is 42.0 μs.

[0096] like Figure 5 As shown, when the Vth compensation period is between 21.0 μs and 42.0 μs, by appropriately determining the total auxiliary capacitance, the image sticking intensity can be included in the range 430. Since the data writing period (1H period) is 4.2 μs, the image sticking intensity can be included in the range 430 by determining the Vth compensation period to be not less than 5H and not more than 10H.

[0097] Figure 6 Observed from another perspective Figure 2 and Figure 3 Graph showing simulation results of the pixel circuit shown. The horizontal axis represents (Cd / Cst)×(Vth compensation period / data writing period) 3 , where Cd represents the total auxiliary capacitance and Cst represents the capacitance of the storage capacitor. The vertical axis represents the image sticking intensity. Different combinations of the value Cd and the length of the Vth compensation period may have the same value on the horizontal axis and different values ​​on the vertical axis. Figure 6The rectangular range 440 in FIG. 4 is a range where the image sticking strength indicator is within the range of -2.0E-03 to 2.0E-03. Figure 6 As can be understood from the graph, the image sticking intensity can be included in the above-mentioned ideal range by satisfying the following conditions:

[0098] 100≤(Cd / Cst)×(Vth compensation period / data writing period) 3 ≤700.

[0099] Device structure

[0100] Hereinafter, an example of a device structure of a pixel circuit is described. Figure 7 is a plan view schematically showing an example of a device structure of a pixel circuit when viewed from a stacking direction. Figure 7 The polysilicon layer and the conductive layer in the pixel circuit are shown. The white rectangles represent the contact areas of different conductive layers. The contact areas are conductive areas set in the through holes that pass through the insulating layer along the stacking direction.

[0101] The transmission lines M1S1, M1S2, M1S3 and M1E transmit the selection signals S1, S2 and S3 and the light emission control signal Em respectively, and are included in the first metal layer, which is a conductive layer. Figure 7 These transmission lines in the example extend in the X-axis direction. Figure 7 The selection signal S1 in the example of is common to the selection signal S2 of the previous row.

[0102] As reference Figure 2 As described, the pixel circuit includes transistors M1 to M8. The channels of the transistors are contained in the polysilicon layer p-Si. Figure 7 In FIG. 1 , the polysilicon layer p-Si is represented by the same pattern. The gate electrodes of transistors M1 to M8 are included in the first metal layer. Figure 7 , the gate electrode of the driving transistor M3 is denoted by reference symbol M1G.

[0103] The conductive region MCP covers the entire gate electrode M1G of the driving transistor M3. The conductive region MCP is connected to a power line M2V for transmitting an anode power supply potential VDD through a contact hole. The conductive region MCP is included in an intermediate conductive layer higher than the first metal layer. A portion of the conductive region MCP is included in the storage capacitor Cst. The intermediate conductive layer also includes transmission lines MCV and MCV2 extending in the X-axis direction to transmit a reset potential Vrst. The transmission lines M2V and M2D extend in the Y-axis direction and transmit the anode power supply potential VDD and the data signal Vdata, respectively. They are included in a second metal layer higher than the intermediate conductive layer. The second metal layer is a conductive layer.

[0104] The capacitor electrode M3C is included in a third metal layer higher than the second metal layer. The third metal layer is a conductive layer. The capacitor electrode M3C is connected to the source or drain of the transistor M2 and the source or drain of the transistor M8 through the contact region M2C of the second metal layer. The capacitor electrode M3C is Figure 2 The common electrode of the auxiliary capacitors Cd1 and Cd2 in the pixel circuit shown.

[0105] The capacitor electrode M3C covers at least a portion of the power line M2V for transmitting the anode power supply potential VDD. The auxiliary capacitor Cd1 is configured between the capacitor electrode M3C and the power line M2V. In addition, the anode electrode RE of the OLED element covers at least a portion of the capacitor electrode M3C. The anode electrode RE is located above the third metal layer including the capacitor electrode M3C. The auxiliary capacitor Cd2 is configured between the capacitor electrode M3C and the anode electrode RE.

[0106] Figure 8 Schematically shows the Figure 7 Cross-sectional structure along section line VIII-VIII'. Figure 8 The transistors M1 and M2 and the auxiliary capacitor Cd2 are mainly shown. The stacked structure of the pixel circuit is made on a substrate SUB made of polyimide or glass. For example, an undercoat layer UC of silicon nitride is placed on the substrate SUB. A polysilicon layer p-Si is placed on the undercoat layer UC. In addition, a gate insulating layer GI is placed to cover the polysilicon layer p-Si. The gate insulating layer GI can be made of silicon oxide or silicon nitride.

[0107] The first metal layer is disposed on the gate insulating layer GI. Specifically, the transmission line M1E for transmitting the light emitting control signal Em, the transmission lines M1S1, M1S2 and M1S3 for transmitting the selection signals S1, S2 and S3 are shown in FIG. Figure 8 In. Figure 8 In FIG. 4 , the transmission line M1S2 corresponds to the gate electrode of the transistor M2. The first metal layer may be made of a metal having a high melting point, such as W, Mo or Ta, or an alloy of such metals.

[0108] The interlayer insulating layer IMD is provided to cover the first metal layer. The interlayer insulating layer IMD may be made of silicon oxide or silicon nitride. The intermediate conductive layer is provided on the interlayer insulating layer IMD. Specifically, a transmission line MCV for transmitting a reset potential and a conductive region MCP as a part of a storage capacitor Cst are shown in FIG. Figure 8 The middle conductive layer may include a single layer structure of a metal having a high melting point (eg, W, Mo, or Ta, or an alloy of such metals), or a multilayer structure of Al, or Ti / Al / Ti.

[0109] The interlayer insulating layer ILD is disposed to cover the intermediate conductive layer. The interlayer insulating layer ILD may be made of silicon oxide or silicon nitride. The second metal layer is disposed on the interlayer insulating layer ILD. Figure 8 Transmission lines M2V for anode power supply potential VDD, transmission lines M2D for data signal Vdata, and contact region M2C are shown. Transmission lines M2V and M2D and contact region M2C contact the polysilicon layer P-Si through vias opened through the interlayer insulating layer ILD and the gate insulating layer GI.

[0110] The passivation layer PAS and the planarization layer PLN1 on the passivation layer PAS are arranged to cover the layers below them. These layers can be made of organic or inorganic insulators. The third metal layer including the capacitor electrode M3C is arranged on the planarization layer PLN1. The capacitor electrode M3C contacts the contact area M2C through a through hole opened through the planarization layer PLN1 and the passivation layer PAS.

[0111] Another planarization layer PLN2 is provided to cover the layer below it. The planarization layer PLN2 may be made of an organic or inorganic insulator. The anode electrode RE of the OLED element is provided on the planarization layer PLN2. The anode electrode RE may have an ITO / Ag / ITO structure or an IZO / Ag / IZO structure.

[0112] A portion of the anode electrode RE faces the capacitor electrode M3C via the planarization layer PLN2 to form an auxiliary capacitor Cd2. The auxiliary capacitor Cd2 disposed between the anode electrode RE and the capacitor electrode M3C of the third metal layer effectively increases the capacitance for storing an auxiliary voltage for Vth compensation in the storage capacitor Cst.

[0113] Fig. 9 Schematically shows the Figure 7 Cross-sectional structure along section line IX-IX'. Fig. 9 The cross-sectional structure of the driving transistor M3 and its surroundings is shown. The gate electrode M1G of the driving transistor M3 covers the channel of the polysilicon layer p-Si via the gate insulating layer GI to control the current flowing through the channel.

[0114] The conductive region MCP of the intermediate conductive layer faces the gate electrode M1G via the interlayer insulating layer IMD. In addition, the conductive region MCP faces the transmission line M2V for the anode power supply potential VDD via the interlayer insulating layer ILD. The storage capacitor Cst is arranged between the gate electrode M1G and the transmission line M2V facing each other via the conductive region MCP.

[0115] The contact region MB of the second metal layer is disposed to contact the gate electrode M1G through the interlayer insulating layer ILD, the opening of the conductive region MCP and the gate insulating layer IMD. The contact region MB connects the gate electrode M1G of the driving transistor M3 and the source / drain of the transistor M4.

[0116] The transmission line M2V of the anode power supply potential VDD of the second metal layer is opposite to the capacitor electrode M3C of the third metal layer via the passivation layer PAS and the planarization layer PLN1. The auxiliary capacitor Cd1 is arranged between the transmission line M2V and the capacitor electrode M3C. Figure 8 As shown, the auxiliary capacitor Cd2 is arranged between the anode electrode RE and the capacitor electrode M3C.

[0117] As described above, an auxiliary capacitor is provided between the anode power supply line and the capacitor electrode, and another auxiliary capacitor is provided between the capacitor electrode and the anode electrode, thereby realizing the auxiliary capacitance required for applying appropriate Vth compensation to the control voltage of the drive transistor in a small area.

[0118] Other configuration examples

[0119] In the following, some different configuration examples of pixel circuits are described. Transistor M8 can be Figure 2 The pixel circuit 400 is shown removed. Fig.10 1 is a plan view schematically showing a structural example of a pixel circuit after the transistor M8 is removed. Figure 7 The differences in the structures shown.

[0120] like Fig.10 As shown, the pixel circuit includes an electrode region M2E1 of the second metal layer across the transmission line M1S3. The electrode region M2E1 is connected to the source / drain of the transistor M2 through the contact region M2C, and is further connected to the source / drain of the transistor M1 and the source of the transistor M3 through another contact region M2C2. This configuration does not include the transistor M8. Fig.10 Compared with this structure, Figure 7 The structure in may not include the electrode region M2E1 crossing the transmission line M1S3. The transistor M8 increases the number of circuit elements but makes the device structure simpler.

[0121] Fig.11 Another example of the circuit configuration of the pixel circuit is shown. Figure 2 The pixel circuit 500 includes n-type transistors M12, M14, M15, M17 and M18. They correspond to Figure 2The p-type transistors M2, M4, M5, M7 and M8 in the pixel circuit 400. The transistors M1, M3 and M6 through which the driving current of the OLED element E1 flows are p-type polysilicon transistors having high mobility.

[0122] The selection signals S1, S2 and S3 for controlling the pixel circuit 500 show the same Figure 3 The time variation shown is the opposite of the variation shown. In other words, Figure 3 The high level and low level in the light emitting control signal Em are replaced with each other. Figure 3 The same changes in FIG. 1 are shown in FIG. 2 . The n-type transistor may be an oxide semiconductor transistor. Compared with polysilicon transistors, oxide semiconductor transistors exhibit low leakage current. Reducing the leakage current of transistor M12 reduces the loss of stored charge of auxiliary capacitors Cd1 and Cd2. Reducing the leakage current of transistors M14 and M15 reduces the loss of stored charge of storage capacitor Cst. Fig.11 One or more of the n-type transistors may be a p-type transistor.

[0123] Fig.12 It is schematically shown Fig.11 FIG. 5 is a plan view of an example of a device structure of a pixel circuit 500 shown in FIG. Figure 7 As mentioned above, Figure 7 The p-type transistors M2, M4, M5, M7 and M8 in the structural example are replaced by n-type transistors M12, M14, M15, M17 and M18 respectively. The p-type transistors are polysilicon TFTs, and the n-type transistors are oxide semiconductor TFTs. The oxide semiconductor can be InGaZnO or ZnO.

[0124] exist Fig.12 , the oxide semiconductor layer OX includes channels of transistors M12, M14, M15, M17 and M18. The electrodes M2E5, M2E6 and M2E7 of the second metal layer connect the source / drain of a transistor of one conductivity type to the source / drain of a transistor of another conductivity type. Specifically, the electrode M2E5 connects the p-type transistor M1 to the n-type transistor M18. The electrode M2E6 connects the p-type transistors M3 and M6 to the n-type transistor M18. The electrode M2E6 connects the p-type transistors M3 and M6 to the n-type transistor M14. The electrode M2E7 connects the p-type transistor M6 to the n-type transistor M17.

[0125] Transmission lines MDS1, MDS2 and MDS3 for transmitting selection signals S1, S2 and S3 are included in the fourth metal layer. The fourth metal layer is a conductive layer. As described later, the fourth metal layer is located between the intermediate metal layer and the second metal layer.

[0126] Fig.13 Schematically shows the Fig.12 The cross-sectional structure of the section line XIII-XIII' in FIG. Figure 8 The oxide semiconductor layer OX and the gate insulating layer GI2 are placed between the interlayer insulating layer ILD and the passivation layer PAS. The oxide semiconductor layer OX is provided on the interlayer insulating layer ILD and is covered by the gate insulating layer GI2.

[0127] The electrode M2E5 of the second metal layer connects the source / drain of the polysilicon transistor M1 and the source / drain of the oxide semiconductor transistor M12 to each other. Specifically, the electrode M2E5 of the second metal layer contacts the source / drain of the p-type transistor M1 through a through hole that penetrates the passivation layer PAS, the gate insulating layer GI2, the interlayer insulating layer ILD, the interlayer insulating layer IMD, and the gate insulating layer GI. Moreover, the electrode M2E5 of the second metal layer contacts the source / drain of the n-type transistor M12 through a through hole that penetrates the passivation layer PAS and the gate insulating layer GI2.

[0128] Transmission lines MDS1, MDS2 and MDS3 for transmitting selection signals S1, S2 and S3 are included in the fourth metal layer. The fourth metal layer can be made of a metal with a high melting point, such as W, Mo or Ta or an alloy of these metals. The fourth metal layer is disposed between the gate insulating layer GI2 and the passivation layer PAS. The fourth metal layer is a metal layer (conductive layer) between the intermediate conductive layer and the second metal layer.

[0129] Similar to Figure 2 The transistor M8 in the pixel circuit 400 can be obtained from Fig.11 The transistor M18 is removed from the pixel circuit 500. Fig.14 1 is a plan view schematically showing an example of a device structure of the circuit 500 from which the transistor M18 is removed. Fig.12 In the structural example, instead of electrode M2E5, electrode M2E8 is used.

[0130] The electrode M2E8 is included in the second metal layer. It crosses the conductive region MCP and the transmission line MDS3 and connects the source / drain of the p-type transistor M1 and the source / drain of the n-type transistor M12 to each other. Including the transistor M18 in the pixel circuit 500 makes the device structure simpler.

[0131] Fig.15 FIG. 1 shows another example of a circuit configuration of a pixel circuit. Figure 2 The difference between the pixel circuit 400 in FIG. Figure 2In addition to the configuration of the pixel circuit 400 in FIG. 6 , the pixel circuit 600 further includes a third auxiliary capacitor Cd3 and a second capacitor electrode SH. One end of the third auxiliary capacitor Cd3 is the second capacitor electrode SH, and the other end is connected to the node N2. The second capacitor electrode SH can be supplied with a fixed potential. The remaining configuration is the same as the configuration of the pixel circuit 400.

[0132] Fig.16 It is schematically shown Fig.15 A plan view of an example of a device structure of a pixel circuit shown. Fig.17 Schematically shows the Fig.16 Cross-sectional structure along section line XVII-XVII'. Fig.18 Schematically shows the Fig.16 The cross-sectional structure of the section line XVIII-XVIII' in FIG. Figures 7 to 9 The differences between the structural examples described.

[0133] Figures 16 to 18 The structural example shown in FIG. 1 includes a second capacitor electrode SH between the substrate SUB and the undercoat layer UC. Fig.16 As shown, the second capacitor electrode SH is disposed below the driving transistor M3 and at least partially overlaps the driving transistor M3.

[0134] The second capacitor electrode SH may be supplied with a fixed potential, for example, a ground potential. The third auxiliary capacitor Cd3 is configured with a polysilicon layer p-Si including the drain of the driving transistor M3 and the second capacitor electrode SH. Figures 16 to 18 The structural example shown in includes a capacitor electrode M3C, which is optional.

[0135] Since the total capacitance of the auxiliary capacitor can be made large, ghosting can be effectively controlled even if the pixel size is reduced to improve the resolution. In addition, in the case of using a polyimide film as a substrate, the undesired current drift in the drive transistor caused by the fixed charge generated in the polyimide can be blocked by the second capacitor electrode layer to stabilize the drive transistor. As a result, the brightness drift and ghosting that appear soon after the panel is started, especially the ghosting caused by long-term stress, are reduced.

[0136] Fig.19 1 shows another example of the circuit configuration of the pixel circuit. Fig.11 The pixel circuit 700 is different from the pixel circuit 500 in FIG. The pixel circuit 700 includes a third auxiliary capacitor Cd3 and a second capacitor electrode SH. One end of the third auxiliary capacitor Cd3 is the second capacitor electrode SH, and the other end is connected to the node N2. The second capacitor electrode SH can be supplied with a fixed potential. The remaining configuration is the same as the configuration of the pixel circuit 500.

[0137] Fig. 20 It is schematically shown Fig.19 A plan view of an example of a device structure of a pixel circuit. Fig.21 Schematically shows the Fig. 20 The cross-sectional structure of the section line XXI-XXI' in FIG. Fig.12 and Fig.13 The differences between the structural examples described.

[0138] Fig. 20 and Fig.21 The structural example shown in FIG. 1 includes a second capacitor electrode SH between the substrate SUB and the undercoat layer UC. Fig. 20 As shown, the second capacitor electrode SH is disposed below the driving transistor M3 and at least partially overlaps the driving transistor M3.

[0139] The second capacitor electrode SH may be supplied with a fixed potential, for example, a ground potential. The third auxiliary capacitor Cd3 is composed of a polysilicon layer p-Si including the drain of the driving transistor M3 and the second capacitor electrode SH. Fig. 20 and Fig.21 The structural example shown in includes a capacitor electrode M3C, which is optional.

[0140] In addition, bottom gate lines MCS2 and MCS3 are added to make the oxide semiconductor transistors M12, M17, and M18 double-gate TFTs. The bottom gate lines MCS2 and MCS3 are provided between the interlayer insulating layers IMD and ILD. Fig. 20 and Fig.21 In the structural example, when viewed from above, the top gate line MDS2 overlaps with the bottom gate line MCS2, and the top gate line MDS3 overlaps with the bottom gate line MCS3. The top gate line MDS2 is connected to the bottom gate line MCS2, and the top gate line MDS3 is connected to the bottom gate line MCS3, for example, outside the display area, so that the top gate and the bottom gate are driven at the same potential.

[0141] In the case of using a polyimide film as a substrate, the undesired Vth drift of the oxide semiconductor transistor caused by the fixed charge generated in the polyimide can be shielded by the bottom gate line to stabilize the characteristics of the transistor. The oxide semiconductor transistor with a dual-gate structure can reduce the short channel effect. Therefore, the oxide semiconductor transistor can have a shorter channel, which improves the driving capability to achieve a high-resolution pixel layout.

[0142] As described above, the embodiments of the present invention have been described; however, the present disclosure is not limited to the above-mentioned embodiments. Those skilled in the art can easily modify, add or convert each element in the aforementioned embodiments within the scope of the present invention. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, or the configuration of one embodiment can be incorporated into the configuration of another embodiment.

Claims

1. A display device, comprising: substrate, and a plurality of pixels on the substrate, Each of the plurality of pixels includes a light emitting element and a pixel circuit, wherein the pixel circuit is configured to control the amount of light emitting current flowing to the light emitting element, and Wherein, the pixel circuit comprises: a drive transistor having a first conductivity type; a first switch transistor having a second conductivity type and configured to be connected or disconnected between a gate and a drain of the drive transistor; a second switching transistor having the second conductivity type and configured to supply a reset voltage to a gate of the driving transistor; a storage capacitor including a gate electrode of the driving transistor, an interlayer insulating layer covering the gate electrode of the driving transistor, and an intermediate conductive layer disposed on the interlayer insulating layer; and An auxiliary capacitor includes a capacitor electrode disposed under the driving transistor, a semiconductor layer of the driving transistor, and an insulating layer between the capacitor electrode and the semiconductor layer of the driving transistor.

2. The display device according to claim 1, in, The first switch transistor has a double-gate structure, and the double-gate structure includes: A bottom gate electrode disposed on the interlayer insulating layer; an oxide semiconductor layer above the bottom gate electrode; a second interlayer insulating layer disposed between the bottom gate electrode and the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer; and A top gate electrode is disposed on the gate insulating layer and overlaps with the bottom gate electrode in a plan view.

3. The display device according to claim 2, wherein: The top gate electrode and the bottom gate electrode are driven at the same potential.

4. The display device according to claim 2, wherein: The intermediate conductive layer of the storage capacitor and the bottom gate electrode are included in a layer made of a high melting point metal material.

5. The display device according to claim 1, wherein: The substrate is made of polyimide.

6. The display device according to claim 1, further comprising: a third switching transistor having the first conductivity type and being between a power supply line and the driving transistor, and a fourth switching transistor having the first conductivity type and being between the driving transistor and the light emitting element, The first conductivity type is p-type, and the second conductivity type is n-type.

7. The display device according to claim 1, further comprising: a fifth switch transistor, the fifth switch transistor having the second conductivity type and a dual gate structure; a sixth switch transistor, the sixth switch transistor having the second conductivity type and a dual gate structure; as well as a seventh switching transistor having the second conductivity type and a double gate structure and configured to supply a reset voltage to an anode of the light emitting element, The fifth switch transistor and the sixth switch transistor are connected in series between the data line and the source of the driving transistor, and The first conductivity type is p-type, and the second conductivity type is n-type.

8. The display device according to claim 1, wherein: The intermediate conductive layer and the bottom gate electrode of the first switch transistor are composed of parts of the same metal layer.

9. The display device according to claim 1, wherein: The capacitor electrode of the auxiliary capacitor of each pixel circuit is connected to the capacitor electrode of the auxiliary capacitor of the adjacent pixel circuit.

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