Scanning driving circuit, array substrate and display panel

Abstract

The invention provides a scanning driving circuit, an array substrate and a display panel. The scanning drive circuit comprises n cascaded first shift register units and n cascaded second shift register units. The output end of the ith-level first shift register unit is connected with the first scanning line signal line of the corresponding pixel row, the third scanning line signal line of the pixel row is connected to the output end of the (i + 2) th-level first shift register unit, i = 1... n, and n is the number of the first shift register units; a third scanning line signal line of the pixel row corresponding to the (n-1) th stage of first shift register unit is connected with the output end of the first stage of second shift register unit; a third scanning line signal line corresponding to the pixel row of the nth-stage first shifting register unit is connected with the output end of the second-stage second shifting register unit, and the output ends of the second shifting register units are connected to the compensation module, so that the problem of uneven display brightness caused by inconsistent row loads of the last two rows is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a scanning drive circuit, an array substrate and a display panel. Background Art

[0002] With the development of display technology, people have higher and higher requirements on the display quality of display panels. At present, the existing display panels have the phenomenon of uneven display brightness, presenting an uneven display visual effect, thereby reducing the display quality. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a scan driving circuit, an array substrate and a display panel.

[0004] Based on the above purpose, the present application provides a scan driving circuit, which includes:

[0005] n cascaded first shift register units and 2 cascaded second shift register units;

[0006] The output end of the first shift register unit of the i-th stage is connected to the first scan line signal line of the corresponding pixel row, and the third scan line signal line of the pixel row is connected to the output end of the first shift register of the i+2-th stage, wherein i=1…n, n is the number of the first shift register units (the number of the first shift register units is consistent with the number of pixel rows, so n is also called the number of pixel rows),

[0007] The third scan line signal line of the pixel row corresponding to the first shift register unit of the n-1th level is connected to the output end of the second shift register unit of the first level; the third scan line signal line corresponding to the pixel row of the first shift register unit of the nth level is connected to the output end of the second shift register unit of the second level, and the output end of the first-level second shift register unit and the output end of the second-level second shift register unit of the second level are respectively connected to the compensation module. The scan drive circuit is used in an integrated gate drive circuit (Scan N cascade circuit), which can improve the brightness difference caused by the inconsistency of the row load between the last row of pixels and the adjacent rows of pixels (i.e., the last 2 rows of pixels) when the last row of pixels cannot be compensated.

[0008] In one embodiment, the number of the first shift register units matches the number of the pixel rows, the output end of the first shift register unit of the first stage is connected to the first scan line signal line of the corresponding pixel row, and the third scan line signal line of the pixel row is connected to the output end of the first shift register of the third stage;

[0009] Preferably, each stage of the first shift register unit matches a corresponding pixel row.

[0010] In one embodiment, the compensation module includes a first compensation module and a second compensation module, the output end of the first-stage second shift register unit is connected to the first compensation module, and the output end of the second-stage second shift register unit is connected to the second compensation module;

[0011] Preferably, the first compensation module and the second compensation module have the same structure.

[0012] In one embodiment, the compensation module includes a virtual capacitor located in the non-display area;

[0013] Preferably, the capacitance of the virtual capacitor is equal to the capacitance of the total capacitance of the pixels in the first row or the last row of pixels, or the difference between them is within a threshold range; preferably, the threshold is between 3% and 15% (such as 3%, 5%, 10% or 15%);

[0014] Preferably, the number of the virtual capacitors is one or more, and the capacitance of their combination is equal to the capacitance of the total capacitance of the pixels in the pixel row in the first row or the last row, or the difference (the capacitance of the virtual capacitor and the capacitance of the total capacitance of the pixels in the first row or the last row) is within a threshold range; preferably, the threshold is between 3% and 15% (such as 3%, 5%, 7%, 9%, 10%, 13% or 15%) of the capacitance of the virtual capacitor;

[0015] In one embodiment, the compensation module includes a dummy pixel or a dummy pixel row located in a non-display area;

[0016] Preferably, the virtual pixel includes a first virtual pixel and a second virtual pixel, the output end of the first-stage second shift register unit is connected to the first virtual pixel, and the output end of the second-stage second shift register unit is connected to the second virtual pixel, or,

[0017] The virtual pixel row includes a first virtual pixel row and a second virtual pixel row, the output end of the first-stage second shift register unit is connected to the first virtual pixel row, and the output end of the second-stage second shift register unit is connected to the second virtual pixel row;

[0018] Preferably, the first virtual pixel row and the second virtual pixel row have the same structure;

[0019] Preferably, the first virtual pixel row and the second virtual pixel row have the same structure as the pixel row located in the display area.

[0020] In one embodiment, the first shift register unit is cascaded with the second shift register unit;

[0021] The first scan line signal line is electrically connected to the gate of the initialization transistor (fourth transistor) of the driving circuit matching the pixel row,

[0022] The third scan line signal line is electrically connected to a gate of a threshold compensation transistor (third transistor) of the driving circuit of a matching pixel row.

[0023] In one embodiment, the initialization transistor and the threshold compensation transistor are indium gallium zinc oxide thin film transistors (IGZO).

[0024] Based on the same inventive concept, the present application proposes an array substrate, which includes the above-mentioned driving circuit.

[0025] Based on the same inventive concept, the present application proposes a display panel, which includes the above-mentioned array substrate.

[0026] It comprises a display area and a non-display area at least partially surrounding the display area, and the compensation module is configured in the non-display area.

[0027] Compared with the prior art, the scan drive circuit provided in the present application includes a cascaded first shift register unit and a second shift register unit, the second shift register unit is electrically connected to a compensation module located in a non-display area (border area), and the scan signal connection lines of the gates of the third transistor and the fourth transistor of the driving circuit of the last two rows of pixels are connected to the compensation module in the non-display area (border area), so as to avoid the problem of uneven display brightness caused by inconsistent row loads of the last two rows of pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A functional module block diagram of a display panel according to an embodiment of the present application;

[0030] Figure 2 A schematic diagram of a pixel scanning driving circuit according to an embodiment of the present application;

[0031] Figure 3 A schematic diagram of a pixel scanning driving circuit according to another embodiment of the present application;

[0032] Figure 4 for Figure 3 A schematic diagram of the driving timing of the embodiment;

[0033] Figure 5 A schematic diagram of a display panel according to an embodiment of the present application;

[0034] Figure 6 is a schematic diagram of a scan driving circuit according to an embodiment of the present application;

[0035] Figure 7 FIG. 4 is a schematic diagram of a scan driving circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0037] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] With the development of display technology, integrated gate-driven OLED display panels have been widely used in smaller wearable products (such as smart watches). The applicant conducted further research on the architecture of the integrated gate driving circuit of this type of display panel and found that in the Scan N cascade circuit architecture (Scan N cascade circuit is used to control capacitor initialization) currently designed with GIP (gate in panel), at the opposite side of the driver chip (IC), where the signal ends, if the signal is ended directly, it will cause the load of the pixels in the last two rows to be different from the load of the pixels in the previous rows, resulting in the problem of brightness difference caused by the different loads of the pixels in the rows.

[0039] To this end, the applicant proposes a scanning driving circuit, an array substrate and a display panel. The display panel can improve the problem of brightness difference caused by different row loads.

[0040] like Figure 1 FIG. 1 is a schematic diagram of functional modules of a display panel according to an embodiment of the present application.

[0041] The display panel includes a display unit 100 , a scan driver 200 , an emission driver 300 , and a data driver 400 .

[0042] The display unit 100 includes a plurality of light emitting units, each of which includes a plurality of pixels (eg, red / green / blue pixels). The pixels are usually arranged in an array.

[0043] The scan driver 200 is configured to sequentially supply scan signals to pixels through scan lines based on a scan start signal. For example, the scan driver 200 receives a scan start signal, at least one clock signal, etc. from a timing controller (not shown). The scan driver 200 may be configured in a non-display area (border area) of the display panel (such as one side or two opposite sides of the border area). The scan driver is also called a scan drive circuit.

[0044] The data driver 400 receives a data control signal DCS and an image data signal RGB from a timing controller (not shown) and supplies a data signal (data voltage) to a pixel driving circuit through a data line based on the data control signal DCS and the image data signal RGB.

[0045] The timing controller may control driving of the scan driver 200, the emission driver 300 and the data driver 400 based on a timing signal supplied from the outside. The data control signal DCS for controlling the data driver 400 may include a source start signal, a source output enable signal, a source sampling clock signal and the like.

[0046] In one embodiment, the display panel further includes a power supply that generates a power voltage ELVSS and an initialization voltage based on a power control signal received from the timing controller and provides the generated voltages to the display unit 100 .

[0047] Figure 2 for Figure 1 Module schematic diagram of the driving circuit of the pixel of the light-emitting unit.

[0048] The pixel driving circuit comprises: a driving module, a data writing module, a threshold compensation module, an initialization module and a light emitting module.

[0049] The data writing module is used to write a data voltage (also called a data signal) to the control terminal of the driving module.

[0050] The driving module generates a driving current according to the voltage of the control terminal to drive the light-emitting module to emit light.

[0051] The control end of the initialization module is electrically connected to the first scan line, the first end is electrically connected to the first initialization signal line, and the second end is electrically connected to the control end of the driving module. The first end of the driving module is electrically connected to the second end of the data writing module, the first end of the data writing module is electrically connected to the data signal line to receive the data voltage (DATA signal), the control end of the data writing module is electrically connected to the second scan line to receive the data writing signal, the second end of the driving module is electrically connected to the first end of the threshold compensation module and the first end of the light-emitting module, the control end of the threshold compensation module is electrically connected to the second scan line, and the second end of the light-emitting module is electrically grounded / ELVSS.

[0052] The control end of the threshold compensation module is electrically connected to the second scan line, the first end of the threshold compensation module is electrically connected to the second end of the driving module, and the second end of the threshold compensation module is electrically connected to the control end of the driving module.

[0053] In this embodiment, a first initialization voltage VREFN1 is provided through a first initialization signal line, and a second initialization voltage VREFN2 is provided through a second initialization signal line.

[0054] Next, combine Figure 3 And refer to Figure 2 The pixel driving circuit provided by the embodiment of the present disclosure is described in detail.

[0055] The driving module includes a first transistor T1 (also called a driving transistor);

[0056] The data writing module includes a second transistor T2;

[0057] The threshold compensation module includes a capacitor C;

[0058] The first initialization module includes a third transistor T3 and a fourth transistor T4;

[0059] The second initialization module includes a seventh transistor T7 and an eighth transistor T8.

[0060] The storage capacitor module includes a storage capacitor Cst.

[0061] The gate of the first transistor T1 is electrically connected to the first end of the storage capacitor Cst and the second electrode of the third transistor T3. The first electrode of the third transistor T3 is electrically connected to the second electrode of the fourth transistor T4, the first electrode of the first transistor T1, the second electrode of the sixth transistor T6 and the first end of the capacitor C. The first electrode of the fourth transistor T4 is electrically connected to the first initialization signal line VERFN1.

[0062] The gate of the third transistor T3 is electrically connected to the third scan line S3.

[0063] The gate of the fourth transistor T4 is electrically connected to the first scan line S1.

[0064] The first electrode of the first transistor T1 is electrically connected to the second electrode of the sixth transistor T6 and the second electrode of the eighth transistor T8, the first electrode of the eighth transistor T8 is electrically connected to the initialization signal line VERFNP1, the gate of the eighth transistor T8 and the gate of the seventh transistor T7 are electrically connected to the fourth scan line S4, respectively, the first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line VERFN2 (for initializing the anode of the light emitting diode OLED), the second electrode of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode OLED, and the cathode of the organic light emitting diode OLED is electrically grounded / ELVSS.

[0065] The second electrode of the first transistor T1 is electrically connected to the second electrode of the fifth transistor T5 and the second electrode of the second transistor T2. The first electrode of the fifth transistor T5 is electrically connected to the second end of the storage capacitor Cst and the ELVDD end.

[0066] The first electrode of the second transistor T2 is electrically connected to the data voltage line (receives the data voltage DATA), and the gate of the second transistor T2 is electrically connected to the second scan line S2 and the second end of the capacitor C.

[0067] The gate of the sixth transistor T6 is electrically connected to the gate of the fifth transistor T5 and the emission control terminal to receive the emission control signal EM. In this embodiment, the driving circuit adopts an 8T1C circuit, and in other embodiments, a 7T1C circuit or a 7T2C circuit can be adopted. In this embodiment, the third transistor T3 and the fourth transistor T4 can adopt indium gallium zinc oxide (IGZO) thin film transistors, and other transistors can adopt low temperature polysilicon (LTPS) thin film transistors.

[0068] Next, combine Figure 4 To describe the driving timing (ie, driving process) of the driving circuit of the pixel, the operation of the pixel driving circuit includes an initialization phase, a data writing phase, and a light emitting phase.

[0069] In stage t1 (also called the initialization stage), the first scan line S1 is at a high level, the third scan line S3 is at a high level, the fourth transistor T4 and the third transistor T3 are turned on, and the gate of the first transistor T1 is initialized to the Vref potential, which facilitates the subsequent data voltage Vdata to be charged into the storage capacitor Cst.

[0070] In the t2 stage (data writing stage), the third scan line S3 is at a high level, the third transistor T3 is turned on / conducted, the second scan line S2 is at a low level, the second transistor T2 is turned on / conducted, the gate of the first transistor T1 is at a low potential of Vref, the first transistor T1 is turned on, and the potential of the gate of the first transistor T1 continues to rise. When the voltage Vgs between the gate and source of the first transistor T1 increases to 2Vth, the first transistor T1 is turned off. At this time, the voltage of the first transistor T1 is Vdata-Vth. At the same time (in the t2 stage, the anode of the organic light emitting diode OLED is initialized), the fourth scan line S4 is at a low level, the seventh transistor T7 and the eighth transistor T8 are turned on respectively, and the anode of the organic light emitting diode OLED is initialized to Vref. Through such a design, the residual charge of the previous frame can be cleared, which is beneficial to improving the contrast of the display screen.

[0071] In the t3 stage (OLED light emitting stage), the EM signal of the emission driver 300 is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on / on respectively, and the current flowing through the organic light emitting diode OLED is equal to the turn-on threshold voltage V of the first transistor T1. th No matter, that is, V th is compensated until the next scan.

[0072] The present application embodiment provides a display panel, such as Figure 5 As shown, the display panel 100 includes a display area 110 and a non-display area 120 surrounding the display area, and a plurality of light-emitting units 111 are arranged in the display area 110, such as the light-emitting units 111 are arranged in an array. The non-display area includes a border area, and the border area is provided with a compensation module, and the compensation module is configured to be close to the first row / last row of light-emitting units of the display area adjacent to the border area. Preferably, the border area includes an upper border area 121, and a compensation module is provided in the upper border area 121. Preferably, the non-display area also includes a binding area, through which a control module is bound, and a preset pattern is displayed in the display area based on the control of the control module.

[0073] In one embodiment, a dummy pixel or a dummy pixel row (including a plurality of dummy pixels) is provided in a border area (such as an upper border), and the dummy pixel is electrically isolated from the pixel in the light-emitting unit of the display area (that is, the dummy pixel is not connected to the pixel in the light-emitting unit of the display area). The dummy pixel may include a dummy red / green / blue pixel. The configuration of the dummy pixel may be the same as the pixel in the first row (the first row) of the light-emitting unit, except that the dummy pixel does not emit light. The dummy pixel row may be configured in the same structure as the pixel row in the display area, and the dummy pixel does not emit light when working (such as the dummy pixel is not provided with an organic light-emitting diode OLED).

[0074] In one embodiment, a dummy capacitor is provided in the border area. Preferably, the capacitance of the dummy capacitor is the same as the capacitance of the total capacitance of the pixels in the first row (the first row) or the last row of pixels, or the difference is within the range of a preset threshold value (the threshold is between 3% and 15%, such as the threshold is selected from 3%, 5%, 10%, 11%, 12%, 13%, 14% or 15%). The number of the dummy capacitors may be one or more, and the capacitance of their combination is the same as the capacitance of the total capacitance of the pixels in the first row (the first row) of pixels, or the difference is within the range of a preset threshold value (the threshold is between 3% and 15%, such as the threshold is selected from 3%, 5%, 10%, 11%, 12%, 13%, 14% or 15%).

[0075] like Figure 6 FIG. 1 is a topological diagram of a scan driving circuit according to an embodiment of the present application, and is described by taking four first shift register units (matching and connecting four rows of pixels) as an example.

[0076] The scan driver includes four cascaded first shift register units 210 and two second shift register units 220. One of the two second shift register units 220 is cascaded with the first shift register unit 210, and is called the first-stage second shift register unit (also called the compensation stage 1), and the other is called the second-stage second shift register unit (also called the compensation stage 2). Each stage of the first shift register unit 210 is matched with a corresponding pixel row, and the pixel row is located in the display area (the number of pixel rows is the same as the number of the first shift register units 210). The two second shift register units 220 and the corresponding virtual pixel rows (see Figure 6 In a) in the border area, NVGH in the first shift register unit 210 provides a high level signal, NVGL provides a low level signal, and RST provides a reset signal.

[0077] The output end of the first-stage first shift register unit 210 is connected to the first scan line signal line S1 of the first-stage / 1st-row pixel row (the first scan line signal line S1 is electrically connected to the gate of the fourth transistor of the driving circuit of the corresponding pixel row to transmit a signal thereto).

[0078] The output end of the first shift register unit 210 of the second stage is connected to the first scan line signal line S1 of the second stage / 2nd row of pixels (the first scan line signal line S1 is electrically connected to the gate of the fourth transistor of the driving circuit of the corresponding pixel row to transmit a signal thereto).

[0079] The output end of the first shift register unit 210 of the third stage is connected to the first scan line signal line S1 of the third stage / 3rd pixel row (the first scan line signal line S1 is electrically connected to the gate of the fourth transistor of the pixel driving circuit in the row to transmit a signal thereto).

[0080] The output end of the first shift register unit 210 of the fourth stage is connected to the first scan line signal line S1 of the fourth stage / 4th pixel row (the first scan line signal line S1 is electrically connected to the gate of the fourth transistor of the driving circuit of the corresponding pixel row to transmit a signal thereto).

[0081] And the output end of the first shift register unit 210 of the third stage is connected to the third scan line S3 of the corresponding row of the first shift register unit 210 of the first stage (the third scan line S3 is electrically connected to the gate of the third transistor of the pixel driving circuit in the row), that is, the transmission signal line S3 of the first pixel row is cascaded to the output end of the first shift register unit 210 of the third stage. The third transistor is also called a threshold compensation transistor. The fourth transistor is also called an initialization transistor.

[0082] The output end of the first shift register unit 210 of the fourth stage is connected to the third scan line S3 of the second stage / second row of pixel rows (the third scan line S3 is electrically connected to the gate of the third transistor of the driving circuit of the pixel row), that is, the third scan line S3 of the second row of pixel rows is cascaded to the output end of the first shift register unit 210 of the fourth stage.

[0083] The third scan line S3 of the pixel row corresponding to the third-stage first shift register unit 210 is connected to the output end of the first-stage second shift register unit (also called compensation stage 1), and the output end of the first-stage second shift register unit is connected to the first virtual pixel row.

[0084] The third scan line S3 of the pixel row corresponding to the first shift register unit 210 of the fourth stage is connected to the output end of the second shift register unit of the second stage (also called compensation stage 2), the output end of the second shift register unit of the first stage is connected to the first virtual pixel row, and the output end of the second shift register unit of the second stage is connected to the second virtual pixel row. Through such a design, it is avoided that when the last row of pixels cannot be compensated, the brightness difference caused by the inconsistency of the row load with the adjacent row pixels (i.e., the last two rows of pixels) is avoided. In this embodiment, the combination of two first shift register units 210 constitutes a GIP driving unit (such as the combination of the first shift register unit of the first stage and the first shift register unit of the second stage constitutes one GIP driving unit, and the combination of the third shift register unit and the fourth first shift register unit constitutes one GIP driving unit).

[0085] As Figure 6 Variations of the embodiments, such as Figure 7 FIG. 1 is a topological diagram of a scan driving circuit according to an embodiment of the present application.

[0086] The scan driver includes n cascaded first shift register units 210 and two second shift register units 220 (i.e., n cascaded first shift register units match and connect n rows of pixels, where n is a natural number, such as n is selected from 128, 256, 512, 720, 1024, 1080, 2160, 4320, etc., depending on the resolution of the display panel).

[0087] The number of the first shift register units corresponds to the matching of the pixel rows (e.g., the display area includes i rows of pixel rows, i=1…n, n is the number of the first shift register units and the number of pixel rows). Each row of pixel rows is matched with a first shift register unit 210, that is, it includes i-level first shift register units 210 matching the corresponding i-th row of pixel rows.

[0088] The output end of the first shift register unit of the i-th stage is connected to the first scan line signal line S1 corresponding to the pixel row of the current stage (i.e., the i-th row), and the third scan line signal line S3 corresponding to the pixel row of the i-th row is connected to the output end of the first shift register of the i+2-th stage. The first scan line signal line is used to provide a first scan line signal, and the third scan line signal line is used to provide a third scan line signal. The first scan line signal line S1 is electrically connected to the gate of the fourth transistor T4 of the driving circuit of the matching pixel row (refer to Figure 3 ), the third scan line signal line S3 is electrically connected to the gate of the third transistor T3 of the driving circuit of the matching pixel row (reference Figure 3 ). The third transistor T3 and the fourth transistor T4 are IGZO transistors.

[0089] The third scan line signal line of the pixel row corresponding to the first shift register unit 210 of the n-1th level is connected to the output end of the first second shift register unit (compensation level 1), the third scan line signal line corresponding to the pixel row of the first shift register unit 210 of the nth level is connected to the output end of the second second shift register unit (compensation level 2), the output end of the first second shift register unit is connected to the first virtual pixel row, and the output end of the second second shift register unit is connected to the second virtual pixel row. The first virtual pixel row and the second virtual pixel row are collectively referred to as virtual pixel rows. The virtual pixel row provides a compensation signal (i.e., serves as a compensation module).

[0090] The second shift register unit 220 is cascaded with the first shift register unit 210, and the second shift register unit 220 is electrically connected to the virtual pixels in the border area. One of the two second shift register units 220 is cascaded with the first shift register unit 210, and is called the first-stage second shift register unit (also called the compensation stage 1), and the other is called the second-stage second shift register unit (also called the compensation stage 2). The two second shift register units 220 and the corresponding virtual pixel rows (see Figure 7a) is located in the border area. This design connects the cascade connection to the virtual pixel located in the border area (i.e., used to provide load compensation), which avoids the brightness difference caused by the load inconsistency between the last row of pixels and the adjacent pixel rows (i.e., the last two rows of pixels) when the pixels cannot be compensated by the normal compensation module. The simulation verifies that the current difference between adjacent pixel rows in this way is about 1.85%, and there is almost no brightness difference.

[0091] As Figure 6 A variation of the implementation method, the second shift register unit 220 is electrically connected to a virtual capacitor in the border area (the capacitance of the virtual capacitor is equal to or approximately equal to the capacitance of the total capacitance of the pixel rows in the light-emitting units of the adjacent i rows) to avoid brightness differences caused by different loads. Simulation has verified that the capacitance difference between adjacent rows under the implementation method proposed in the present application is 0.75pf, and there is almost no brightness difference.

[0092] Although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0093] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0094] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A scanning driving circuit, characterized in that: include: n cascaded first shift register units and 2 cascaded second shift register units; The output end of the first shift register unit of the i-th stage is connected to the first scan line signal line of the corresponding pixel row, and the third scan line signal line of the pixel row is connected to the output end of the first shift register of the i+2-th stage, wherein i=1…n, and n is the number of the first shift register units; The third scan line signal line of the pixel row corresponding to the first shift register unit of the n-1th stage is connected to the output end of the second shift register unit of the first stage; The third scan line signal line corresponding to the pixel row of the first shift register unit of the nth stage is connected to the output end of the second shift register unit of the second stage, The output end of the first-stage second shift register unit and the output end of the second-stage second shift register unit are respectively connected to the compensation module.

2. The scanning driving circuit according to claim 1, characterized in that: The number of the first shift register units matches the number of the pixel rows, the output end of the first shift register unit of the first stage is connected to the first scan line signal line of the corresponding pixel row, and the third scan line signal line of the pixel row is connected to the output end of the first shift register of the third stage; Preferably, each stage of the first shift register unit matches a corresponding pixel row.

3. The scanning driving circuit according to claim 2, characterized in that: The compensation module includes a first compensation module and a second compensation module, the output end of the first-stage second shift register unit is connected to the first compensation module, and the output end of the second-stage second shift register unit is connected to the second compensation module; Preferably, the first compensation module and the second compensation module have the same structure.

4. The scanning driving circuit according to claim 1, wherein: The compensation module includes a virtual capacitor, and the virtual capacitor is located in the non-display area; Preferably, the difference between the capacitance of the virtual capacitor and the capacitance of the total capacitance of the pixels in the first row or the last row of pixels is within a threshold range; Preferably, the number of the virtual capacitors is one or more, and the difference between the capacitance of the virtual capacitor combination and the capacitance of the total capacitance of the pixels in the pixel row in the first row or the last row is within a threshold range; Preferably, the threshold is between 3% and 15% of the capacitance of the virtual capacitor.

5. The scanning driving circuit according to claim 1, wherein: The compensation module includes a virtual pixel or a virtual pixel row, and the virtual pixel or the virtual pixel row is located in a non-display area; Preferably, the virtual pixel includes a first virtual pixel and a second virtual pixel, the output end of the first-stage second shift register unit is connected to the first virtual pixel, and the output end of the second-stage second shift register unit is connected to the second virtual pixel, or, The virtual pixel row includes a first virtual pixel row and a second virtual pixel row, the output end of the first-stage second shift register unit is connected to the first virtual pixel row, and the output end of the second-stage second shift register unit is connected to the second virtual pixel row; Preferably, the first virtual pixel row and the second virtual pixel row have the same structure; Preferably, the first virtual pixel row and the second virtual pixel row have the same structure as the pixel row located in the display area.

6. The scanning driving circuit according to claim 1, characterized in that: The first shift register unit is cascade-connected to the second shift register unit; The first scan line signal line is electrically connected to the gate of the initialization transistor of the driving circuit of the matching pixel row, The third scan line signal line is electrically connected to a gate of a threshold compensation transistor of the driving circuit of a matching pixel row.

7. The scanning driving circuit according to claim 6, characterized in that: The initialization transistor and the threshold compensation transistor are indium gallium zinc oxide thin film transistors.

8. An array substrate, characterized in that: The invention comprises the scan driving circuit as claimed in any one of claims 1 to 7.

9. A display panel, characterized in that: Comprising the array substrate as claimed in claim 8.

10. The display panel according to claim 9, wherein: It comprises a display area and a non-display area at least partially surrounding the display area, and the compensation module is configured in the non-display area.

Images