Display device and driving method of display panel

Abstract

The invention provides a display device and a driving method of a display panel, the display device comprises the display panel, the display panel comprises M scanning lines, N data lines and M rows of pixel units, and the M scanning lines are used for scanning the M rows of pixel units line by line according to a preset time sequence. And a scanning gap is formed between the scanning ending moment of the previous scanning line and the scanning starting moment of the next scanning line in any two adjacent scanning lines. The display device further comprises Q switch modules. Each switch module comprises a first connecting end and a second connecting end, the first connecting end is used for receiving actual target gray-scale voltage, and the second connecting end is electrically connected to the corresponding data line. And each switch module is switched on during the scanning period of any scanning line so as to output the received actual target gray-scale voltage to the corresponding data line, and is switched off during at least part of the period of each scanning gap. The display device can avoid the problem of horizontal bright and dark lines.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and a driving method for a display panel. Background Art

[0002] The basic principle of LCD (Liquid Crystal Display) panel display is to control the rotation angle of the liquid crystal by controlling the electric field strength applied to the liquid crystal, so as to change the light flux passing through the liquid crystal to achieve the display of different grayscales, and to achieve the display of various colors by matching the RGB color resistance ratio. Among them, the electric field applied to the liquid crystal is provided by the storage capacitor and the liquid crystal capacitor that write the actual target grayscale voltage through the data line. However, due to the increasing refresh rate and resolution of the current panel, the time for charging the capacitor (storage capacitor and liquid crystal capacitor) is also getting shorter and shorter, and there is parasitic capacitance in the routing of the data line in the panel. Therefore, when the grayscale switching is large, it is easy to cause the problem of insufficient charging of the storage capacitor and the liquid crystal capacitor, resulting in horizontal bright and dark lines.

[0003] The basic principle of OLED (Organic Light-Emitting Diode) panel display is to charge the storage capacitor. The voltage on the storage capacitor determines the current flowing through a single OLED and thus determines its brightness. The three colors of RGB OLED are combined to achieve the display of various colors. Similarly, high-resolution and high-refresh OLED panels, like LCD panels, will also face the problem of horizontal bright and dark lines caused by insufficient charging due to parasitic capacitance. Summary of the invention

[0004] In view of this, the main purpose of the present application is to propose a display device and a driving method for a display panel, aiming to solve the problem of horizontal bright and dark lines caused by insufficient charging due to parasitic capacitance in existing display panels.

[0005] To achieve the above-mentioned purpose, a first aspect of the present application provides a display device, the display device comprising a display panel, the display panel comprising M scan lines, N data lines and M rows of pixel units, the M scan lines extending in the row direction and arranged in the column direction, the N data lines extending in the column direction and arranged in the row direction, the M rows of pixel units arranged in an array and located at the intersection of the M scan lines and the N data lines, the M scan lines are used to scan the M rows of pixel units row by row according to a preset timing; wherein M and N are both positive integers, and the scanning end time of the previous scan line of any two adjacent scan lines is the same as the scanning end time of the next scan line The scanning start time of each scan line is separated by a scanning gap; the display device also includes Q switch modules, wherein Q is a positive integer, and Q is less than or equal to N; each of the switch modules corresponds to a data line, and each of the switch modules includes a first connection end and a second connection end, the first connection end is used to receive the actual target grayscale voltage, and the second connection end is electrically connected to the corresponding data line; each of the switch modules is turned on during a period when any scan line is scanned to output the received actual target grayscale voltage to the corresponding data line, and is turned off during at least part of each scanning gap to stop outputting the actual target grayscale voltage to the corresponding data line.

[0006] The display device provided by the present application, by setting a switch module electrically connected to the input end of the data line, controls the switch module to be turned on during a period when any scanning line is scanned, so as to output the corresponding target grayscale voltage to the data line through the turned-on switch module, and controls the switch module to be turned off during at least a part of the period of each scanning interval, so as to stop outputting the voltage to the data line. In this way, the switch module cuts off the data line during at least a part of the period after the previous row of pixel units is charged and before the current row of pixel units is charged, which can eliminate the influence of the actual target grayscale voltage of the previous row of pixel units on the current row of pixel units, thereby ensuring that the current row of pixel units can be charged to the corresponding actual target grayscale voltage, and avoiding the problem of horizontal bright and dark lines on the display panel.

[0007] In some embodiments, Q is equal to N, and the Q switch modules correspond to the N data lines one by one.

[0008] In some embodiments, the display device further includes a timing control module, which is used to output a switch control signal to control each of the switch modules to be turned on during a period when any scan line is scanned, and to be turned off during at least part of each scan interval.

[0009] In some embodiments, the display device also includes a column driving module, which is located on one side of the display panel in the column direction; the N switch modules are all arranged in the display panel and connected between the column driving module and the corresponding data lines; the column driving module is electrically connected to the first connection end of each of the switch modules, and is used to output the corresponding actual target grayscale voltage to the first connection end of each of the switch modules.

[0010] In some embodiments, each of the switch modules further includes a control end; the display device further includes a level conversion module, which is electrically connected to the timing control module and the control end of each of the switch modules, and is used to receive a switch control signal output by the timing control module, and to perform level conversion on the switch control signal, and to output the switch control signal after the level conversion to the control end of each of the switch modules, so as to control each of the switch modules to be turned on during the period when any scan line is scanned, and to be turned off during at least part of each scan interval.

[0011] In some embodiments, the display device further includes a column driving module, which is located on one side of the display panel in the column direction; the N switch modules are arranged in the column driving module, and the column driving module further includes N output stage circuits corresponding to the N switch modules one by one, each of the output stage circuits is electrically connected to the first connection end of the corresponding switch module, and is used to output the corresponding actual target grayscale voltage to the first connection end of the corresponding switch module; each of the switch modules also includes a control end for receiving the switch control signal, and each of the switch modules is turned on during the period of scanning any scan line in response to the switch control signal, and is turned off during at least part of the period of each scan gap.

[0012] In some embodiments, the timing control module is also used to receive an image signal, and determine the initial target grayscale voltage of each pixel unit according to the image signal, and determine the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column according to the relationship between the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column; wherein 2≤i≤M, 1≤j≤N.

[0013] In some embodiments, the timing control module is specifically used to increase the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column when the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column is higher than the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column; and to reduce the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column when the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column is lower than the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column.

[0014] The second aspect of the present application also provides a method for driving a display panel, wherein the display panel comprises M scan lines, N data lines and M rows of pixel units, wherein the M scan lines extend in a row direction and are arranged in a column direction, wherein the N data lines extend in a column direction and are arranged in a row direction, wherein the M rows of pixel units are arranged in an array and are located at intersections of the M scan lines and the N data lines, wherein the M scan lines are used to scan the M rows of pixel units row by row according to a preset timing sequence, wherein the driving method comprises: receiving an image signal, and determining an initial position of each pixel unit according to the image signal; target grayscale voltage; and, determining the actual target grayscale voltage of the pixel unit located at the i-th row and j-th column according to the relationship between the initial target grayscale voltage of the pixel unit located at the i-1th row and j-th column and the initial target grayscale voltage of the pixel unit located at the i-2th row and j-th column, and the relationship between the initial target grayscale voltage of the pixel unit located at the i-th row and j-th column and the initial target grayscale voltage of the pixel unit located at the i-1th row and j-th column; wherein the actual target grayscale voltage of each pixel unit is used to drive the pixel unit to display, 3≤i≤M, 1≤j≤N.

[0015] In some embodiments, the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column is determined according to the size relationship between the initial target grayscale voltage of the pixel unit located in the i-1th row and j-th column and the initial target grayscale voltage of the pixel unit located in the i-2th row and j-th column, and the size relationship between the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit located in the i-1th row and j-th column, including: when a first difference obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-2th row and j-th column from the initial target grayscale voltage of the pixel unit located in the i-1th row and j-th column is greater than a first preset threshold value, and a second difference obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column from the initial target grayscale voltage of the pixel unit located in the i-1th row and j-th column is less than or equal to zero and greater than a second preset threshold value, reducing The actual target grayscale voltage of the pixel unit located in the i-th row and j-th column is obtained by taking the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column into consideration; wherein the first preset threshold value is greater than zero and the second preset threshold value is less than zero; and when a first difference value obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-2-th row and j-th column from the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column is less than a third preset threshold value, and a second difference value obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column from the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column is greater than or equal to zero and less than a fourth preset threshold value, the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column is increased to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column; wherein the third preset threshold value is less than zero and the fourth preset threshold value is greater than zero.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a pixel unit in an LCD display panel provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the structure of a pixel unit in an OLED display panel provided in an embodiment of the present application;

[0019] Figure 3 A first driving signal timing diagram of a display panel provided in an embodiment of the present application;

[0020] Figure 4 A second driving signal timing diagram of a display panel provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0022] Figure 6 A third driving signal timing diagram of the display panel provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of the structure of a column driver module provided in an embodiment of the present application;

[0024] Figure 8 A flowchart of a method for driving a display panel provided in an embodiment of the present application;

[0025] Fig. 9 This is a fourth driving signal timing diagram of the display panel provided in an embodiment of the present application.

[0026] The following are the descriptions of the reference numerals:

[0027] Display device 1

[0028] Display panel 100

[0029] Column driver module 21

[0030] Timing control module 22

[0031] Level conversion module 23

[0032] Data line 102

[0033] Scan Line 101

[0034] Pixel units P1, P2, P

[0035] Transistors T11, T12, T13

[0036] Pixel electrode 11

[0037] The first common electrode 12

[0038] The second common electrode 13

[0039] Liquid crystal capacitance Clc

[0040] Storage capacitor Cst

[0041] Switch module 10

[0042] Switch control signal TTL, TTL1

[0043] Output stage circuit 211

[0044] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] In addition, the terms "first", "second", etc. in the specification of the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0048] See also Figure 1 , Figure 1 Schematic diagram of the structure of a pixel unit in an LCD display panel in the related art. In an LCD display panel, a pixel unit P1 generally includes a pixel electrode 11, a first common electrode 12, a second common electrode 13 and a transistor T11.

[0049] The first common electrode 12 is used to receive a first common voltage Vcom1 (also called a color film substrate side common voltage V CF_COM ), the second common electrode 13 is used to receive the second common voltage Vcom2 (also called the array substrate side common voltage V A_COM The transistor T11 includes a control terminal, a first connection terminal and a second connection terminal. The control terminal of the transistor T11 is used to be electrically connected to a corresponding scan line 101 to receive a corresponding scan signal. The first connection terminal of the transistor T11 is used to be electrically connected to a corresponding data line 102 to receive a corresponding data voltage Vdata (also called grayscale voltage). The first common electrode 12 and the pixel electrode 11 are relatively spaced apart to form a liquid crystal capacitor Clc. The second common electrode 13 and the pixel electrode 11 are relatively spaced apart to form a storage capacitor Cst.

[0050] When working, the transistor T1 is turned on when the received scanning signal is a turn-on voltage, thereby writing the data voltage Vdata provided by the data line 102 into the pixel electrode 11, so that there is a voltage difference between the pixel electrode 11 and the first common electrode 12 and an electric field is generated, thereby driving the liquid crystal molecules between the pixel electrode 11 and the first common electrode 12 to deflect, so that the pixel unit P1 displays the gray scale corresponding to the data voltage Vdata.

[0051] However, as the refresh rate and resolution of the current panel are getting higher and higher, the time for charging the storage capacitor Cst and the liquid crystal capacitor Clc is getting shorter and shorter, and there is parasitic capacitance in the routing of the data line 102 in the panel. Therefore, when the grayscale switching is large, the storage capacitor and the liquid crystal capacitor are easily undercharged, causing the problem of horizontal bright and dark lines.

[0052] See also Figure 2 , Figure 2 Schematic diagram of the structure of a pixel unit in an OLED display panel in the related art. In an OLED display panel, a pixel unit P2 generally includes a transistor T12, a transistor T13, a storage capacitor Cst and a light emitting device OLED.

[0053] The cathode of the light emitting device OLED is electrically connected to the reference voltage terminal VSS to receive the reference voltage VSS, the anode of the light emitting device OLED is electrically connected to the source of the transistor T13, the drain of the transistor T13 is used to receive the driving voltage VDD, the gate of the transistor T13 is electrically connected to the source of the transistor T12, the drain of the transistor T12 is used to be electrically connected to a corresponding data line 102 to receive the corresponding data voltage Vdata, and the gate of the transistor T12 is used to be electrically connected to a corresponding scan line 101 to receive the corresponding scan signal. The first end of the storage capacitor Cst is electrically connected to the gate of the transistor T13, and the second end of the storage capacitor Cst is electrically connected to the drain of the transistor T13. Exemplarily, the transistor T12 is turned on when receiving the scanning signal, and the data voltage Vdata on the data line 102 charges the storage capacitor Cst through the transistor T11 to adjust the voltage of the first end of the storage capacitor Cst to the data voltage Vdata. The transistor T13 drives the light-emitting device OLED to emit light based on the data voltage Vdata received by its gate. At this time, the gate-source voltage Vgs of the transistor T13 is Vg-Vs=Vdata-Voled, where Voled is the conduction voltage between the anode and cathode of the light-emitting device OLED and the light-emitting device OLED2 when emitting light. The driving current Ids flowing through the transistor T13 and the gate-source voltage Vgs of the transistor T13 have the following relationship:

[0054] Ids=(K / 2)(Vgs-Vth) 2 =(K / 2)(Vdata-Voled-Vth) 2

[0055] Wherein, K=Cox×μ×W / L, Cox is the gate capacitance per unit area; μ is the mobility of channel electrons; W / L is the width-to-length ratio of the channel of the transistor T13; and Vth is the threshold voltage of the transistor T13.

[0056] Similarly, for OLED display panels, as the refresh rate and resolution of the panels are getting higher and higher, the time for charging the storage capacitor Cst is getting shorter and shorter, and there is parasitic capacitance in the routing of the data line 102 in the panel. Therefore, when the grayscale switching is large, the storage capacitor Cst is prone to insufficient charging, causing the problem of horizontal bright and dark lines.

[0057] See also Figure 3 , Figure 3 The first driving signal timing diagram of the display panel provided in the embodiment of the present application. In order to solve the problem that horizontal bright and dark lines are prone to appear in the existing display panel, the related art proposes a Line OD (LineOver Drive) algorithm, which is a Source Driver IC (source driver chip) that compares the difference between the initial target grayscale voltage of the previous line and the current line, corrects the initial target grayscale voltage of the current line (increases / lowers the initial target grayscale voltage), obtains the corrected target grayscale voltage, and outputs the corrected target grayscale voltage to drive the display panel for display.

[0058] Specifically, Figure 3 As shown, taking the grayscale voltage on the j-th column data line as an example, assuming that the initial target grayscale voltages of the pixel units located in the j-th column and the i-2th to i+1th rows are Dj_i-2, Dj_i-1, Dj_i and Dj_i+1 respectively, since the parasitic capacitance on the j-th column data line will cause the grayscale voltage delay, therefore, when the difference between the grayscale voltages between rows is large, if the initial target grayscale voltages Dj_i-2 to Dj_i+1 are output to the j-th column data line in sequence, it may happen that at the end of the scanning line scanning, the grayscale voltage on the j-th column data line cannot reach the corresponding initial target grayscale voltage, resulting in pixel units in different rows not being bright enough or dark enough. When several rows continuously display similar grayscales, the following rows can reach the initial target grayscale voltage, thereby forming a problem of displaying bright and dark lines.

[0059] The Line OD algorithm compares Dj_i-2 and Dj_i-1 to obtain that Dj_i-1 is greater than Dj_i-2 and the difference between the two is large, thereby increasing Dj_i-1 to obtain the corrected target grayscale voltage Dj_i-1' of the pixel unit located in the jth column and the i-1th row, which can ensure that the storage capacitor in the pixel unit located in the jth column and the i-1th row can be charged to Dj_i-1 at the end of the scan line scan of the i-1th row; The Line OD algorithm compares Dj_i-1 and Dj_i to obtain that Dj_i is less than Dj_i-1 and the difference between the two is large, thereby reducing Dj_i to obtain the corrected target grayscale voltage Dj_i' of the pixel unit located in the jth column and the i-th row, which can ensure that the storage capacitor in the pixel unit located in the jth column and the i-th row can be charged to Dj_i at the end of the scan line scan of the i-1th row; Line The OD algorithm compares Dj_i and Dj_i+1 and concludes that Dj_i+1 is greater than Dj_i and the difference between the two is large, thereby increasing Dj_i+1 to obtain the corrected target grayscale voltage Dj_i+1' of the pixel unit located in the jth column and the i-th row, which can ensure that when the scan line of the i+1th row ends, the storage capacitor in the pixel unit located in the jth column and the i+1th row can be charged to Dj_i+1.

[0060] However, there is a problem with the line OD algorithm: Figure 4 As shown, assuming that the initial target grayscale voltages of the pixel units located in the jth column and the i-2th to i+1th rows are Dj_i-2, Dj_i-1, Dj_i and Dj_i+1 respectively, Dj_i-1=Dj_i=Dj_i+1>Dj_i-2, the line OD algorithm compares Dj_i-2 and Dj_i-1 to obtain that Dj_i-1 is greater than Dj_i-2 and the difference between the two is large, thereby increasing Dj_i-1 to obtain the corrected target grayscale voltage Dj_i-1' of the pixel unit located in the jth column and the i-1th row, which can ensure that when the scan line of the i-1th row is finished, the storage capacitor in the pixel unit located in the jth column and the i-1th row can be charged to Dj_i-1. After the scan line of the i-1th row is finished and before the scan line of the i-1th row is turned on, the voltage output by the Source Driver IC to the data line of the jth column is still Dj_i-1'. Thus, when the charging of the i-1th row is finished, the voltage on the jth data line will continue to rise to be greater than Dj_i-1. However, since Dj_i-1 = Dj_i = Dj_i+1, the line OD algorithm will not modify Dj_i and Dj_i+1. Therefore, when the i-th row scan line starts scanning, due to the parasitic capacitance of the data line, the Dj_i-1 output by the Source Driver IC is not enough to pull back the voltage stored on the data line. Figure 4As shown, at the end of the scan of the i-th row scan line, the voltage on the j-th column data line cannot return to the initial target grayscale voltage Dj_i, so that the storage capacitor in the pixel unit located in the j-th column and the i-1-th row will be charged to a level higher than its initial target grayscale voltage Dj_i, so that the i-th row pixel unit will appear as a bright line.

[0061] In order to solve the problem of horizontal bright and dark lines caused by insufficient charging due to parasitic capacitance in existing display panels, the present application provides a display device 1, see Figure 5 , Figure 5 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0062] like Figure 5 As shown, the display device 1 includes a display panel 100, and the display panel 100 includes M scan lines 101, N data lines 102 and M rows of pixel units P, the M scan lines 101 extend along the row direction and are arranged along the column direction, the N data lines 102 extend along the column direction and are arranged along the row direction, and the M rows of pixel units P are arranged in an array and are located at the intersection of the M scan lines 101 and the N data lines 102.

[0063] The M scan lines 101 are used to scan the M rows of pixel units P row by row according to a preset timing sequence. Wherein, M and N are both positive integers, and there is a scanning gap between the scanning end time of the previous scan line 101 and the scanning start time of the next scan line 101 of any two adjacent scan lines 101.

[0064] The display device 1 further includes Q switch modules 10, where Q is a positive integer, and Q is less than or equal to N. Each of the switch modules 10 corresponds to a data line 102, and each of the switch modules 10 includes a first connection end and a second connection end, wherein the first connection end is used to receive an actual target grayscale voltage, and the second connection end is electrically connected to the corresponding data line 102. Each of the switch modules 10 is turned on during a period when any scanning line 101 is scanned, so as to output the received actual target grayscale voltage to the corresponding data line 102, and is turned off during at least a part of a period of each scanning gap, so as to stop outputting the actual target grayscale voltage to the corresponding data line 102.

[0065] The display device 1 provided in the present application is provided with a switch module 10 electrically connected to the input end of the data line 102, and controls the switch module 10 to be turned on during a period when any scanning line 101 is scanned, so as to output the corresponding target grayscale voltage to the data line 102 through the turned-on switch module 10, and controls the switch module 10 to be turned off during at least a part of the period of each scanning interval, so as to stop outputting the voltage to the data line 102. In this way, the switch module 10 cuts off the data line 102 during at least a part of the period after the previous row of pixel units P is charged and before the current row of pixel units P is charged, which can eliminate the influence of the actual target grayscale voltage of the previous row of pixel units P on the current row of pixel units P, thereby ensuring that the current row of pixel units P can be charged to the corresponding actual target grayscale voltage, and avoiding the problem of horizontal bright and dark lines in the display panel 100.

[0066] Exemplarily, the switch module 10 includes but is not limited to switch tubes such as thin film transistor (TFT), triode, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and the like.

[0067] In some embodiments, Q is equal to N, and the Q switch modules 10 correspond to the N data lines 102 one by one.

[0068] It should be noted that when the switch module 10 is provided for each column of data lines 102, it can be ensured that each pixel unit P in each column of pixel units P will not be affected by the actual target grayscale voltage of the previous pixel unit P when charging, and the display effect of the display device 1 is better. Of course, in other embodiments, in order to save costs, the switch module 10 can also be provided only for some data lines 102.

[0069] In some embodiments, the timing control module 22 is further used to receive an image signal, and determine the initial target grayscale voltage of each pixel unit P according to the image signal, and determine the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column according to the magnitude relationship between the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the i-1-th row and j-th column. Wherein, 2≤i≤M, 1≤j≤N. Wherein, the actual target grayscale voltage of the pixel unit P in the first row may be the initial target grayscale voltage.

[0070] Further, the timing control module 22 is specifically used to increase the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column when the initial target grayscale voltage of the pixel unit P located in the i-1-th row and j-th column is higher than the initial target grayscale voltage of the pixel unit P located in the i-1-th row and j-th column; and to reduce the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column when the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column is lower than the initial target grayscale voltage of the pixel unit P located in the i-1-th row and j-th column.

[0071] For example, see Figure 6 , Figure 6 The third driving signal timing diagram of the display panel provided by the embodiment of the present application. Taking the data line 102 of the jth column as an example, assuming that the initial target grayscale voltages of the pixel units P located in the jth column and the i-2th to i+1th rows are Dj_i-2, Dj_i-1, Dj_i and Dj_i+1, respectively, Dj_i-1=Dj_i=Dj_i+1>Dj_i-2, the timing control module 22 compares Dj_i-2 and Dj_i-1 to obtain that Dj_i-1 is greater than Dj_i-2, thereby increasing Dj_i-1 to obtain the corrected target grayscale voltage Dj_i-1' of the pixel unit P located in the jth column and the i-1th row, which can ensure that when the scan line 101 of the i-1th row is turned off, the storage capacitor in the pixel unit P located in the jth column and the i-1th row can be charged to Dj_i-1. Since Dj_i-1=Dj_i=Dj_i+1, the timing control module 22 will not adjust Dj_i and Dj_i+1, so that Dj_i is directly determined as the initial target grayscale voltage of the pixel unit P located in the i-th row and the j-th column, and Dj_i+1 is directly determined as the initial target grayscale voltage of the pixel unit P located in the i+1-th row and the j-th column.

[0072] In some embodiments, the timing control module 22 is specifically used to determine the grayscale voltage adjustment value according to the difference between the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the first preset corresponding relationship when the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column is higher than the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column, and to add the grayscale voltage adjustment value to the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column. Wherein, the grayscale voltage adjustment value>0, and the first preset corresponding relationship includes a one-to-one correspondence between a plurality of difference ranges and a plurality of grayscale voltage adjustment values.

[0073] The timing control module 22 is also used to determine the grayscale voltage adjustment value according to the difference between the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the first preset corresponding relationship when the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column is lower than the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column, and to obtain the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column by subtracting the grayscale voltage adjustment value from the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column. In other embodiments, the actual target grayscale voltage of each pixel unit P can also be determined by other methods, which are not limited here.

[0074] In some embodiments, the display device 1 further includes a timing control module 22, which is used to output a switch control signal TTL to control each of the switch modules 10 to be turned on during the scanning period of any scan line 101 and to be turned off during at least part of each scanning gap.

[0075] Exemplarily, the turn-off voltage of the switch control signal TTL is 0V, and the turn-on voltage is 3.3V, that is, when the voltage of the switch control signal TTL is 0V, the Q switch modules 10 are all turned off in response to the switch control signal TTL, and when the voltage of the switch control signal TTL is 3.3V, the Q switch modules 10 are all turned on in response to the switch control signal TTL.

[0076] In some embodiments, the display device 1 further includes a column driver module 21, and the column driver module 21 is located on one side of the display panel 100 in the column direction. The column driver module 21 is electrically connected to the first connection end of each of the switch modules 10, and is used to output a corresponding actual target grayscale voltage to the first connection end of each of the switch modules 10. The column driver module 21 may include at least one Source Driver IC.

[0077] In some embodiments, the N switch modules 10 are all disposed in the display panel 100 and connected between the column driving module 21 and the corresponding data line 102 .

[0078] In some embodiments, each of the switch modules 10 is turned off when the scan of the i-1th row of scan lines 101 ends, and is turned on when the column driving module 21 starts to output the actual target grayscale voltage of the i-th row of pixel units P. Wherein, 2≤i≤M.

[0079] like Figure 6 As shown, at this time, since the switch module 10 is turned off at the end of the scan of the i-1th row scan line 101, the jth column data line 102 stops receiving Dj_i-1', and its voltage no longer continues to rise but remains at Dj_i-1, and since Dj_i-1=Dj_i=Dj_i+1, the timing control module 22 will not correct Dj_i and Dj_i+1, so that when the column driving module 21 starts to output the actual target grayscale voltage Dj_i of the i-th row pixel unit P, the switch module 10 is turned on, and the j-th column data line 102 receives Dj_i from the column driving module 21 through the turned-on switch module, so that during the scanning process of the i-th row scan line 101, the actual voltage clock of the j-th column data line 102 remains at Dj_i, so that the pixel unit P located in the j-th column and the i-th row can be charged to Dj_i and can display the target grayscale.

[0080] In other embodiments, each of the switch modules 10 may be disconnected at the end of scanning of the i-1th row of scan lines 101, and turned on at the start of scanning of the i-th row of scan lines 101. In order to ensure that the pixel unit P can be fully charged, each of the switch modules 10 may be disconnected after a preset time has passed after the end of scanning of the i-1th row of scan lines 101, which is not limited here.

[0081] In some embodiments, the switch module 10 may be a thin film transistor, so that it can be manufactured in the same process as other thin film transistors in the display panel 100. Since the on-voltage of a thin film transistor is usually above 20V and the off-voltage is usually below 0V, in this embodiment, the switch control signal TTL output by the timing control module 22 needs to be level-converted to control the normal on and off of the switch module 10.

[0082] Specifically, the display device 1 also includes a level conversion module 23, which is electrically connected to the timing control module 22 and the control end of each of the switch modules 10, and is used to receive the switch control signal TTL output by the timing control module 22, and perform level conversion on the switch control signal TTL, and output the switch control signal TTL1 after the level conversion to the control end of each of the switch modules 10, so as to control each of the switch modules 10 to be turned on during the period when any scan line 101 is scanned, and to be turned off during at least part of each scanning interval.

[0083] See also Figure 7 , Figure 7 is a schematic diagram of the structure of the column driver module provided in an embodiment of the present application. In some embodiments, the N switch modules 10 may also be arranged in the column driver module 21, and the column driver module 21 further includes N output stage circuits 211 corresponding to the N switch modules 10 one by one, each of the output stage circuits is electrically connected to the first connection end of the corresponding switch module 10, and is used to output the corresponding actual target grayscale voltage to the first connection end of the corresponding switch module 10. Each of the switch modules 10 also includes a control end for receiving the switch control signal TTL, and each of the switch modules 10 is turned on during the period of scanning any scan line 101 in response to the switch control signal TTL, and is turned off during at least part of the period of each scan gap.

[0084] In this embodiment, the switch module 10 can use MOSFET. Since the driving voltage of MOSFET is relatively low, the switch control signal TTL output by the timing control module 22 can directly drive the switch module 10 without level conversion, and the circuit structure is simpler.

[0085] The output stage circuit 211 includes a push-pull circuit, specifically, the push-pull circuit includes a high-side transistor Th and a low-side transistor Tl. The high-side transistor Th is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the low-side transistor Tl is an N-channel MOSFET. The gate of the high-side transistor Th and the gate of the low-side transistor Tl are connected together to form the input end of the output stage circuit 211, receiving the corresponding actual target grayscale voltage, the drain of the high-side transistor Th is used to receive the high level provided by the voltage source VA, the source of the high-side transistor Th and the source of the low-side transistor Tl are connected together to form the output end of the output stage circuit 211, so as to output the corresponding actual target grayscale voltage to the first connection end of the corresponding switch module 10, and the drain of the low-side transistor Tl is grounded.

[0086] See also Figure 8 , Figure 8 Flow chart of a method for driving a display panel provided in an embodiment of the present application. The present application also provides a method for driving a display panel 100, wherein the display panel 100 includes M scan lines 101, N data lines 102, and M rows of pixel units P, wherein the M scan lines 101 extend in a row direction and are arranged in a column direction, the N data lines 102 extend in a column direction and are arranged in a row direction, and the M rows of pixel units P are arranged in an array and are located at the intersection of the M scan lines 101 and the N data lines 102.

[0087] The driving method comprises:

[0088] Step S1, receiving an image signal, and determining an initial target grayscale voltage of each pixel unit P according to the image signal; and

[0089] Step S2, determining the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column according to the relationship between the initial target grayscale voltage of the pixel unit P located in the i-1th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the i-2th row and j-th column, and the relationship between the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the i-1th row and j-th column; wherein the actual target grayscale voltage of each pixel unit P is used to drive the pixel unit P to display, 3≤i≤M, 1≤j≤N.

[0090] The driving method of the display panel provided in the present application corrects the initial target grayscale voltage of the current row of pixel units P by combining the changing trend of the initial target grayscale voltage of the first two rows of pixel units P to the initial target grayscale voltage of the previous row of pixel units P and the changing trend of the initial target grayscale voltage of the previous row of pixel units P to the initial target grayscale voltage of the current row of pixel units P. This can eliminate the influence of the actual target grayscale voltage of the previous row of pixel units P on the current row of pixel units P, thereby ensuring that the current row of pixel units P can be charged to the corresponding actual target grayscale voltage, and avoiding the problem of horizontal bright and dark lines in the display panel 100.

[0091] In some embodiments, determining the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column according to the magnitude relationship between the initial target grayscale voltage of the pixel unit P located in the i-1th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the i-2th row and j-th column, and the magnitude relationship between the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the i-1th row and j-th column, comprises:

[0092] When a first difference value obtained by subtracting the initial target grayscale voltage of the pixel unit P located in the i-2nd row and jth column from the initial target grayscale voltage of the pixel unit P located in the i-1th row and jth column is greater than a first preset threshold, and a second difference value obtained by subtracting the initial target grayscale voltage of the pixel unit P located in the i-1th row and jth column from the initial target grayscale voltage of the pixel unit P located in the i-1th row and jth column is less than or equal to zero and greater than a second preset threshold, the initial target grayscale voltage of the pixel unit P located in the i-th row and jth column is reduced to obtain an actual target grayscale voltage of the pixel unit P located in the i-th row and jth column; wherein the first preset threshold is greater than zero and the second preset threshold is less than zero; and,

[0093] When a first difference obtained by subtracting the initial target grayscale voltage of the pixel unit P located in the i-1th row and jth column from the initial target grayscale voltage of the pixel unit P located in the i-2th row and jth column is less than the third preset threshold, and a second difference obtained by subtracting the initial target grayscale voltage of the pixel unit P located in the i-1th row and jth column from the initial target grayscale voltage of the pixel unit P located in the i-1th row and jth column is greater than or equal to zero and less than the fourth preset threshold, the initial target grayscale voltage of the pixel unit P located in the i-1th row and jth column is increased to obtain the actual target grayscale voltage of the pixel unit P located in the i-th row and jth column; wherein the third preset threshold is less than zero, and the fourth preset threshold is greater than zero.

[0094] For example, see Fig. 9 , Fig. 9The fourth driving signal timing diagram of the display panel provided by the embodiment of the present application. Taking the data line 102 of the jth column as an example, assuming that the initial target grayscale voltages of the pixel units P located in the jth column and the i-2th to i+1th rows are Dj_i-2, Dj_i-1, Dj_i and Dj_i+1, respectively, Dj_i-1=Dj_i=Dj_i+1>Dj_i-2, the timing control module 22 compares Dj_i-2 and Dj_i-1 to obtain that Dj_i-1 is greater than Dj_i-2, thereby increasing Dj_i-1 to obtain the corrected target grayscale voltage Dj_i-1' of the pixel unit P located in the jth column and the i-1th row, which can ensure that when the scan line 101 of the i-1th row is turned off, the storage capacitor in the pixel unit P located in the jth column and the i-1th row can be charged to Dj_i-1. The timing control module 22 compares Dj_i-2 and Dj_i-1 to obtain a first difference value obtained by subtracting Dj_i-2 from Dj_i-1 that is greater than a first preset threshold value, and compares Dj_i-1 and Dj_i to obtain a second difference value obtained by subtracting Dj_i-1 from Dj_i-1 that is less than or equal to zero and greater than a second preset threshold value, then Dj_i is reduced to obtain Dj_i'. In this way, the output Dj_i' charges the pixel unit P located in the jth column and the i-th row, and the voltage of the jth column data line 102 can be pulled down to Dj_i, thereby ensuring that the pixel is charged to Dj_i.

[0095] In some embodiments, the step of reducing the initial target grayscale voltage of the pixel unit P located in the i-th row and the j-th column to obtain the actual target grayscale voltage of the pixel unit P located in the i-th row and the j-th column includes:

[0096] A grayscale voltage adjustment value is determined according to the first difference, the second difference, and a second preset corresponding relationship, and an actual target grayscale voltage of the pixel unit P located in the i-th row and the j-th column is obtained by subtracting the grayscale voltage adjustment value from the initial target grayscale voltage of the pixel unit P located in the i-th row and the j-th column. The grayscale voltage adjustment value>0, and the second preset corresponding relationship includes a plurality of first difference ranges, a plurality of second difference ranges, and a plurality of grayscale voltage adjustment values.

[0097] The step of increasing the initial target grayscale voltage of the pixel unit P located in the i-th row and the j-th column to obtain the actual target grayscale voltage of the pixel unit P located in the i-th row and the j-th column comprises:

[0098] A grayscale voltage adjustment value is determined according to the first difference, the second difference and the second preset corresponding relationship, and an initial target grayscale voltage of the pixel unit P located in the i-th row and the j-th column is added to the grayscale voltage adjustment value to obtain an actual target grayscale voltage of the pixel unit P located in the i-th row and the j-th column.

[0099] Based on the same inventive concept, the present application also provides a computer-readable storage medium, which stores a computer program, and the computer program is used for being called and executed by a processor to implement the steps in the display panel driving method described in any of the above embodiments.

[0100] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive lists) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing programs, which can be used by instruction execution systems, devices or devices or used in combination with them.

[0101] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0102] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0103] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer or may be connected to an external computer (e.g., via the Internet using an Internet service provider) through any type of network, including a local area network (LAN) or a wide area network (WAN).

[0104] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display device, comprising a display panel, the display panel comprising M scan lines, N data lines and M rows of pixel units, the M scan lines extending in a row direction and arranged in a column direction, the N data lines extending in a column direction and arranged in a row direction, the M rows of pixel units being arranged in an array and located at intersections of the M scan lines and the N data lines, the M scan lines being used to scan the M rows of pixel units row by row according to a preset timing sequence; wherein M and N are both positive integers. There is a scanning gap between the scanning end time of the previous scanning line and the scanning start time of the next scanning line in any two adjacent scanning lines. The characteristic is that: The display device also includes Q switch modules, where Q is a positive integer and Q is less than or equal to N; each of the switch modules corresponds to a data line, and each of the switch modules includes a first connection end and a second connection end, the first connection end is used to receive the actual target grayscale voltage, and the second connection end is electrically connected to the corresponding data line; each of the switch modules is turned on during a period when any scanning line is scanned to output the received actual target grayscale voltage to the corresponding data line, and is turned off during at least a part of each scanning gap to stop outputting the actual target grayscale voltage to the corresponding data line.

2. The display device according to claim 1, wherein: Q is equal to N, and the Q switch modules correspond to the N data lines one by one.

3. The display device according to claim 2, wherein: The display device further comprises a timing control module, which is used to output a switch control signal to control each of the switch modules to be turned on during a period when any scan line is scanned, and to be turned off during at least a part of a period of each scanning gap.

4. The display device according to claim 3, characterized in that The display device also includes a column driving module, which is located on one side of the display panel in the column direction; the N switch modules are all arranged in the display panel and connected between the column driving module and the corresponding data lines; the column driving module is electrically connected to the first connection end of each of the switch modules, and is used to output the corresponding actual target grayscale voltage to the first connection end of each of the switch modules.

5. The display device according to claim 4, characterized in that Each of the switch modules also includes a control end; the display device also includes a level conversion module, which is electrically connected to the timing control module and the control end of each of the switch modules, and is used to receive a switch control signal output by the timing control module, perform level conversion on the switch control signal, and output the switch control signal after the level conversion to the control end of each of the switch modules, so as to control each of the switch modules to be turned on during the period when any scan line is scanned, and to be turned off during at least part of each scan interval.

6. The display device according to claim 3, wherein: The display device also includes a column driving module, which is located on one side of the display panel in the column direction; the N switch modules are arranged in the column driving module, and the column driving module also includes N output stage circuits corresponding to the N switch modules one by one, each of the output stage circuits is electrically connected to the first connection end of the corresponding switch module, and is used to output the corresponding actual target grayscale voltage to the first connection end of the corresponding switch module; each of the switch modules also includes a control end for receiving the switch control signal, and each of the switch modules is turned on during the period of scanning any scan line in response to the switch control signal, and is turned off during at least part of the period of each scan gap.

7. The display device according to claim 3, characterized in that: The timing control module is also used to receive an image signal, and determine the initial target grayscale voltage of each pixel unit according to the image signal, and determine the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column according to the relationship between the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column; wherein 2≤i≤M, 1≤j≤N.

8. The display device according to claim 7, characterized in that The timing control module is specifically used to increase the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column when the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column is higher than the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column; and to reduce the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column when the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column is lower than the initial target grayscale voltage of the pixel unit located in the i-1-th row and j-th column.

9. A method for driving a display panel, the display panel comprising M scan lines, N data lines and M rows of pixel units, the M scan lines extending in a row direction and arranged in a column direction, the N data lines extending in a column direction and arranged in a row direction, the M rows of pixel units being arranged in an array and being located at intersections of the M scan lines and the N data lines, the M scan lines being used to scan the M rows of pixel units row by row according to a preset timing, characterized in that: The driving method comprises: receiving an image signal, and determining an initial target grayscale voltage of each pixel unit according to the image signal; and According to the relationship between the initial target grayscale voltage of the pixel unit located in the i-1th row and jth column and the initial target grayscale voltage of the pixel unit located in the i-2th row and jth column, and the relationship between the initial target grayscale voltage of the pixel unit located in the i-1th row and jth column and the initial target grayscale voltage of the pixel unit located in the i-1th row and jth column, the actual target grayscale voltage of the pixel unit located in the i-1th row and jth column is determined; wherein the actual target grayscale voltage of each pixel unit is used to drive the pixel unit to display, 3≤i≤M, 1≤j≤N.

10. The method for driving a display panel according to claim 9, wherein: The determining the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column according to the magnitude relationship between the initial target grayscale voltage of the pixel unit located in the i-1th row and j-th column and the initial target grayscale voltage of the pixel unit located in the i-2th row and j-th column, and the magnitude relationship between the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit located in the i-1th row and j-th column, comprises: When a first difference value obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-2nd row and the jth column from the initial target grayscale voltage of the pixel unit located in the i-1th row and the jth column is greater than a first preset threshold, and a second difference value obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-1th row and the jth column from the initial target grayscale voltage of the pixel unit located in the i-1th row and the jth column is less than or equal to zero and greater than a second preset threshold, reducing the initial target grayscale voltage of the pixel unit located in the i-th row and the jth column to obtain an actual target grayscale voltage of the pixel unit located in the i-th row and the jth column; wherein the first preset threshold is greater than zero and the second preset threshold is less than zero; and When a first difference obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-1th row and jth column from the initial target grayscale voltage of the pixel unit located in the i-2th row and jth column is less than a third preset threshold, and a second difference obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-1th row and jth column from the initial target grayscale voltage of the pixel unit located in the i-1th row and jth column is greater than or equal to zero and less than a fourth preset threshold, the initial target grayscale voltage of the pixel unit located in the i-1th row and jth column is increased to obtain an actual target grayscale voltage of the pixel unit located in the i-th row and jth column; wherein the third preset threshold is less than zero and the fourth preset threshold is greater than zero.

Images