Undervoltage protection circuit

Abstract

The embodiment of the present application provides an undervoltage protection circuit, including: an input module, an adjustment module, a capacitor and a flip module; the input module is connected to a power supply, the adjustment module and the flip module are both connected to the input module, and the adjustment module is connected to the capacitor; the input module is used to output a first signal to the adjustment module and the flip module according to the output voltage of the power supply; the adjustment module is used to charge or discharge the capacitor according to the first signal and the target signal output by the flip module, and output a second signal to the flip module based on the voltage across the capacitor; the flip module is used to output a target signal according to the first signal and the second signal, wherein when the output voltage of the power supply is less than the first voltage threshold, the target signal indicates that the power supply is in an undervoltage state, and when a voltage burr appears in the output voltage of the power supply, the target signal is kept unchanged. Thus, this scheme can reduce the probability of damage to the system where the undervoltage protection circuit is located.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of undervoltage protection, and in particular to an undervoltage protection circuit. Background Art

[0002] In analog integrated circuit systems, undervoltage protection can be achieved by using the signal output by the protection circuit module to minimize damage to the system due to long-term operation under low voltage conditions.

[0003] During the operation of the protection circuit module, if the voltage of the power supply is lower than the flip voltage, the protection circuit module will output a low-level signal. At this time, the low-level signal can control other circuit modules outside the protection circuit module to turn on or off, thereby realizing undervoltage protection for the system.

[0004] However, if Figure 1 As shown, when an overshoot glitch appears in the changing waveform of the voltage vdd of the power supply (i.e., vdd gradually rises quickly from a smaller voltage lower than the flip voltage to a larger voltage higher than the flip voltage, and then gradually drops quickly from the larger voltage to the smaller voltage), the signal UVLO1 output by the protection circuit module will appear a short high level in the process of maintaining a low level. When an undershoot glitch appears in the changing waveform of vdd (i.e., vdd gradually drops quickly from a larger voltage to a smaller voltage, and then gradually rises quickly from a smaller voltage to a larger voltage), UVLO1 will appear a short low level in the process of maintaining a high level. Therefore, when an overshoot glitch or an undershoot glitch appears in the changing waveform of vdd, UVLO1 will appear a situation where the level repeatedly jumps rapidly, so that the other circuit modules mentioned above are repeatedly turned on and off rapidly, thereby easily causing damage to the system where the protection circuit module is located. Summary of the invention

[0005] In view of this, an embodiment of the present application provides an undervoltage protection circuit to at least partially solve the above-mentioned problem.

[0006] An embodiment of the present application provides an undervoltage protection circuit, comprising: an input module, an adjustment module, a capacitor and a flip module; the input module is connected to a power supply, the adjustment module and the flip module are both connected to the input module, and the adjustment module is connected to the capacitor; the input module is used to output a first signal to the adjustment module and the flip module according to the output voltage of the power supply; the adjustment module is used to charge or discharge the capacitor according to the first signal and a target signal output by the flip module, and output a second signal to the flip module based on the voltage across the capacitor; the flip module is used to output the target signal according to the first signal and the second signal, wherein when the output voltage of the power supply is less than a first voltage threshold, the target signal indicates that the power supply is in an undervoltage state, and when a voltage glitch occurs in the output voltage of the power supply, the target signal is kept unchanged.

[0007] In a possible implementation, the input module is used to output the first signal with a low level value to the adjustment module and the flip module when the output voltage of the power supply is less than the first voltage threshold, and output the first signal with a high level value to the adjustment module and the flip module when the output voltage is greater than the first voltage threshold; the adjustment module is used to discharge the capacitor when the level values ​​of the first signal and the target signal are the same to reduce the voltage difference across the capacitor, charge the capacitor when the level values ​​of the first signal and the target signal are different to increase the voltage difference across the capacitor, and output a second signal with a high level value when the voltage difference across the capacitor is equal to or greater than a second voltage threshold, and output a second signal with a low level value when the voltage difference across the capacitor is less than the second voltage threshold, wherein the speed at which the adjustment module discharges the capacitor is greater than the speed at which the capacitor is charged; and the flip module is used to flip the level value of the target signal after the level value of the second signal flips from a low level to a high level.

[0008] In a possible implementation, the adjustment module includes a first XOR gate, a first inverter, a first N-channel transistor, a first P-channel transistor, a second P-channel transistor, a third P-channel transistor, a first current source, a second inverter, and a third inverter; the first input end of the first XOR gate is used to input the first signal, the second input end of the first XOR gate is used to input the target signal, the output end of the first XOR gate is connected to the input end of the first inverter, the output end of the first inverter is connected to the gate of the first N-channel transistor, and is connected to the gate of the first P-channel transistor; the source of the first N-channel transistor is grounded, the drain of the first N-channel transistor is connected to the first end of the capacitor, and the second end of the capacitor is grounded ; the source of the first P-channel transistor is connected to the drain of the second P-channel transistor, and the drain of the first P-channel transistor is connected to the first end of the capacitor; the gate of the second P-channel transistor is connected to the gate of the third P-channel transistor, and the source of the second P-channel transistor is connected to the power supply; the source of the third P-channel transistor is connected to the power supply, the drain of the third P-channel transistor is connected to the negative electrode of the first current source and to the gate of the third P-channel transistor, and the positive electrode of the first current source is grounded; the input end of the second inverter is connected to the first end of the capacitor, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter is used to output the second signal.

[0009] In a possible implementation, the adjustment module also includes a fourth P-channel transistor and a fifth P-channel transistor; the gate of the fourth P-channel transistor is connected to the output end of the second inverter, the source of the fourth P-channel transistor is connected to the power supply, and the drain of the fourth P-channel transistor is connected to the source of the fifth P-channel transistor; the gate of the fifth P-channel transistor is connected to the gate of the third P-channel transistor, and the drain of the fifth P-channel transistor is connected to the source of the first P-channel transistor.

[0010] In a possible implementation, the input module is used to output the first signal with a low level value to the adjustment module and the flip module when the output voltage of the power supply is less than the first voltage threshold, and output the first signal with a high level value to the adjustment module and the flip module when the output voltage is greater than the first voltage threshold; the adjustment module is used to charge the capacitor when the level values ​​of the first signal and the target signal are the same, so that the voltage difference across the capacitor increases, and discharge the capacitor when the level values ​​of the first signal and the target signal are different, so that the voltage difference across the capacitor decreases, and output a second signal with a low level value when the voltage difference across the capacitor is equal to or greater than a second voltage threshold, and output a second signal with a high level value when the voltage difference across the capacitor is less than the second voltage threshold, wherein the speed at which the adjustment module charges the capacitor is greater than the speed at which the capacitor is discharged; the flip module is used to flip the level value of the target signal after the level value of the second signal flips from a low level to a high level.

[0011] In a possible implementation, the adjustment module includes a second XOR gate, a sixth P-channel transistor, a second N-channel transistor, a third N-channel transistor, a fourth N-channel transistor, a second current source, a fourth inverter, a fifth inverter and a sixth inverter; the first input end of the second XOR gate is used to input the first signal, the second input end of the second XOR gate is used to input the target signal, the output end of the second XOR gate is connected to the gate of the sixth P-channel transistor and to the gate of the second N-channel transistor; the source of the sixth P-channel transistor is connected to the power supply, the drain of the sixth P-channel transistor is connected to the first end of the capacitor, and the second end of the capacitor is grounded; the The source is connected to the drain of the third N-channel transistor, and the drain of the second N-channel transistor is connected to the first end of the capacitor; the gate of the third N-channel transistor is connected to the positive electrode of the second current source, and the source of the third N-channel transistor is grounded; the gate and drain of the fourth N-channel transistor are both connected to the positive electrode of the second current source, and the source of the fourth N-channel transistor is grounded; the negative electrode of the second current source is connected to the power supply; the input end of the fourth inverter is connected to the first end of the capacitor, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is used to output the second signal.

[0012] In a possible implementation, the adjustment module also includes a fifth N-channel transistor and a sixth N-channel transistor; the gate of the fifth N-channel transistor is connected to the output end of the sixth inverter, the source of the fifth N-channel transistor is connected to the drain of the sixth N-channel transistor, and the drain of the fifth N-channel transistor is connected to the source of the second N-channel transistor; the gate of the sixth N-channel transistor is connected to the positive electrode of the second current source, and the source of the sixth N-channel transistor is grounded.

[0013] In one possible implementation, after the output voltage of the power supply increases from a state less than the first voltage threshold to a state greater than the first voltage threshold, the first voltage threshold is reduced; after the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, the first voltage threshold is increased.

[0014] In a possible implementation, the input module includes a first resistor, a second resistor, a third resistor, a comparator, a seventh inverter and a seventh N-channel transistor; the first end of the first resistor is connected to the power supply, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded; the non-inverting input end of the comparator is connected to a reference voltage, the inverting input end of the comparator is connected between the first resistor and the second resistor, the output end of the comparator is connected to the input end of the seventh inverter, and the output end of the seventh inverter is used to output the first signal; the source of the seventh N-channel transistor is grounded, the drain of the seventh N-channel transistor is connected between the second resistor and the third resistor, and the gate of the seventh N-channel transistor is connected to the output end of the seventh inverter.

[0015] In a possible implementation, the flip module includes an eighth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate and a ninth inverter; the input end of the eighth inverter is used to input the first signal, the output end of the eighth inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is used to input the second signal, the first input end of the second NAND gate is used to input the first signal, the second input end of the second NAND gate is used to input the second signal, the output end of the first NAND gate is connected to the first input end of the third NAND gate, the output end of the second NAND gate is connected to the first input end of the fourth NAND gate, the second input end of the third NAND gate is connected to the output end of the fourth NAND gate, the second input end of the fourth NAND gate is connected to the output end of the third NAND gate, the output end of the third NAND gate is connected to the input end of the ninth inverter, and the output end of the ninth inverter is used to output the target signal.

[0016] According to the undervoltage protection circuit provided by the embodiment of the present application, it includes an input module, an adjustment module, a capacitor and a flip module, wherein the input module can output a first signal according to the output voltage of the power supply, the adjustment module controls the charging and discharging of the capacitor according to the first signal and the target signal output by the flip module to obtain and output the second signal, and the flip module outputs the target signal according to the first signal and the second signal, so that when the output voltage of the power supply is small, the target signal is used to indicate that the power supply is in an undervoltage state, and when the output voltage of the power supply has an overshoot burr and an undershoot burr, the target signal can be maintained unchanged. Thus, when the output voltage of the power supply is small, the target signal can be used to indicate that the power supply is in an undervoltage state, so that in the system where the voltage protection circuit is located, the subsequent circuit of the undervoltage protection circuit is turned on or off, thereby realizing the undervoltage protection of the system, and at the same time, when the output voltage of the power supply has a voltage burr, the target signal can be maintained unchanged, so as to try to ensure that the target signal will not have repeated and rapid level jumps due to the voltage burr of the output voltage of the power supply, thereby reducing the possibility of the subsequent circuit of the undervoltage protection circuit being repeatedly and rapidly turned on and off, and thus, the probability of damage to the system where the undervoltage protection circuit is located can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0018] Figure 1 is a waveform diagram of a signal output by a protection circuit module of the background technology;

[0019] Figure 2 is a waveform diagram of a target signal output by an undervoltage protection circuit according to an embodiment of the present application;

[0020] Figure 3 is a circuit diagram of an input module of an embodiment of the present application;

[0021] Figure 4 is a circuit diagram of an adjustment module according to an embodiment of the present application;

[0022] Figure 5 is a circuit diagram of an adjustment module according to another embodiment of the present application;

[0023] Figure 6 It is a circuit diagram of a flip module according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] An embodiment of the present application provides an undervoltage protection circuit, and the undervoltage protection circuit is described in detail below through multiple embodiments.

[0025] The undervoltage protection circuit includes an input module, an adjustment module, a capacitor and a flip module, wherein the input module is connected to a power supply, the adjustment module and the flip module are both connected to the input module, and the adjustment module is connected to the capacitor; the input module is used to output a first signal to the adjustment module and the flip module according to the output voltage of the power supply; the adjustment module is used to charge or discharge the capacitor according to the first signal and a target signal output by the flip module, and output a second signal to the flip module based on the voltage across the capacitor; and the flip module is used to output a target signal according to the first signal and the second signal.

[0026] Among them, when the output voltage of the power supply is less than the first voltage threshold, the target signal indicates that the power supply is in an undervoltage state, and when a voltage glitch appears in the output voltage of the power supply, no matter whether the voltage glitch is an overshoot glitch or an undershoot glitch, the target signal can be kept unchanged. The overshoot glitch and the undershoot glitch have been introduced in the background technology, and the embodiments of the present application will not be repeated here.

[0027] For example, Figure 2 As shown, when an overshoot burr appears in the changing waveform of the output voltage vdd of the power supply, the target signal UVLO2 output by the undervoltage protection circuit will maintain a low level. When an undershoot burr appears in the changing waveform of the output voltage vdd of the power supply, the target signal UVLO2 output by the undervoltage protection circuit will maintain a high level.

[0028] In the embodiment of the present application, the undervoltage protection circuit includes an input module, an adjustment module, a capacitor and a flip module, wherein the input module can output a first signal according to the output voltage of the power supply, the adjustment module controls the charging and discharging of the capacitor according to the first signal and the target signal output by the flip module to obtain and output the second signal, and the flip module outputs the target signal according to the first signal and the second signal, so that when the output voltage of the power supply is small, the target signal is used to indicate that the power supply is in an undervoltage state, and when the output voltage of the power supply has an overshoot burr and an undershoot burr, the target signal can be maintained unchanged. Thus, when the output voltage of the power supply is small, the target signal can be used to indicate that the power supply is in an undervoltage state, so that in the system where the voltage protection circuit is located, the subsequent circuit of the undervoltage protection circuit is turned on or off, thereby realizing the undervoltage protection of the system, and at the same time, when the output voltage of the power supply has a voltage burr, the target signal can be maintained unchanged, so as to try to ensure that the target signal will not have repeated and rapid level jumps due to the voltage burr of the output voltage of the power supply, thereby reducing the possibility of the subsequent circuit of the undervoltage protection circuit being repeatedly and rapidly turned on and off, and therefore, the probability of damage to the system where the undervoltage protection circuit is located can be reduced.

[0029] In addition, in order to avoid the influence of one type of voltage glitches, namely, overshoot glitches and undershoot glitches, in the related art, an RC circuit is usually used in the undervoltage protection circuit. Compared with the related art, the undervoltage protection circuit in the present application can not only avoid the output voltage of the undervoltage protection circuit from being affected by the overshoot glitches generated by the power supply, but also avoid the output voltage of the undervoltage protection circuit from being affected by the undershoot glitches generated by the power supply, thereby further reducing the probability of damage to the system in which the undervoltage protection circuit is located.

[0030] Specifically, the undervoltage protection circuit can be implemented in at least two ways:

[0031] In a first possible implementation, the input module is used to output a first signal with a low level value to the adjustment module and the flip module when the output voltage of the power supply is less than the first voltage threshold, and output a first signal with a high level value to the adjustment module and the flip module when the output voltage is greater than the first voltage threshold; the adjustment module is used to discharge the capacitor when the level values ​​of the first signal and the target signal are the same to reduce the voltage difference across the capacitor, charge the capacitor when the level values ​​of the first signal and the target signal are different to increase the voltage difference across the capacitor, and output a second signal with a high level value when the voltage difference across the capacitor is equal to or greater than a second voltage threshold, and output a second signal with a low level value when the voltage difference across the capacitor is less than the second voltage threshold, wherein the speed at which the adjustment module discharges the capacitor is greater than the speed at which the capacitor is charged; the flip module is used to flip the level value of the target signal after the level value of the second signal flips from a low level to a high level.

[0032] When the undervoltage protection circuit is just powered on, the level value of the target signal is a low level. If the output voltage of the power supply is less than the first voltage threshold, the level value of the first signal is a low level. At this time, the level value of the first signal is the same as the level value of the target signal. The adjustment module discharges the capacitor faster, and the voltage difference across the capacitor decreases faster. When the voltage difference across the capacitor is less than the second voltage threshold, the adjustment module outputs a second signal with a low level. At this time, since the second signal has not flipped from a low level to a high level, the target signal will maintain a low level to indicate that the power supply is in an undervoltage state, thereby achieving undervoltage protection.

[0033] Similarly, when the output voltage of the power supply is less than the first voltage threshold, and the working state of each module included in the undervoltage protection circuit is stable, the level value of the first signal is low, the level value of the second signal is low, and the level value of the target signal is low. Based on this, if the output voltage of the power supply increases to be greater than the first voltage threshold, the first signal flips to a high level. At this time, the level values ​​of the first signal and the target signal are different. The adjustment module will charge the capacitor more slowly, and the voltage difference across the capacitor increases more slowly. When the voltage difference across the capacitor is equal to or greater than the second voltage threshold, the level value of the second signal output by the adjustment module flips from a low level to a high level, so that the target signal flips to a high level. At this time, the level values ​​of the first signal and the target signal are the same, and the adjustment module discharges the capacitor more quickly, and the voltage difference across the capacitor decreases more quickly. When the voltage difference across the capacitor is less than the second voltage threshold, the adjustment module outputs a second signal with a low level. At this time, since the second signal does not flip from a low level to a high level, the target signal will maintain a high level to indicate that the power supply is in a non-undervoltage state.

[0034] When the undervoltage protection circuit is just powered on, the level value of the target signal is a low level. If the output voltage of the power supply is greater than the first voltage threshold, the level value of the first signal is a high level. At this time, the level values ​​of the first signal and the target signal are different. The adjustment module charges the capacitor more slowly, and the voltage difference across the capacitor increases more slowly. When the voltage difference across the capacitor is equal to or greater than the second voltage threshold, the level value of the second signal output by the adjustment module flips from a low level to a high level, so that the target signal flips to a high level. At this time, the level values ​​of the first signal and the target signal are the same. The adjustment module discharges the capacitor more quickly, and the voltage difference across the capacitor decreases more quickly. When the voltage difference across the capacitor is less than the second voltage threshold, the adjustment module outputs a second signal with a low level. At this time, since the second signal has not flipped from a low level to a high level, the target signal will maintain a high level to indicate that the power supply is in a non-undervoltage state.

[0035] Similarly, when the output voltage of the power supply is greater than the first voltage threshold, and the working state of each module included in the undervoltage protection circuit is stable, the level value of the first signal is high, the level value of the second signal is low, and the level value of the target signal is high. Based on this, if the output voltage of the power supply is reduced to less than the first voltage threshold, the first signal flips to a low level. At this time, the level values ​​of the first signal and the target signal are different. The adjustment module will charge the capacitor more slowly, and the voltage difference across the capacitor increases more slowly. When the voltage difference across the capacitor is greater than the second voltage threshold, the level value of the second signal output by the adjustment module flips from a low level to a high level, so that the target signal flips to a low level. At this time, the level values ​​of the first signal and the target signal are the same, and the adjustment module discharges the capacitor more quickly, and the voltage difference across the capacitor decreases more quickly. When the voltage difference across the capacitor is less than the second voltage threshold, the adjustment module outputs a second signal with a low level level. At this time, since the second signal does not flip from a low level to a high level, the target signal will maintain a low level to indicate that the power supply is in an undervoltage state, thereby achieving undervoltage protection.

[0036] In an embodiment of the present application, when the output voltage of the power supply increases from a state less than a first voltage threshold to a state greater than the first voltage threshold, the adjustment module will first charge the capacitor more slowly to flip the target signal to a high level when the voltage difference across the capacitor is large enough, and then discharge the capacitor more quickly to maintain the target signal, and when the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, the adjustment module will first charge the capacitor more slowly to flip the target signal to a low level when the voltage difference across the capacitor is large enough, and then discharge the capacitor more quickly to maintain the target signal. Therefore, when the output voltage of the power supply has an overshoot burr, the output voltage of the power supply will rapidly increase from a state less than the first voltage threshold to a state greater than the first voltage threshold, and then rapidly decrease to a state less than the first voltage threshold, so that the capacitor begins to be discharged before being charged to a voltage difference between the two ends of the capacitor that is large enough, and the target signal is maintained at a low level before it has time to be flipped to a high level. Similarly, when the output voltage of the power supply has an overshoot burr, the output voltage of the power supply will rapidly decrease from a state greater than the first voltage threshold to a state less than the first voltage threshold, and then rapidly increase to a state greater than the first voltage threshold, so that the capacitor begins to be discharged before being charged to a voltage difference between the two ends of the capacitor that is large enough, and the target signal is maintained at a high level before it has time to be flipped to a low level. Therefore, the undervoltage protection circuit not only realizes the undervoltage protection function, but also realizes the function of keeping the target signal unchanged when voltage glitches appear in the output voltage of the power supply.

[0037] In a second possible implementation, the input module is used to output a first signal with a low level value to the adjustment module and the flip module when the output voltage of the power supply is less than the first voltage threshold, and output a first signal with a high level value to the adjustment module and the flip module when the output voltage is greater than the first voltage threshold; the adjustment module is used to charge the capacitor when the level values ​​of the first signal and the target signal are the same to increase the voltage difference across the capacitor, discharge the capacitor when the level values ​​of the first signal and the target signal are different to reduce the voltage difference across the capacitor, and output a second signal with a low level value when the voltage difference across the capacitor is equal to or greater than a second voltage threshold, and output a second signal with a high level value when the voltage difference across the capacitor is less than the second voltage threshold, wherein the speed at which the adjustment module charges the capacitor is greater than the speed at which the capacitor is discharged; the flip module is used to flip the level value of the target signal after the level value of the second signal flips from a low level to a high level.

[0038] When the undervoltage protection circuit is just powered on, the level value of the target signal is a low level. If the output voltage of the power supply is less than the first voltage threshold, the level value of the first signal is a low level. At this time, the level value of the first signal is the same as the level value of the target signal. The adjustment module charges the capacitor faster, and the voltage difference across the capacitor increases faster. When the voltage difference across the capacitor is equal to or greater than the second voltage threshold, the adjustment module outputs a second signal with a low level. At this time, since the second signal has not flipped from a low level to a high level, the target signal will maintain a low level to indicate that the power supply is in an undervoltage state, thereby achieving undervoltage protection.

[0039] Similarly, when the output voltage of the power supply is less than the first voltage threshold, and the working state of each module included in the undervoltage protection circuit is stable, the level value of the first signal is low, the level value of the second signal is low, and the level value of the target signal is low. Based on this, if the output voltage of the power supply increases to be greater than the first voltage threshold, the first signal flips to a high level. At this time, the level values ​​of the first signal and the target signal are different. The adjustment module will discharge the capacitor more slowly, and the voltage difference across the capacitor will decrease more slowly. When the voltage difference across the capacitor is less than the second voltage threshold, the level value of the second signal output by the adjustment module flips from a low level to a high level, so that the target signal flips to a high level. At this time, the level values ​​of the first signal and the target signal are the same, and the adjustment module charges the capacitor faster, and the voltage difference across the capacitor increases faster. When the voltage difference across the capacitor is equal to or greater than the second voltage threshold, the adjustment module outputs a second signal with a low level. At this time, since the second signal does not flip from a low level to a high level, the target signal will maintain a high level to indicate that the power supply is in a non-undervoltage state.

[0040] When the undervoltage protection circuit is just powered on, the level value of the target signal is a low level. If the output voltage of the power supply is greater than the first voltage threshold, the level value of the first signal is a high level. At this time, the level values ​​of the first signal and the target signal are different. The adjustment module discharges the capacitor more slowly, and the voltage difference across the capacitor decreases more slowly. When the voltage difference across the capacitor is less than the second voltage threshold, the level value of the second signal output by the adjustment module flips from a low level to a high level, so that the target signal flips to a high level. At this time, the level values ​​of the first signal and the target signal are the same. The adjustment module charges the capacitor more quickly, and the voltage difference across the capacitor increases more quickly. When the voltage difference across the capacitor is equal to or greater than the second voltage threshold, the adjustment module outputs a second signal with a low level. At this time, since the second signal has not flipped from a low level to a high level, the target signal will maintain a high level to indicate that the power supply is in a non-undervoltage state.

[0041] Similarly, when the output voltage of the power supply is greater than the first voltage threshold, and the working state of each module included in the undervoltage protection circuit is stable, the level value of the first signal is high, the level value of the second signal is low, and the level value of the target signal is high. Based on this, if the output voltage of the power supply is reduced to less than the first voltage threshold, the first signal is flipped to a low level. At this time, the level values ​​of the first signal and the target signal are different. The adjustment module will discharge the capacitor more slowly, and the voltage difference across the capacitor will decrease more slowly. When the voltage difference across the capacitor is less than the second voltage threshold, the level value of the second signal output by the adjustment module is flipped from a low level to a high level, so that the target signal is flipped to a low level. At this time, the level values ​​of the first signal and the target signal are the same, and the adjustment module charges the capacitor faster, and the voltage difference across the capacitor increases faster. When the voltage difference across the capacitor is equal to or greater than the second voltage threshold, the adjustment module outputs a second signal with a low level. At this time, since the second signal does not flip from a low level to a high level, the target signal will maintain a low level to indicate that the power supply is in an undervoltage state, thereby achieving undervoltage protection.

[0042] In an embodiment of the present application, when the output voltage of the power supply increases from a state less than a first voltage threshold to a state greater than the first voltage threshold, the adjustment module will first discharge the capacitor relatively slowly to flip the target signal to a high level when the voltage difference across the capacitor is small enough, and then charge the capacitor relatively quickly to maintain the target signal, and when the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, the adjustment module will first discharge the capacitor relatively slowly to flip the target signal to a low level when the voltage difference across the capacitor is small enough, and then charge the capacitor relatively quickly to maintain the target signal. Therefore, when the output voltage of the power supply has an overshoot burr, the output voltage of the power supply will rapidly increase from a state less than the first voltage threshold to a state greater than the first voltage threshold, and then rapidly decrease to a state less than the first voltage threshold, so that the capacitor begins to be quickly charged before being discharged to a voltage difference between the two ends of the capacitor is small enough, and the target signal is maintained at a low level before it has time to be flipped to a high level. Similarly, when the output voltage of the power supply has an overshoot burr, the output voltage of the power supply will rapidly decrease from a state greater than the first voltage threshold to a state less than the first voltage threshold, and then rapidly increase to a state greater than the first voltage threshold, so that the capacitor begins to be quickly charged before being discharged to a voltage difference between the two ends of the capacitor is small enough, and the target signal is maintained at a high level before it has time to be flipped to a low level. Therefore, the undervoltage protection circuit not only realizes the undervoltage protection function, but also realizes the function of keeping the target signal unchanged when voltage glitches appear in the output voltage of the power supply.

[0043] The first voltage threshold may be a fixed value. However, if the first voltage threshold is a fixed value, when the output voltage of the power supply fluctuates near the first voltage threshold, the target signal output by the undervoltage protection circuit will continuously flip in level, so that the stability of the undervoltage protection circuit is poor. To address this problem:

[0044] In a possible implementation, the first voltage threshold may also be a variable value. Specifically, after the output voltage of the power supply increases from a state less than the first voltage threshold to a state greater than the first voltage threshold, the first voltage threshold is reduced; after the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, the first voltage threshold is increased.

[0045] For example, after the output voltage of the power supply increases from a state less than the first voltage threshold to a state greater than the first voltage threshold, the first voltage threshold is reduced to be equal to UVLO_L, and after the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, the first voltage threshold is increased to be equal to UVLO_H, wherein UVLO_H>UVLO_L.

[0046] In the embodiment of the present application, after the output voltage of the power supply increases from a state less than the first voltage threshold to a state greater than the first voltage threshold, the first voltage threshold is reduced, and conversely, after the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, the first voltage threshold is increased. Thus, after the output voltage of the power supply increases from a state less than the first voltage threshold to a state greater than the first voltage threshold, even if the output voltage of the power supply decreases slightly again, the output voltage of the power supply is still substantially greater than the current first voltage threshold, and after the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, even if the output voltage of the power supply increases slightly again, the output voltage of the power supply is still substantially less than the current first voltage threshold. Therefore, when the output voltage of the power supply jitters near the first voltage threshold at any time, the number of level flips of the target signal output by the undervoltage protection circuit can be reduced, so as to make the undervoltage protection circuit more stable.

[0047] In one possible implementation, Figure 3 As shown, the input module includes a first resistor R1, a second resistor R2, a third resistor R3, a comparator AMP1, a seventh inverter INV7 and a seventh N-channel transistor MN7; a first end of the first resistor R1 is connected to a power supply VDD, a second end of the first resistor R1 is connected to a first end of the second resistor R2, a second end of the second resistor R2 is connected to a first end of the third resistor R3, and a second end of the third resistor R3 is grounded; a non-inverting input end of the comparator AMP1 is connected to a reference voltage VREF, an inverting input end of the comparator AMP1 is connected between the first resistor R1 and the second resistor R2, an output end of the comparator AMP1 is connected to an input end of the seventh inverter INV7, and an output end of the seventh inverter INV7 is used to output a first signal V0; a source of the seventh N-channel transistor MN7 is grounded, a drain of the seventh N-channel transistor MN7 is connected between the second resistor R2 and the third resistor R3, and a gate of the seventh N-channel transistor MN7 is connected to an output end of the seventh inverter INV7.

[0048] Based on the above “after the output voltage of the power supply increases from a state less than the first voltage threshold to a state greater than the first voltage threshold, the first voltage threshold is reduced to be equal to UVLO_L, and after the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, the first voltage threshold is increased to be equal to UVLO_H”:

[0049] When the output voltage of the power supply is extremely small, the first voltage threshold is equal to UVLO_H, the output voltage of the voltage is less than UVLO_H, the input voltage VCPM of the inverting input terminal of the comparator is less than VREF, and then the comparator outputs a high level, and the seventh inverter outputs a low level, thereby, the seventh N-channel transistor is turned off, so that the first resistor, the second resistor and the third resistor are connected in series between the power supply and the ground, therefore, it can be concluded that UVLO_H = VREF*(r1+r2+r3) / (r2+r3); at this time, if the output voltage of the voltage increases to be greater than UVLO_H, the first voltage threshold is adjusted to UVLO_L, since UVLO_H>UVLO_L, the output voltage of the voltage is still greater than the current first voltage threshold UVLO_L, at this time VCPM>VREF, and then the comparator outputs a low level, and the seventh inverter outputs a high level, thereby, the seventh N-channel transistor is turned on, so that the first resistor and the second resistor are connected in series between the power supply and the ground, and the third resistor is short-circuited by the seventh N-channel transistor. Therefore, it can be concluded that UVLO_L=VREF*(r1+r2) / r2, wherein r1 is the resistance value of the first resistor, r2 is the resistance value of the second resistor, and r3 is the resistance value of the third resistor.

[0050] Therefore, the automatic adjustment of the first voltage threshold can be achieved through the specific circuit of the above-mentioned input module, which has a simple structure, low cost and is easy to implement.

[0051] The second voltage threshold is usually a fixed value, and the specific value of the second voltage threshold can be determined according to actual conditions, which is not limited in the embodiments of the present application.

[0052] In a possible implementation, corresponding to the first implementation of the undervoltage protection module, such as Figure 4As shown, the adjustment module includes a first XOR gate XOR1, a first inverter INV1, a first N-channel transistor MN1, a first P-channel transistor MP1, a second P-channel transistor MP2, a third P-channel transistor MP3, a first current source I1, a second inverter INV2 and a third inverter INV3; the first input end of the first XOR gate XOR1 is connected to the output end of the seventh inverter INV7 through the A1 port, so that the first input end of the first XOR gate XOR1 is used to input the first signal V0, the second input end of the first XOR gate XOR1 is connected to the output end of the flip module for outputting the target signal UVLO2 through the A2 port, so that the second input end of the first XOR gate XOR1 is used to input the target signal UVLO2, the output end of the first XOR gate XOR1 is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the gate of the first N-channel transistor MN1 through the A3 port, and is connected to the gate of the first P-channel transistor MP1 through the A 3 ports are connected; the source of the first N-channel transistor MN1 is grounded, the drain of the first N-channel transistor MN1 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is grounded; the source of the first P-channel transistor MP1 is connected to the drain of the second P-channel transistor MP2, and the drain of the first P-channel transistor MP1 is connected to the first end of the capacitor C1; the gate of the second P-channel transistor MP2 is connected to the gate of the third P-channel transistor MP3, and the source of the second P-channel transistor MP2 is connected to the power supply VDD; the source of the third P-channel transistor MP3 is connected to the power supply VDD, the drain of the third P-channel transistor MP3 is connected to the negative electrode of the first current source I1, and is connected to the gate of the third P-channel transistor MP3, and the positive electrode of the first current source I1 is grounded; the input end of the second inverter INV2 is connected to the first end of the capacitor C1, the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is used to output the second signal V1. It should be noted that the second inverter INV2 is a Schmitt inverter.

[0053] When the first signal and the target signal are the same, the first XOR gate outputs a low level, the first inverter outputs a high level, the first N-channel transistor is turned on, the first P-channel transistor is turned off, and the first N-channel transistor with the source grounded will discharge the capacitor faster. When the first signal and the target signal are different, the first XOR gate outputs a high level, the first inverter outputs a low level, the first N-channel transistor is turned off, the first P-channel transistor is turned on, and the first current source will charge the capacitor more slowly through the first P-channel transistor.

[0054] Therefore, by adopting the above-mentioned adjustment module, the capacitor is charged through the first current source, and the capacitor is discharged through the first N-channel transistor with the source grounded, so that the speed of discharging the capacitor is greater than the speed of charging the capacitor. The structure is simple, the cost is low, and it is easy to implement.

[0055] Based on this, in a possible implementation, Figure 4 As shown, the adjustment module also includes a fourth P-channel transistor MP4 and a fifth P-channel transistor MP5; the gate of the fourth P-channel transistor MP4 is connected to the output end of the second inverter INV2 through the A4 port, the source of the fourth P-channel transistor MP4 is connected to the power supply VDD, and the drain of the fourth P-channel transistor MP4 is connected to the source of the fifth P-channel transistor MP5; the gate of the fifth P-channel transistor MP5 is connected to the gate of the third P-channel transistor MP3, and the drain of the fifth P-channel transistor MP5 is connected to the source of the first P-channel transistor MP1.

[0056] Thus, when the first signal and the target signal are different, the first XOR gate outputs a high level, the first inverter outputs a low level, the first N-channel transistor is turned off, the first P-channel transistor is turned on, and the first current source charges the capacitor more slowly through the first P-channel transistor. When the first end of the capacitor is charged to a high level and the output end of the second inverter outputs a low level, the fourth P-channel transistor switches from an off state to an on state, so that the power supply also charges the capacitor through the fourth P-channel transistor and the fifth P-channel transistor, so as to reduce the possibility that the voltage at the first end of the capacitor cannot be maintained due to too slow charging of the capacitor while the first end of the capacitor is maintained at a high level.

[0057] Optionally, the speed of charging the capacitor can be adjusted by changing the capacitance value of the capacitor, the output current value of the first current source and / or the size of the second P-channel transistor, thereby adjusting the voltage change speed of the first end of the capacitor. The undervoltage protection circuit can also shield voltage glitches of different sizes, thereby improving the applicability of the undervoltage protection circuit.

[0058] In a possible implementation, corresponding to the second implementation of the undervoltage protection module, such as Figure 5As shown, the adjustment module includes a second XOR gate XOR2, a sixth P-channel transistor MP6, a second N-channel transistor MN2, a third N-channel transistor MN3, a fourth N-channel transistor MN4, a second current source I2, a fourth inverter INV4, a fifth inverter INV5 and a sixth inverter INV6; the first input end of the second XOR gate XOR2 is connected to the output end of the seventh inverter INV7 through the A1 port, so that the first input end of the second XOR gate XOR2 is used to input the first signal V0, the second input end of the second XOR gate XOR2 is connected to the output end of the flip module for outputting the target signal UVLO2 through the A2 port, so that the second input end of the second XOR gate XOR2 is used to input the target signal UVLO2, the output end of the second XOR gate XOR2 is connected to the gate of the sixth P-channel transistor MP6, and is connected to the gate of the second N-channel transistor MN2; the source of the sixth P-channel transistor MP6 is connected to the power supply VDD, The drain of the sixth P-channel transistor MP6 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is grounded; the source of the second N-channel transistor MN2 is connected to the drain of the third N-channel transistor MN3, and the drain of the second N-channel transistor MN2 is connected to the first end of the capacitor C1; the gate of the third N-channel transistor MN3 is connected to the positive electrode of the second current source I2 through the A5 port, and the source of the third N-channel transistor MN3 is grounded; the gate and drain of the fourth N-channel transistor MN4 are both connected to the positive electrode of the second current source I2, and the source of the fourth N-channel transistor MN4 is grounded; the negative electrode of the second current source I2 is connected to the power supply VDD; the input end of the fourth inverter INV4 is connected to the first end of the capacitor C1, the output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5, the output end of the fifth inverter INV5 is connected to the input end of the sixth inverter INV6, and the output end of the sixth inverter INV6 is used to output the second signal V1. It should be noted that the fourth inverter INV4 is a Schmitt inverter.

[0059] When the first signal and the target signal are the same, the second XOR gate outputs a low level, the second N-channel transistor is turned off, the sixth P-channel transistor is turned on, and the sixth P-channel transistor whose source is connected to the power supply will charge the capacitor faster. When the first signal and the target signal are different, the second XOR gate outputs a high level, the second N-channel transistor is turned on, the sixth P-channel transistor is turned off, and the second current source will discharge the capacitor more slowly through the second N-channel transistor whose source is grounded.

[0060] Therefore, by adopting the above-mentioned adjustment module, the discharge of the capacitor is realized through the second current source, and the charging of the capacitor is realized through the sixth P-channel transistor whose source is connected to the power supply, so that the speed of charging the capacitor is greater than the speed of discharging the capacitor. The structure is simple, the cost is low, and it is easy to implement.

[0061] Based on this, in a possible implementation, Figure 5 As shown, the adjustment module also includes a fifth N-channel transistor MN5 and a sixth N-channel transistor MN6; the gate of the fifth N-channel transistor MN5 is connected to the output end of the sixth inverter INV6 through the A0 port, the source of the fifth N-channel transistor MN5 is connected to the drain of the sixth N-channel transistor MN6, and the drain of the fifth N-channel transistor MN5 is connected to the source of the second N-channel transistor MN2; the gate of the sixth N-channel transistor MN6 is connected to the positive electrode of the second current source I2 through the A5 port, and the source of the sixth N-channel transistor MN6 is grounded.

[0062] Thus, when the first signal and the target signal are different, the second XOR gate outputs a high level, the second N-channel transistor is turned on, the sixth P-channel transistor is turned off, and the second current source discharges the capacitor more slowly through the second N-channel transistor with the source grounded. When the first end of the capacitor is lowered to the output end of the fourth inverter outputs a high level, the output end of the sixth inverter outputs a high level, the fifth N-channel transistor is turned on, and the sixth N-channel transistor is also in the on state. The fifth N-channel transistor and the sixth N-channel transistor also discharge the capacitor, so as to reduce the possibility that the voltage at the first end of the capacitor cannot be maintained due to the slow discharge of the capacitor while the first end of the capacitor is maintained at a low level.

[0063] Optionally, the speed of discharging the capacitor can be adjusted by changing the capacitance value of the capacitor, the output current value of the second current source and / or the size of the third N-channel transistor, thereby adjusting the voltage change speed of the first end of the capacitor. The undervoltage protection circuit can also shield voltage glitches of different sizes, thereby improving the applicability of the undervoltage protection circuit.

[0064] In one possible implementation, Figure 6As shown, the flip module includes an eighth inverter INV8, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4 and a ninth inverter INV9; the input end of the eighth inverter INV8 is connected to the output end of the seventh inverter INV7 through the A1 port, so that the input end of the eighth inverter INV8 is used to input the first signal V0, the output end of the eighth inverter INV8 is connected to the first input end of the first NAND gate NAND1, the second input end of the first NAND gate NAND1 is connected to the output end of the third inverter INV3 through the A0 port, or is connected to the output end of the sixth inverter INV6 through the A0 port, so that the second input end of the first NAND gate NAND1 is used to input the second signal V1, the first input end of the second NAND gate NAND2 is used to input the first signal V0, and the second NAND gate N The second input end of AND2 is connected to the output end of the third inverter INV3 through the A0 port, or is connected to the output end of the sixth inverter INV6 through the A0 port, so that the second input end of the second NAND gate NAND2 is used to input the second signal V1, the output end of the first NAND gate NAND1 is connected to the first input end of the third NAND gate NAND3, the output end of the second NAND gate NAND2 is connected to the first input end of the fourth NAND gate NAND4, the second input end of the third NAND gate NAND3 is connected to the output end of the fourth NAND gate NAND4, the second input end of the fourth NAND gate NAND4 is connected to the output end of the third NAND gate NAND3, the output end of the third NAND gate NAND3 is connected to the input end of the ninth inverter INV9, and the output end of the ninth inverter INV9 is the output end of the above-mentioned flip module for outputting the target signal UVLO2.

[0065] Therefore, through the above-mentioned flip module, no matter whether the current level value of the target signal is low or high, after the level value of the second signal flips from low to high, the level value of the target signal can be flipped. The structure is simple, the cost is low, and it is easy to implement.

[0066] It should be noted that the N-channel transistor in this article is usually NMOS, and the P-channel transistor is usually PMOS.

[0067] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the existence of other identical factors in the process, method, article or device including the elements.

[0068] Not all steps and modules in the above-mentioned processes and system structure diagrams are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in the above-mentioned embodiments can be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or some components in multiple independent devices may be implemented together.

[0069] In the above embodiments, the hardware module can be implemented mechanically or electrically. For example, a hardware module can include permanent dedicated circuits or logic (such as special processors, FPGA or ASIC) to complete the corresponding operation. The hardware module can also include programmable logic or circuits (such as general-purpose processors or other programmable processors), which can be temporarily set by software to complete the corresponding operation. The specific implementation method (mechanical method, or dedicated permanent circuit, or temporarily set circuit) can be determined based on cost and time considerations.

[0070] The present application is presented and described in detail above through the accompanying drawings and preferred embodiments; however, the present application is not limited to these disclosed embodiments, and those skilled in the art may know based on the above-mentioned multiple embodiments that the code review methods in the above-mentioned different embodiments may be combined to obtain more embodiments of the present application, and these embodiments are also within the protection scope of the present application.

Claims

1. An undervoltage protection circuit, characterized in that: include: Input module, adjustment module, capacitor and flip module; The input module is connected to a power source, the adjustment module and the flip module are both connected to the input module, and the adjustment module is connected to the capacitor; The input module is used to output a first signal to the adjustment module and the flip module according to the output voltage of the power supply; The adjustment module is used to charge or discharge the capacitor according to the first signal and the target signal output by the flip module, and output a second signal to the flip module based on the voltage across the capacitor; The flip module is used to output the target signal according to the first signal and the second signal, wherein when the output voltage of the power supply is less than a first voltage threshold, the target signal indicates that the power supply is in an undervoltage state, and when a voltage glitch occurs in the output voltage of the power supply, the target signal is kept unchanged.

2. The circuit according to claim 1, characterized in that The input module is configured to output the first signal having a low level value to the adjustment module and the flip module when the output voltage of the power supply is less than the first voltage threshold, and to output the first signal having a high level value to the adjustment module and the flip module when the output voltage is greater than the first voltage threshold; The adjustment module is used to discharge the capacitor when the level values ​​of the first signal and the target signal are the same so as to reduce the voltage difference across the capacitor, charge the capacitor when the level values ​​of the first signal and the target signal are different so as to increase the voltage difference across the capacitor, and output a second signal with a high level value when the voltage difference across the capacitor is equal to or greater than a second voltage threshold, and output a second signal with a low level value when the voltage difference across the capacitor is less than the second voltage threshold, wherein the speed at which the adjustment module discharges the capacitor is greater than the speed at which the capacitor is charged; The flip module is used to flip the level value of the target signal after the level value of the second signal flips from a low level to a high level.

3. The circuit according to claim 2, characterized in that The adjustment module includes a first XOR gate, a first inverter, a first N-channel transistor, a first P-channel transistor, a second P-channel transistor, a third P-channel transistor, a first current source, a second inverter, and a third inverter; The first input terminal of the first XOR gate is used to input the first signal, the second input terminal of the first XOR gate is used to input the target signal, the output terminal of the first XOR gate is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the gate of the first N-channel transistor, and is connected to the gate of the first P-channel transistor; The source of the first N-channel transistor is grounded, the drain of the first N-channel transistor is connected to the first end of the capacitor, and the second end of the capacitor is grounded; the source of the first P-channel transistor is connected to the drain of the second P-channel transistor, and the drain of the first P-channel transistor is connected to the first end of the capacitor; the gate of the second P-channel transistor is connected to the gate of the third P-channel transistor, and the source of the second P-channel transistor is connected to the power supply; the source of the third P-channel transistor is connected to the power supply, the drain of the third P-channel transistor is connected to the negative electrode of the first current source, and is connected to the gate of the third P-channel transistor, and the positive electrode of the first current source is grounded; The input end of the second inverter is connected to the first end of the capacitor, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter is used to output the second signal.

4. The circuit according to claim 3, characterized in that The adjustment module also includes a fourth P-channel transistor and a fifth P-channel transistor; The gate of the fourth P-channel transistor is connected to the output terminal of the second inverter, the source of the fourth P-channel transistor is connected to the power supply, and the drain of the fourth P-channel transistor is connected to the source of the fifth P-channel transistor; A gate of the fifth P-channel transistor is connected to a gate of the third P-channel transistor, and a drain of the fifth P-channel transistor is connected to a source of the first P-channel transistor.

5. The circuit according to claim 1, characterized in that The input module is configured to output the first signal having a low level value to the adjustment module and the flip module when the output voltage of the power supply is less than the first voltage threshold, and to output the first signal having a high level value to the adjustment module and the flip module when the output voltage is greater than the first voltage threshold; The adjustment module is used to charge the capacitor when the level values ​​of the first signal and the target signal are the same, so that the voltage difference across the capacitor increases; discharge the capacitor when the level values ​​of the first signal and the target signal are different, so that the voltage difference across the capacitor decreases; and output a second signal with a low level value when the voltage difference across the capacitor is equal to or greater than a second voltage threshold, and output a second signal with a high level value when the voltage difference across the capacitor is less than the second voltage threshold, wherein the speed at which the adjustment module charges the capacitor is greater than the speed at which the adjustment module discharges the capacitor; The flip module is used to flip the level value of the target signal after the level value of the second signal flips from a low level to a high level.

6. The circuit according to claim 5, characterized in that The adjustment module includes a second XOR gate, a sixth P-channel transistor, a second N-channel transistor, a third N-channel transistor, a fourth N-channel transistor, a second current source, a fourth inverter, a fifth inverter and a sixth inverter; The first input terminal of the second XOR gate is used to input the first signal, the second input terminal of the second XOR gate is used to input the target signal, and the output terminal of the second XOR gate is connected to the gate of the sixth P-channel transistor and to the gate of the second N-channel transistor; The source of the sixth P-channel transistor is connected to the power supply, the drain of the sixth P-channel transistor is connected to the first end of the capacitor, and the second end of the capacitor is grounded; the source of the second N-channel transistor is connected to the drain of the third N-channel transistor, and the drain of the second N-channel transistor is connected to the first end of the capacitor; the gate of the third N-channel transistor is connected to the positive electrode of the second current source, and the source of the third N-channel transistor is grounded; the gate and drain of the fourth N-channel transistor are both connected to the positive electrode of the second current source, and the source of the fourth N-channel transistor is grounded; The negative electrode of the second current source is connected to the power supply; The input end of the fourth inverter is connected to the first end of the capacitor, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is used to output the second signal.

7. The circuit according to claim 6, characterized in that The adjustment module also includes a fifth N-channel transistor and a sixth N-channel transistor; The gate of the fifth N-channel transistor is connected to the output terminal of the sixth inverter, the source of the fifth N-channel transistor is connected to the drain of the sixth N-channel transistor, and the drain of the fifth N-channel transistor is connected to the source of the second N-channel transistor; A gate of the sixth N-channel transistor is connected to a positive electrode of the second current source, and a source of the sixth N-channel transistor is grounded.

8. The circuit according to any one of claims 2 to 7, characterized in that: After the output voltage of the power supply increases from a state less than the first voltage threshold to a state greater than the first voltage threshold, the first voltage threshold is reduced; after the output voltage of the power supply decreases from a state greater than the first voltage threshold to a state less than the first voltage threshold, the first voltage threshold is increased.

9. The circuit according to any one of claims 8, characterized in that The input module includes a first resistor, a second resistor, a third resistor, a comparator, a seventh inverter and a seventh N-channel transistor; The first end of the first resistor is connected to the power supply, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded; The non-inverting input terminal of the comparator is connected to a reference voltage, the inverting input terminal of the comparator is connected between the first resistor and the second resistor, the output terminal of the comparator is connected to the input terminal of the seventh inverter, and the output terminal of the seventh inverter is used to output the first signal; A source of the seventh N-channel transistor is grounded, a drain of the seventh N-channel transistor is connected between the second resistor and the third resistor, and a gate of the seventh N-channel transistor is connected to an output end of the seventh inverter.

10. The circuit according to any one of claims 2 to 7, characterized in that: The flip module includes an eighth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate and a ninth inverter; The input end of the eighth inverter is used to input the first signal, the output end of the eighth inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is used to input the second signal, the first input end of the second NAND gate is used to input the first signal, the second input end of the second NAND gate is used to input the second signal, the output end of the first NAND gate is connected to the first input end of the third NAND gate, the output end of the second NAND gate is connected to the first input end of the fourth NAND gate, the second input end of the third NAND gate is connected to the output end of the fourth NAND gate, the second input end of the fourth NAND gate is connected to the output end of the third NAND gate, the output end of the third NAND gate is connected to the input end of the ninth inverter, and the output end of the ninth inverter is used to output the target signal.

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