Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display, a channel region of an anode reset transistor of an ith row of pixel circuits in the same column of pixel circuits is directly connected with a channel region of a gate reset transistor of an (i + 1) th row of pixel circuits through a first connecting part located on an active layer, so that the pixel circuits in the i + 1 row of pixel circuits in the same column of pixel circuits are directly connected. As long as the first connecting part is electrically connected with the reference voltage line, the reference voltage line can be electrically connected with the anode reset transistor of the pixel circuit in the ith row and the grid reset transistor of the pixel circuit in the (i + 1) th row in the pixel circuits in the same column through the first connecting part. Therefore, the number of holes in electrical connection between the reference voltage line and the anode reset transistor of the pixel circuit in the ith row and the grid reset transistor of the pixel circuit in the (i + 1) th row in the same column of pixel circuits can be reduced, the occupied space of the pixel circuits is saved, and the display panel can be developed towards the direction of high pixel density and high resolution.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, the display panel can display images according to different refresh frequencies. When high-speed driving is required, the pixel circuit can be driven by increasing the refresh frequency. When power consumption needs to be reduced or low-speed driving is required, the pixel circuit can be driven by reducing the refresh frequency. The pixel circuit then drives the light-emitting element to emit light.

[0003] However, when the refresh frequency is reduced to drive the pixel circuit, the leakage current of the pixel circuit will be more serious due to the low refresh frequency, and the display panel is prone to screen shaking. Therefore, different designs and improvements are needed for the pixel circuit working at a low frequency. For example, the scanning lines can be increased and the driving mode of the pixel circuit working at a low frequency can be changed to improve the screen shaking phenomenon of the display panel; for another example, the area of ​​the storage capacitor in the pixel circuit can be increased, which can also improve the screen shaking phenomenon of the display panel. However, these methods will require the pixel circuit working at a low frequency to occupy a larger space, which is not conducive to the development of the display panel towards high pixel density and high resolution. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a display panel and a display device to reduce the space occupied by pixel circuits operating at low frequencies, which is conducive to the development of display panels towards high pixel density and high resolution.

[0005] To achieve the above objectives, the present application provides the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a display panel, the display panel comprising:

[0007] substrate substrate;

[0008] An active layer, located on one side of the substrate base;

[0009] A plurality of pixel circuits are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect;

[0010] A plurality of first scan lines, a plurality of second scan lines and a plurality of reference voltage lines, wherein the first scan lines, the second scan lines and the reference voltage lines extend along a first direction;

[0011] The pixel circuit includes a gate reset transistor and an anode reset transistor; the gate reset transistor includes a first channel region located in the active layer, and the first channel region overlaps with the first scan line in a direction perpendicular to the plane where the substrate is located; the anode reset transistor includes a second channel region located in the active layer, and the second channel region overlaps with the second scan line in a direction perpendicular to the plane where the substrate is located;

[0012] For the same column of pixel circuits, the second channel region of the anode reset transistor in the i-th row of pixel circuits and the first channel region of the gate reset transistor in the i+1-th row of pixel circuits are directly connected through a first connection portion, the first connection portion is located in the active layer, and the reference voltage line is electrically connected to the first connection portion, where i is a positive integer.

[0013] In a second aspect, an embodiment of the present application provides a display device, comprising the above-mentioned display panel.

[0014] Compared with the prior art, the above technical solution has the following advantages:

[0015] The display panel provided in the embodiment of the present application directly connects the second channel region of the anode reset transistor of the i-th row pixel circuit in the same column of pixel circuits and the first channel region of the gate reset transistor of the i+1-th row pixel circuit through the first connection portion located in the same active layer. Therefore, as long as the first connection portion is electrically connected to the reference voltage line, the reference voltage line can be electrically connected to the anode reset transistor of the i-th row pixel circuit in the same column of pixel circuits and the gate reset transistor of the i+1-th row pixel circuit through the first connection portion. In this way, the number of holes for electrically connecting the reference voltage line to the anode reset transistor of the i-th row pixel circuit in the same column of pixel circuits and the gate reset transistor of the i+1-th row pixel circuit can be reduced, thereby saving the space occupied by the pixel circuit. If the pixel circuit operates in a low-frequency driving mode, the space occupied by the pixel circuit operating at a low frequency can be reduced, which is conducive to the development of the display panel towards high pixel density and high resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic cross-sectional structure diagram of a display panel provided in an embodiment of the present application;

[0018] Figure 2 A schematic top view of a display panel provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of a circuit structure of a pixel circuit in a display panel provided in an embodiment of the present application;

[0020] Figure 4 To provide Figure 3 A timing diagram of various signals of the pixel circuit shown;

[0021] Figure 5 A schematic diagram of the layout structure of two adjacent rows of pixel circuits in a column of pixel circuits in a display panel provided in an embodiment of the present application;

[0022] Figure 6 for Figure 5 A magnified schematic diagram of a local area;

[0023] Figure 7 for Figure 5 A schematic diagram of the circuit structure of two adjacent rows of pixel circuits in the same column of pixel circuits shown;

[0024] Figure 8 To provide Figure 7 A timing diagram of each signal of two adjacent rows of pixel circuits in the same column of pixel circuits shown;

[0025] Fig. 9 A schematic diagram of the layout structure of two adjacent rows of pixel circuits in a column of pixel circuits in another display panel provided by an embodiment of the present application;

[0026] Fig.10 for Fig. 9 A magnified schematic diagram of a local area;

[0027] Fig.11 for Fig. 9 A schematic diagram of the circuit structure of two adjacent rows of pixel circuits in the same column of pixel circuits shown;

[0028] Fig.12 A schematic diagram of the layout structure of three adjacent rows of pixel circuits in a column of pixel circuits in another display panel provided in an embodiment of the present application;

[0029] Fig.13 for Fig.12 A magnified schematic diagram of a local area;

[0030] Fig.14 for Fig.12 The circuit structure diagram of three adjacent rows of pixel circuits in the same column of pixel circuits shown;

[0031] Fig.15 To provide Fig.14 A timing diagram of each signal of three adjacent rows of pixel circuits in the same column of pixel circuits shown;

[0032] Fig.16 A schematic top view of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0035] Figure 1 A schematic cross-sectional structure diagram of a display panel provided in an embodiment of the present application is shown. Figure 1 As shown, the display panel includes a substrate sub, an active layer poly located on one side of the substrate sub, a multi-layer metal layer located on the side of the active layer poly away from the substrate sub, and an oxide layer IGZO, wherein the multi-layer metal layer includes a metal layer M1, a metal layer MC, a metal layer MG, a metal layer M2, a metal layer M3, a metal layer M4 and a metal layer RE arranged in a direction away from the substrate sub, the oxide layer IGZO is located between the metal layer MC and the metal layer MG, and different metal layers, between the metal layer and the active layer, and between the metal layer and the oxide layer are all isolated by insulating layers.

[0036] Figure 2 A schematic top view of a display panel provided in an embodiment of the present application is shown. Figure 2 As shown, the display panel includes a plurality of pixel circuits 10, and the plurality of pixel circuits 10 are arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y intersect, and the first direction X and the second direction Y are parallel to the plane where the substrate is located.

[0037] like Figure 2 As shown, the display panel further includes a plurality of first scan lines SN1, a plurality of second scan lines SP and a plurality of reference voltage lines Ref, and the first scan lines S1, the second scan lines SP and the reference voltage lines Ref extend along a first direction X.

[0038] Combination Figure 1 and Figure 2As shown, the pixel circuit 10 is located on the substrate sub, mainly distributed in the active layer poly and some metal layers, the signal lines 20 electrically connected to the pixel circuit 10 such as the first scan line SN1, the second scan line SN2 and the reference voltage line Ref are located in some metal layers, the light-emitting element 30 is located on the side of the pixel circuit 10 away from the substrate sub, and the pixel circuit 10 is used to drive the light-emitting element 30 to emit light.

[0039] Figure 3 FIG. 1 shows a schematic diagram of a circuit structure of a pixel circuit 10 in a display panel provided in an embodiment of the present application. Figure 3 As shown, the pixel circuit 10 includes a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a gate reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7 and a storage capacitor Cst, and the signal line 20 electrically connected to the pixel circuit 10 includes a first scan line SN1, a second scan line SP, a third scan line SN2, a light-emitting control line Emit, a data line data and a first power supply voltage line PVDD, the pixel circuit 10 is electrically connected to the anode of the light-emitting element 30, and the cathode of the light-emitting element 30 is electrically connected to the second power supply voltage line PVEE.

[0040] The first electrode of the first light emitting control transistor T1 is electrically connected to the first power supply voltage line PVDD, the second electrode of the first light emitting control transistor T1 is electrically connected to the second node N2, and the gate of the first light emitting control transistor T1 is electrically connected to the light emitting control line Emit;

[0041] A first electrode of the data writing transistor T2 is electrically connected to the data line data, a second electrode of the data writing transistor T2 is electrically connected to the second node N2, and a gate of the data writing transistor T2 is electrically connected to the second scanning line SP;

[0042] A first electrode of the driving transistor T3 is electrically connected to the second node N2, a second electrode of the driving transistor T3 is electrically connected to the third node N3, and a gate of the driving transistor T3 is electrically connected to the first node N1;

[0043] A first electrode of the compensation transistor T4 is electrically connected to the third node N3, a second electrode of the compensation transistor T4 is electrically connected to the first node N1, and a gate of the compensation transistor T4 is electrically connected to the third scan line SN2;

[0044] A first electrode of the gate reset transistor T5 is electrically connected to the reference voltage line Ref, a second electrode of the gate reset transistor T5 is electrically connected to the first node N1, and a gate of the gate reset transistor T5 is electrically connected to the first scan line SN1;

[0045] A first electrode of the second light emitting control transistor T6 is electrically connected to the third node N3, a second electrode of the second light emitting control transistor T6 is electrically connected to the fourth node N4, and a gate of the second light emitting control transistor T6 is electrically connected to the light emitting control line Emit;

[0046] A first electrode of the anode reset transistor T7 is electrically connected to the reference voltage line Ref, a second electrode of the anode reset transistor T7 is electrically connected to the fourth node N4, and a gate of the anode reset transistor T7 is electrically connected to the second scan line SP;

[0047] Thus, the pixel circuit 10 with a 7T1C structure is realized.

[0048] It can be understood that the first node N1, the second node N2, the third node N3 and the fourth node N4 may be virtually existing connection nodes or actually existing connection nodes.

[0049] It should be noted that Figure 3 The pixel circuit 10 shown is only an example. In practical applications, pixel circuits with other circuit structures can be selected based on needs, and are not limited to Figure 3 The 7T1C pixel circuit shown.

[0050] It should also be noted that, combined with Figure 1 and Figure 3 As shown, for each thin film transistor in the pixel circuit 10, it can be a low temperature polycrystalline silicon (Low Temperature Polycrystalline, LTPS) thin film transistor Qx, specifically, the LTPS thin film transistor Qx includes an active layer b1, a gate g, a source electrode s1 and a drain electrode d1, or it can be an indium gallium zinc oxide (IndiumGalliumZincOxide, IGZO) thin film transistor Qy, specifically, the IGZO thin film transistor Qy includes an oxide layer b2, a bottom gate dg, a top gate tg, a source electrode s2 and a drain electrode d2.

[0051] Optional, combined Figure 1 and Figure 3 As shown, in the pixel circuit 10, the compensation transistor T4 and the gate reset transistor T5 can be IGZO thin film transistors, having a double gate structure of a bottom gate dg and a top gate tg, and other thin film transistors can be LTPS thin film transistors. Since the IGZO thin film transistor has less leakage, the pixel circuit 10 can achieve low-frequency driving, that is, a low-frequency pixel circuit. At this time, each thin film transistor in the pixel circuit 10 can be a PMOS thin film transistor.

[0052] Alternatively, all thin film transistors in the pixel circuit 10 may be LTPS thin film transistors. In this case, the compensation transistor T4 and the gate reset transistor T5 may be NMOS thin film transistors, and the other thin film transistors may be PMOS thin film transistors.

[0053] like Figure 3 As shown, the compensation transistor T4 and the gate reset transistor T5 may be transistors with a double-gate structure or a multi-gate structure, so as to reduce the leakage current of the transistors and improve the display effect of the display panel.

[0054] Figure 4 Shows the provided Figure 3 A timing diagram of each signal of the pixel circuit 10 shown in FIG. Figure 3 and Figure 4 As shown, the first scan line SN1 provides the first scan signal VSN1 to the pixel circuit 10, the second scan line SP provides the second scan signal VSP to the pixel circuit 10, the third scan line SN2 provides the third scan signal VSN2 to the pixel circuit 10, the light-emitting control line Emit provides the light-emitting control signal VEmit to the pixel circuit 10, the reference voltage line Ref provides the reference voltage signal VRef to the pixel circuit 10, the first power supply voltage line PVDD provides the first power supply voltage signal VPVDD to the pixel circuit 10, and the second power supply voltage line PVEE provides the second power supply voltage signal VPVEE. Taking the case that all thin film transistors in the pixel circuit 10 are PMOS thin film transistors as an example, the effective levels of the first scan signal VSN1, the second scan signal VSP, the third scan signal VSN2 and the light-emitting control signal VEmit are low levels, and the invalid levels are high levels. For the convenience of description, in the subsequent structural drawings of the pixel circuit 10 of this application, each signal is used instead of the corresponding signal line to represent the electrical connection relationship with the pixel circuit 10.

[0055] Combination Figure 3 and Figure 4 As shown, the working process of the pixel circuit 10 is roughly divided into the following periods, wherein:

[0056] During period t1, the first scanning signal VSN1 is at an effective level (low level), turning on the gate reset transistor T5, and the reference voltage signal VRef provided by the reference voltage line Ref resets the first node N1 (ie, the gate of the driving transistor T3) through the turned-on gate reset transistor T5.

[0057] During the t2 period, the third scanning signal VSN2 is at a valid level (low level), turning on the compensation transistor T4, and the second scanning signal VSP is at a valid level (low level), turning on the data writing transistor T2, and writing the data signal Vdata provided by the data line data into the gate of the driving transistor T3, also known as the threshold capture of the driving transistor T3; during the t2 period, the second scanning signal VSP is at a valid level (low level), and also turning on the anode reset transistor T7, and the reference voltage signal VRef provided by the reference voltage line Ref resets the fourth node N4 through the turned-on anode reset transistor T7.

[0058] During the period t3 , the light emission control signal VEmit is at an effective level (low level), the first light emission control transistor T1 and the second light emission control transistor T6 are turned on, and the driving transistor T3 drives the light emitting element 30 to emit light.

[0059] In the display panel, the light emitting control signal VEmit scans each row of pixel circuits at a fixed frequency, such as Figure 4 As shown, the total period during which the light-emitting control signal Emit undergoes a valid level period and an invalid level period is called a frame, a frame including periods t1, t2 and t3 is called a data writing frame P1, and the total period during which all rows of pixel circuits in the display panel complete the writing of data signals is called a data writing cycle. In this way, a data writing cycle of the display panel includes M frames of refresh screen, M≥2, and the M frames include a data writing frame P1 and at least one holding frame P2, wherein, in the data writing frame P1, the pixel circuit 10 writes a new data signal to display a new frame of screen; in the holding frame P2, the pixel circuit 10 is refreshed normally, but the pixel circuit 10 maintains the data signal of the previous frame to display the previous frame of screen.

[0060] As described in the background technology section, when the refresh frequency is reduced to drive the pixel circuit, due to the low refresh frequency, the leakage current of the pixel circuit will be more serious, and the display panel is prone to screen shaking. Figure 3 and Figure 4As shown, in the pixel circuit 10, a gate reset transistor T5 is electrically connected to the first scan line SN1, so that the gate reset transistor T5 is driven by the first scan signal VSN1; an anode reset transistor T7 is electrically connected to the second scan line SP, so that the anode reset transistor T7 is driven by the second scan signal VSP; a compensation transistor T4 is electrically connected to the third scan line SN2, so that the compensation transistor T4 is driven by the third scan signal VSN2; in this way, under low-frequency driving, in the holding frame P2 stage of the pixel circuit 10, the first scan signal VSN1 and the third scan signal VSN2 can be kept at an invalid level, so that the gate reset transistor T5 and the compensation transistor T4 are turned off, thereby keeping the potential of the first node N1 unchanged, and the second scan signal VSP can still turn on the anode reset transistor T7 to reset the fourth node N4, thereby improving the screen jitter phenomenon of the display panel under low-frequency driving.

[0061] Figure 5 A schematic diagram of the layout structure of two adjacent rows of pixel circuits 10 in a column of pixel circuits in a display panel provided by an embodiment of the present application is shown, combined with Figure 1 , Figure 3 and Figure 5 As shown, the pixel circuit 10 includes a gate reset transistor T5 and an anode reset transistor T7. The gate reset transistor T5 includes a first channel region C1 located in the active layer poly. In a direction perpendicular to the plane where the substrate sub is located, the first channel region C1 overlaps with the first scan line SN1, and the overlapping portion of the first scan line SN1 and the first channel region C1 is the gate of the gate reset transistor T5; the anode reset transistor T7 includes a second channel region C2 located in the active layer poly. In a direction perpendicular to the plane where the substrate sub is located, the second channel region C2 overlaps with the second scan line SP, and the overlapping portion of the second scan line SP and the second channel region C2 is the gate of the anode reset transistor T7.

[0062] In order to understand this application more clearly, Figure 6 Shows Figure 5 The enlarged schematic diagram of the local area in Figure 5 and Figure 6As shown, for the same column of pixel circuits, the second channel region C2 of the anode reset transistor T7 in the i-th row of pixel circuits 10 and the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits are directly connected through the first connection portion L1, and the first connection portion L1 is located in the active layer poly. In other words, the second channel region C2 of the anode reset transistor T7 of the i-th row of pixel circuits 10 in the same column of pixel circuits 10 is located in the active layer poly and directly connected to the first connection portion L1, and the first channel region C1 of the gate reset transistor T5 of the i+1-th row of pixel circuits 10 in the same column of pixel circuits 10 is also located in the active layer poly and directly connected to the first connection portion L1, so that the second channel region C2 of the anode reset transistor T7 in the i-th row of pixel circuits 10 in the same column of pixel circuits 10 is directly connected to the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits 10 through the first connection portion L1 of the same layer. In other words, the second channel region C2 of the anode reset transistor T7 of the pixel circuit 10 in the i-th row and the first channel region C1 of the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the same column of pixel circuits are directly connected in the active layer poly through the first connection portion L1, where i is a positive integer.

[0063] And, if Figure 5 and Figure 6 As shown, the first connection portion L1 is electrically connected to the reference voltage line Ref, so that the reference voltage line Ref can be electrically connected to the anode reset transistor T7 of the i-th row pixel circuit 10 and the gate reset transistor T5 of the i+1-th row pixel circuit 10 in the same column of pixel circuits through the first connection portion L1.

[0064] In this way, the number of holes for electrically connecting the reference voltage line Ref with the anode reset transistor T7 of the pixel circuit 10 in the i-th row and the gate reset transistor T5 of the pixel circuit in the i+1-th row in the same column of pixel circuits can be reduced, thereby saving the space occupied by the pixel circuit 10. If the pixel circuit 10 operates in a low-frequency driving mode, the space occupied by the low-frequency operating pixel circuit can be reduced, which is conducive to the development of the display panel towards high pixel density and high resolution.

[0065] Combination Figure 1 , Figure 5 and Figure 6 As shown, the first scan line SN1 may be located in the metal layer M1, and the second scan line SP may also be located in the metal layer M1.

[0066] Combination Figure 1 , Figure 5 and Figure 6As shown, the reference voltage line Ref may be located in the first metal layer, the first metal layer is located on the side of the active layer poly away from the substrate sub, the first metal layer may be the metal layer MC, and the first connection portion L2 is located in the active layer poly, so that the reference voltage line Ref and the first connection portion L1 are arranged in different layers.

[0067] Combination Figure 1 , Figure 5 and Figure 6 As shown, the reference voltage line Ref is electrically connected to the first connection part L1 through the second connection part L2, the second connection part L2 is located in the second metal layer, and the second metal layer is located on the side of the first metal layer away from the substrate sub. Optionally, the first metal layer is the metal layer MC, the second metal layer is the metal layer M2, the metal layer M2 is located on the side of the metal layer MC away from the substrate sub, and the reference voltage line Ref located in the metal layer MC is electrically connected to the first connection part L1 located in the active layer poly through the second connection part L2 located in the metal layer M2.

[0068] It can be understood from this that the reference voltage line Ref is electrically connected to the second connection part L2 through a via between the first metal layer (i.e., metal layer MC) and the second metal layer (i.e., metal layer M2), and the second connection part L2 is electrically connected to the first connection part L1 through a via between the second metal layer (i.e., metal layer M2) and the active layer poly, and the first connection part L1 is electrically connected to the second channel region C2 of the anode reset transistor T7 of the i-th row pixel circuit 10 in the same column of pixel circuits and the first channel region C1 of the gate reset transistor T5 of the i+1-th row of pixel circuits in the active layer poly. In this way, the reference voltage line Ref only needs to pass through two vias to transmit the reference voltage signal VRef to the second channel region C2 of the anode reset transistor T7 of the i-th row pixel circuit 10 in the same column of pixel circuits and the first channel region C1 of the gate reset transistor T5 of the i+1-th row of pixel circuits.

[0069] In some existing display panels, the second channel region C2 of the anode reset transistor T7 in the pixel circuit 10 of the i-th row in the same column of pixel circuits and the first channel region C1 of the gate reset transistor T5 in the pixel circuit of the i+1th row are disconnected, so that the reference voltage line Ref is electrically connected to the second connection portion L2 through a via hole between the first metal layer (i.e., the metal layer MC) and the second metal layer (i.e., the metal layer M2), and the second connection portion L2 not only needs to be electrically connected to the pixel circuit 10 of the i-th row in the same column of pixel circuits through a via hole between the second metal layer (i.e., the metal layer M2) and the active layer poly, but also needs to be electrically connected to the pixel circuit 10 of the i-th row in the same column of pixel circuits. In order to transmit the reference voltage signal VRef to the second channel region C2 of the anode reset transistor T7 of the pixel circuit 10 in the i-th row in the pixel circuit 10 in the i-th row and the first channel region C1 of the gate reset transistor T5 of the pixel circuit 10 in the i-th row in the pixel circuit 10 in the i-th row, the reference voltage line Ref needs to pass through at least three vias to transmit the reference voltage signal VRef to the second channel region C2 of the anode reset transistor T7 of the pixel circuit 10 in the i-th row in the pixel circuit 10 in the i-th row and the first channel region C1 of the gate reset transistor T5 of the pixel circuit 10 in the i-th row in the pixel circuit 10 in the i-th row.

[0070] It can be seen that the display panel provided in the embodiment of the present application directly connects the second channel region C2 of the anode reset transistor T7 of the i-th row pixel circuit 10 in the same column of pixel circuits and the first channel region C1 of the gate reset transistor T5 of the i+1-th row pixel circuit 10 through the first connection portion L1 located in the active layer poly. In this way, the reference voltage line Ref only needs to pass through two vias to transmit the reference voltage signal VRef to the second channel region C2 of the anode reset transistor T7 of the i-th row pixel circuit 10 in the same column of pixel circuits and the first channel region C1 of the gate reset transistor T5 of the i+1-th row pixel circuit, which can save the space occupied by the pixel circuit. In particular, considering that the number of pixel circuits in the display panel is huge, reducing one hole in the space occupied by each pixel circuit can improve the pixel density of the display panel, and thus improve the resolution of the display panel.

[0071] like Figure 5 As shown, a row of pixel circuits 10 is electrically connected to a first scan line SN1 and a second scan line SP, and the first scan line SN1 and the second scan line SP are alternately arranged along the second direction Y; the reference voltage line Ref is located between the second scan line SP electrically connected to the i-th row of pixel circuits 10 and the first scan line SN1 electrically connected to the i+1-th row of pixel circuits 10; thus, along the second direction Y, the first scan line SN1, the second scan line SP and the reference voltage line Ref are arranged in sequence.

[0072] like Figure 5As shown, for the same column of pixel circuits, the second channel region C2 of the anode reset transistor T7 in the i-th row pixel circuit 10 and the first channel region C1 of the gate reset transistor T5 in the (i+1)-th row pixel circuit 10 are located on opposite sides of the reference voltage line Ref along the second direction Y.

[0073] Combination Figure 5 and Figure 6 As shown, one end of the second connection part L2 is electrically connected to the reference voltage line Ref through the first via hole K1; the other end of the second connection part L2 is electrically connected to the first connection part L1 through the second via hole K2; the first via hole K1 and the second via hole K2 are located between the second scan line SP electrically connected to the pixel circuit 10 of the i-th row and the first scan line SN1 electrically connected to the pixel circuit 10 of the i+1-th row.

[0074] It can be understood that in a direction perpendicular to the plane of the substrate, the second connection portion L2 at least partially overlaps with the reference voltage line Ref, so that the second connection portion L2 and the reference voltage line Ref are electrically connected through the first via K1 between the first metal layer (such as metal layer MC) and the second metal layer (such as metal layer M2).

[0075] Similarly, in a direction perpendicular to the plane of the substrate, the second connection portion L2 also at least partially overlaps with the first connection portion L1, so that the second connection portion L2 and the first connection portion L1 are electrically connected through a second via K2 between the second metal layer (such as metal layer M2) and the active layer poly.

[0076] Combination Figure 5 and Figure 6 As shown, the first via hole K1 and the second via hole K2 may overlap, so that the length of the second connection portion L2 may be shorter, which may further save the space occupied by the pixel circuit.

[0077] Combination Figure 5 and Figure 6As shown, the gate reset transistor T5 in the pixel circuit 10 may include a first sub-transistor T51, a second sub-transistor T52 and a third sub-transistor T53; the first channel region C1 of the gate reset transistor T5 includes a first sub-channel region C11 of the first sub-transistor T51, a second sub-channel region C12 of the second sub-transistor T52 and a third sub-channel region C13 of the third sub-transistor T53, in a direction perpendicular to the plane where the substrate is located, the first sub-channel region C11, the second sub-channel region C12 and the third sub-channel region C13 all overlap with the first scan line SN1, the portion where the first scan line SN1 overlaps with the first sub-channel region C11 is the gate of the first sub-transistor T51, the portion where the first scan line SN1 overlaps with the second sub-channel region C12 is the gate of the second sub-transistor T52, and the portion where the first scan line SN1 overlaps with the third sub-channel region C13 is the gate of the third sub-transistor T53.

[0078] Combination Figure 5 and Figure 6 As shown, one end of the first sub-channel region C11 is directly connected to the first connection portion L1, the other end of the first sub-channel region C11 is directly connected to one end of the second sub-channel region C12 through the first sub-connection portion D1 located in the active layer poly, and the other end of the second sub-channel region C12 is directly connected to one end of the third sub-channel region C13 through the second sub-connection portion D2 located in the active layer poly.

[0079] Combination Figure 1 , Figure 5 and Figure 6 As shown, the driving transistor T3 includes a channel region C30 located in the active layer poly and a gate g3 located in the metal layer M1. In a direction perpendicular to the plane where the substrate is located, the gate g3 of the driving transistor T3 overlaps with the channel region C30. Figure 5 As shown, one end of the third sub-channel region C13 in the gate reset transistor T5 away from the second sub-connection portion D2 is electrically connected to the gate g3 of the driving transistor T3 through the connection portion J1.

[0080] From the above, it can be seen that the gate reset transistor T5 includes a first sub-transistor T51, a second sub-transistor T52 and a third sub-transistor T53, that is, the gate reset transistor T5 is a transistor with a three-gate structure, which is beneficial to reduce the leakage current of the gate reset transistor T5 to the gate g3 of the driving transistor T3 to maintain the stability of the gate potential of the driving transistor T3, which is beneficial to improve the screen jitter phenomenon of the display panel under low-frequency driving.

[0081] Combination Figure 5 and Figure 6As shown, in a direction perpendicular to the plane where the substrate is located, the second sub-connection portion D2 and the reference voltage line Ref at least partially overlap, that is, the reference voltage line Ref at least covers a portion of the second sub-connection portion D2, and the reference voltage signal VRef on the reference voltage line Ref is a constant voltage signal, so that the second sub-connection portion D2 and the reference voltage line Ref form a shielding capacitor, so that when the potential change on the first scan line SN1 causes the charge change in the first channel region C1 of the gate reset transistor T5, since the charge in the first channel region C1 of the gate reset transistor T5 can be stored in the shielding capacitor formed by the second sub-connection portion D2 and the reference voltage line Ref, the influence on the gate potential of the driving transistor T3 can be reduced, the stability of the gate potential of the driving transistor T3 is maintained, and the screen shaking phenomenon of the display panel under low-frequency driving is improved. In addition, since the reference voltage line Ref can be located in the metal layer MC, the reference voltage line Ref can also shield the second sub-connection portion D2, which is also conducive to maintaining the stability of the gate potential of the driving transistor T3 and improving the screen shaking phenomenon of the display panel under low-frequency driving.

[0082] Combination Figure 5 and Figure 6 As shown, the display panel includes a plurality of first power supply voltage lines PVDD, and refers to Figure 3 As shown, the display panel also includes a plurality of light emitting elements 30 , and the first power supply voltage line PVDD is electrically connected to the light emitting elements 30 through the pixel circuit 10 .

[0083] like Figure 5 As shown, the first power supply voltage line PVDD extends along the second direction Y. Figure 1 and Figure 5 As shown, the first power supply voltage line PVDD may be located at the metal layer M2. Figure 3 and Figure 5 As shown, the first power supply voltage line PVDD is electrically connected to the first electrode of the first light-emitting control transistor T1 through the connecting portion J2, and is electrically connected to one electrode plate Cst2 of the storage capacitor Cst through the connecting portion J3. The other electrode plate of the storage capacitor Cst is also the gate g3 of the driving transistor T3. The second electrode of the first light-emitting control transistor T1 is electrically connected to the first electrode of the driving transistor T3 in the active layer poly. The second electrode of the driving transistor T3 is electrically connected to the first electrode of the second light-emitting control transistor T6 in the active layer poly. The second electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the anode reset transistor T7 in the active layer poly. The second electrode of the second light-emitting control transistor T6 and the second electrode of the anode reset transistor T7 are electrically connected to the light-emitting element 30 through the connecting portion J4.

[0084] Combination Figure 5 and Figure 6As shown, in the direction perpendicular to the plane where the substrate is located, the second sub-connection portion D2 at least partially overlaps with the first power supply voltage line PVDD, that is, in the direction perpendicular to the plane where the substrate is located, the second sub-connection portion D2 may at least partially overlap with the reference voltage line Ref and / or the first power supply voltage line PVDD. Similar to the overlap of the second sub-connection portion D2 and the reference voltage line Ref in the direction perpendicular to the plane where the substrate is located, the second sub-connection portion D2 and the first power supply voltage line PVDD overlap in the direction perpendicular to the plane where the substrate is located, and the first power supply voltage signal VPVDD on the first power supply voltage line PVDD is a constant voltage signal, then the second sub-connection portion D2 and the first power supply voltage line PVDD may also constitute a shielding capacitor, which may reduce the influence on the gate potential of the driving transistor T3, maintain the stability of the gate potential of the driving transistor T3, and improve the screen shaking phenomenon of the display panel under low-frequency driving. Furthermore, since the first power supply voltage line PVDD can be located in the metal layer M2, the first power supply voltage line PVDD can also shield the second sub-connection portion D2, which is also beneficial to maintaining the stability of the gate potential of the driving transistor T3 and improving the screen jitter phenomenon of the display panel under low-frequency driving.

[0085] Combination Figure 3 and Figure 5 As shown, in the pixel circuit 10 , the compensation transistor T4 may include a sub-transistor T41 and a sub-transistor T42 , the sub-transistor T41 includes a channel region C41 located in the active layer poly, and the sub-transistor T42 includes a channel region C42 located in the active layer poly.

[0086] like Figure 5 As shown, the third scan line SN2 includes a main body portion G3 extending along the first direction X and a protruding portion G4 protruding from the main body portion G3 along the second direction Y.

[0087] like Figure 5 As shown, in the direction perpendicular to the plane where the substrate is located, the channel region C41 overlaps with the protruding portion G4 of the third scan line SN2, and the portion where the protruding portion G4 of the third scan line SN2 overlaps with the channel region C41 is the gate of the sub-transistor T41; in the direction perpendicular to the plane where the substrate is located, the channel region C42 overlaps with the main portion G3 of the third scan line SN2, and the portion where the main portion G3 of the third scan line SN2 overlaps with the channel region C42 is the gate of the sub-transistor T42.

[0088] like Figure 5As shown, one end of the channel region C41 of the sub-transistor T41 is electrically connected to the gate g3 of the driving transistor T3 through the connecting portion J1, the other end of the channel region C41 of the sub-transistor T41 is electrically connected to one end of the channel region C42 of the sub-transistor T42 in the active layer poly, and the other end of the channel region C42 of the sub-transistor T42 is electrically connected to the second electrode of the driving transistor T3 in the active layer poly.

[0089] Since the compensation transistor T4 includes a sub-transistor T41 and a sub-transistor T42, the compensation transistor T4 is a transistor with a dual-gate structure, which is beneficial to reducing the leakage current from the compensation transistor T4 to the gate of the driving transistor T3, so as to maintain the stability of the gate potential of the driving transistor T3 and improve the screen jitter phenomenon of the display panel under low-frequency driving.

[0090] Combination Figure 3 and Figure 5 As shown, the display panel includes multiple data lines data, which extend along the second direction Y. The first electrode of the data writing transistor T2 in the pixel circuit 10 is electrically connected to the data line data through the connecting portion J5, and the second electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T3 in the active layer poly.

[0091] Figure 7 Shows Figure 5 The circuit structure diagram of two adjacent rows of pixel circuits 10 in the same column of pixel circuits shown in FIG. Figure 5 and Figure 7 As shown, a reference voltage line Ref is electrically connected to the anode reset transistor T7 of the pixel circuit 10 in the i-th row in the same column of pixel circuits, and is also electrically connected to the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the same column of pixel circuits. In this way, the reference voltage signal VRef on the reference voltage line Ref can reset the fourth node N4 of the pixel circuit 10 in the i-th row through the anode reset transistor T7 of the pixel circuit 10 in the i-th row in the same column of pixel circuits, and can also reset the first node N1 of the pixel circuit 10 in the i+1-th row through the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the same column of pixel circuits.

[0092] Combination Figure 5 and Figure 7 As shown, in the pixel circuit 10, the gate reset transistor T5 is a transistor with a triple-gate structure, including three sub-transistors; the compensation transistor T4 is a transistor with a double-gate structure, including two sub-transistors.

[0093] Figure 8 It is further shown that Figure 7 A timing diagram of each signal of two adjacent rows of pixel circuits 10 in the same column of pixel circuits shown in FIG. Figure 5, Figure 7 and Figure 8 As shown, for the same column of pixel circuits, the first scanning signal VSN1(i) driving the pixel circuit 10 in the i-th row is first at a valid level, the pixel circuit 10 in the i-th row is in the t1 period, and the gate reset transistor T5 in the pixel circuit 10 in the i-th row is turned on, so that the reference voltage signal VRef(i) provided by the reference voltage line Ref electrically connected to the gate reset transistor T5 in the pixel circuit 10 in the i-th row resets the first node N1 in the pixel circuit 10 in the i-th row.

[0094] Next, the third scanning signal VSN2(i) driving the pixel circuit 10 in the i-th row is at an effective level, the pixel circuit 10 in the i-th row is in the t2 period, and the compensation transistor T4 in the pixel circuit 10 in the i-th row is turned on; and the second scanning signal VSP(i) driving the pixel circuit 10 in the i-th row is at an effective level, so that the data writing transistor T2 of the pixel circuit 10 in the i-th row is turned on, and the data signal is written to the gate of the driving transistor T3 of the pixel circuit 10 in the i-th row; the second scanning signal VSP(i) driving the pixel circuit 10 in the i-th row is at an effective level, and the pixel circuit 10 in the i-th row is turned on. The anode reset transistor T7 of the pixel circuit 10 is turned on, and the fourth node N4 of the i-th row pixel circuit 10 is reset; at the same time, the first scanning signal VSN1(i+1) driving the i+1-th row pixel circuit 10 is at a valid level, the i+1-th row pixel circuit 10 is in the t1 period, and the gate reset transistor T5 in the i+1-th row pixel circuit 10 is turned on, so that the reference voltage signal VRef(i+1) provided by the reference voltage line Ref electrically connected to the gate reset transistor T5 in the i+1-th row pixel circuit 10 resets the first node N1 in the i+1-th row pixel circuit 10.

[0095] Afterwards, the light emission control signal VEmit driving the pixel circuit 10 in the i-th row is at an effective level, so that the pixel circuit 10 in the i-th row enters the t3 period and drives the light emitting element 40 to emit light. In addition, the pixel circuit in the i+1th row also enters the t2 period and the t3 period in sequence.

[0096] It can be seen that when the second scanning signal VSP(i) driving the pixel circuit 10 in the i-th row and the first scanning signal VSN1(i+1) driving the pixel circuit 10 in the i+1-th row are both at the effective level, that is, the anode reset transistor T7 in the pixel circuit 10 in the i-th row and the gate reset transistor T5 in the pixel circuit 10 in the i+1-th row are turned on at the same time, the reference voltage signal VRef on the reference voltage line Ref can reset the fourth node N4 in the pixel circuit 10 in the i-th row through the anode reset transistor T7 in the pixel circuit 10 in the i-th row, and can reset the first node N1 in the pixel circuit 10 in the i+1-th row through the gate reset transistor T5 in the pixel circuit 10 in the i+1-th row.

[0097] Of course, the effective level period of the second scanning signal VSP(i) driving the i-th row pixel circuit 10 may also not overlap with the effective level period of the first scanning signal VSN1(i+1) driving the i+1-th row pixel circuit 10. At this time, the anode reset transistor T7 in the i-th row pixel circuit 10 and the gate reset transistor T5 in the i+1-th row pixel circuit 10 are turned on in a time-sharing manner, and the reference voltage signal VRef on the reference voltage line Ref is used in a time-sharing manner to reset the fourth node N4 in the i-th row pixel circuit 10 through the anode reset transistor T7 in the i-th row pixel circuit 10, and to reset the first node N1 in the i+1-th row pixel circuit 10 through the gate reset transistor T5 in the i+1-th row pixel circuit 10.

[0098] Fig. 9 A schematic diagram of the layout structure of two adjacent rows of pixel circuits 10 in a column of pixel circuits in another display panel provided by an embodiment of the present application is shown, combined with Figure 1 , Figure 3 and Fig. 9 As shown, the pixel circuit 10 includes a gate reset transistor T5 and an anode reset transistor T7. The gate reset transistor T5 includes a first channel region C1 located in the active layer poly. In a direction perpendicular to the plane where the substrate sub is located, the first channel region C1 overlaps with the first scan line SN1, and the overlapping portion of the first scan line SN1 and the first channel region C1 is the gate of the gate reset transistor T5; the anode reset transistor T7 includes a second channel region C2 located in the active layer poly. In a direction perpendicular to the plane where the substrate sub is located, the second channel region C2 overlaps with the second scan line SP, and the overlapping portion of the second scan line SP and the second channel region C2 is the gate of the anode reset transistor T7.

[0099] In order to understand this application more clearly, Fig.10 Shows Fig. 9 The enlarged schematic diagram of the local area in Fig. 9 and Fig.10As shown, for the same column of pixel circuits, the second channel region C2 of the anode reset transistor T7 in the i-th row of pixel circuits 10 and the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits are directly connected through the first connection portion L1, and the first connection portion L1 is located in the active layer poly. In other words, the second channel region C2 of the anode reset transistor T7 of the i-th row of pixel circuits 10 in the same column of pixel circuits 10 is located in the active layer poly and directly connected to the first connection portion L1, and the first channel region C1 of the gate reset transistor T5 of the i+1-th row of pixel circuits 10 in the same column of pixel circuits 10 is also located in the active layer poly and directly connected to the first connection portion L1, so that the second channel region C2 of the anode reset transistor T7 in the i-th row of pixel circuits 10 in the same column of pixel circuits 10 is directly connected to the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits 10 through the first connection portion L1 of the same layer. In other words, the second channel region C2 of the anode reset transistor T7 of the pixel circuit 10 in the i-th row and the first channel region C1 of the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the same column of pixel circuits are directly connected in the active layer poly through the first connection portion L1, where i is a positive integer.

[0100] And, if Fig. 9 and Fig.10 As shown, the first connection portion L1 is electrically connected to the reference voltage line Ref, so that the reference voltage line Ref can be electrically connected to the anode reset transistor T7 of the i-th row pixel circuit 10 and the gate reset transistor T5 of the i+1-th row pixel circuit 10 in the same column of pixel circuits through the first connection portion L1.

[0101] In this way, the number of holes for electrically connecting the reference voltage line Ref with the anode reset transistor T7 of the pixel circuit 10 in the i-th row and the gate reset transistor T5 of the pixel circuit in the i+1-th row in the same column of pixel circuits can be reduced, thereby saving the space occupied by the pixel circuit 10. If the pixel circuit 10 operates in a low-frequency driving mode, the space occupied by the low-frequency operating pixel circuit can be reduced, which is conducive to the development of the display panel towards high pixel density and high resolution.

[0102] Combination Figure 1 , Fig. 9 and Fig.10 As shown, the first scan line SN1 may be located in the metal layer M1, and the second scan line SP may also be located in the metal layer M1.

[0103] Combination Figure 1 , Fig. 9 and Fig.10As shown, the reference voltage line Ref may be located in the first metal layer, the first metal layer is located on the side of the active layer poly away from the substrate sub, the first metal layer may be the metal layer MC, and the first connection portion L2 is located in the active layer poly, so that the reference voltage line Ref and the first connection portion L1 are arranged in different layers.

[0104] Combination Figure 1 , Fig. 9 and Fig.10 As shown, the reference voltage line Ref is electrically connected to the first connection part L1 through the second connection part L2, the second connection part L2 is located in the second metal layer, and the second metal layer is located on the side of the first metal layer away from the substrate sub. Optionally, the first metal layer is the metal layer MC, the second metal layer is the metal layer M2, the metal layer M2 is located on the side of the metal layer MC away from the substrate sub, and the reference voltage line Ref located in the metal layer MC is electrically connected to the first connection part L1 located in the active layer poly through the second connection part L2 located in the metal layer M2.

[0105] It can be understood from this that the reference voltage line Ref is electrically connected to the second connection part L2 through a via between the first metal layer (i.e., metal layer MC) and the second metal layer (i.e., metal layer M2), and the second connection part L2 is electrically connected to the first connection part L1 through a via between the second metal layer (i.e., metal layer M2) and the active layer poly, and the first connection part L1 is electrically connected to the second channel region C2 of the anode reset transistor T7 of the i-th row pixel circuit 10 in the same column of pixel circuits and the first channel region C1 of the gate reset transistor T5 of the i+1-th row of pixel circuits in the active layer poly. In this way, the reference voltage line Ref only needs to pass through two vias to transmit the reference voltage signal VRef to the second channel region C2 of the anode reset transistor T7 of the i-th row pixel circuit 10 in the same column of pixel circuits and the first channel region C1 of the gate reset transistor T5 of the i+1-th row of pixel circuits.

[0106] like Fig. 9 As shown, a row of pixel circuits 10 is electrically connected to a first scan line SN1 and a second scan line SP, and the first scan line SN1 and the second scan line SP are alternately arranged along the second direction Y; along the second direction Y, the reference voltage line Ref is located on the side of the first scan line SN1 electrically connected to the pixel circuit 10 in the i+1th row, away from the second scan line SP electrically connected to the pixel circuit 10 in the i-th row; thus, along the second direction Y, the first scan line SN1, the reference voltage line Ref and the second scan line SN2 are arranged sequentially.

[0107] Combination Fig. 9 and Fig.10As shown, for the same column of pixel circuits, the second channel region C2 of the anode reset transistor T5 in the i-th row of pixel circuits 10 and the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits 10 are located on the same side of the reference voltage line Ref along the second direction Y; such a configuration not only facilitates the direct connection of the second channel region C2 of the anode reset transistor T5 in the i-th row of pixel circuits 10 and the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits 10 in the same column of pixel circuits through the first connecting portion L1 located in the active layer poly, but also helps to shorten the length of the first connecting portion L1, which can further save the occupied space of the pixel circuit.

[0108] Combination Fig. 9 and Fig.10 As shown, one end of the second connection part L2 is electrically connected to the reference voltage line Ref through the third via hole K3; the other end of the second connection part L2 is electrically connected to the first connection part L1 through the fourth via hole K4; along the second direction Y, the third via hole K3 and the fourth via hole K4 are located on both sides of the first scan line SN1 electrically connected to the pixel circuit 10 in the i+1th row.

[0109] It can be understood that in a direction perpendicular to the plane of the substrate, the second connection portion L2 at least partially overlaps with the reference voltage line Ref, so that the second connection portion L2 and the reference voltage line Ref are electrically connected through a third via K3 between the first metal layer (such as metal layer MC) and the second metal layer (such as metal layer M2).

[0110] Similarly, in a direction perpendicular to the plane of the substrate, the second connection portion L2 also at least partially overlaps with the first connection portion L1, so that the second connection portion L2 and the first connection portion L1 are electrically connected through a fourth via K4 between the second metal layer (such as metal layer M2) and the active layer poly.

[0111] Since the reference voltage line Ref is located on the side of the first scan line SN1 electrically connected to the pixel circuit 10 in the i+1th row away from the second scan line SP electrically connected to the pixel circuit 10 in the i+1th row, and the second channel region C2 of the anode reset transistor T5 in the pixel circuit 10 in the i+1th row and the first channel region C1 of the gate reset transistor T5 in the pixel circuit 10 in the i+1th row in the same column of pixel circuits are located on the same side of the reference voltage line Ref along the second direction Y, the second connection portion L2 needs to cross the first scan line SN1 to be electrically connected to the reference voltage line Ref, and the third via hole K3 electrically connecting the second connection portion L2 and the reference voltage line Ref and the fourth via hole K4 electrically connecting the second connection portion L2 and the first connection portion L1 are located on both sides of the first scan line SN1 electrically connected to the pixel circuit 10 in the i+1th row along the second direction Y.

[0112] Combination Fig. 9 and Fig.10As shown, the first scan line SN1 includes a main body portion G1 extending along the first direction X and a first protruding portion G2 protruding along the second direction Y from the main body portion G1.

[0113] Combination Fig. 9 and Fig.10 As shown, the gate reset transistor T5 includes a fourth sub-transistor T54 and a fifth sub-transistor T55, and the first channel region C1 of the gate reset transistor T5 includes a fourth sub-channel region C14 of the fourth sub-transistor T54 and a fifth sub-channel region C15 of the fifth sub-transistor T55. In a direction perpendicular to the plane where the substrate is located, the fourth sub-channel region C14 overlaps with the first protrusion G2 of the first scan line SN1, and the fifth sub-channel region C15 overlaps with the main body G1 of the first scan line SN1. The portion where the first protrusion G2 of the first scan line SN1 overlaps with the fourth sub-channel region C14 is the gate of the fourth sub-transistor T54, and the portion where the main body G1 of the first scan line SN1 overlaps with the fifth sub-channel region C15 is the gate of the fifth sub-transistor T55.

[0114] Combination Fig. 9 and Fig.10 As shown, one end of the fourth sub-channel region C14 is directly connected to the first connection portion L1, and the other end of the fourth sub-channel region C14 is directly connected to one end of the fifth sub-channel region C15 through the third sub-connection portion D3 located in the active layer poly.

[0115] Combination Figure 1 , Figure 5 and Figure 6 As shown, the driving transistor T3 includes a channel region C30 located in the active layer poly and a gate g3 located in the metal layer M1. In a direction perpendicular to the plane where the substrate is located, the gate g3 of the driving transistor T3 overlaps with the channel region C30. Fig. 9 As shown, one end of the fifth sub-channel region C15 in the gate reset transistor T5 away from the third sub-connection portion D3 is electrically connected to the gate g3 of the driving transistor T3 through the connection portion J1.

[0116] From the above, it can be seen that the gate reset transistor T5 includes a fourth sub-transistor T54 and a fifth sub-transistor T55, that is, the gate reset transistor T5 is a transistor with a dual-gate structure, which is beneficial to reducing the leakage current of the gate reset transistor T5 to the gate g3 of the driving transistor T3 to maintain the stability of the gate potential of the driving transistor T3, which is beneficial to improving the screen jitter phenomenon of the display panel under low-frequency driving.

[0117] Combination Figure 1 , Fig. 9 and Fig.10As shown, the pixel circuit 10 further includes a first shielding portion B1 , which is located on a side of the active layer poly away from the substrate. Optionally, the first shielding portion B1 is located in the metal layer MC.

[0118] Combination Fig. 9 and Fig.10 As shown, in the direction perpendicular to the plane where the substrate is located, the third sub-connection portion D3 and the first shielding portion B1 at least partially overlap, that is, the first shielding portion B1 at least covers part of the third sub-connection portion D3, so that the third sub-connection portion D3 and the first shielding portion B1 form a shielding capacitor, so that when the potential change on the first scan line SN1 causes the charge change of the first channel region C1 of the gate reset transistor T5, since the charge of the first channel region C1 of the gate reset transistor T5 can be stored in the shielding capacitor formed by the third sub-connection portion D3 and the first shielding portion B1, the influence on the gate potential of the driving transistor T3 can be reduced, the stability of the gate potential of the driving transistor T3 is maintained, and the screen shaking phenomenon of the display panel under low-frequency driving is improved. In addition, since the first shielding portion B1 can be located on the metal layer MC, the first shielding portion B1 can also shield the third sub-connection portion D3, which is also conducive to maintaining the stability of the gate potential of the driving transistor T3 and improving the screen shaking phenomenon of the display panel under low-frequency driving.

[0119] Combination Fig. 9 and Fig.10 As shown, the display panel includes a plurality of first power supply voltage lines PVDD, and refers to Figure 3 As shown, the display panel also includes a plurality of light emitting elements 30 , and the first power supply voltage line PVDD is electrically connected to the light emitting elements 30 through the pixel circuit 10 .

[0120] like Fig. 9 As shown, the first power supply voltage line PVDD extends along the second direction Y. Figure 1 and Fig. 9 As shown, the first power supply voltage line PVDD may be located at the metal layer M2. Figure 3 and Fig. 9As shown, the first power supply voltage line PVDD is electrically connected to the first electrode of the first light-emitting control transistor T1 through the connecting portion J2, and is electrically connected to one electrode plate Cst2 of the storage capacitor Cst through the connecting portion J3. The other electrode plate of the storage capacitor Cst is also the gate g3 of the driving transistor T3. The second electrode of the first light-emitting control transistor T1 is electrically connected to the first electrode of the driving transistor T3 in the active layer poly. The second electrode of the driving transistor T3 is electrically connected to the first electrode of the second light-emitting control transistor T6 in the active layer poly. The second electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the anode reset transistor T7 in the active layer poly. The second electrode of the second light-emitting control transistor T6 and the second electrode of the anode reset transistor T7 are electrically connected to the light-emitting element 30 through the connecting portion J4.

[0121] Combination Fig. 9 and Fig.10 As shown, in the direction perpendicular to the plane where the substrate is located, the third sub-connection portion D3 at least partially overlaps with the first power supply voltage line PVDD, that is, in the direction perpendicular to the plane where the substrate is located, the third sub-connection portion D3 may at least partially overlap with the first shielding portion B1 and / or the first power supply voltage line PVDD. Similar to the overlap of the third sub-connection portion D3 and the first shielding portion B1 in the direction perpendicular to the plane where the substrate is located, the third sub-connection portion D3 and the first power supply voltage line PVDD overlap in the direction perpendicular to the plane where the substrate is located, and the first power supply voltage signal VPVDD on the first power supply voltage line PVDD is a constant voltage signal, then the third sub-connection portion D2 and the first power supply voltage line PVDD may also constitute a shielding capacitor, which may reduce the influence on the gate potential of the driving transistor T3, maintain the stability of the gate potential of the driving transistor T3, and improve the screen shaking phenomenon of the display panel under low-frequency driving. Furthermore, since the first power supply voltage line PVDD can be located in the metal layer M2, the first power supply voltage line PVDD can also shield the third sub-connection portion D3, which is also beneficial to maintaining the stability of the gate potential of the driving transistor T3 and improving the screen jitter phenomenon of the display panel under low-frequency driving.

[0122] Combination Figure 1 , Figure 3 and Fig. 9 As shown, in the pixel circuit 10 , the compensation transistor T4 may include a sub-transistor T41 and a sub-transistor T42 , the sub-transistor T41 includes a channel region C41 located in the active layer poly, and the sub-transistor T42 includes a channel region C42 located in the active layer poly.

[0123] like Fig. 9 As shown, the third scan line SN2 includes a main body portion G3 extending along the first direction X and a protruding portion G4 protruding from the main body portion G3 along the second direction Y.

[0124] like Fig. 9 As shown, in the direction perpendicular to the plane where the substrate is located, the channel region C41 overlaps with the protruding portion G4 of the third scan line SN2, and the portion where the protruding portion G4 of the third scan line SN2 overlaps with the channel region C41 is the gate of the sub-transistor T41; in the direction perpendicular to the plane where the substrate is located, the channel region C42 overlaps with the main portion G3 of the third scan line SN2, and the portion where the main portion G3 of the third scan line SN2 overlaps with the channel region C42 is the gate of the sub-transistor T42.

[0125] like Fig. 9 As shown, one end of the channel region C41 of the sub-transistor T41 is electrically connected to the gate g3 of the driving transistor T3 through the connecting portion J1, the other end of the channel region C41 of the sub-transistor T41 is electrically connected to one end of the channel region C42 of the sub-transistor T42 in the active layer poly, and the other end of the channel region C42 of the sub-transistor T42 is electrically connected to the second electrode of the driving transistor T3 in the active layer poly.

[0126] Since the compensation transistor T4 includes a sub-transistor T41 and a sub-transistor T42, the compensation transistor T4 is a transistor with a dual-gate structure, which is beneficial to reducing the leakage current from the compensation transistor T4 to the gate of the driving transistor T3, so as to maintain the stability of the gate potential of the driving transistor T3 and improve the screen jitter phenomenon of the display panel under low-frequency driving.

[0127] Combination Figure 3 and Fig. 9 As shown, the display panel includes a plurality of data lines data, the data lines data extend along the second direction Y, the first electrode of the data writing transistor T2 in the pixel circuit 10 is electrically connected to the data line data through the connecting portion J5, and the second electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T3 in the active layer poly. Figure 1 and Fig. 9 As shown, the data line data may be located in the metal layer M2.

[0128] Fig.11 Shows Fig. 9 The circuit structure diagram of two adjacent rows of pixel circuits 10 in the same column of pixel circuits shown in FIG. Fig. 9 and Fig.11As shown, a reference voltage line Ref is electrically connected to the anode reset transistor T7 of the pixel circuit 10 in the i-th row in the same column of pixel circuits, and is also electrically connected to the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the same column of pixel circuits. In this way, the reference voltage signal VRef on the reference voltage line Ref can reset the fourth node N4 of the pixel circuit 10 in the i-th row through the anode reset transistor T7 of the pixel circuit 10 in the i-th row in the same column of pixel circuits, and can also reset the first node N1 of the pixel circuit 10 in the i+1-th row through the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the same column of pixel circuits.

[0129] Combination Fig. 9 and Fig.11 As shown, in the pixel circuit 10, the gate reset transistor T5 is a transistor with a dual-gate structure, including two sub-transistors; the compensation transistor T4 is also a transistor with a dual-gate structure, including two sub-transistors.

[0130] Figure 8 It can also be expressed Fig.11 A timing diagram of two adjacent rows of pixel circuits 10 in the same column of pixel circuits shown in FIG. Figure 8 , Fig. 9 and Fig.11 As shown, for the same column of pixel circuits, the first scanning signal VSN1(i) driving the pixel circuit 10 in the i-th row is first at a valid level, the pixel circuit 10 in the i-th row is in the t1 period, and the gate reset transistor T5 in the pixel circuit 10 in the i-th row is turned on, so that the reference voltage signal VRef(i) provided by the reference voltage line Ref electrically connected to the gate reset transistor T5 in the pixel circuit 10 in the i-th row resets the first node N1 in the pixel circuit 10 in the i-th row.

[0131] Next, the third scanning signal VSN2(i) driving the pixel circuit 10 in the i-th row is at an effective level, the pixel circuit 10 in the i-th row is in the t2 period, and the compensation transistor T4 in the pixel circuit 10 in the i-th row is turned on; and the second scanning signal VSP(i) driving the pixel circuit 10 in the i-th row is at an effective level, so that the data writing transistor T2 of the pixel circuit 10 in the i-th row is turned on, and the data signal is written to the gate of the driving transistor T3 of the pixel circuit 10 in the i-th row; the second scanning signal VSP(i) driving the pixel circuit 10 in the i-th row is at an effective level, and the pixel circuit 10 in the i-th row is turned on. The anode reset transistor T7 of the pixel circuit 10 is turned on, and the fourth node N4 of the i-th row pixel circuit 10 is reset; at the same time, the first scanning signal VSN1(i+1) driving the i+1-th row pixel circuit 10 is at a valid level, the i+1-th row pixel circuit 10 is in the t1 period, and the gate reset transistor T5 in the i+1-th row pixel circuit 10 is turned on, so that the reference voltage signal VRef(i+1) provided by the reference voltage line Ref electrically connected to the gate reset transistor T5 in the i+1-th row pixel circuit 10 resets the first node N1 in the i+1-th row pixel circuit 10.

[0132] Afterwards, the light emission control signal VEmit driving the pixel circuit 10 in the i-th row is at an effective level, so that the pixel circuit 10 in the i-th row enters the t3 period and drives the light emitting element 40 to emit light. In addition, the pixel circuit in the i+1th row also enters the t2 period and the t3 period in sequence.

[0133] It can be seen that when the second scanning signal VSP(i) driving the pixel circuit 10 in the i-th row and the first scanning signal VSN1(i+1) driving the pixel circuit 10 in the i+1-th row are both at the effective level, that is, the anode reset transistor T7 in the pixel circuit 10 in the i-th row and the gate reset transistor T5 in the pixel circuit 10 in the i+1-th row are turned on at the same time, the reference voltage signal VRef on the reference voltage line Ref can reset the fourth node N4 in the pixel circuit 10 in the i-th row through the anode reset transistor T7 in the pixel circuit 10 in the i-th row, and can reset the first node N1 in the pixel circuit 10 in the i+1-th row through the gate reset transistor T5 in the pixel circuit 10 in the i+1-th row.

[0134] Of course, the effective level period of the second scanning signal VSP(i) driving the i-th row pixel circuit 10 may also not overlap with the effective level period of the first scanning signal VSN1(i+1) driving the i+1-th row pixel circuit 10. At this time, the anode reset transistor T7 in the i-th row pixel circuit 10 and the gate reset transistor T5 in the i+1-th row pixel circuit 10 are turned on in a time-sharing manner, and the reference voltage signal VRef on the reference voltage line Ref is used in a time-sharing manner to reset the fourth node N4 in the i-th row pixel circuit 10 through the anode reset transistor T7 in the i-th row pixel circuit 10, and to reset the first node N1 in the i+1-th row pixel circuit 10 through the gate reset transistor T5 in the i+1-th row pixel circuit 10.

[0135] Fig.12 A schematic diagram of the layout structure of three adjacent rows of pixel circuits 10 in a column of pixel circuits in another display panel provided by an embodiment of the present application is shown, combined with Figure 1 , Figure 3 and Fig.12 As shown, the pixel circuit 10 includes a gate reset transistor T5 and an anode reset transistor T7. The gate reset transistor T5 includes a first channel region C1 located in the active layer poly. In a direction perpendicular to the plane where the substrate sub is located, the first channel region C1 overlaps with the first scan line SN1, and the overlapping portion of the first scan line SN1 and the first channel region C1 is the gate of the gate reset transistor T5; the anode reset transistor T7 includes a second channel region C2 located in the active layer poly. In a direction perpendicular to the plane where the substrate sub is located, the second channel region C2 overlaps with the second scan line SP, and the overlapping portion of the second scan line SP and the second channel region C2 is the gate of the anode reset transistor T7.

[0136] In order to understand this application more clearly, Fig.13 Shows Fig.12 The enlarged schematic diagram of the local area in Fig.12 and Fig.13As shown, for the same column of pixel circuits, the second channel region C2 of the anode reset transistor T7 in the i-th row of pixel circuits 10 and the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits are directly connected through the first connection portion L1, and the first connection portion L1 is located in the active layer poly. In other words, the second channel region C2 of the anode reset transistor T7 of the i-th row of pixel circuits 10 in the same column of pixel circuits 10 is located in the active layer poly and directly connected to the first connection portion L1, and the first channel region C1 of the gate reset transistor T5 of the i+1-th row of pixel circuits 10 in the same column of pixel circuits 10 is also located in the active layer poly and directly connected to the first connection portion L1, so that the second channel region C2 of the anode reset transistor T7 in the i-th row of pixel circuits 10 in the same column of pixel circuits 10 is directly connected to the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits 10 through the first connection portion L1 of the same layer. In other words, the second channel region C2 of the anode reset transistor T7 of the pixel circuit 10 in the i-th row and the first channel region C1 of the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the same column of pixel circuits are directly connected in the active layer poly through the first connection portion L1, where i is a positive integer.

[0137] And, if Fig.12 and Fig.13 As shown, the first connection portion L1 is electrically connected to the reference voltage line Ref, so that the reference voltage line Ref can be electrically connected to the anode reset transistor T7 of the i-th row pixel circuit 10 and the gate reset transistor T5 of the i+1-th row pixel circuit 10 in the same column of pixel circuits through the first connection portion L1.

[0138] In this way, the number of holes for electrically connecting the reference voltage line Ref with the anode reset transistor T7 of the pixel circuit 10 in the i-th row and the gate reset transistor T5 of the pixel circuit in the i+1-th row in the same column of pixel circuits can be reduced, thereby saving the space occupied by the pixel circuit 10. If the pixel circuit 10 operates in a low-frequency driving mode, the space occupied by the low-frequency operating pixel circuit can be reduced, which is conducive to the development of the display panel towards high pixel density and high resolution.

[0139] Combination Figure 1 , Fig.12 and Fig.13 As shown, the first scan line SN1 may be located in the metal layer M1, and the second scan line SP may also be located in the metal layer M1.

[0140] Combination Figure 1 , Fig.12 and Fig.13As shown, the reference voltage line Ref may be located in the first metal layer, the first metal layer is located on the side of the active layer poly away from the substrate sub, the first metal layer may be the metal layer MC, and the first connection portion L2 is located in the active layer poly, so that the reference voltage line Ref and the first connection portion L1 are arranged in different layers.

[0141] Combination Fig.12 and Fig.13 As shown, the pixel circuit 10 also includes a connecting transistor T8, and the connecting transistor T8 includes a third channel region C3 located in the active layer poly; for the same column of pixel circuits, in a direction perpendicular to the plane where the substrate is located, the third channel region C3 of the connecting transistor T8 in the pixel circuit 10 of the i-th row and the first channel region C1 of the gate reset transistor T5 in the pixel circuit 10 of the i+1th row overlap with the same first scanning line SN1; in a direction perpendicular to the plane where the substrate is located, the portion where the first scanning line SN1 overlaps with the third channel region C3 is the gate of the connecting transistor T8; in this way, when the first scanning signal VSN1 on the first scanning line SN1 is at an effective level, turning on the gate reset transistor T5 in the pixel circuit 10 of the i+1th row, the connecting transistor T8 in the pixel circuit 10 of the i-th row will be turned on at the same time.

[0142] Combination Figure 1 , Fig.12 and Fig.13 As shown, the reference voltage line Ref is electrically connected to the first connection part L1 through the second connection part L2, the third connection part L3 and the third channel region C3 in sequence, the second connection part L2 is located in the second metal layer, the second metal layer is located on the side of the first metal layer away from the substrate sub, and the third connection part L3 is located in the active layer poly. Optionally, the first metal layer is the metal layer MC, the second metal layer is the metal layer M2, the metal layer M2 is located on the side of the metal layer MC away from the substrate sub, the reference voltage line Ref located in the metal layer MC is electrically connected to the third connection part L3 located in the active layer poly through the second connection part L2 located in the metal layer M2, the third connection part L3 is electrically connected to the third channel region C3 in the active layer poly, and the third channel region C3 is electrically connected to the first connection part L1 in the active layer poly.

[0143] It can be understood from this that the reference voltage line Ref is electrically connected to the second connection part L2 through a via between the first metal layer (i.e., metal layer MC) and the second metal layer (i.e., metal layer M2), and the second connection part L2 is electrically connected to the third connection part L3 through a via between the second metal layer (i.e., metal layer M2) and the active layer poly, and the third connection part L3 is electrically connected to the first connection part L1 through the third channel region C3 in the active layer poly, and the first connection part L1 is electrically connected to the second channel region C2 of the anode reset transistor T7 of the i-th row pixel circuit 10 and the first channel region C1 of the gate reset transistor T5 of the i+1-th row pixel circuit in the same column of pixel circuits in the active layer poly. In this way, the reference voltage line Ref only needs to transmit the reference voltage signal VRef to the second channel region C2 of the anode reset transistor T7 of the i-th row pixel circuit 10 and the first channel region C1 of the gate reset transistor T5 of the i+1-th row pixel circuit in the same column of pixel circuits through two vias.

[0144] It should be noted that the third connection portion L3 and the third channel region C3 are both located in the active layer poly, and the third connection portion L3 and the third channel region C3 both play the role of electrically connecting the reference voltage line Ref and the first connection portion L1. If only a part of the active layer poly is used for electrical connection, the resistance of this part of the active layer poly is relatively large. If the part of the active layer poly that plays the role of electrical connection forms a channel, the resistance can be reduced. Based on this, the third channel region C3 located in the active layer poly is overlapped with the first scanning line SN1 in a direction perpendicular to the plane where the substrate is located, so that the connection resistance of the third channel region C3 located in the active layer poly can be reduced, and the length of the first connection portion L1 and the third connection portion L3 located in the active layer poly can be shortened, so that the reference voltage signal VRef on the reference voltage line Ref is more efficiently transmitted to the second channel region C2 of the anode reset transistor T7 in the i-th row pixel circuit 10 and the first channel region C1 of the gate reset transistor T5 in the i+1-th row pixel circuit 10.

[0145] Combination Fig.12 and Fig.13As shown, the gate reset transistor T5 in the pixel circuit 10 of the i-th row is electrically connected to a first scan line SN1, the connecting transistor T8 in the pixel circuit 10 of the i-th row and the gate reset transistor T5 in the pixel circuit 10 of the i+1th row are electrically connected to another first scan line SN1, and the anode reset transistor T7 in the pixel circuit of the i-th row is electrically connected to a second scan line SP; in this way, the gate reset transistor T5 and the connecting transistor T8 in the pixel circuit 10 of the i-th row are respectively electrically connected to a first scan line SN1, that is, the pixel circuit 10 of the i-th row is electrically connected to two first scan lines SN1, and the connecting transistor T8 in the pixel circuit 10 of the i-th row and the gate reset transistor T5 in the pixel circuit 10 of the i+1th row are electrically connected to the same first scan line SN1, so that the connecting transistor T8 in the pixel circuit 10 of the i-th row and the gate reset transistor T5 in the pixel circuit 10 of the i+1th row are turned on at the same time.

[0146] Combination Fig.12 and Fig.13 As shown, the reference voltage line Ref is located on the side of the first scan line SN1 electrically connected to the connection transistor T8 in the i-th row pixel circuit 10 and the gate reset transistor T5 in the i+1-th row pixel circuit 10, away from the second scan line SN2 electrically connected to the anode reset transistor T7 in the i-th row pixel circuit 10; thus, along the second direction Y, the first scan line SN1, the reference voltage line Ref and the second scan line SN2 are arranged sequentially.

[0147] Combination Fig.12 and Fig.13 As shown, for the same column of pixel circuits, the second channel region C2 of the anode reset transistor T7 in the i-th row of pixel circuits 10, the third channel region C3 of the connection transistor T8 in the i-th row of pixel circuits 10, and the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits 10 are located on the same side of the reference voltage line Ref along the second direction Y; such an arrangement not only facilitates the direct connection of the second channel region C2 of the anode reset transistor T5 in the i-th row of pixel circuits 10 and the first channel region C1 of the gate reset transistor T5 in the i+1-th row of pixel circuits in the same column through the first connection portion L1 located in the same active layer poly, but also facilitates the electrical connection of the reference voltage line Ref with the first connection portion L1 through the third channel region C3, which can further save the occupied space of the pixel circuit.

[0148] Combination Fig.12 and Fig.13As shown, one end of the second connection portion L2 is electrically connected to the reference voltage line Ref through the fifth via K5; the other end of the second connection portion L2 is electrically connected to the third connection portion L3 through the sixth via K6; along the second direction Y, the fifth via K5 and the sixth via K6 are located on the same side of the first scan line SN1 to which the connection transistor T8 in the i-th row pixel circuit 10 and the gate reset transistor T5 in the i+1-th row pixel circuit 10 are electrically connected.

[0149] It can be understood that in a direction perpendicular to the plane of the substrate, the second connection portion L2 at least partially overlaps with the reference voltage line Ref, so that the second connection portion L2 and the reference voltage line Ref are electrically connected through the fifth via K5 between the first metal layer (such as metal layer MC) and the second metal layer (such as metal layer M2).

[0150] Similarly, in a direction perpendicular to the plane of the substrate, the second connection portion L2 also at least partially overlaps with the third connection portion L3, so that the second connection portion L2 and the third connection portion L3 are electrically connected through the sixth via K6 between the second metal layer (such as metal layer M2) and the active layer poly.

[0151] Combination Fig.12 and Fig.13 As shown, the fifth via hole K5 and the sixth via hole K6 may overlap, so that the length of the second connection portion L2 may be shorter, which may further save the space occupied by the pixel circuit.

[0152] Combination Fig.12 and Fig.13 As shown, the first scan line SN1 includes a main body portion G1 extending along the first direction X and a second protruding portion G5 protruding along the second direction Y from the main body portion G1.

[0153] Combine 12 and Fig.13 As shown, the gate reset transistor T5 includes a sixth sub-transistor T56 and a seventh sub-transistor T57, and the first channel region C1 of the gate reset transistor T5 includes a sixth sub-channel region C16 of the sixth sub-transistor T56 and a seventh sub-channel region C17 of the seventh sub-transistor T57. In a direction perpendicular to the plane where the substrate is located, the sixth sub-channel region C16 overlaps with the second protrusion G5 of the first scan line SN1, and the seventh sub-channel region C17 overlaps with the main body G1 of the first scan line SN1. The portion where the second protrusion G5 of the first scan line SN1 overlaps with the sixth sub-channel region C16 is the gate of the sixth sub-transistor T56, and the portion where the main body G1 of the first scan line SN1 overlaps with the seventh sub-channel region C17 is the gate of the seventh sub-transistor T57.

[0154] Combination Fig.12 and Fig.13As shown, one end of the sixth sub-channel region C16 is directly connected to the first connection portion L1, and the other end of the sixth sub-channel region C16 is directly connected to one end of the seventh sub-channel region C17 through the fourth sub-connection portion D4 located in the active layer poly.

[0155] Combination Figure 1 , Fig.12 and Fig.13 As shown, the driving transistor T3 includes a channel region C30 located in the active layer poly and a gate g3 located in the metal layer M1. In a direction perpendicular to the plane where the substrate is located, the gate g3 of the driving transistor T3 overlaps with the channel region C30. Fig.12 As shown, one end of the seventh sub-channel region C17 in the gate reset transistor T5 away from the fourth sub-connection portion D4 is electrically connected to the gate g3 of the driving transistor T3 through the connection portion J1.

[0156] From the above, it can be seen that the gate reset transistor T5 includes a sixth sub-transistor T56 and a seventh sub-transistor T57, that is, the gate reset transistor T5 is a transistor with a dual-gate structure, which is beneficial to reducing the leakage current from the gate reset transistor T5 to the gate g3 of the driving transistor T3 to maintain the stability of the gate potential of the driving transistor T3, which is beneficial to improving the screen jitter phenomenon of the display panel under low-frequency driving.

[0157] Combination Fig.12 and Fig.13 As shown, the display panel includes a plurality of first power supply voltage lines PVDD, and refers to Figure 3 As shown, the display panel also includes a plurality of light emitting elements 30 , and the first power supply voltage line PVDD is electrically connected to the light emitting elements 30 through the pixel circuit 10 .

[0158] like Fig.12 As shown, the first power supply voltage line PVDD extends along the second direction Y. Figure 1 and Fig.12 As shown, the first power supply voltage line PVDD may be located at the metal layer M2. Figure 3 and Fig.11As shown, the first power supply voltage line PVDD is electrically connected to the first electrode of the first light-emitting control transistor T1 through the connecting portion J2, and is electrically connected to one electrode plate Cst2 of the storage capacitor Cst through the connecting portion J3. The other electrode plate of the storage capacitor Cst is also the gate g3 of the driving transistor T3. The second electrode of the first light-emitting control transistor T1 is electrically connected to the first electrode of the driving transistor T3 in the active layer poly. The second electrode of the driving transistor T3 is electrically connected to the first electrode of the second light-emitting control transistor T6 in the active layer poly. The second electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the anode reset transistor T7 in the active layer poly. The second electrode of the second light-emitting control transistor T6 and the second electrode of the anode reset transistor T7 are electrically connected to the light-emitting element 30 through the connecting portion J4.

[0159] Combination Fig.12 and Fig.13 As shown, in a direction perpendicular to the plane where the substrate is located, the fourth sub-connection portion D4 at least partially overlaps with the first power supply voltage line PVDD, and the first power supply voltage line PVDD can be located in the metal layer M2. In this way, the first power supply voltage line PVDD at least covers part of the fourth sub-connection portion D4, and the first power supply voltage signal VPVDD on the first power supply voltage line PVDD is a constant voltage signal. Then, the third sub-connection portion D2 and the first power supply voltage line PVDD can form a shielding capacitor, which can reduce the influence on the gate potential of the driving transistor T3, maintain the stability of the gate potential of the driving transistor T3, and improve the screen shaking phenomenon of the display panel under low-frequency driving. In addition, since the first power supply voltage line PVDD can be located in the metal layer M2, the first power supply voltage line PVDD can also shield the third sub-connection portion D3, which is also conducive to maintaining the stability of the gate potential of the driving transistor T3 and improving the screen shaking phenomenon of the display panel under low-frequency driving.

[0160] Combination Figure 1 , Figure 3 and Fig.12 As shown, in the pixel circuit 10 , the compensation transistor T4 may include a sub-transistor T41 and a sub-transistor T42 , the sub-transistor T41 includes a channel region C41 located in the active layer poly, and the sub-transistor T42 includes a channel region C42 located in the active layer poly.

[0161] like Fig.12 As shown, the third scan line SN2 includes a main body portion G3 extending along the first direction X and a protruding portion G4 protruding from the main body portion G3 along the second direction Y.

[0162] like Fig.12As shown, in the direction perpendicular to the plane where the substrate is located, the channel region C41 overlaps with the protruding portion G4 of the third scan line SN2, and the portion where the protruding portion G4 of the third scan line SN2 overlaps with the channel region C41 is the gate of the sub-transistor T41; in the direction perpendicular to the plane where the substrate is located, the channel region C42 overlaps with the main portion G3 of the third scan line SN2, and the portion where the main portion G3 of the third scan line SN2 overlaps with the channel region C42 is the gate of the sub-transistor T42.

[0163] like Fig.12 As shown, one end of the channel region C41 of the sub-transistor T41 is electrically connected to the gate g3 of the driving transistor T3 through the connecting portion J1, the other end of the channel region C41 of the sub-transistor T41 is electrically connected to one end of the channel region C42 of the sub-transistor T42 in the active layer poly, and the other end of the channel region C42 of the sub-transistor T42 is electrically connected to the second electrode of the driving transistor T3 in the active layer poly.

[0164] Since the compensation transistor T4 includes a sub-transistor T41 and a sub-transistor T42, the compensation transistor T4 is a transistor with a dual-gate structure, which is beneficial to reducing the leakage current from the compensation transistor T4 to the gate of the driving transistor T3, so as to maintain the stability of the gate potential of the driving transistor T3 and improve the screen jitter phenomenon of the display panel under low-frequency driving.

[0165] Combination Figure 3 and Fig.12 As shown, the display panel includes a plurality of data lines data, the data lines data extend along the second direction Y, the first electrode of the data writing transistor T2 in the pixel circuit 10 is electrically connected to the data line data through the connecting portion J5, and the second electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T3 in the active layer poly. Figure 1 and Fig. 9 As shown, the data line data may be located in the metal layer M2.

[0166] Fig.14 Shows Fig.12 The circuit structure diagram of the three adjacent rows of pixel circuits 10 in the same column of pixel circuits shown in FIG. Fig.12 and Fig.14As shown, a reference voltage line Ref is electrically connected to the anode reset transistor T7 of the pixel circuit 10 in the i-th row in the pixel circuit in the same column, and is electrically connected to the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the pixel circuit in the same column through the connection transistor T8 of the pixel circuit 10 in the i-th row in the pixel circuit in the same column. In addition, the connection transistor T8 of the pixel circuit 10 in the i-th row in the pixel circuit in the same column and the gate reset transistor T5 of the pixel circuit 10 in the i+1-th row in the pixel circuit in the same column are electrically connected to the same first scanning line SN1, and are turned on under the driving of the same first scanning signal VSN1; thus, for the pixel circuit in the same column, when the scanning signal (i.e., the second scanning signal VSP) transmitted by the second scanning line SP received by the gate of the anode reset transistor T7 in the pixel circuit 10 in the i-th row is at an effective level, the scanning signal (i.e., the first scanning signal VSN1) transmitted by the first scanning line SN1 received by the gate of the gate reset transistor T5 in the pixel circuit in the i+1-th row is at an effective level. VSN1) is also at an effective level, so that when the anode reset transistor T7 in the pixel circuit 10 of the i-th row is turned on by the driving of the second scanning signal VSP of the effective level transmitted by the electrically connected second scanning line SP, the connecting transistor T8 in the pixel circuit 10 of the i-th row is also turned on by the driving of the first scanning signal VSN1 of the effective level transmitted by the electrically connected first scanning line SN1, so that the reference voltage signal VRef on the reference voltage line Ref resets the fourth node N4 of the pixel circuit 10 of the i-th row through the turned-on connecting transistor T8 and the anode reset transistor T7. At the same time, the gate reset transistor T5 in the pixel circuit 10 of the i+1-th row is also turned on by the driving of the first scanning signal VSN1 of the effective level transmitted, so that the reference voltage signal VRef on the reference voltage line Ref also resets the first node N1 of the pixel circuit 10 of the i+1-th row through the turned-on connecting transistor T8 and the gate reset transistor T5.

[0167] Fig.15 Shows the provided Fig.14 A timing diagram of each signal of three adjacent rows of pixel circuits 10 in the same column of pixel circuits shown in FIG. Fig.12 , Fig.14 and Fig.15As shown, for the same column of pixel circuits, when the first scanning signal VSN1(i) driving the gate reset transistor T5 in the pixel circuit 10 of the i-th row is at a valid level, the pixel circuit 10 of the i-th row is in the t1 period, the gate reset transistor T5 in the pixel circuit 10 of the i-th row is turned on, and the connecting transistor T8 in the pixel circuit 10 of the i-1th row is also turned on, so that the reference voltage line Ref electrically connected to the gate reset transistor T5 in the pixel circuit 10 of the i-th row is provided by the reference voltage signal VRef(i), which resets the first node N1 in the pixel circuit 10 of the i-th row through the connecting transistor T8 in the pixel circuit 10 of the i-1th row and the gate reset transistor T5 in the pixel circuit 10 of the i-th row. At the same time, the second scanning signal VSP(i-1) driving the anode reset transistor T7 in the i-1th row pixel circuit 10 is also at an effective level during at least part of the effective level period of the first scanning signal VSN1(i), so that the anode reset transistor T7 in the i-1th row pixel circuit 10 is turned on, so that the reference voltage signal VRef(i) provided by the reference voltage line Ref electrically connected to the anode reset transistor T7 in the i-1th row pixel circuit 10 resets the fourth node N4 in the i-1th row pixel circuit 10 through the connecting transistor T8 in the i-1th row pixel circuit 10 and the anode reset transistor T7 in the i-1th row pixel circuit 10.

[0168] Next, the third scanning signal VSN2(i) driving the pixel circuit 10 in the i-th row is at a valid level, the pixel circuit 10 in the i-th row is in the t2 period, and the compensation transistor T4 in the pixel circuit 10 in the i-th row is turned on; and the second scanning signal VSP(i) driving the pixel circuit 10 in the i-th row is at a valid level, so that the data writing transistor T2 of the pixel circuit 10 in the i-th row is turned on, and the data signal is written to the gate of the driving transistor T3 of the pixel circuit 10 in the i-th row.

[0169] At the same time, the second scanning signal VSP(i) driving the pixel circuit 10 in the i-th row is at an effective level, and the anode reset transistor T7 of the pixel circuit 10 in the i-th row is turned on; and the first scanning signal VSN1(i+1) driving the gate reset transistor T5 in the pixel circuit 10 in the i+1-th row is at an effective level, so that the connection transistor T8 in the pixel circuit 10 in the i-th row is turned on, and the gate reset transistor T5 in the pixel circuit 10 in the i+1-th row is turned on, so that not only the reference voltage line Ref electrically connected to the anode reset transistor T7 in the pixel circuit 10 in the i-th row is turned on, but also the reference voltage line Ref provided by the reference voltage line Ref electrically connected to the anode reset transistor T7 in the pixel circuit 10 in the i-th row is turned on. The reference voltage signal VRef(i) resets the fourth node N4 in the i-th row pixel circuit 10 through the connecting transistor T8 in the i-th row pixel circuit 10 and the anode reset transistor T7 in the i-th row pixel circuit 10, and the reference voltage signal VRef(i) provided by the reference voltage line Ref electrically connected to the gate reset transistor T5 in the i+1-th row pixel circuit 10 resets the first node N1 in the i+1-th row pixel circuit 10 through the connecting transistor T8 in the i-th row pixel circuit 10 and the gate reset transistor T5 in the i+1-th row pixel circuit 10.

[0170] Afterwards, the light emission control signal VEmit driving the pixel circuit 10 in the i-th row is at an effective level, so that the pixel circuit 10 in the i-th row enters the t3 period and drives the light emitting element 40 to emit light. In addition, the pixel circuit in the i+1th row also enters the t2 period and the t3 period in sequence.

[0171] It can be seen that, for the same column of pixel circuits, as long as the scanning signal transmitted by the second scanning line SP received by the gate of the anode reset transistor T7 in the pixel circuit 10 of the i-th row (i.e., the second scanning signal VSP) is at a valid level, the scanning signal transmitted by the first scanning line SN1 received by the gate of the gate reset transistor T5 in the pixel circuit of the i+1th row (i.e., the first scanning signal VSN1) is also at a valid level, and the effective level period of the scanning signal transmitted by the second scanning line SP received by the gate of the anode reset transistor T7 in the pixel circuit 10 of the i-th row (i.e., the second scanning signal VSP) can be shorter than the effective level period of the scanning signal transmitted by the first scanning line SN1 received by the gate of the gate reset transistor T5 in the pixel circuit of the i+1th row (i.e., the first scanning signal VSN1).

[0172] Based on the same inventive concept, the embodiment of the present application further provides a display device, such as Fig.16 As shown, the display device 100 includes a display panel 200 provided in any of the above embodiments. Since the display panel 200 has been described in detail in the above embodiments, it will not be described again here.

[0173] The display device 100 can be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a notebook computer, an e-reader, or a television.

[0174] The various parts in this manual are described in a combination of parallel and progressive ways. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0175] With respect to the above description of the disclosed embodiments, the features described in the embodiments in this specification may be replaced or combined with each other, so that professionals in the field can implement or use the present application. Various modifications to these embodiments will be apparent to professionals in the field, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: substrate substrate; An active layer, located on one side of the substrate; A plurality of pixel circuits are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect; a plurality of first scan lines, a plurality of second scan lines and a plurality of reference voltage lines, wherein the first scan lines, the second scan lines and the reference voltage lines extend along the first direction; The pixel circuit includes a gate reset transistor and an anode reset transistor; the gate reset transistor includes a first channel region located in the active layer, and the first channel region overlaps with the first scan line in a direction perpendicular to the plane where the substrate is located; the anode reset transistor includes a second channel region located in the active layer, and the second channel region overlaps with the second scan line in a direction perpendicular to the plane where the substrate is located; For the pixel circuits in the same column, the second channel region of the anode reset transistor in the pixel circuit in the i-th row and the first channel region of the gate reset transistor in the pixel circuit in the i+1-th row are directly connected through a first connection portion, the first connection portion is located in the active layer, and the reference voltage line is electrically connected to the first connection portion, wherein i is a positive integer.

2. The display panel according to claim 1, characterized in that: The reference voltage line is located in a first metal layer, and the first metal layer is located on a side of the active layer away from the substrate; The reference voltage line is electrically connected to the first connection portion through a second connection portion, the second connection portion is located in a second metal layer, and the second metal layer is located on a side of the first metal layer away from the base substrate.

3. The display panel according to claim 2, characterized in that: A row of the pixel circuits is electrically connected to one of the first scanning lines and one of the second scanning lines; The reference voltage line is located between the second scan line electrically connected to the pixel circuits in the i-th row and the first scan line electrically connected to the pixel circuits in the (i+1)-th row; For the pixel circuits in the same column, the second channel region of the anode reset transistor in the pixel circuit in the i-th row and the first channel region of the gate reset transistor in the pixel circuit in the (i+1)-th row are located on opposite sides of the reference voltage line along the second direction.

4. The display panel according to claim 3, characterized in that: One end of the second connection portion is electrically connected to the reference voltage line through a first via hole; The other end of the second connection portion is electrically connected to the first connection portion through a second via hole; The first via hole and the second via hole are located between the second scan line electrically connected to the pixel circuit in the i-th row and the first scan line electrically connected to the pixel circuit in the (i+1)-th row.

5. The display panel according to claim 4, characterized in that: The gate reset transistor includes a first sub-transistor, a second sub-transistor and a third sub-transistor; The first channel region of the gate reset transistor includes a first sub-channel region of the first sub-transistor, a second sub-channel region of the second sub-transistor, and a third sub-channel region of the third sub-transistor, and in a direction perpendicular to the plane where the substrate is located, the first sub-channel region, the second sub-channel region, and the third sub-channel region all overlap with the first scan line; One end of the first sub-channel region is directly connected to the first connection portion, the other end of the first sub-channel region is directly connected to one end of the second sub-channel region through a first sub-connection portion located in the active layer, and the other end of the second sub-channel region is directly connected to one end of the third sub-channel region through a second sub-connection portion located in the active layer.

6. The display panel according to claim 5, characterized in that: In a direction perpendicular to a plane where the substrate is located, the second sub-connection portion at least partially overlaps with the reference voltage line.

7. The display panel according to claim 5 or 6, characterized in that: The display panel comprises a plurality of first power supply voltage lines and a plurality of light emitting elements, wherein the first power supply voltage lines are electrically connected to the light emitting elements through the pixel circuits; The first power supply voltage line extends along the second direction, and in a direction perpendicular to a plane where the base substrate is located, the second sub-connection portion at least partially overlaps with the first power supply voltage line.

8. The display panel according to claim 2, characterized in that: A row of the pixel circuits is electrically connected to one of the first scanning lines and one of the second scanning lines; Along the second direction, the reference voltage line is located at a side of the first scan line electrically connected to the pixel circuits in the (i+1)th row away from the second scan line electrically connected to the pixel circuits in the (i)th row; For the pixel circuits in the same column, the second channel region of the anode reset transistor in the pixel circuit in the i-th row and the first channel region of the gate reset transistor in the pixel circuit in the (i+1)-th row are located on the same side of the reference voltage line along the second direction.

9. The display panel according to claim 8, characterized in that: One end of the second connection portion is electrically connected to the reference voltage line through a third via hole; The other end of the second connection portion is electrically connected to the first connection portion through a fourth via hole; Along the second direction, the third via hole and the fourth via hole are located at two sides of the first scan line to which the pixel circuit in the (i+1)th row is electrically connected.

10. The display panel according to claim 9, characterized in that: The first scanning line includes a main body portion extending along the first direction and a first protruding portion protruding from the main body portion along the second direction; The gate reset transistor includes a fourth sub-transistor and a fifth sub-transistor, the first channel region of the gate reset transistor includes a fourth sub-channel region of the fourth sub-transistor and a fifth sub-channel region of the fifth sub-transistor, and in a direction perpendicular to the plane where the substrate is located, the fourth sub-channel region overlaps with the first protruding portion, and the fifth sub-channel region overlaps with the main body; One end of the fourth sub-channel region is directly connected to the first connection portion, and the other end of the fourth sub-channel region is directly connected to one end of the fifth sub-channel region through a third sub-connection portion located in the active layer.

11. The display panel according to claim 10, characterized in that: The pixel circuit further includes a first shielding portion, which is located on a side of the active layer away from the substrate; In a direction perpendicular to the plane where the substrate is located, the third sub-connection portion at least partially overlaps with the first shielding portion.

12. The display panel according to claim 10 or 11, characterized in that: The display panel comprises a plurality of first power supply voltage lines and a plurality of light emitting elements, wherein the first power supply voltage lines are electrically connected to the light emitting elements through the pixel circuits; The first power supply voltage line extends along the second direction, and in a direction perpendicular to a plane where the substrate is located, the third sub-connection portion at least partially overlaps with the first power supply voltage line.

13. The display panel according to claim 1, characterized in that: The reference voltage line is located in a first metal layer, and the first metal layer is located on a side of the active layer away from the substrate; The pixel circuit further includes a connecting transistor, wherein the connecting transistor includes a third channel region located in the active layer; For the pixel circuits in the same column, in a direction perpendicular to the plane where the substrate is located, the third channel region of the connecting transistor in the pixel circuit in the i-th row and the first channel region of the gate reset transistor in the pixel circuit in the (i+1)-th row overlap with the same first scanning line; The reference voltage line is electrically connected to the first connection part through a second connection part, a third connection part and the third channel region in sequence, the second connection part is located in a second metal layer, the second metal layer is located on a side of the first metal layer away from the substrate, and the third connection part is located in the active layer.

14. The display panel according to claim 13, characterized in that: The gate reset transistors in the pixel circuits in the i-th row are electrically connected to one of the first scan lines, the connection transistors in the pixel circuits in the i-th row and the gate reset transistors in the pixel circuits in the (i+1)th row are electrically connected to another of the first scan lines, and the anode reset transistors in the pixel circuits in the i-th row are electrically connected to one of the second scan lines; The reference voltage line is located at a side of the first scan line electrically connected to the connection transistor in the pixel circuit of the i-th row and the gate reset transistor in the pixel circuit of the i+1-th row, away from the second scan line electrically connected to the anode reset transistor in the pixel circuit of the i-th row; For the pixel circuits in the same column, the second channel region of the anode reset transistor in the pixel circuit in the i-th row, the third channel region of the connecting transistor in the pixel circuit in the i-th row, and the first channel region of the gate reset transistor in the pixel circuit in the i+1-th row are located on the same side of the reference voltage line along the second direction.

15. The display panel according to claim 14, characterized in that: One end of the second connection portion is electrically connected to the reference voltage line through a fifth via hole; The other end of the second connection portion is electrically connected to the third connection portion through a sixth via hole; Along the second direction, the fifth via hole and the sixth via hole are located on the same side of the first scan line to which the connection transistor in the pixel circuit of the i-th row and the gate reset transistor in the pixel circuit of the (i+1)th row are electrically connected.

16. The display panel according to claim 15, characterized in that: The first scanning line includes a main body portion extending along the first direction and a second protruding portion protruding from the main body portion along the second direction; The gate reset transistor includes a sixth sub-transistor and a seventh sub-transistor, the first channel region of the gate reset transistor includes a sixth sub-channel region of the sixth sub-transistor and a seventh sub-channel region of the seventh sub-transistor, and in a direction perpendicular to a plane where the substrate is located, the sixth sub-channel region overlaps with the second protruding portion, and the seventh sub-channel region overlaps with the main body; One end of the sixth sub-channel region is directly connected to the first connection portion, and the other end of the sixth sub-channel region is directly connected to one end of the seventh sub-channel region through a fourth sub-connection portion located in the active layer.

17. The display panel according to claim 16, characterized in that: The display panel comprises a plurality of first power supply voltage lines and a plurality of light emitting elements, wherein the first power supply voltage lines are electrically connected to the light emitting elements through the pixel circuits; The first power supply voltage line extends along the second direction, and in a direction perpendicular to a plane where the substrate is located, the fourth sub-connection portion at least partially overlaps with the first power supply voltage line.

18. The display panel according to claim 13, characterized in that: For the pixel circuits in the same column, when the scanning signal transmitted by the second scanning line and received by the gate of the anode reset transistor in the pixel circuit in the i-th row is at a valid level, the scanning signal transmitted by the first scanning line and received by the gate of the gate reset transistor in the pixel circuit in the i+1-th row is also at a valid level.

19. A display device, characterized in that: A display panel comprising any one of claims 1-18.

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