A display panel and display device

Abstract

This application provides a display panel and display device. The display panel includes multiple sub-pixels and multiple data lines. Each sub-pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel is electrically connected to a first data line, and the second sub-pixel is electrically connected to a second data line. The first and second data lines sequentially receive data signals, and the time when the first data line receives a data signal at least partially coincides with the time when the second data line is reset. This application helps to reduce the idle time of the second data line between the start of data signal reception by the first and second data lines, thus preparing for extending the data writing time of the first and second sub-pixels. It also facilitates resetting the second data line earlier when the first data line receives a data signal, and allows for earlier activation of the data writing modules in the first and second sub-pixels, thereby extending the data writing time of the first and second sub-pixels.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display panel and display device. Background Technology

[0002] Before a sub-pixel in the display panel emits light, a data writing phase is required. During this phase, the data line electrically connected to the sub-pixel first receives data signals, and then the pixel circuit within the sub-pixel activates the data writing module to write the data signals into the driving transistor. Since multiple sub-pixels are electrically connected to the same data line, the data line sequentially receives the data signals required by sub-pixels in different rows. When the data line begins receiving data signals for the next row of sub-pixels, it also receives data signals for the previous row. Therefore, there needs to be a certain time gap between the activation of the data writing module in the pixel circuit of the sub-pixel and the start of data signal reception by the data line, allowing the new data signal to update the data line to the required data signal state for the current row of sub-pixels.

[0003] In a typical display panel, multiple pixel circuits within sub-pixels distributed in the same row are electrically connected to the same data writing module control signal line. When the data writing module control signal line transmits an enable signal, all sub-pixels begin receiving data signals. However, if, when the data writing module is enabled, a data line electrically connected to a sub-pixel has not been reset to the latest data signal, the data signal required by the previous row of sub-pixels may be injected into the current row of sub-pixels, preventing the current row of sub-pixels from receiving accurate data signals. To avoid this, the data writing module control signal line typically transmits an enable signal only after all the data lines electrically connected to sub-pixels in the same row have been reset, ensuring accurate data signal transmission. However, when the display panel includes a multiplexer, the data signals of the data lines electrically connected to multiple sub-pixels all originate from the same source data line, and these multiple data lines electrically connected to the same source data line need to receive different data signals sequentially. In this case, the data writing module control signal line must wait for the last data line electrically connected to it by the source data line to be reset before transmitting an enable signal, thus ensuring accurate data signals received by the sub-pixels. The long waiting time compresses the actual start time of the data writing module for each sub-pixel. Insufficient data signal writing time for each sub-pixel can also lead to inaccurate data signals received by the driving transistor, and significantly increase time costs. Summary of the Invention

[0004] In view of this, this application provides a display panel and a display device to help solve the above problems.

[0005] In a first aspect, embodiments of this application provide a display panel including multiple sub-pixels and multiple data lines, wherein the data lines are electrically connected to the sub-pixels; the sub-pixels include first sub-pixels and second sub-pixels arranged alternately along a first direction, and the data lines include first data lines and second data lines, wherein the first sub-pixels are electrically connected to the first data lines, and the second sub-pixels are electrically connected to the second data lines.

[0006] The first data line and the second data line receive data signals sequentially, and the time when the first data line receives the data signal coincides at least partially with the time when the second data line is reset.

[0007] Secondly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.

[0008] In this embodiment, the timing of the first data line receiving a data signal is set to at least partially coincide with the timing of resetting the second data line. This helps reduce the idle time of the second data line between the start of data signal reception by the first and second data lines, improving the operational efficiency between them and preparing for extending the data writing time of the first and second sub-pixels. Furthermore, it facilitates resetting the second data line earlier when the first data line receives a data signal, allowing for earlier activation of the data writing modules in the first and second sub-pixels, thereby extending the data writing time of both sub-pixels. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a plan view of a display panel provided in an embodiment of this application;

[0011] Figure 2 A timing diagram of sub-pixels in a related art provided in an embodiment of this application;

[0012] Figure 3 A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0013] Figure 4 A timing diagram of a sub-pixel is provided as an embodiment of this application;

[0014] Figure 5 A plan view of yet another display panel provided in an embodiment of this application;

[0015] Figure 6 A plan view of yet another display panel provided in an embodiment of this application;

[0016] Figure 7 A plan view of yet another display panel provided in an embodiment of this application;

[0017] Figure 8 A plan view of yet another display panel provided in an embodiment of this application;

[0018] Figure 9 This application provides yet another sub-pixel timing diagram.

[0019] Figure 10 A plan view of yet another display panel provided in an embodiment of this application;

[0020] Figure 11 A plan view of yet another display panel provided in an embodiment of this application;

[0021] Figure 12 A comparative structural diagram of a driving transistor and a data writing transistor provided for embodiments of this application;

[0022] Figure 13 This is a plan view of a display device provided in an embodiment of this application. Detailed Implementation

[0023] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0024] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0025] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0026] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0027] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0028] It should be understood that although terms such as "first," "second," etc., may be used to describe sub-pixels, data lines, gating switches, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish sub-pixels, data lines, gating switches, etc., from each other. For example, without departing from the scope of the embodiments of this application, a first sub-pixel may also be referred to as a second sub-pixel, and similarly, a second sub-pixel may also be referred to as a first sub-pixel. Through meticulous and in-depth research, the applicant of this application provides a solution to the problems existing in the prior art.

[0029] Figure 1 This is a plan view of a display panel provided in an embodiment of this application. Figure 2 This application provides a timing diagram of the operation of a sub-pixel in a related art. Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 4 This is a timing diagram of a sub-pixel provided in an embodiment of this application.

[0030] This application embodiment provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes a plurality of sub-pixels 10 and a plurality of data lines 20, with the data lines 20 electrically connected to the sub-pixels 10. Each sub-pixel 10 includes a first sub-pixel 101 and a second sub-pixel 102 alternately arranged along a first direction X1. In this embodiment, the example is described with the first direction X1 as the row direction, and the first sub-pixel 101 and the second sub-pixel 102 located in the same row. Each data line 20 includes a first data line 201 and a second data line 202. The first sub-pixel 101 is electrically connected to the first data line 201, and the second sub-pixel 102 is electrically connected to the second data line 202. The first data line 201 and the second data line 202 sequentially receive the data signal Vdata.

[0031] like Figure 2 As shown, in related technologies, when multiple sub-pixels 10 located in the same row enter the data writing stage E1, the time when the first data line 201 receives the data signal Vdata and the time when the second data line 202 receives the data signal Vdata both include a reset time t1 and a remaining writing time t2. During the reset time t1, the latest data signal Vdata mainly covers the data signal Vdata written in the previous row, while the remaining writing time t2 mainly involves the data lines continuously writing the latest data signal Vdata. Combined with... Figure 3As shown, since the first data line 201 and the second data line 202 need to receive data signals sequentially, and the first sub-pixel 101 and the second sub-pixel 102 are located in the same row, after the first data line 201 receives the data signal Vdata, it must wait at least until the second data line 202 completes the reset time t1 before the data writing module 200A in the pixel circuit 200 of the first pixel 101 and the second sub-pixel 102 can be turned on. Taking the total time of multiple sub-pixels 10 in the same row being in the data writing stage E1 as time1, the time left for the driving transistor Md in the pixel circuit 200 to write the data signal Vdata on the first data line 201 and the second data line 202 is only time1-2*t1-t2.

[0032] It should be noted that in this embodiment, the first control signal S1 is used to control whether the first data line 201 can receive the data signal Vdata, the second control signal S2 is used to control whether the second data line 202 can receive the data signal Vdata, and the third control signal S3 is used to control whether the data writing module 200A in the pixel circuit 200 is turned on. Furthermore, the first control signal S1, the second control signal S2, and the third control signal S3 are all at a low level as enable signals.

[0033] As can be seen from the aforementioned related technologies, after the first data line 201 electrically connected to the first sub-pixel 101 receives the data signal Vdata, the pixel circuit 200 in the first sub-pixel 101 cannot immediately start receiving the data signal Vdata. Instead, it must wait at least until the second data line 202 electrically connected to the second sub-pixel 101 receives the data signal Vdata to complete the reset time t1. Thus, the time that the first sub-pixel 101 and the second sub-pixel 102 can receive the data signal Vdata before the next row of sub-pixels enters the data writing stage E1 is relatively short, which is detrimental to the correct writing of the data signal Vdata to the sub-pixel 10.

[0034] To extend the data signal reception time of sub-pixel 10 and ensure the accuracy of the data signal received by sub-pixel 10, combined with Figure 4 As shown, in this embodiment of the application, the time when the first data line 201 receives the data signal Vdata at least partially coincides with the time when the second data line 202 is reset. (Continue to refer to...) Figure 2As shown, in related technologies, when the first data line 201, electrically connected to the first sub-pixel 101, receives the data signal Vdata, the second data line 202, electrically connected to the second sub-pixel 102, is in a waiting phase. At this time, the second sub-pixel 102 is not activated and the second data line 202 does not receive the data signal Vdata. Therefore, this application proposes resetting the second data line 202 during the time the first data line 201 receives the data signal Vdata. This is equivalent to resetting the second data line 202 in advance. Thus, after the first data line 201 completes its data signal Vdata reception phase, there is no need to wait for the second data line 202 to reset; the first sub-pixel 101 and the second sub-pixel 102 can be simultaneously activated to receive the data signal Vdata, making it possible to extend the data writing time of the first sub-pixel 101 and the second sub-pixel 102.

[0035] For example, such as Figure 4 As shown, when the first data line 201 starts receiving the data signal Vdata, the second data line 202 is reset. After a reset time t1, both the first data line 201 and the second data line 202 are ready to simultaneously activate the data writing module 200A in both the first sub-pixel 101 and the second sub-pixel 102. This extends the data writing time of the first sub-pixel 101 to (time1-t1) and the data writing time of the second sub-pixel 102 to (time1-t1-t2).

[0036] In this embodiment, the time when the first data line 201 receives the data signal Vdata coincides at least partially with the time when the second data line 202 is reset. This helps reduce the idle time of the second data line 202 between the start of the first data line 201 receiving the data signal Vdata and the start of the second data line 202 receiving the data signal Vdata, thus improving the operational efficiency between the first data line 201 and the second data line 202. This prepares for extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102. Furthermore, it facilitates the earlier reset of the second data line 202 when the first data line 201 receives the data signal Vdata, which allows for earlier activation of the data writing module 200A in the first sub-pixel 101 and the second sub-pixel 102, thereby extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102.

[0037] In one embodiment of this application, reference continues to be made to... Figure 4As shown, the time when the first sub-pixel 101 receives the data signal Vdata is at least partially coincided with the time when the second data line 202 receives the data signal Vdata. When the first sub-pixel 101 starts receiving the data signal Vdata, since the first sub-pixel 101 and the second sub-pixel 102 are located in the same row, the data writing module 200A in the second sub-pixel 102 is also activated. Furthermore, the reset operation of the second data line 202 is completed before the first sub-pixel 101 starts receiving the data signal Vdata. Therefore, the time when the second data line 202 receives the data signal Vdata is at least partially coincided with the time when the first sub-pixel 101 receives the data signal Vdata is facilitated by writing the data signal Vdata into the second sub-pixel 102 simultaneously with the second data line 202 receiving the data signal Vdata, thus extending the duration of writing the data signal Vdata into the second sub-pixel 102.

[0038] Figure 5 This is a plan view of another display panel provided in an embodiment of this application.

[0039] In one embodiment of this application, combined with Figure 4 , Figure 5 As shown, the display panel 100 also includes a reset module 30, which is electrically connected to the second data line 202 and is used to reset the second data line 202. Optionally, a fourth control signal S4 is set as a control signal to control the reset module 30 to turn on, and the fourth control signal S4 is a valid signal when it is at a low level.

[0040] In related technologies, the reset of the first data line 201 and the second data line 202 involves the source data line transmitting the data signal Vdata required by the current row sub-pixel 10 to the data line 20 for a period of time, thereby overriding the data signal Vdata transmitted by the data line 20 to the previous row sub-pixel 10. However, the same source data line typically transmits the data signal Vdata required by the first sub-pixel 101 and the second sub-pixel 102 sequentially during operation. When the first data line 101 receives the data signal Vdata, the source data line cannot simultaneously transmit the data signal Vdata required by the second data line 102. This results in the reset of the second data line 201 having to wait until the first data line 201 has finished receiving the data signal Vdata, thus delaying the start time for the first sub-pixel 101 and the second sub-pixel 102 to receive the data signal Vdata.

[0041] In this embodiment, the display panel 100 includes a reset module 30. When the first data line 201 receives the data signal Vdata, a fourth control signal S4 transmits an enable signal to control the reset module 30 to be turned on, for resetting the second data line 202. This embodiment uses a separate module to reset the second data line 202, which helps to resolve the situation where the first data line 201 and the second data line 202 are queuing to be reset using the source data line. It also allows the reset module 30 to reset the second data line 202 simultaneously with the first data line 201 receiving the data signal Vdata, thus enabling the second data line 202 to be reset earlier. This advances the time when the first sub-pixel 101 and the second sub-pixel 102 begin receiving the data signal Vdata, extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102, ensuring the accuracy of the received data signal Vdata, thereby improving the accuracy of the light emission brightness of the sub-pixel 101 and the display panel 100.

[0042] Figure 6 This is a plan view of another display panel provided in an embodiment of this application.

[0043] In one embodiment of this application, combined with Figure 5 , Figure 6 As shown, the reset module 30 includes a first transistor T1. The first terminal of the first transistor T1 receives the reset signal Vref, and the second terminal is electrically connected to the input terminal 202A of the second data line 202. In this embodiment, the first transistor T1 is described as a P-type transistor.

[0044] In this embodiment, the reset module 30 includes a first transistor T1, which facilitates the use of the first transistor T1 to reset the second data line 202. Optionally, when the first data line 201 begins receiving the data signal Vdata, the fourth control signal S4 transmits an enable signal to control the first transistor T1 to also turn on. This causes the first transistor T1 to transmit the reset signal Vref to the second data line 202, resetting the second data line 202. Figure 4 As shown, the duration for the first transistor T1 to reset the second data line 202 can be similar to the duration for the first data line 201 to receive the data signal Vdata. This is because the source data line only transmits the data signal Vdata required by the first sub-pixel 101 at this time. This helps reduce the time the second data line 202 is idle between the start of the first data line 201 receiving the data signal Vdata and the start of the second data line 202 receiving the data signal Vdata. Furthermore, setting a longer turn-on time for the first transistor T1 helps to improve the completion of the reset operation for the second data line 202.

[0045] It should be noted that when the data writing module 200A in the first sub-pixel 101 and the second sub-pixel 102 begins after the first data line 201 completes the reset time t1, the second sub-pixel 102 receives the reset signal Vref at this time. The reset signal Vref proposed in this embodiment has a low potential, which allows the process of the second data line 202 starting to receive the data signal Vdata and writing the data signal Vdata into the pixel circuit 200 to be completed smoothly, and ensures that the second sub-pixel 102 can receive the accurate data signal Vdata.

[0046] In one embodiment of this application, reference continues to be made to... Figure 5 , Figure 6 As shown, the first terminal of the first transistor T1 is electrically connected to either the ground terminal GND or the light-emitting test terminal V1. In the display panel 100, the ground terminal GND is a commonly used signal terminal. Connecting the first terminal of the first transistor T1 to the ground terminal GND facilitates the smooth release of the signal on the second data line 202 to ground after the first transistor T1 is turned on, thereby completing the reset of the second data line 202. Furthermore, using the ground terminal GND as the reset signal terminal helps reduce the number of signal terminals in the display panel 100.

[0047] The light-emitting test terminal V1 is used during the fabrication of the display panel 100 to detect whether the light-emitting device 300 can emit light normally. During testing, a virtual data signal can be set at the light-emitting test terminal V1 to drive the light-emitting device 300 to emit light. After the testing is completed, some idle light-emitting test terminals V1 may remain on the display panel 100. In this case, the light-emitting test terminal V1 can be used as a port for outputting the reset signal Vref, which helps to reduce the number of fabrication signal terminals in the display panel 100 and reduce the fabrication cost of the display panel 100. Furthermore, the magnitude of the output reset signal Vref can be flexibly adjusted using the light-emitting test terminal V1, which helps to improve the applicability of the reset module 30.

[0048] In one embodiment of this application, reference continues to be made to... Figure 4 As shown, the operation of sub-pixel 10 includes a data writing stage E1 and a light emission stage E2, with the data writing stage E1 occurring before the light emission stage E2. After sub-pixel 10 completes the data writing stage E1, the pixel circuit 200 in sub-pixel 10 receives a valid light emission control signal EMI T, causing the pixel circuit 200 to generate a light emission driving current and transmit it to the light emission device 300, thus completing the display of sub-pixel 10.

[0049] The data writing phase E1 includes:

[0050] In the first charging stage E11, the first data line 201 receives the data signal Vdata. In the first charging stage E11, the source data line transmits the data signal Vdata required by the first sub-pixel 101 to the first data line 201.

[0051] The reset sub-stage E12 is performed simultaneously with the first charging sub-stage E11. The reset module 30 transmits a reset signal Vref to the second data line 202, which is beneficial to complete the reset of the second data line 202 in advance.

[0052] The data writing sub-stage E13 begins after the first charging sub-stage E11, following the first time period t3. At this time, the data writing module 200A of the pixel circuit 200 in the first sub-pixel 101 and the second sub-pixel 102 receives the enable signal transmitted by the data writing control signal line SCAN1, and the data writing module 200A is activated. The first sub-pixel 101 begins receiving the data signal Vdata transmitted by the first data line 201, and the second sub-pixel 102 begins receiving the reset signal Vref transmitted by the second data line 202.

[0053] The second charging sub-stage E14 occurs after the first charging sub-stage E11 is completed. At this time, the source data line begins to transmit the data signal Vdata required by the second sub-pixel 102. The second data line 202 receives the data signal Vdata, and the data writing module 200A of the pixel circuit 200 in the second sub-pixel 102 remains on, allowing the second sub-pixel 102 to receive the data signal Vdata transmitted by the second data line 202.

[0054] Specifically, the data writing sub-stage E13 is performed some time after the start of the first charging sub-stage E11, and continues until the end of the second charging sub-stage E14 and before the start of the first charging sub-stage E11 for the next row of sub-pixels 10, thus avoiding writing the data signal Vdata required by the next row of sub-pixels 10 into the current row of sub-pixels 10.

[0055] In this embodiment, the reset sub-stage E12 and the first charging sub-stage E11 are performed simultaneously, and the data writing sub-stage E13 is performed after the beginning of the first charging sub-stage E11. This helps to extend the time for the first sub-pixel 101 and the second sub-pixel 102 to be written with the data signal Vdata, thereby improving the accuracy of the data signal Vdata received by the sub-pixel 10.

[0056] In one embodiment of this application, reference continues to be made to... Figure 4As shown, the first time period t3 is used to reset the first data line 101. As mentioned in the above embodiment, the time for the first data line 101 to receive the data signal Vdata includes the reset time t1 and the remaining write time t2. The first time period t3 described here is the same as the reset time t1, both being the time for resetting the first data line 101. During the operation of the display panel 100, it is necessary to reset the first data line 201 and the second data line 202 before starting the data writing sub-stage E13. This helps ensure the accuracy of the data signals received by the first sub-pixel 101 and the second sub-pixel 102.

[0057] Figure 7 This is a plan view of another display panel provided in an embodiment of this application.

[0058] In one embodiment of this application, such as Figure 7 As shown, the display panel 100 also includes a multiplexing circuit 40, which is used to transmit data signals Vdata for the first data line 201 and the second data line 202 in a time-division multiplexing manner. The multiplexing circuit 40 includes at least a first gating switch 401 and a second gating switch 402. The first terminal of the first gating switch 401 is electrically connected to the source data line Sdata, and the second terminal is electrically connected to the input terminal 101A of the first data line 201. The first terminal of the second gating switch 402 is electrically connected to the source data line Sdata, and the second terminal is electrically connected to the input terminal 202A of the second data line 202. Based on the above, in this embodiment, a first control signal S1 controls whether the first gating switch 401 is turned on, and a second control signal S2 controls whether the second gating switch 402 is turned on. This embodiment uses the example of two adjacent first data lines 201 and second data lines 201 being electrically connected to the same source data line Sdata. Optionally, both the first gating switch 401 and the second gating switch 402 are switching transistors. The transistors described in the embodiments of this application are all P-type transistors.

[0059] The reset module 30 is electrically connected between the input terminal 202A of the second data line 202 and the second terminal of the second selector switch 402. When the reset module 30 is turned on, it directly transmits the reset signal Vref to the second data line 202, which helps to avoid the signal transmitted by the reset module 30 from conflicting with the signal transmitted by the source data line.

[0060] In this embodiment, using a multiplexer circuit 40 to transmit the data signal Vdata for the data line 20 helps reduce the number of data signal terminals in the display panel 100 and improves the space utilization of the display panel 100. Furthermore, as described above, when using a multiplexer circuit 40 in the display panel 100, multiple data lines 20 electrically connected to multiple sub-pixels 10 in the same row need to wait for the source data line Sdata to sequentially transmit the currently required data signal Vdata. Moreover, the data lines 20 must be reset for a period of time before the data writing module 200A of the pixel circuit 200 in the multiple sub-pixels 10 can be activated. This significant waiting time compresses the time when the sub-pixel 10 is in the data writing sub-stage E13, affecting the accuracy of the data signal Vdata received by the sub-pixel 10. In this embodiment, a reset module 30 is provided, and the reset module 30 works in conjunction with the multiplexer circuit 40. Figure 4 As shown, when the first selection switch 401 is turned on, the source data line Sdata and the first data line 101 are connected, and the data signal Vdata transmitted by the source data line Sdata resets and charges the first data line 201. At the same time, the reset module 30 is also turned on, so that the reset signal Vref is transmitted to the second data line 202, completing the reset of the second data line 202. After both the first data line 201 and the second data line 202 have been reset, the first sub-pixel 101 and the second sub-pixel 102 located in the same row are controlled to enable the data writing control signal line SCAN1 of the data writing module 200A to transmit the enable signal, and the first sub-pixel 101 and the second sub-pixel 102 can receive the data signal Vdata. In summary, by setting the display panel 100 to include the multiplexer circuit 40 and the reset module 30, it is beneficial to use the reset module 30 to fill the working blank time between the sub-pixels 10 in the same row, advance the reset time of multiple sub-pixels 10, thereby providing conditions for advancing the start time of the data writing sub-stage E13, and improving the time when the sub-pixel 10 is in the data writing sub-stage E13.

[0061] Figure 8 This is a plan view of yet another display panel provided in an embodiment of this application. Figure 9 This is another working timing diagram of a sub-pixel provided in the embodiments of this application.

[0062] For example, the multiplexing circuit 40 proposed in the embodiments of this application can also be as follows: Figure 8As shown, the display panel 100 also includes a plurality of sub-pixels 10 arranged along a sixth direction X6. The sixth direction X6 intersects with the first direction X1. Optionally, the sixth direction X6 is a column direction. In this embodiment, it is taken that the plurality of sub-pixels 10 located in odd-numbered columns are all first sub-pixels 101, and the plurality of sub-pixels 10 located in even-numbered columns are all second sub-pixels 102. Among them, the first data line 201 for transmitting the data signal Vdata of the first sub-pixels 101 in the same column is divided into a first sub-data line 201A and a second sub-data line 201B. The first sub-data line 201A is electrically connected to the plurality of sub-pixels located in odd-numbered rows of the first sub-pixels 101 in the same column, and the second sub-data line 201B is electrically connected to the plurality of sub-pixels located in even-numbered rows of the first sub-pixels 101 in the same column. The second data line 202 of the second sub-pixel 102 located in the same column that transmits the data signal Vdata is divided into a third sub-data line 202A and a fourth sub-data line 202B. The third sub-data line 202A is electrically connected to multiple sub-pixels located in odd-numbered rows of the second sub-pixel 102 in the same column, and the fourth sub-data line 202B is electrically connected to multiple sub-pixels located in even-numbered rows of the second sub-pixel 102 in the same column.

[0063] Optionally, a group of first sub-data lines 201A, second sub-data lines 201B, third sub-data lines 202A, and fourth sub-data lines 202B electrically connected to adjacent columns of sub-pixels 10 in the first direction X1 are electrically connected to the same source data line Sdata. This helps to avoid the risk of long waiting times when multiple data lines 20 are electrically connected to the same source data line Sdata, which requires the source data line Sdata to transmit the data signals Vdata required by multiple data lines 20 sequentially, thereby improving the working efficiency of the display panel 100. In addition, the first selection switch 401 includes a first sub-selection switch 401A and a second sub-selection switch 401B. The first sub-selection switch 401A controls whether the first sub-data line 201A can receive the data signal Vdata, and the second sub-selection switch 401B controls whether the second sub-data line 201B can receive the data signal Vdata. The second selector switch 402 includes a third sub-selector switch 402A and a fourth sub-selector switch 402B. The third sub-selector switch 402A controls whether the third sub-data line 202A can receive the data signal Vdata, and the fourth sub-selector switch 402B controls whether the fourth sub-data line 202B can receive the data signal Vdata. The first control signal S1 includes a first sub-control signal S11 and a second sub-control signal S12. The first sub-control signal S11 controls whether the first sub-selector switch 401A is on, and the second sub-control signal S12 controls whether the second sub-selector switch 401B is on. The second control signal S2 includes a third sub-control signal S21 and a fourth sub-control signal S22. The third sub-control signal S11 controls whether the third sub-selector switch 402A is on, and the fourth sub-control signal S22 controls whether the fourth sub-selector switch 402B is on.

[0064] Furthermore, the reset module 30 includes a first sub-reset module 301 and a second sub-reset module 302. Since the first sub-pixel 101 starts receiving the data signal Vdata earlier than the data line 20 electrically connected to the second sub-pixel 102, the second sub-pixel 102 has an idle time. Therefore, the first sub-reset module 301 is electrically connected between the third sub-data line 202A and the third sub-selector switch 402A, and the second sub-reset module 302 is electrically connected between the fourth sub-data line 202B and the fourth sub-selector switch 402B. The first sub-reset module 301 is used to reset the third sub-data line 202A, and the second sub-reset module 302 is used to reset the fourth sub-data line 202B. Optionally, the input terminals of the first sub-reset module 301 and the second sub-reset module 302 are electrically connected to the same signal terminal. The fourth control signal S4 includes a fifth sub-control signal S41 and a sixth sub-control signal S42. The fifth sub-control signal S41 is used to control whether the first sub-reset module 301 is turned on, and the sixth sub-control signal S42 is used to control whether the second sub-reset module 302 is turned on.

[0065] Combination Figure 9 As shown, when multiple sub-pixels 10 located in the first odd-numbered row of the display panel 100 enter the data writing stage E1:

[0066] Multiple first sub-pixels 101 located in odd-numbered columns enter the first charging sub-stage E11. At this time, the first sub-selection switch 401A is turned on to transmit the data signal Vdata to the first sub-data line 201A.

[0067] At the same time, multiple second sub-pixels 102 located in even-numbered columns enter the reset sub-stage E12. At this time, the first sub-reset module 301 is turned on to transmit the reset signal Vref to the third sub-data line 202A.

[0068] After the first time period t3 in the first charging sub-stage E11, the data writing module 200A in the first odd-numbered row receives a valid seventh sub-control signal S31, causing the first sub-pixel 101 and the second sub-pixel 102 in the first odd-numbered row to both enter the data writing sub-stage E13. The third control signal S3 includes the seventh sub-control signal S31 and the eighth sub-control signal S81. The seventh sub-control signal S31 controls whether the data writing module 200A in the odd-numbered row is activated, and the eighth sub-control signal S32 controls whether the data writing module 200A in the even-numbered row is activated.

[0069] After the first charging sub-stage E11 ends, multiple second sub-pixels 102 located in even-numbered columns enter the second charging sub-stage E14. At this time, the third sub-selection switch 402A is turned on, transmitting the data signal Vdata to the third sub-data line 202A. Simultaneously, the data signal Vdata is also transmitted to the second sub-pixels 102.

[0070] As can be seen from the above working process, after the sub-pixel 10 in the same row enters the data writing stage E1, while receiving the data signal Vdata by the first sub-data line 201A electrically connected to the first sub-pixel 101 in the odd column, the third sub-data line 202A electrically connected to the second sub-pixel 102 in the even column is reset to complete the extension of the data writing sub-stage E13 time.

[0071] Continue to combine Figure 9 As shown, when multiple sub-pixels 10 located in the first even-numbered row of the display panel 100, that is, multiple sub-pixels 10 located in adjacent rows to the multiple sub-pixels 10 in the first odd-numbered row, enter the data writing stage E1:

[0072] Multiple first sub-pixels 101 located in odd-numbered columns enter the first charging sub-stage E11. At this time, the second sub-gating switch 401B is turned on to transmit the data signal Vdata to the second sub-data line 202A.

[0073] At the same time, multiple second sub-pixels 102 located in even-numbered columns enter the reset sub-stage E12. At this time, the second sub-reset module 302 is turned on to transmit the reset signal Vref to the fourth sub-data line 202B.

[0074] After the first time period t3 in the first charging sub-stage E11, the data writing module 200A controlling the sub-pixel 10 in the first even row receives a valid eighth sub-control signal S32, so that the first sub-pixel 101 and the second sub-pixel 102 located in the first even row both enter the data writing sub-stage E13.

[0075] After the first charging sub-stage E11 ends, multiple second sub-pixels 102 located in even-numbered columns enter the second charging sub-stage E14. At this time, the fourth sub-selection switch 402B is turned on, transmitting the data signal Vdata to the fourth sub-data line 202B. Simultaneously, the data signal Vdata is also transmitted to the second sub-pixels 102.

[0076] Similarly, the sub-pixels 10 in the next multiple odd and even rows of the display panel 100 sequentially enter the data writing stage E1, and the operation steps are similar to the working process of the sub-pixels 10 in the first odd and even rows mentioned above.

[0077] Figure 10This is a plan view of yet another display panel provided in an embodiment of this application. Figure 11 This is a plan view of another display panel provided in an embodiment of this application.

[0078] In one embodiment of this application, such as Figures 10-11 As shown, the control terminal of the first gating switch 401 and the control terminal of the reset module 30 are electrically connected to the same control signal line. As can be seen from the above embodiment, when the first gating switch 401 is turned on and transmits the data signal Vdata to the first data line 201, the reset module 30 can simultaneously transmit the reset signal Vref to the second data line 202. Therefore, the first gating switch 401 and the reset module 30 have the condition to be turned on simultaneously. Furthermore, as mentioned above, the first control signal S1 can control the first gating switch 401, and the fourth control signal S4 can control whether the reset module 30 is turned on. Optionally, as... Figure 10 As shown, both the first selector switch 401 and the reset module 30 are electrically connected to the port of the first control signal S1. Alternatively, both the first control switch 401 and the reset module 30 are electrically connected to the port of the fourth control signal S4.

[0079] Alternatively, as can be seen from the above embodiments, the first sub-control signal S11 is used to control the first sub-selector switch 401A in the first selector switch 401, the second sub-control signal S12 is used to control the second sub-selector switch 401B in the first selector switch 401; the fifth sub-control signal S41 is used to control the first sub-reset module 301, and the sixth sub-control signal S42 is used to control the second sub-reset module 301. Optionally, as... Figure 11 As shown, the first sub-selection switch 401A and the first sub-reset module 301 are both electrically connected to the port of the first sub-control signal S11. Alternatively, the first sub-selection switch 401A and the first sub-reset module 301 are both electrically connected to the port of the fifth sub-control signal S41. Optionally, refer to... Figure 11 As shown, the second sub-selection switch 401B and the second sub-reset module 302 are both electrically connected to the port of the second sub-control signal S12. Alternatively, the second sub-selection switch 401B and the second sub-reset module 302 are both electrically connected to the port of the sixth sub-control signal S42.

[0080] In this embodiment, the control terminal 401A of the first selector switch 401 and the control terminal 30A of the reset module 30 are electrically connected to the same control signal line S2. This allows the first selector switch 401 and the reset module 30 to be turned on simultaneously, facilitating unified control of both and reducing the risk of malfunction between them. Furthermore, connecting the control terminal 401A of the first selector switch 401 and the control terminal 30A of the reset module 30 to the same control signal line S2 helps reduce the number of control signal lines fabricated in the display panel 100, thus lowering the manufacturing cost of the display panel 100.

[0081] Figure 12 This is a comparative structural diagram of a driving transistor and a data writing transistor provided in an embodiment of this application.

[0082] In one embodiment of this application, combined with Figure 3 As shown, sub-pixel 10 includes a pixel circuit 200, which includes a driving transistor Md and a data writing transistor T2. The data writing transistor T2 is turned on during the data writing stage E1 and writes the data signal Vdata to the driving transistor Md. As can be seen from the above embodiments, in this application embodiment, when the pixel circuit 200 enters the data writing stage E1, the data writing transistor T2 is turned on when the sub-pixel 10 enters the data writing sub-stage E13. At this time, the data signal Vdata flows along the data writing transistor T2 to the driving transistor Md.

[0083] Among them, such as Figure 12 As shown in Figure (a), the driving transistor Md includes a first active layer Md1, a first source Md2, and a first drain Md3. The first active layer Md1 extends by a distance L1 in the second direction X2, and extends by a distance L2 in the third direction X3. The second direction X2 is the direction in which the first source Md2 in the first active layer Md1 extends towards the first drain Md3. The third direction X3 intersects the second direction X2 and is parallel to the plane containing the first active layer Md1. The pixel circuit 200 also includes a threshold write transistor T3. Optionally, one terminal of the threshold write transistor T3 is electrically connected to the first drain Md3 of the driving transistor Md, and the other terminal is electrically connected to the gate of the driving transistor Md. Optionally, the data writing transistor T2 is electrically connected to the first source Md2 of the driving transistor Md. After the driving transistor Md receives the data signal Vdata, the data signal Vdata is transmitted along the first source Md2 of the driving transistor Md to the first drain Md3, and then the data signal Vdata is written to the gate of the driving transistor Md through the threshold writing transistor T3.

[0084] Combination Figure 12As shown in Figure (b), the data writing transistor T2 includes a second active layer T21, a second source T22, and a second drain T23. The second active layer T21 extends by a distance L3 in the fourth direction X4 and by a distance L4 in the fifth direction X5. The fourth direction X4 is the direction in which the second source T22 extends from the second drain T23 in the second active layer T21. The fifth direction X5 intersects with the fourth direction X4 and is parallel to the plane in which the second active layer T21 is located.

[0085] In this embodiment, L2 < L1 is set, meaning the shape of the first active layer Md1 of the driving transistor Md is such that the length of the first active layer Md1 extending from the first source Md2 to the first drain Md3 is greater than the width of the first active layer Md1 in the third direction X3. Taking the direction from the source to the drain in the active layer of the transistor as the length direction of the active layer, and the direction intersecting the direction extending from the source to the drain in the active layer as the width direction of the active layer, L2 / L1 < L4 / L3 is set so that the width-to-length ratio of the first active layer Md1 of the driving transistor Md is less than the width-to-length ratio of the second active layer T21 of the data writing transistor T2. This is beneficial for making the width of the first active layer Md1 of the driving transistor Md narrower, which helps to slow down the writing speed of the data signal Vdata. This is beneficial for significantly improving the data writing time of the sub-pixel 10 applicable to this scheme, and for reducing the impact of coupling effects in the pixel circuit 200 when the data signal Vdata writing time is too long and the data signal writing time is fast.

[0086] In addition, combined Figure 3 As shown, the pixel circuit 200 also includes a power supply voltage writing transistor T4, a light emission control module 200B, and a reset module 200C. The power supply voltage writing transistor T4 turns on after receiving a valid light emission control signal EMI T during the light emission phase E2, and writes the power supply voltage PVDD into the driving transistor Md, causing the driving transistor Md to generate a light emission driving current. The light emission control module 200B is used to turn on during the light emission phase E2 and transmit the light emission driving current to the light-emitting device 300. The reset module 200C is used to reset the light-emitting device 300 after the end of the light emission phase E2 and before the arrival of the next light emission phase E2, ensuring that the light emission driving current received by the light-emitting device 300 during the light emission phase E2 is accurate.

[0087] Figure 13 This is a plan view of a display device provided in an embodiment of this application.

[0088] This application provides a display device 400, such as... Figure 13 As shown, the display device 400 includes the display panel 100 as described in the above embodiment. The display device 400 can be a display device such as a computer, television, or mobile phone.

[0089] In the display device 400, the time when the first data line 201 receives the data signal Vdata coincides at least partially with the time when the second data line 202 is reset. This helps reduce the idle time of the second data line 202 between the start of the first data line 201 receiving the data signal Vdata and the start of the second data line 202 receiving the data signal Vdata, thereby improving the operational efficiency between the first data line 201 and the second data line 202. This prepares for extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102. Furthermore, it facilitates completing the reset of the second data line 202 earlier when the first data line 201 receives the data signal Vdata, which helps to activate the data writing module 200A in the first sub-pixel 101 and the second sub-pixel 102 earlier, thereby extending the data writing time of the first sub-pixel 101 and the second sub-pixel 102.

[0090] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, It includes multiple sub-pixels and multiple data lines, wherein the data lines are electrically connected to the sub-pixels; the sub-pixels include first sub-pixels and second sub-pixels arranged alternately along a first direction, and the data lines include first data lines and second data lines, wherein the first sub-pixels are electrically connected to the first data lines, and the second sub-pixels are electrically connected to the second data lines. The first data line and the second data line receive data signals sequentially, and the time when the first data line receives the data signal coincides at least partially with the time when the second data line is reset. The sub-pixel includes a pixel circuit, which includes a driving transistor and a data writing transistor. The data writing transistor is turned on during the data writing phase and writes the data signal to the driving transistor. The driving transistor includes a first active layer, a first source, and a first drain. The first active layer extends for a distance L1 in a second direction and for a distance L2 in a third direction. The second direction is the direction in which the first source in the first active layer extends towards the first drain. The third direction intersects the second direction and is parallel to the plane where the first active layer is located. The data writing transistor includes a second active layer, a second source, and a second drain. The second active layer extends for a distance L3 in a fourth direction and for a distance L4 in a fifth direction. The fourth direction is the direction in which the second source in the second active layer extends towards the second drain. The fifth direction intersects the fourth direction and is parallel to the plane where the second active layer is located. L2 < L1, and L2 / L1 < L4 / L3.

2. The display panel according to claim 1, characterized in that, The time when the first sub-pixel receives the data signal coincides at least partially with the time when the second data line receives the data signal.

3. The display panel according to claim 1, characterized in that, The display panel also includes a reset module, which is electrically connected to the second data line and is used to reset the second data line.

4. The display panel according to claim 3, characterized in that, The reset module includes a first transistor, the first terminal of which receives a reset signal, and the second terminal of which is electrically connected to the input terminal of the second data line.

5. The display panel according to claim 4, characterized in that, The first terminal of the first transistor is electrically connected to either the ground terminal or the light-emitting test terminal.

6. The display panel according to claim 3, characterized in that, The operation of the sub-pixel includes a data writing stage and a light emission stage, wherein the data writing stage is performed before the light emission stage; the data writing stage includes: During the first charging stage, the first data line receives the data signal; The reset sub-stage is performed simultaneously with the first charging sub-stage, during which the reset module transmits a reset signal to the second data line. The data writing sub-stage is performed after the first charging sub-stage begins for a first time period. The first sub-pixel begins to receive the data signal transmitted by the first data line, and the second sub-pixel begins to receive the reset signal transmitted by the second data line. In the second charging stage, the second data line receives the data signal, and the second sub-pixel receives the data signal transmitted by the second data line; The data writing sub-stage is performed some time after the start of the first charging sub-stage and continues until the second charging sub-stage ends and the next first charging stage begins.

7. The display panel according to claim 6, characterized in that, The first time period is used to reset the first data line.

8. The display panel according to claim 6, characterized in that, The display panel further includes a multiplexing circuit, which is used to transmit the data signal to the first data line and the second data line in a time-division multiplexing manner. The multiplexing circuit includes at least a first gating switch and a second gating switch. The first terminal of the first gating switch is electrically connected to the source data line and the second terminal is electrically connected to the input terminal of the first data line. The first terminal of the second gating switch is electrically connected to the source data line and the second terminal is electrically connected to the input terminal of the second data line. The reset module is electrically connected between the input end of the second data line and the second end of the second selector switch.

9. The display panel according to claim 8, characterized in that, The control terminal of the first selector switch and the control terminal of the reset module are electrically connected to the same control signal line.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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