Scanning drive circuit and touch display panel

Abstract

An embodiment of the present application discloses a scanning driving circuit and a touch display panel, including a plurality of scanning driving units. The plurality of scanning driving units are configured to sequentially output scanning signals to control image display in a display area. The scanning driving unit includes a signal generation unit and a signal adjustment unit. The signal generation unit and the signal adjustment unit are electrically connected to a scanning signal output node. The signal generation unit is configured to output a scanning signal at a first potential to the scanning signal output node. The signal adjustment unit is configured to adjust the scanning signal at the first potential to control the scanning signal to maintain at the first potential in a first period and at a second potential in a second period among at least two consecutive periods, so as to reduce the coupling effect of adjacent scanning lines on the first scanning line, and further reduce the coupling effect of the first scanning line on a common electrode.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a scanning driving circuit and a touch display panel. Background Art

[0002] With the increase of the Internet of Things, the human-computer interaction is becoming more and more frequent, and the demand for touch display screens is also increasing. The In-cell touch technology (In-cell refers to a method of embedding the touch panel function into the liquid crystal pixels) has been favored by the market because of its advantages such as narrow bezel, IC (chip) integrated display and touch functions, reduced IC cost, reduced module thickness and mature process. The Touch and Display Driver Integration (TDDI) technology is a commonly used method in the In-cell touch technology. The principle of the TDDI technology is usually self-capacitance touch. The common electrode of the entire panel is divided into multiple touch blocks. Each touch block is connected to the touch trace through a via, and then connected to the ICtouch (touch) channel through the touch trace.

[0003] However, in the current design, when the scanning line transmits the scanning signal to the pixel unit, it usually couples with the touch block, causing the common voltage to be pulled down, resulting in a change in the voltage difference between the pixel electrode and the common electrode in the pixel unit, and further causing horizontal stripes to appear when the touch display panel performs image display. Therefore, how to eliminate the horizontal stripes on the touch display panel is an urgent problem to be solved. Summary of the Invention

[0004] In view of the above deficiencies of the prior art, the present application provides a touch display panel and a display device that can effectively eliminate horizontal stripes.

[0005] An embodiment of the present application provides a scanning driving circuit, including a plurality of scanning driving units. The plurality of scanning driving units are used to sequentially output scanning signals to control the display area to perform image display. The scanning driving unit includes a signal generating unit and a signal adjusting unit. The signal generating unit and the signal adjusting unit are electrically connected to the scanning signal output node. The signal generating unit is used to output a scanning signal of a first potential to the scanning signal output node. The signal adjusting unit is used to adjust the scanning signal of the first potential to control the scanning signal to maintain at the first potential in at least two consecutive time periods and maintain at a second potential in a second time period, wherein the first potential is greater than the second potential.

[0006] Optionally, the signal generation unit is electrically connected to the i-th clock signal terminal, and the signal adjustment unit is electrically connected to the (i + 1)-th clock signal terminal and the (i + 2)-th clock signal terminal. The signal generation unit is configured to output a scan signal of a first potential according to the clock signal output from the i-th clock signal terminal. The signal adjustment unit pulls down the scan signal to a second potential in a first period according to the clock signal output from the (i + 1)-th clock signal terminal, and pulls up the scan signal to the first potential in a second period according to the clock signal output from the (i + 2)-th clock signal terminal.

[0007] Optionally, the signal generation unit is electrically connected to the i-th clock signal terminal, and the signal adjustment unit is electrically connected to the (i + 1)-th clock signal terminal, the (i + 2)-th clock signal terminal, the (i + 3)-th clock signal terminal, and the (i + 4)-th clock signal terminal. The signal generation unit is configured to output a scan signal of a first potential according to the clock signal output from the i-th clock signal terminal. In four consecutive periods, the signal adjustment unit pulls down the scan signal to a second potential in a first period according to the clock signal output from the (i + 1)-th clock signal terminal, pulls up the scan signal to the first potential in a second period according to the clock signal output from the (i + 2)-th clock signal terminal, pulls down the scan signal to a second potential in a third period according to the clock signal output from the (i + 3)-th clock signal terminal, and pulls up the scan signal to the first potential in a fourth period according to the clock signal output from the (i + 4)-th clock signal terminal.

[0008] Optionally, the signal adjustment unit includes a control module and a control node. The control module is electrically connected to the control node and the scan signal output node. During the process of the signal generation unit outputting a scan signal of a first potential, when the control node is at the first potential, the control module controls the scan signal output node to output a scan signal of a second potential; when the control node is at the second potential, the control module controls the scan signal output node to output a scan signal of the first potential, and the first potential is greater than the second potential.

[0009] Optionally, the signal adjustment unit further includes a first adjustment module, a second adjustment module, a third adjustment module, and a fourth adjustment module. The first adjustment module is electrically connected to the control node, the (i + 1)-th clock signal terminal, and the first voltage terminal, and is configured to control the first voltage terminal to pull up the control node to a first potential during a second period according to the clock signal output from the (i + 1)-th clock signal terminal, so as to control the control module to control the scan signal output node to output a scan signal with a second potential during the second period; the second adjustment module is electrically connected to the control node, the (i + 2)-th clock signal terminal, and the second voltage terminal, and is configured to control the second voltage terminal to pull down the control node to a second potential during a third period according to the clock signal output from the (i + 2)-th clock signal terminal, so as to control the control module to control the scan signal output node to output a scan signal with a first potential during the third period; the third adjustment module is electrically connected to the control node, the (i + 3)-th clock signal terminal, and the first voltage terminal, and is configured to control the first voltage terminal to pull up the control node to a first potential during a fourth period according to the clock signal output from the (i + 3)-th clock signal terminal, so as to control the control module to control the scan signal output node to output a scan signal with a second potential during the fourth period; the fourth adjustment module is electrically connected to the control node, the (i + 4)-th clock signal terminal, and the second voltage terminal, and is configured to control the second voltage terminal to pull down the control node to a second potential during a fifth period according to the clock signal output from the (i + 4)-th clock signal terminal, so as to control the control module to control the scan signal output node to output a scan signal with a first potential during the fifth period.

[0010] Optionally, the signal generation unit includes a pull-up module, an output module, and a first node. The pull-up module is electrically connected to the input terminal, the power supply voltage terminal, and the first node, and is configured to receive the power supply voltage from the power supply voltage terminal to pull up the first node to a first potential under the control of the input terminal. The output module is electrically connected to the i-th clock signal terminal, the first node, and the scan signal output node. When the first node is at the first potential, the output module outputs a scan signal with a first potential from the scan signal output node according to the clock signal output from the i-th clock signal terminal.

[0011] Optionally, the signal generation unit further includes a maintenance module, a pull-down control module, a pull-down module, and a second node. The maintenance module is electrically connected to the first voltage terminal, the pull-down module, and the second node, and is configured to receive a first-level signal from the first voltage terminal and transmit it to the pull-down control module and the second node, for controlling the second node to maintain at a first potential. The pull-down control module is electrically connected to the first node, the second node, and the second voltage terminal. When the first node is at the first potential, the pull-down control module controls the second voltage terminal to output a second-level signal to the second node to pull down the second node to a second potential. When the first node is at the second potential, the pull-down control module controls the second voltage terminal to stop outputting the second-level signal to the second node, for controlling the second node to pull up to the first potential under the control of the maintenance module. The pull-down module is electrically connected to the second node, the scan signal output node, and the second voltage terminal. When the second node is at the first potential, the pull-down module controls the scan signal output node to output a scan signal at the second potential. When the second node is at the second potential, the pull-down module controls the scan signal output node to output a scan signal at the first potential.

[0012] Optionally, the signal generation unit further includes a first reset module and a second reset module. The first reset module is electrically connected to the first reset control terminal, the low-voltage terminal, and the first node, and is configured to connect the first node to the low-voltage terminal under the control of the first reset control terminal, for resetting the first node to a preset potential. The second reset module is electrically connected to the scan signal output node, the output module, the second reset control terminal, and the third reset control terminal, and is configured to reset the scan signal output node and the output module to a preset potential under the control of the second reset control terminal and the third reset control terminal.

[0013] Optionally, the first adjustment module includes a first control transistor, the second adjustment module includes a second control transistor, the third adjustment module includes a third control transistor, and the fourth adjustment module includes a fourth control transistor; the control terminal of the first control transistor is electrically connected to the (i + 1)-th clock signal terminal, the first conductive terminal of the first control transistor is electrically connected to the first voltage terminal, and the second conductive terminal of the first control transistor is electrically connected to the control node, and is used to conduct under the control of the clock signal output from the (i + 1)-th clock signal terminal, so as to control the first voltage terminal to output a first level signal to the control node to pull up the control node to the first potential; the control terminal of the second control transistor is electrically connected to the (i + 2)-th clock signal terminal, the first conductive terminal of the second control transistor is electrically connected to the control node, and the second conductive terminal of the second control transistor is electrically connected to the second voltage terminal, and is used to conduct under the control of the clock signal output from the (i + 2)-th clock signal terminal, so as to control the second voltage terminal to output a second level signal to the control node to pull down the control node to the second potential; the control terminal of the third control transistor is electrically connected to the (i + 3)-th clock signal terminal, the first conductive terminal of the third control transistor is electrically connected to the first voltage terminal, and the second conductive terminal of the third control transistor is electrically connected to the control node, and is used to conduct under the control of the clock signal output from the (i + 3)-th clock signal terminal, so as to control the first voltage terminal to output a first level signal to the control node to pull up the control node to the first potential; the control terminal of the fourth control transistor is electrically connected to the (i + 4)-th clock signal terminal, the first conductive terminal of the fourth control transistor is electrically connected to the control node, and the second conductive terminal of the fourth control transistor is electrically connected to the second voltage terminal, and is used to conduct under the control of the clock signal output from the (i + 4)-th clock signal terminal, so as to control the second voltage terminal to output a second level signal to the control node to pull down the control node to the second potential.

[0014] Optionally, the control module includes a fifth control transistor, the control terminal of the fifth control transistor is electrically connected to the control node, the first conductive terminal of the fifth control transistor is electrically connected to the scan signal output node, and the second conductive terminal of the fifth control transistor is electrically connected to the second voltage terminal; in the second time period, the control node controls the fifth control transistor to conduct, and the second voltage terminal outputs a second level signal to the scan signal output node to control the scan signal output node to output a scan signal of the second potential; in the third time period, the control node controls the fifth control transistor to cut off, and the second voltage terminal stops outputting the second level signal to the scan signal output node to control the scan signal output node to output a scan signal of the first potential; in the fourth time period, the control node controls the fifth control transistor to conduct, and the second voltage terminal outputs a second level signal to the scan signal output node to control the scan signal output node to output a scan signal of the second level signal.

[0015] The embodiment of the present application further provides a touch display panel, which includes pixel units arranged in an array, a data driving circuit, and the scanning driving circuit as described above. The scanning driving circuit is configured to output the scanning signal to the pixel units through scanning lines, and control the pixel units to receive the data signal from the data driving circuit through data lines. The pixel unit includes a pixel electrode and a common electrode. The pixel electrode and the common electrode perform image display according to the data signal during the display period within a frame image display period. The common electrode is further configured to detect a touch operation during the touch period within a frame image display period. The display period and the touch period are continuous in time.

[0016] Compared with the prior art problems, in the embodiment of the present application, by controlling each scanning signal in at least two consecutive periods, the scanning signal is controlled to be at a first potential in one period and at a second potential in another period, thereby reducing the coupling effect of adjacent scanning lines on the first scanning line, effectively reducing the coupling effect of the first scanning line on the common electrode, further narrowing the coupling difference between the first scanning line and the middle scanning lines on the common electrode, and eliminating the horizontal stripe phenomenon during image display. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the following described drawings are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic structural diagram of a display device provided by an embodiment of the present application;

[0019] Figure 2 For Figure 1 a schematic plan layout diagram of the touch display panel in

[0020] Figure 3 a schematic plan layout diagram of the common electrode;

[0021] Figure 4 a schematic diagram of the time-division driving for touch and display of the touch display panel;

[0022] Figure 5 For Figure 2 the output timing diagram of the scanning signal in

[0023] Figure 6 a schematic circuit architecture diagram of a scanning driving circuit provided by an embodiment of the present application;

[0024] Figure 7 For Figure 6Schematic diagram of the equivalent circuit of the scan driving unit;

[0025] Figure 8 is Figure 7 Schematic diagram of the output waveform of the scan signal in;

[0026] Figure 9 Schematic diagram of the waveforms of a plurality of sequentially output scan signals.

[0027] Reference numerals:

[0028] Display device - 100, touch display panel - 10, power supply module - 30, display area - 10a, array substrate - 10c, first direction - F1, second direction - F2, timing control circuit - 11, data driving circuit - 12, scan driving circuit - 20, m data lines - S1~Sm, n scan lines - G1~Gn, pixel unit - P, common electrode - Vcom, first period - t1, second period - t2, third period - t3, fourth period - t4, fifth period - t5, sixth period - t6, first clock signal terminal to sixth clock signal terminal - CLK1~CLK6, start signal - STV, scan driving unit - 20a, signal generating unit - 21, signal adjusting unit - 22, pull-up module - 211, output module - 212, maintaining module - 213, pull-down control module - 214, pull-down module - 215, first reset module - 216, second reset module - 217, first adjusting module - 221, second adjusting module - 222, third adjusting module - 223, fourth adjusting module - 224, control module - 225, control node - QT, first capacitor - C1, first switching transistor - T1, second switching transistor - T2, third switching transistor - T3, fourth switching transistor - T4, fifth switching transistor - T5, sixth switching transistor - T6, seventh switching transistor - T7, eighth switching transistor - T8, ninth switching transistor - T9, tenth switching transistor - T10, eleventh switching transistor - T11, first control transistor - CT1, second control transistor - CT2, third control transistor - CT3, fourth control transistor - CT4, fifth control transistor - CT5, i-th clock signal terminal - CLKi, (i + 1)-th clock signal terminal - CLKi+1, (i + 2)-th clock signal terminal - CLKi+2, (i + 3)-th clock signal terminal - CLKi+3, (i + 4)-th clock signal terminal - CLKi+4, i-th scan line - Gi, (i + 1)-th scan line - Gi+1, (i + 2)-th scan line - Gi+2, (i + 3)-th scan line - Gi+3, (i + 4)-th scan line - Gi+4, (i + 5)-th scan line - Gi+5, (i + 6)-th scan line - Gi+6, input terminal - IN, power supply voltage terminal - VDD, first node - Q1, second node - Q2, scan signal output node - OUT, first voltage terminal - VGH, second voltage terminal - VGL, first reset control terminal - R1, second reset control terminal - R2, third reset control terminal - R3, low voltage terminal - VSS. Detailed implementation manners

[0029] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0030] The descriptions of the following embodiments refer to the attached drawings, which are used to illustrate specific embodiments in which the present application can be implemented. The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meanings. The terms "connection" and "coupling" as used in the present application, unless otherwise specified, both include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present application.

[0031] In the description of the present application, it should be noted that, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order.

[0032] In addition, the terms "include", "may include", "comprise", or "may comprise" used in the present application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. Moreover, the term "include" or "comprise" means the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and does not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, intending to cover non-exclusive inclusion. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0034] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a display device provided for an embodiment of the present application. AsFigure 1 As shown, the display device 100 includes a touch display panel 10 and a power supply module 30. The power supply module 30 is disposed on the back surface of the touch display panel 10, that is, the non-display surface of the touch display panel 10. The power supply module 30 is used to provide a power voltage for the touch display panel 10 to perform image display. In the embodiment of the present application, the display device 100 may be a portable electronic device, such as a mobile phone, a tablet computer, etc.

[0035] Please refer to Figure 2 , Figure 2 is Figure 1 a schematic plan layout diagram of the touch display panel in

[0036] As Figure 2 shown, the touch display panel 10 includes a display area 10a. The display area 10a is provided with a plurality of pixel units arranged in an array, as well as m data lines S1~Sm and n scan lines G1~Gn, where m and n are natural numbers greater than 1.

[0037] Among them, the n scan lines G1~Gn extend along a first direction F1 and are insulated from each other and arranged in parallel along a second direction F2. The m data lines S1~Sm extend along the second direction F2 and are insulated from each other and arranged in parallel along the first direction F1. The first direction F1 is perpendicular to the second direction F2.

[0038] In the non-display area of the touch display panel 10, the display device 100 is further provided with a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 20 for driving the pixel units to perform image display.

[0039] Among them, the timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 20, and is used to control the working timing of the data driving circuit 12 and the scan driving circuit 20, that is, to output corresponding timing control signals to the data driving circuit 12 to the scan driving circuit 20 to control when to output corresponding scan signals and data signals.

[0040] The data driving circuit 12 is electrically connected to the m data lines S1~Sm, and is used to transmit the data signal (Data) to be displayed to a plurality of pixel units P in the form of a data voltage through the m data lines S1~Sm. The pixel unit P transmits the received data signal to a pixel electrode (not labeled) to control a voltage difference formed between the pixel electrode and a common electrode ( Figure 3 ) so as to drive the display medium (liquid crystal molecules in this embodiment) to rotate to emit light for image display.

[0041] The scan driving circuit 20 is used to be electrically connected to the n scan lines G1~Gn, and is configured to output scan signals through the n scan lines G1~Gn to control when the pixel unit P receives data signals. Among them, the scan driving circuit 20 outputs scan signals from the scan lines G1, G2, ……, Gn in sequence according to the scan cycle from the n scan lines G1~Gn in the order of position arrangement.

[0042] In this embodiment, the circuit elements in the scan driving circuit 20 and the pixel unit P in the array substrate 10c are fabricated in the array substrate 10c in the same manufacturing process, that is, the GOA (Gate Driver on Array) technology.

[0043] Please refer to Figure 3 、 Figure 4 and Figure 5 , Figure 3 for the planar layout schematic diagram of the common electrode, Figure 4 for the time-sharing driving schematic diagram of touch and display of the touch display panel, Figure 5 and Figure 2 for the scan signal output timing diagram in

[0044] As shown in Figure 3 、 Figure 4 and Figure 5 the touch display panel 10 includes a plurality of common electrodes Vcom arranged in an array, and the plurality of common electrodes Vcom are driven and displayed by a time-sharing driving method. The specific driving and displaying method is that when the touch display panel 10 performs touch display, it includes multiple frame display scanning periods that are continuous in time. As shown in the figure, the a-th frame display scanning period and the (a + 1)-th frame display scanning period are any two adjacent frame display scanning periods among the multiple frame display scanning periods, where a is an integer greater than or equal to 1. Among them, each frame display scanning period includes a display period and a touch period. During the display period, each common electrode Vcom inputs a common voltage, and the pixel electrodes in the pixel unit P form a voltage difference based on the data signal and the common voltage in the common electrode Vcom to drive the display medium to perform image display. During the touch period, each common electrode Vcom serves as a touch electrode to input a touch signal for sensing touch instructions.

[0045] Among them, during the display period of a frame of image, n scan lines G1 to Gn sequentially output scan signals. When the scan lines transmit the scan signals, they will interact with each other through coupling, and then interact with the common electrode Vcom, resulting in a change in the common voltage on the common electrode. When the scan lines extend along the first direction F1 and are located at the middle position of each common electrode Vcom, that is, the scan lines covered by the common electrode Vcom, the coupling effects of the upper and lower adjacent scan lines on each scan line can cancel each other out, thereby eliminating the coupling effect on the common electrode Vcom. However, at the edge position of the common electrode Vcom, the coupling effect on the scan line cannot be cancelled, which further increases the coupling effect on the common electrode Vcom and causes a change in the voltage of the common electrode Vcom.

[0046] For example, the second scan line G2, the third scan line G3, and the fourth scan line G4 extend along the first direction F1 and are located at the middle position of the common electrode Vcom. That is, in the thickness direction of the array substrate 10c, the common electrode Vcom covers the second scan line G2, the third scan line G3, and the fourth scan line G4. Among them, during the process of the third scan line G3 outputting the scan signal, the falling edge of the second scan signal has a downward coupling effect on the third scan signal, resulting in a decrease in the voltage of the third scan signal, while the rising edge of the fourth scan signal has an upward coupling effect on the third scan signal, resulting in an increase in the voltage of the third scan signal, thereby canceling the upward coupling effect of the second scan signal and making the coupling effect of the third scan line G3 on the common electrode Vcom smaller. Similarly, the coupling effects of other scan lines set at the middle position on the common electrode Vcom are also smaller.

[0047] The first scan line G1 is located at the edge position of the common electrode Vcom. During the process of the first scan line outputting the scan signal, the second scan line G2 to the sixth scan line G6 sequentially output the second scan signal to the sixth scan signal. Among them, the rising edges of the second scan signal to the sixth scan signal all have an upward coupling effect on the first scan signal, resulting in the cumulative coupling effect on the first scan signal that cannot be cancelled, thereby causing a large upward coupling effect on the first scan signal, resulting in an increase in the voltage of the first scan signal, thereby causing an increase in the coupling effect of the first scan line G1 on the common electrode Vcom, resulting in a difference in the voltage of the common electrode Vcom at the position corresponding to the first scan line G1 and the voltage of the common electrode Vcom at the positions corresponding to the second scan line G2 to the sixth scan line G6, thereby causing a horizontal stripe phenomenon when the display panel displays an image.

[0048] Based on this, the present application provides a scan driving circuit, which adjusts the scan signal to eliminate the horizontal stripe phenomenon in image display caused by the coupling effect between the scan line and the common electrode Vcom.

[0049] Please refer to Figure 6, Figure 6 It is a schematic diagram of the circuit architecture of a scan driving circuit provided by an embodiment of the present application.

[0050] As Figure 6 shown, the scan driving circuit 20 includes a plurality of cascaded scan driving units 20a. The scan driving circuit 20 includes n cascaded scan driving units 20a, six clock signal terminals (the first clock signal terminal CLK1 to the sixth clock signal terminal CLK6), a start signal STV, a reset signal R, and a low voltage terminal VSS, where n is an integer greater than or equal to 1.

[0051] Among them, in the scan driving circuit 20, each scan driving unit correspondingly outputs a scan signal to one of the scan lines in the display area 10a. During the display process of one frame of image, n scan driving units sequentially output n scan signals to n scan lines G1~Gn.

[0052] The six clock signal terminals CLK1-CLK6 are used to respectively output six clock signals to control the n scan driving units 20a to sequentially output scan signals. The start signal STV is the enabling start signal of the first scan driving unit 20a, and the other scan driving units use the cascading signal output by the cascaded scan unit as the start signal. The low voltage terminal VSS is used to provide a low voltage for the nodes in the scan driving unit.

[0053] In an exemplary embodiment, the number of clock signals can also be set to other numbers according to specific needs. For example, it can also be set to 2, 4, 8, etc. The present application does not limit this.

[0054] Please refer to Figure 7 , Figure 7 is Figure 6 the equivalent circuit schematic diagram of the scan driving unit in

[0055] As Figure 7 shown, the scan driving unit 20a includes a signal generation unit 21 and a signal adjustment unit 22. The signal generation unit 21 is electrically connected to the signal adjustment unit 22, the input terminal IN, the i-th clock signal terminal CLKi, and the scan signal output node OUT, and is used to output a scan signal of the first potential to the scan signal output node OUT under the control of the clock signal input by the i-th clock signal terminal CLKi according to the control signal input by the input terminal IN. Among them, i is an integer greater than or equal to 1. The signal adjustment unit 22 is used to control the scan signal to maintain at the first potential in the first period and at the second potential in the second period in at least two consecutive periods.

[0056] When adjusting the scanning signal in two consecutive time periods, the signal adjustment unit 22 is electrically connected to the (i + 1)-th clock signal terminal CLK(i + 1) and the (i + 2)-th clock signal terminal CLK(i + 2), and is used to adjust the scanning signal of the first potential under the control of the clock signals output by the (i + 1)-th clock signal terminal CLK(i + 1) and the (i + 2)-th clock signal terminal CLK(i + 2), so as to control the scanning signal to be at the first potential in the first time period and at the second potential in the second time period.

[0057] In another embodiment, the scanning signal can also be adjusted in four consecutive time periods. At this time, the signal adjustment unit 22 is electrically connected to the (i + 1)-th clock signal terminal CLK(i + 1), the (i + 2)-th clock signal terminal CLK(i + 2), the (i + 3)-th clock signal terminal CLK(i + 3), and the (i + 4)-th clock signal terminal CLK(i + 4), and is used to adjust the scanning signal of the first potential under the control of the clock signals output by the (i + 1)-th clock signal terminal CLK(i + 1), the (i + 2)-th clock signal terminal CLK(i + 2), the (i + 3)-th clock signal terminal CLK(i + 3), and the (i + 4)-th clock signal terminal CLK(i + 4), so as to control the scanning signal to maintain at the first potential in the first time period and the third time period among the four consecutive time periods, and maintain at the second potential in the second time period and the fourth time period, wherein the first potential is greater than the second potential.

[0058] By controlling each scanning signal in at least two consecutive time periods, so that the scanning signal is at the first potential in one time period and at the second potential in another time period, the coupling effect of adjacent scanning lines on the first scanning line is reduced, thereby effectively reducing the coupling effect of the first scanning line on the common electrode Vcom, further narrowing the coupling difference between the first scanning line and the middle scanning lines on the common electrode, and eliminating the horizontal stripe phenomenon during image display.

[0059] Among them, the signal generation unit 21 includes a pull-up module 211, an output module 212, and a first node Q1. The pull-up module 211 is electrically connected to the input terminal IN, the power supply voltage terminal VDD, and the first node Q1, and is used to receive the power supply voltage from the power supply voltage terminal VDD under the control of the input terminal IN to pull up the first node Q1 to the first potential. The output module 212 is electrically connected to the i-th clock signal terminal CLK(i), the first node Q1, and the scanning signal output node OUT. When the first node Q1 is at the first potential, the output module outputs a scanning signal of the first potential from the scanning signal output node OUT according to the clock signal output by the i-th clock signal terminal CLK(i). Among them, the scanning signal output node OUT is connected to the i-th scanning line G(i), that is, the scanning signal output by the scanning signal output node OUT is transmitted to the i-th scanning line G(i).

[0060] The signal generation unit 21 further includes a maintenance module 213, a pull-down control module 214, a pull-down module 215, and a second node Q2. Among them, the maintenance module 213 is electrically connected to the first voltage terminal VGH, the pull-down control module 214, the second node Q2, and is electrically connected to the pull-down module 215 through the second node Q2. The maintenance module 213 is configured to receive a first-level signal from the first voltage terminal VGH and transmit it to the pull-down control module 214 and the second node Q2, and is used to control the second node Q2 to maintain at the first potential.

[0061] The pull-down control module 214 is electrically connected to the first node Q1, the second node Q2, and the second voltage terminal VGL. When the first node Q1 is at the first potential, the pull-down control module 214 controls the second voltage terminal VGL to output a second-level signal to the second node Q2 to pull down the second node Q2 from the first potential to the second potential. When the first node Q1 is at the second potential, the pull-down control module 214 controls the second voltage terminal VGL to stop outputting the second-level signal to the second node Q2, so that the second node Q2 is pulled up to the first potential under the control of the maintenance module 213.

[0062] The pull-down module 215 is electrically connected to the second node Q2, the scan signal output node OUT, and the second voltage terminal VGL. When the second node Q2 is at the first potential, the pull-down module 215 outputs a second-level signal to the scan signal output node OUT according to the second voltage terminal to control the scan signal output node OUT to stop outputting the scan signal, or to output a scan signal of the second potential. When the second node Q2 is at the second potential, the pull-down module 215 stops outputting the second-level signal to the scan signal output node OUT, so that the output module 212 can output a scan signal of the first potential through the scan signal output node OUT. Among them, the scan signal of the first potential is a high-level signal, and the scan signal of the second potential is a low-level signal.

[0063] The signal generation unit 21 further includes a first reset module 216 and a second reset module 217. The first reset module 216 is electrically connected to the first reset control terminal R1, the low-voltage terminal VSS, and the first node Q1, and is used to connect the first node Q1 to the low-voltage terminal VSS under the control of the first reset control terminal R1, and is used to reset the preset potential of the first node Q1 to eliminate the residual charge in the first node Q1. The second reset module 217 is electrically connected to the scan signal output node OUT, the output module 212, the second reset control terminal R2, and the third reset control terminal R3, and is used to reset the scan signal output node and the output module 212 to the preset potential under the control of the second reset control terminal R2 and the third reset control terminal R3 to eliminate the residual charge in the scan signal output node OUT and the output module 212.

[0064] Specifically, the pull-up module 211 includes a first switching transistor T1, the output module 212 includes a second switching transistor T2 and a first capacitor C1. The control terminal of the first switching transistor T1 is electrically connected to the input terminal IN, the first conducting terminal of the first switching transistor T1 is electrically connected to the power supply voltage terminal VDD, the second conducting terminal of the first switching transistor T1 is electrically connected to the first node Q1. The first switching transistor T1 is used to conduct under the control of the input terminal to control the power supply voltage terminal VDD to charge the first node Q1, for pulling up the first node Q1 to the first potential. The control terminal of the second switching transistor T2 is electrically connected to the first node Q1, the first conducting terminal of the second switching transistor T2 is electrically connected to the i-th clock signal terminal CLKi, the second conducting terminal of the second switching transistor T2 is electrically connected to the scan signal output node OUT. The second switching transistor T2 is used to conduct when the first node Q1 is at the first potential, to output the clock signal as the scan signal from the scan signal output node OUT. At this time, the scan signal output node OUT outputs the scan signal of the first potential. The first end of the first capacitor C1 is electrically connected to the control terminal of the second switching transistor T2, the second end of the first capacitor C1 is electrically connected to the second conducting terminal of the second switching transistor T2. The first capacitor C1 is used to maintain the voltage stability when the scan signal output node OUT outputs the scan signal.

[0065] The maintaining module 213 includes a third switching transistor T3 and a fourth switching transistor T4. Wherein, the control terminal and the first conducting terminal of the third switching transistor T3 are electrically connected to the first voltage terminal VGH, the second conducting terminal of the third switching transistor T3 is electrically connected to the pull-down control module 214, the control terminal of the fourth switching transistor T4 is electrically connected to the second conducting terminal of the third switching transistor T3, the first conducting terminal of the fourth switching transistor T4 is electrically connected to the first voltage terminal VGH, the second conducting terminal of the fourth switching transistor T4 is electrically connected to the second node Q2. The third switching transistor T3 is used to conduct under the control of the first level signal output from the first voltage terminal VGH to transmit the first level signal output from the first voltage terminal VGH to the control terminal of the fourth switching transistor T4. The fourth switching transistor T4 is used to conduct under the control of the first level signal. The first voltage terminal VGH controls the second node Q2 to maintain at the first potential through the fourth switching transistor T4.

[0066] The pull-down control module 214 includes a fifth switching transistor T5 and a sixth switching transistor T6. Among them, the control terminal of the fifth switching transistor T5 is electrically connected to the first node Q1, the first conducting terminal of the fifth switching transistor T5 is electrically connected to the second conducting terminal of the third switching transistor T3 and the control terminal of the fourth switching transistor T4, and the second conducting terminal of the fifth switching transistor T5 is electrically connected to the second voltage terminal VGL. The control terminal of the sixth switching transistor T6 is electrically connected to the first node Q1, the first conducting terminal of the sixth switching transistor T6 is electrically connected to the second node Q2, and the second conducting terminal of the sixth switching transistor T6 is electrically connected to the second voltage terminal VGL. When the first node Q1 is at the first potential, the fifth switching transistor T5 and the sixth switching transistor T6 are turned on. The fifth switching transistor T5 is used to control the second conducting terminal of the third switching transistor T3, and the control terminal of the fourth switching transistor T4 is electrically connected to the second voltage terminal VGL to control the fourth switching transistor T4 to receive a second-level signal, so as to control the fourth switching transistor T4 to turn off, so that the second node Q2 stops receiving the first-level signal from the first voltage terminal VGH.

[0067] The pull-down module 215 further includes a seventh switching transistor T7 and an eighth switching transistor T8. Among them, the control terminal of the seventh switching transistor T7 is electrically connected to the second node Q2, the first conducting terminal of the seventh switching transistor T7 is electrically connected to the first node Q1, the second conducting terminal of the seventh switching transistor T7 is electrically connected to the second voltage terminal VGL, the control terminal of the eighth switching transistor T8 is electrically connected to the second node Q2, the first conducting terminal of the eighth switching transistor T8 is electrically connected to the scan signal output node OUT, and the second conducting terminal of the eighth switching transistor T8 is electrically connected to the second voltage terminal VGL. When the second node Q2 is at the first potential, the seventh switching transistor T7 and the eighth switching transistor T8 are turned on. The seventh switching transistor T7 is used to pull down the first node Q1 to the second potential under the control of the second node Q2, and the eighth switching transistor T8 is used to pull down the scan signal output node OUT to the second potential under the control of the second node Q2, that is, to control the scan signal output node OUT to output a scan signal of the second potential, or to stop outputting the scan signal.

[0068] The first reset module 216 includes a ninth switching transistor T9. The control terminal of the ninth switching transistor T9 is electrically connected to the first reset control terminal R1, the first conducting terminal of the ninth switching transistor T9 is electrically connected to the first node Q1, and the second conducting terminal of the ninth switching transistor T9 is electrically connected to the low-voltage terminal VSS. The ninth switching transistor T9 is used to turn on when the reset control terminal R outputs a reset signal, so as to control the low-voltage terminal VSS to be electrically connected to the first node Q1, and is used to pull down the first node Q1 to the second potential.

[0069] The second reset module 217 includes a tenth switching transistor T10 and an eleventh switching transistor T11. Among them, the control terminal of the tenth switching transistor T10 is electrically connected to the second reset control terminal R2. The first conducting terminal of the tenth switching transistor T10 is electrically connected to the first end of the first capacitor C1 and the first node Q1. The second conducting terminal of the tenth switching transistor T10 is electrically connected to the second voltage terminal VGL. The tenth switching transistor T10 is used to conduct under the control of the reset signal output by the second reset control terminal R2, so as to control the second voltage terminal VGL to output a second-level signal to the first capacitor C1 and the first node Q1, for resetting the first capacitor C1 and the first node Q1 to clear the residual charge in the first capacitor C1.

[0070] The control terminal of the eleventh switching transistor T11 is electrically connected to the third reset control terminal R3. The first conducting terminal of the eleventh switching transistor T11 is electrically connected to the scan signal output node OUT and the second end of the first capacitor C1. The eleventh switching transistor T11 is used to conduct under the control of the third reset control terminal R3, so as to control the second voltage terminal VGL to output a second-level signal to the scan signal output node OUT and the first capacitor C1, for resetting the scan signal output node OUT and the first capacitor C1 to clear the residual charge in the scan signal output node OUT.

[0071] Taking the adjustment of the scan signal in four consecutive time periods as an example, the signal adjustment unit 22 includes a first adjustment module 221, a second adjustment module 222, a third adjustment module 223, a fourth adjustment module 224, a control module 225 and a control node QT.

[0072] Among them, the first adjustment module 221 is electrically connected to the control node QT, the (i + 1)-th clock signal terminal CLKi+1 and the first voltage terminal VGH. The first adjustment module 221 is used to control the first voltage terminal VGH to pull up the control node QT to the first potential in the second time period according to the clock signal output by the (i + 1)-th clock signal terminal CLKi+1.

[0073] The second adjustment module 222 is electrically connected to the control node QT, the (i + 2)-th clock signal terminal CLKi+2 and the second voltage terminal VGL. The second adjustment module 222 is used to control the second voltage terminal VGL to pull down the control node QT to the second potential in the third time period according to the clock signal output by the (i + 2)-th clock signal terminal CLKi+2.

[0074] The third adjustment module 223 is electrically connected to the control node QT, the (i + 3)-th clock signal terminal CLKi+3 and the first voltage terminal VGH. The third adjustment module 223 is used to control the first voltage terminal VGH to pull up the control node QT to the first potential in the fourth time period according to the clock signal output by the (i + 3)-th clock signal terminal CLKi+3.

[0075] The fourth adjustment module 224 is electrically connected to the control node QT, the (i + 4)-th clock signal terminal CLKi+4, and the second voltage terminal VGL. The fourth adjustment module 224 is configured to control the second voltage terminal VGL to pull down the control node QT to a second potential during a fifth period according to the clock signal output from the (i + 4)-th clock signal terminal CLKi+4.

[0076] The control module 225 is electrically connected to the control node QT, the scan signal output node OUT, and the second voltage terminal VGL. When the control node QT is at a first potential, the control module 225 controls the second voltage terminal VGL to be electrically connected to the scan signal output node OUT, for pulling down the scan signal output node OUT to a second potential, that is, controlling the scan signal output node OUT to output a scan signal of the second potential during a second period and a fourth period. When the control node QT is at the second potential, the control module 225 controls the second voltage terminal VGL to be electrically disconnected from the scan signal output node OUT, so that the scan signal output node OUT outputs a scan signal of the first potential during a first period, a third period, and a fifth period.

[0077] The first adjustment module 221 includes a first control transistor CT1. The control terminal of the first control transistor CT1 is electrically connected to the (i + 1)-th clock signal terminal CLKi+1. The first conducting terminal of the first control transistor CT1 is electrically connected to the first voltage terminal. The second conducting terminal of the first control transistor CT1 is electrically connected to the control node QT. The first control transistor CT1 is configured to be turned on under the control of the clock signal output from the (i + 1)-th clock signal terminal CLKi+1, so as to control the first voltage terminal VGH to output a first level signal to the control node QT.

[0078] The second adjustment module 222 includes a second control transistor CT2. The control terminal of the second control transistor CT2 is electrically connected to the (i + 2)-th clock signal terminal CLKi+2. The first conducting terminal of the second control transistor CT2 is electrically connected to the control node QT. The second conducting terminal of the second control transistor CT2 is electrically connected to the second voltage terminal VGL. The second control transistor CT2 is configured to be turned on under the control of the clock signal output from the (i + 2)-th clock signal terminal CLKi+2, so as to control the second voltage terminal VGL to output a second level signal to the control node QT.

[0079] The third adjustment module 223 includes a third control transistor CT3. The control terminal of the third control transistor CT3 is electrically connected to the (i + 3)-th clock signal terminal CLKi+3. The first conducting terminal of the third control transistor CT3 is electrically connected to the first voltage terminal VGH. The second conducting terminal of the third control transistor CT3 is electrically connected to the control node QT. The third control transistor CT3 is configured to be turned on under the control of the clock signal output from the (i + 3)-th clock signal terminal CLKi+3, so as to control the first voltage terminal VGH to output a first level signal to the control node QT.

[0080] The fourth adjustment module 224 includes a fourth control transistor CT4. The control terminal of the fourth control transistor CT4 is electrically connected to the (i + 4)-th clock signal terminal CLKi+4. The first conductive terminal of the fourth control transistor CT4 is electrically connected to the control node QT. The second conductive terminal of the fourth control transistor CT4 is electrically connected to the second voltage terminal VGL. The fourth control transistor CT4 is used to conduct under the control of the clock signal output from the (i + 4)-th clock signal terminal CLKi+4, so as to control the second voltage terminal VGL to output a second-level signal to the control node QT.

[0081] The control module 225 includes a fifth control transistor CT5. The control terminal of the fifth control transistor CT5 is electrically connected to the control node QT. The first conductive terminal of the fifth control transistor CT5 is electrically connected to the scan signal output node OUT. The second conductive terminal of the fifth control transistor CT5 is electrically connected to the second voltage terminal VGL. The fifth control transistor CT5 is used to conduct when the control node QT is at the first potential, and the second voltage terminal VGL outputs a second-level signal through the scan signal output node OUT. The fifth control transistor CT5 is used to cut off when the control node QT is at the second potential, so that the second voltage terminal VGL stops outputting the second-level signal to the scan signal output node OUT.

[0082] It can be understood that when adjusting the scan signal in two consecutive time periods, the signal adjustment unit 22 only needs to set the first adjustment module 221, the second adjustment module 222, the control module 225 and the control node QT. Its specific circuit architecture and connection manner are the same as those in the above embodiments, and will not be elaborated herein.

[0083] Please refer to Figure 8 and Figure 9 , Figure 8 For Figure 7 the schematic diagram of the output waveform of the scan signal in Figure 9 and

[0084] As Figure 8 shown, taking the adjustment of the i-th scan signal in four consecutive time periods as an example, the scan driving unit 20a outputs the i-th scan signal including six consecutive time periods. In the first time period t1, the scan signal output node OUT outputs a scan signal at the first potential. In the second time period t2, the scan signal output node OUT outputs a scan signal at the second potential. In the third time period t3, the scan signal output node OUT outputs a scan signal at the first potential. In the fourth time period t4, the scan signal output node OUT outputs a scan signal at the second potential. In the fifth time period t5, the scan signal output node OUT outputs a scan signal at the first potential. In the sixth time period t6, the scan signal output node OUT outputs a scan signal at the first potential. Wherein, 1 ≤ i ≤ n.

[0085] As Figure 9As shown, taking the i-th scanning line Gi, which is the first scanning line covered by a common electrode Vcom, as an example, the i-th scanning line Gi outputs the i-th scanning signal through the first period t1 to the sixth period t6. During the output process of the i-th scanning signal, the coupling effects of the scanning signals output by the (i + 1)-th scanning line Gi+1 at the rising and falling edges at the beginning and end of the second period t2 cancel each other out, and the coupling effects at the rising and falling edges at the beginning and end of the fourth period t4 cancel each other out. The coupling effect at the rising edge at the initial moment of the sixth period t6 is not cancelled, thus having an upward coupling effect on the i-th scanning signal.

[0086] Similarly, the coupling effect of the scanning signal output by the (i + 2)-th scanning line Gi+2 at the rising edge at the end of the sixth period t6 is not cancelled, thus having an upward coupling effect on the i-th scanning signal. The coupling effect of the scanning signal output by the (i + 4)-th scanning line Gi+4 at the rising edge at the end of the sixth period t6 is not cancelled, thus having an upward coupling effect on the i-th scanning signal. The coupling effect of the scanning signal output by the (i + 6)-th scanning line Gi+6 at the rising edge at the end of the sixth period t6 is not cancelled, thus having an upward coupling effect on the i-th scanning signal.

[0087] However, the coupling effects of the scanning signal output by the (i + 3)-th scanning line Gi+3 at the rising and falling edges at the beginning and end of the fourth period t4 cancel each other out, and the coupling effects at the rising and falling edges at the beginning and end of the sixth period t6 cancel each other out, thus having no upward or downward coupling effect on the i-th scanning signal. The coupling effects of the scanning signal output by the (i + 5)-th scanning line Gi+5 at the rising and falling edges at the beginning and end of the sixth period t6 cancel each other out, thus having no upward or downward coupling effect on the i-th scanning signal.

[0088] Therefore, through the adjustment of the scanning signal in the embodiment of the present application, the coupling effects of multiple scanning lines under the coverage of the same common electrode Vcom on the first scanning line are reduced, thereby reducing the coupling effect of the first scanning line on the common electrode Vcom, and further weakening or eliminating the horizontal stripe phenomenon during image display.

[0089] It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above description. All such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A scan driving circuit includes a plurality of scan driving units, and the plurality of scan driving units are configured to sequentially output scan signals to control an image display in a display area, wherein The scanning driving unit includes a signal generating unit and a signal adjusting unit. The signal generating unit and the signal adjusting unit are electrically connected to a scanning signal output node. The signal generating unit is configured to output a scanning signal at a first potential to the scanning signal output node, and the signal adjusting unit is configured to adjust the scanning signal at the first potential to control the scanning signal to maintain at the first potential in a first period and at a second potential in a second period among at least two consecutive periods, wherein the first potential is greater than the second potential; The signal generating unit is electrically connected to the i-th clock signal terminal, and the signal adjusting unit is electrically connected to the (i + 1)-th clock signal terminal, the (i + 2)-th clock signal terminal, the (i + 3)-th clock signal terminal, and the (i + 4)-th clock signal terminal; The signal generating unit is configured to output the scanning signal at the first potential according to the clock signal output from the i-th clock signal terminal. Among four consecutive periods, the signal adjusting unit pulls down the scanning signal to the second potential in the first period according to the clock signal output from the (i + 1)-th clock signal terminal, pulls up the scanning signal to the first potential in the second period according to the clock signal output from the (i + 2)-th clock signal terminal, pulls down the scanning signal to the second potential in the third period according to the clock signal output from the (i + 3)-th clock signal terminal, and pulls up the scanning signal to the first potential in the fourth period according to the clock signal output from the (i + 4)-th clock signal terminal.

2. The scanning drive circuit according to claim 1, wherein The signal adjusting unit includes a control module and a control node. The control module is electrically connected to the control node and the scanning signal output node. During the process of the signal generating unit outputting the scanning signal at the first potential, when the control node is at the first potential, the control module controls the scanning signal output node to output a scanning signal at the second potential, and when the control node is at the second potential, the control module controls the scanning signal output node to output a scanning signal at the first potential, and the first potential is greater than the second potential.

3. The scanning drive circuit according to claim 2, wherein The signal adjusting unit further includes a first adjusting module, a second adjusting module, a third adjusting module, and a fourth adjusting module. The first adjusting module is electrically connected to the control node, the (i + 1)-th clock signal terminal, and a first voltage terminal, and is configured to control the first voltage terminal to pull up the control node to the first potential in the second period according to the clock signal output from the (i + 1)-th clock signal terminal, so as to control the control module to control the scanning signal output node to output the scanning signal at the second potential in the second period; The second adjusting module is electrically connected to the control node, the (i + 2)-th clock signal terminal, and a second voltage terminal, and is configured to control the second voltage terminal to pull down the control node to the second potential in the third period according to the clock signal output from the (i + 2)-th clock signal terminal, so as to control the control module to control the scanning signal output node to output the scanning signal at the first potential in the third period; The third adjustment module is electrically connected to the control node, the (i + 3)-th clock signal terminal, and the first voltage terminal, and is configured to control the first voltage terminal to pull up the control node to a first potential during the fourth time period according to the clock signal output from the (i + 3)-th clock signal terminal, so as to control the control module to control the scan signal output node to output a scan signal with the second potential during the fourth time period; The fourth adjustment module is electrically connected to the control node, the (i + 4)-th clock signal terminal, and the second voltage terminal, and is configured to control the second voltage terminal to pull down the control node to a second potential during the fifth time period according to the clock signal output from the (i + 4)-th clock signal terminal, so as to control the control module to control the scan signal output node to output a scan signal with the first potential during the fifth time period.

4. The scanning driving circuit according to claim 1, characterized in that The signal generation unit includes a pull-up module, an output module, and a first node. The pull-up module is electrically connected to an input terminal, a power supply voltage terminal, and the first node, and is configured to receive a power supply voltage from the power supply voltage terminal to pull up the first node to a first potential under the control of the input terminal. The output module is electrically connected to the i-th clock signal terminal, the first node, and the scan signal output node. When the first node is at the first potential, the output module outputs a scan signal with the first potential from the scan signal output node according to the clock signal output from the i-th clock signal terminal.

5. The scanning driving circuit according to claim 4, characterized in that, The signal generation unit further includes a maintenance module, a pull-down control module, a pull-down module, and a second node. The maintenance module is electrically connected to the first voltage terminal, the pull-down module, and the second node, and is configured to receive a first level signal from the first voltage terminal and transmit it to the pull-down control module and the second node, for controlling the second node to maintain at the first potential; The pull-down control module is electrically connected to the first node, the second node, and the second voltage terminal. When the first node is at the first potential, the pull-down control module controls the second voltage terminal to output a second level signal to the second node to pull down the second node to a second potential. When the first node is at the second potential, the pull-down control module controls the second voltage terminal to stop outputting the second level signal to the second node, so as to control the second node to be pulled up to the first potential under the control of the maintenance module; The pull-down module is electrically connected to the second node, the scan signal output node, and the second voltage terminal. When the second node is at the first potential, the pull-down module controls the scan signal output node to output a scan signal with the second potential. When the second node is at the second potential, the pull-down module controls the scan signal output node to output a scan signal with the first potential.

6. The scanning driving circuit according to claim 5, wherein The signal generation unit further includes a first reset module and a second reset module. The first reset module is electrically connected to a first reset control terminal, a low voltage terminal, and the first node, and is configured to connect the first node to the low voltage terminal under the control of the first reset control terminal, for resetting the first node to a preset potential; The second reset module is electrically connected to the scan signal output node, the output module, the second reset control end, and the third reset control end, and is configured to reset the scan signal output node and the output module to a preset potential under the control of the second reset control end and the third reset control end.

7. The scanning driving circuit according to claim 3, wherein The first adjustment module includes a first control transistor, the second adjustment module includes a second control transistor, the third adjustment module includes a third control transistor, and the fourth adjustment module includes a fourth control transistor; The control end of the first control transistor is electrically connected to the (i + 1)-th clock signal terminal, the first conduction end of the first control transistor is electrically connected to the first voltage terminal, and the second conduction end of the first control transistor is electrically connected to the control node, and is configured to be turned on under the control of the clock signal output by the (i + 1)-th clock signal terminal, so as to control the first voltage terminal to output a first level signal to the control node, and pull up the control node to a first potential; The control end of the second control transistor is electrically connected to the (i + 2)-th clock signal terminal, the first conduction end of the second control transistor is electrically connected to the control node, and the second conduction end of the second control transistor is electrically connected to the second voltage terminal, and is configured to be turned on under the control of the clock signal output by the (i + 2)-th clock signal terminal, so as to control the second voltage terminal to output a second level signal to the control node, and pull down the control node to a second potential; The control end of the third control transistor is electrically connected to the (i + 3)-th clock signal terminal, the first conduction end of the third control transistor is electrically connected to the first voltage terminal, and the second conduction end of the third control transistor is electrically connected to the control node, and is configured to be turned on under the control of the clock signal output by the (i + 3)-th clock signal terminal, so as to control the first voltage terminal to output a first level signal to the control node, and pull up the control node to a first potential; The control end of the fourth control transistor is electrically connected to the (i + 4)-th clock signal terminal, the first conduction end of the fourth control transistor is electrically connected to the control node, and the second conduction end of the fourth control transistor is electrically connected to the second voltage terminal, and is configured to be turned on under the control of the clock signal output by the (i + 4)-th clock signal terminal, so as to control the second voltage terminal to output a second level signal to the control node, and pull down the control node to a second potential.

8. The scanning drive circuit according to claim 7, wherein, The control module includes a fifth control transistor, the control end of the fifth control transistor is electrically connected to the control node, the first conduction end of the fifth control transistor is electrically connected to the scan signal output node, and the second conduction end of the fifth control transistor is electrically connected to the second voltage terminal; In the second time period, the control node controls the fifth control transistor to be turned on, and the second voltage terminal outputs a second level signal to the scan signal output node, so as to control the scan signal output node to output a scan signal of a second potential; In the third time period, the control node controls the fifth control transistor to be turned off, and the second voltage terminal stops outputting the second level signal to the scan signal output node, so as to control the scan signal output node to output a scan signal of a first potential; In the fourth period, the control node controls the fifth control transistor to conduct, and the second voltage terminal outputs the second level signal to the scan signal output node to control the scan signal output node to output a scan signal of the second level signal.

9. A touch display panel, characterized in that, It includes pixel units arranged in an array, a data driving circuit, and the scan driving circuit according to any one of claims 1-8. The scan driving circuit is configured to output the scan signal to the pixel units through scan lines, and is used to control the pixel units to receive data signals from the data driving circuit through data lines. The pixel unit includes a pixel electrode and a common electrode. The pixel electrode and the common electrode perform image display according to the data signal during a display period within a frame image display period. The common electrode is further configured to detect a touch operation during a touch period within a frame image display period. The display period and the touch period are continuous in time.

Images