Array substrate, display substrate and display device

Abstract

The utility model provides an array substrate. The array substrate comprises a substrate body; the scanning lines extend in the first direction and are arranged in the second direction; a plurality of signal lines; a gate driving circuit; the plurality of binding bonding pads comprise a plurality of first bonding pads and a plurality of second bonding pads; the plurality of first bonding pads comprise a plurality of first sub-bonding pads and a plurality of second sub-bonding pads; in the row of first bonding pads, the multiple first sub bonding pads are arranged at intervals in the first direction, and the distance between at least one second sub bonding pad and the display area in the second direction is not equal to the distance between the first sub bonding pad and the display area; the second bonding pad comprises a plurality of third sub-bonding pads, one end of the gate signal lead is electrically connected with the third sub-bonding pads, the other end of the gate signal lead extends to be electrically connected with the gate driving circuit, and a part of the gate signal lead is located on the sides, away from the display area, of the second sub-bonding pads.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display substrate and a display device. BACKGROUND

[0002] With the continuous development of display technology, consumers have increasingly stringent requirements for the screen-to-body ratio of display screens. On the basis that the full-screen design has gradually been popularized in small-size display devices such as mobile phones, the demand for full-screen design in medium and large-size display devices such as notebooks and tablet computers is increasing. Generally, only structures such as circuits and traces are arranged in the left, right and upper side frames of the display screen, which can achieve a relatively narrow frame, but the lower side frame of the display screen needs to bind electronic components such as driving chips or flexible circuit boards, and it is difficult to achieve a narrow frame. How to achieve a narrow frame display without adding other display problems is one of the concerns of display product researchers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and therefore, the above information can include information that does not constitute the prior art. UTILITY MODEL CONTENT

[0004] In one aspect, an array substrate is provided, comprising a display area and a peripheral area located at a periphery of the display area, the display area having a central axis extending along a second direction, the array substrate comprising:

[0005] a substrate substrate;

[0006] a plurality of scan lines located on the substrate substrate, at least a portion of the scan lines being located in the display area, the plurality of scan lines extending along a first direction and arranged along the second direction, the first direction intersecting the second direction;

[0007] a plurality of signal lines located on the substrate substrate, at least a portion of the signal lines being located in the display area, at least a portion of the signal lines extending along the second direction and arranged along the first direction;

[0008] a gate drive circuit located on the substrate substrate, the gate drive circuit being located in the peripheral area and located on at least one side of the display area along the first direction, the gate drive circuit being electrically connected to the plurality of scan lines; and

[0009] a plurality of binding pads located on the substrate substrate, the plurality of binding pads being located in the peripheral area and located on one side of the display area along the second direction,

[0010] The plurality of binding pads include a plurality of first pads and a plurality of second pads, the plurality of second pads are located on a side of the plurality of first pads away from the display area, and the plurality of first pads and the plurality of second pads are configured to be electrically connected with a driving chip.

[0011] The plurality of first pads include a plurality of first sub-pads and a plurality of second sub-pads, and along the first direction, the plurality of second sub-pads are located on a side of the plurality of first sub-pads away from the central axis.

[0012] The plurality of first pads are arranged in at least one row, in a row of the first pads, the plurality of first sub-pads are arranged at intervals along the first direction, and at least one second sub-pad is not equal to the first sub-pad in the second direction from the display area.

[0013] The second pad includes a plurality of third sub-pads, and the array substrate further includes a plurality of gate signal leads, one end of the gate signal lead is electrically connected with the third sub-pad, and the other end extends to be electrically connected with the gate drive circuit.

[0014] According to some exemplary embodiments, the array substrate further includes a plurality of fan-out wires, and the plurality of first pads are respectively electrically connected with the plurality of signal lines through the plurality of fan-out wires, and in the second direction, at least one part of the fan-out wire is farther away from the display area than at least one first pad.

[0015] According to some exemplary embodiments, along the second direction, the plurality of third sub-pads are located on a side of the plurality of second sub-pads away from the display area, one end of the gate signal lead is electrically connected with one end of the third sub-pad away from the display area, and the other end extends to be electrically connected with the gate drive circuit, and along the second direction, at least one part of the gate signal lead is located on a side of the plurality of second sub-pads away from the display area.

[0016] According to some exemplary embodiments, the plurality of binding pads further include a plurality of third pads, and the plurality of third pads are located on a side of the plurality of second pads away from the plurality of first pads.

[0017] The plurality of second pads further include a plurality of fourth sub-pads, and along the first direction, the plurality of fourth sub-pads are located on a side of the plurality of third sub-pads away from the central axis, and the plurality of fourth sub-pads are respectively electrically connected with the plurality of third pads through a plurality of binding connection lines; and

[0018] At least one part of the gate signal lead is located between the plurality of second sub-pads and the plurality of third pads.

[0019] According to some exemplary embodiments, the line connecting the geometric centers of the orthographic projections of the plurality of second sub-pads near the plurality of first sub-pads on the substrate forms an acute angle with the first direction.

[0020] According to some exemplary embodiments, in a row of first pads, along the first direction away from a plurality of first sub-pads, a plurality of second sub-pads are arranged in the second direction in a trend of gradually moving away from the display area.

[0021] According to some exemplary embodiments, in a row of first pads, along the first direction away from a plurality of first sub-pads, a plurality of second sub-pads are arranged in the second direction with a tendency to gradually approach the display area.

[0022] According to some exemplary embodiments, the plurality of second sub-pads include a first sub-pad group and a second sub-pad group, wherein along the first direction, the second sub-pad group is located on the side of the first sub-pad group away from the plurality of first sub-pads;

[0023] In a row of first pads, along the first direction away from the plurality of first sub-pads, a plurality of second sub-pads belonging to the first sub-pad group are arranged in the second direction with a tendency to gradually move away from the display area; and

[0024] In a row of the first pad, multiple second sub-pads belonging to the second sub-pad group are arranged at intervals along the first direction.

[0025] According to some exemplary embodiments, the plurality of second sub-pads include a first sub-pad group and a second sub-pad group, wherein along the first direction, the second sub-pad group is located on the side of the first sub-pad group away from the plurality of first sub-pads;

[0026] In a row of first pads, along the first direction away from the plurality of first sub-pads, a plurality of second sub-pads belonging to the first sub-pad group are arranged in the second direction with a tendency to gradually move away from the display area; and

[0027] In a row of first pads, along the first direction away from the plurality of first sub-pads, the plurality of second sub-pads belonging to the first sub-pad group are arranged in the second direction with a trend of gradually approaching the display area.

[0028] According to some exemplary embodiments, one end of the fan-out trace is electrically connected to the side of the first pad near the display area, and the other end extends to be electrically connected to the signal line; and

[0029] A portion of the fan-out trace electrically connected to the second sub-pad is further away from the display area than the first sub-pad that is closest to the display area.

[0030] According to some exemplary embodiments, a plurality of first sub-pads are strips extending along the second direction, and a plurality of second sub-pads in the first sub-pad group are strips extending along the second direction.

[0031] In the second sub-pad group, the plurality of second sub-pads on the side away from the plurality of first sub-pads along the first direction are inclined pads, the inclined pads being strip-shaped extending along the third direction, the angle between the third direction and the first direction being an acute angle; and

[0032] Along the first direction, a portion of the fan-out trace electrically connected to the tilted pad is located on the side of the plurality of first pads away from the central axis.

[0033] According to some exemplary embodiments, in at least two adjacent tilted pads along the second direction, a portion of the fan-out trace electrically connected to one of the tilted pads is located between the two tilted pads and extends to the side of the plurality of first pads away from the central axis.

[0034] According to some exemplary embodiments, the trace width of the fan-out trace electrically connected to the tilted pad is greater than the trace width of the fan-out trace electrically connected to the first sub-pad.

[0035] According to some exemplary embodiments, the plurality of fan-out traces include a plurality of first fan-out traces and a plurality of second fan-out traces, the plurality of first sub-pads are electrically connected to the plurality of signal lines through the plurality of first fan-out traces, and the plurality of second sub-pads are electrically connected to the plurality of signal lines through the plurality of second fan-out traces.

[0036] One end of the first fan-out trace is electrically connected to the end of the first sub-pad near the display area, and the other end extends to be electrically connected to the signal line; one end of the second fan-out trace is electrically connected to the end of the second sub-pad away from the display area, and the other end extends to be electrically connected to the signal line; and

[0037] A portion of the second fan-out trace is located on the side of the plurality of second sub-pads away from the display area and on the side of the plurality of first sub-pads along the first direction.

[0038] According to some exemplary embodiments, a portion of the gate signal lead is located on the side of the second fan-out trace away from the second sub-pad.

[0039] According to some exemplary embodiments, the gate signal lead is located on a portion of the plurality of second sub-pads on the side away from the display area and is a straight trace extending along the first direction.

[0040] According to some exemplary embodiments, the plurality of fan-out routing lines include a plurality of third fan-out routing lines and a plurality of fourth fan-out routing lines;

[0041] In at least a portion of the second sub-pad, the end of the second sub-pad away from the display area is electrically connected to the signal line via the fourth fan-out trace;

[0042] In the remaining first pads, the end of the first pad closest to the display area is electrically connected to the signal line via the third fan-out trace; and

[0043] A portion of the multiple fourth fan-out traces is located on the side of multiple second sub-pads away from the display area.

[0044] According to some exemplary embodiments, the plurality of fan-out routing lines include a plurality of third fan-out routing lines and a plurality of fourth fan-out routing lines;

[0045] The ends of the multiple first sub-pads near the display area are respectively electrically connected to the multiple signal lines through the multiple third fan-out traces;

[0046] In the first sub-pad group, the end of the second sub-pad near the display area is electrically connected to the signal line via the third fan-out trace; and

[0047] In the second sub-pad group, the end of the second sub-pad away from the display area is electrically connected to the signal line through the fourth fan-out trace.

[0048] According to some exemplary embodiments, the plurality of fan-out routing lines include a plurality of third fan-out routing lines and a plurality of fourth fan-out routing lines;

[0049] The ends of the multiple first sub-pads near the display area are respectively electrically connected to the multiple signal lines through the multiple third fan-out traces;

[0050] In the first sub-pad group, the end of the second sub-pad near the display area is electrically connected to the signal line via the third fan-out trace; and

[0051] In the second sub-pad group, the end of the second sub-pad away from the display area is electrically connected to the signal line through the fourth fan-out trace.

[0052] According to some exemplary embodiments, the third fan-out trace includes a first trace segment and a second trace segment. One end of the first trace segment is electrically connected to the end of the first pad near the display area and extends along a second direction toward the side near the display area. One end of the second trace segment is electrically connected to the end of the first trace segment near the display area, and the other end extends along a fourth direction toward the side away from the central axis and near the display area. The acute angle between the fourth direction and the first direction is a first angle.

[0053] In the second sub-pad group, the acute angle between the line connecting the geometric center of the orthographic projection of one second sub-pad on the substrate and the geometric center of the orthographic projection of the other second sub-pad on the substrate and the first direction is the second angle, and the second angle is less than or equal to the first angle.

[0054] According to some exemplary embodiments, the second included angle is greater than 0 degrees and less than or equal to 45 degrees.

[0055] According to some exemplary embodiments, the acute angle between the line connecting the geometric center of the orthographic projection of one second sub-pad on the substrate and the geometric center of the orthographic projection of another second sub-pad on the substrate and the first direction is a third angle, wherein the third angle is greater than 0 degrees and less than or equal to 45 degrees.

[0056] According to some exemplary embodiments, a portion of the gate signal lead is located on the side of the fourth fan-out trace away from the second sub-pad.

[0057] According to some exemplary embodiments, along the first direction, a portion of the gate signal lead is located on the side of the fourth fan-out trace closer to the peripheral region.

[0058] According to some exemplary embodiments, along the first direction, a portion of the gate signal lead is located on the side of the plurality of third pads away from the central axis.

[0059] According to some exemplary embodiments, the third pad located on one side of the first direction that is furthest from the central axis is closer to the central axis than the first pad located on the same side of the first direction that is furthest from the central axis; and

[0060] The gate signal lead extends from the side of the plurality of third pads near the display area around the edge of the plurality of third pads to the side of the plurality of third pads away from the central axis.

[0061] According to some exemplary embodiments, the gate signal lead includes a first gate signal lead segment, a second gate signal lead segment, a third gate signal lead segment, and a fourth gate signal lead segment;

[0062] One end of the first gate signal lead segment is electrically connected to the third sub-pad, and the other end extends in a direction away from the central axis and close to the plurality of third pads;

[0063] One end of the second gate signal lead segment is electrically connected to the end of the first gate signal lead segment away from the third sub-pad, and the other end extends along the first direction toward the side away from the central axis;

[0064] One end of the third gate signal lead segment is electrically connected to the end of the second gate signal lead segment away from the first gate signal lead segment, and the other end extends in a direction away from the plurality of first pads and away from the central axis; and

[0065] One end of the fourth gate signal lead segment is electrically connected to the end of the third gate signal lead segment away from the second gate signal lead segment, and the other end extends along the first direction toward the side away from the central axis. The fourth gate signal lead segment is located on one side of the plurality of third pads along the first direction.

[0066] According to some exemplary embodiments, the fourth fan-out trace includes a first portion located away from the display area from a plurality of second sub-pads; and

[0067] Along the first direction, the first portion is located on the side of the third gate signal lead segment away from the central axis, and / or, the first portion is located on the side of the fourth gate signal lead segment closer to the display area.

[0068] According to some exemplary embodiments, the fourth outgoing cable includes a third cable segment, a fourth cable segment, and a fifth cable segment;

[0069] One end of the third trace segment is electrically connected to the end of the second sub-pad away from the display area and extends along the second direction toward the side away from the display area;

[0070] One end of the fourth trace segment is electrically connected to the end of the third trace segment away from the second sub-pad, and the other end extends in a direction away from the second sub-pad and away from the central axis. The fourth trace segment is located on one side of the third gate signal lead segment along the first direction; and

[0071] One end of the fifth trace is electrically connected to the end of the fourth trace away from the third trace, and the other end extends along the first direction toward the side away from the central axis. The fifth trace is located on the side of the fourth gate signal lead segment closer to the display area.

[0072] According to some exemplary embodiments, the array substrate further includes a common electrode and a common voltage lead, the common electrode being located in the display area, at least a portion of the common voltage lead being located in the peripheral area, and the common voltage lead being electrically connected to the common electrode;

[0073] The fan-out routing includes a first fan-out section and a second fan-out section, the first fan-out section and the second fan-out section being arranged at intervals along the first direction; and

[0074] The common voltage lead includes a first common voltage lead, a second common voltage lead, and a third common voltage lead arranged sequentially along the first direction. At least a portion of the first common voltage lead is located on the side of the first fan-out portion away from the second fan-out portion. At least a portion of the third common voltage lead is located on the side of the second fan-out portion away from the first fan-out portion. At least a portion of the second common voltage lead is located between the first fan-out portion and the second fan-out portion.

[0075] According to some exemplary embodiments, the plurality of bonding pads further include a plurality of third pads, the plurality of third pads being located on the side of the plurality of second pads away from the plurality of first pads;

[0076] The plurality of second pads further include a plurality of fourth sub-pads, which are located on the side of the plurality of third sub-pads near the central axis along the first direction. The plurality of fourth sub-pads are electrically connected to the plurality of third pads via a plurality of bonding connection lines. The second common voltage lead includes a fourth portion located between the first fan-out portion and the second fan-out portion. One end of the fourth portion is electrically connected to the common electrode, and the other end extends along the second direction to the side of the plurality of first pads away from the display area. The size of the fourth portion along the first direction is greater than or equal to the size of the first pads along the first direction.

[0077] According to some exemplary embodiments, the plurality of first pads include a plurality of first virtual pads, the plurality of first virtual pads being located between the fourth portion and the first fan-out portion, and the plurality of first virtual pads being located between the fourth portion and the second fan-out portion.

[0078] According to some exemplary embodiments, one end of the first common voltage lead is electrically connected to at least one of the third pads, and the other end extends between a plurality of first pads and a plurality of second pads and extends around the first fan-out portion to be electrically connected to the common electrode; and / or, one end of the third common voltage lead is electrically connected to at least one of the third pads, and the other end extends between a plurality of first pads and a plurality of second pads and extends around the second fan-out portion to be electrically connected to the common electrode.

[0079] According to some exemplary embodiments, the first common voltage lead includes a second portion located between adjacent second pads along the first direction, the dimension of the second portion along the first direction being greater than or equal to the dimension of the second pads along the first direction; and / or,

[0080] The third common voltage lead includes a third portion located between adjacent second pads along the first direction, the third portion having a dimension along the first direction greater than or equal to the dimension of the second pads along the first direction.

[0081] According to some exemplary embodiments, one end of the second common voltage lead away from the display area is electrically connected to at least one of the third pads.

[0082] According to some exemplary embodiments, a shielded trace segment is provided on at least one side of the second common voltage lead along the first direction, and the shielded trace segment is spaced apart from the second common voltage lead; and

[0083] One end of the shielded trace is located between the second common voltage lead and the third pad, and the other end of the shielded trace is located between the second common voltage lead and the second pad.

[0084] According to some exemplary embodiments, the second common voltage lead includes a fifth portion located between adjacent second pads along the first direction, the fifth portion having a dimension along the first direction greater than or equal to the dimension of the second pads along the first direction; and / or,

[0085] The shielded trace segment includes a sixth portion located between adjacent second pads along the first direction, the size of the sixth portion along the first direction being greater than or equal to the size of the second pads along the first direction.

[0086] According to some exemplary embodiments, the second common voltage lead includes a seventh portion located between a plurality of first pads and a plurality of second pads, the seventh portion extending along the first direction, one end of the seventh portion being electrically connected to the fourth portion, and the other end of the seventh portion being electrically connected to the fifth portion.

[0087] According to some exemplary embodiments, along the second direction, the distance between the seventh portion and the row of second pads closest to the display area is equal to the distance between the seventh portion and the row of first pads furthest from the display area.

[0088] According to some exemplary embodiments, the second common voltage lead further includes an eighth portion located between a plurality of first pads and a plurality of second pads, the eighth portion extending along the first direction, one end of the eighth portion being electrically connected to the first common voltage lead, and / or, one end of the eighth portion being electrically connected to the third common voltage lead; and

[0089] The fourth part extends away from the display area and is electrically connected to the eighth part.

[0090] In another aspect, a display substrate is provided, comprising an array substrate as described in any of the preceding claims.

[0091] In another aspect, a display device is provided, comprising a display substrate as described above. Attached Figure Description

[0092] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0093] Figure 1 A schematic plan view of an array substrate in the related art is shown.

[0094] Figure 2 The illustration shows Figure 1 A magnified view of region A in the middle.

[0095] Figure 3 The diagram illustrates the arrangement of pads on an array substrate in the related art.

[0096] Figure 4 A schematic plan view of an array substrate according to some embodiments of the present disclosure is shown.

[0097] Figure 5 The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure.

[0098] Figure 6A Schematic illustration Figure 4 A magnified view of region B in the middle.

[0099] Figure 6B Schematic illustration Figure 6A A magnified view of region N in the middle.

[0100] Figure 7 The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure.

[0101] Figure 8 The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure.

[0102] Figure 9 The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure.

[0103] Figure 10 Schematic illustration Figure 4 Another magnified view of region C in the middle.

[0104] Figure 11 The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure.

[0105] Figure 12 Schematic illustration Figure 4 Another magnified view of region B in the middle.

[0106] Figure 13 Schematic illustration Figure 4 An enlarged view of region D in the middle.

[0107] Figure 14 Schematic illustration Figure 13 An enlarged view of region E in the middle.

[0108] Figure 15 Schematic illustration Figure 4 Another magnified view of region D in the middle.

[0109] Figure 16 Schematic illustration Figure 14 An enlarged view of region F in the middle.

[0110] Figure 17 Schematic illustration Figure 4 Another magnified view of region D in the middle.

[0111] Figure 18 Schematic illustration Figure 14 A magnified view of region G in the middle.

[0112] Figure 19 A schematic plan view of an array substrate according to some embodiments of the present disclosure is shown.

[0113] Figure 20 Schematic illustration Figure 19 A magnified view of region H in the middle.

[0114] Figure 21 Schematic illustration Figure 20 A magnified view of region I in the middle.

[0115] Figure 22 Schematic illustration Figure 20 A magnified view of region J in the middle.

[0116] Figure 23 Schematic illustrationFigure 20 A magnified view of region K in the middle.

[0117] Figure 4 A schematic plan view of an array substrate according to some embodiments of the present disclosure is shown.

[0118] Figure 19 Schematic illustration Figure 20 A magnified view of the central region L.

[0119] Figure 19 Schematic illustration Figure 20 A magnified view of region M in the middle.

[0120] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0121] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0122] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0123] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements present. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Additionally, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0124] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be named a second element, and similarly, a second element may be named a first element.

[0125] Figure 21 A schematic plan view of an array substrate in the related art is shown. Figure 21 The illustration shows Figure 21 A magnified view of region A in the middle. Figure 21 The diagram illustrates the arrangement of pads on an array substrate in the related art.

[0126] Combined with reference Figure 19 , Figure 20 and Figure 21 , Figure 21 An enlarged view of a portion of the array substrate located at the bottom edge is shown. At the bottom edge, there are multiple first pads P1', multiple second pads P2' located below the multiple first pads P1', and multiple third pads P3' located below the multiple second pads P2'. The multiple first pads P1' and multiple second pads P2' are configured to be electrically connected to the driver chip, and the multiple third pads P3' are configured to be electrically connected to the flexible circuit board.

[0127] Figure 21 The diagram illustrates the arrangement of multiple first pads P1' and multiple second pads P2', with the multiple first pads P1' arranged in at least two rows along the horizontal direction and the multiple second pads P2' arranged in one row along the horizontal direction.

[0128] Multiple first pads P1' transmit data signals to the display area AA' via multiple fan-out traces FL'. To fully utilize the wiring space in the lower bezel area, the fan-out traces FL' connected to the multiple first pads P1' in the middle are led out from the upper end of the first pads P1', and the fan-out traces FL' connected to the multiple first pads P1' on both sides are led out from the lower end of the first pads P1'. Due to limited space, some of the fan-out traces FL' leading out from the lower end will pass through the gap of the second pads P2' and extend between the second pads P2' and the third pads P3' before extending to the left or right (i.e., ...). Figure 21 The fan-out traces within the box marked ①.

[0129] A portion of the second pad P2' transmits the gate drive signal to the gate drive circuits located on the left and right bezels via the gate signal lead L3'. Due to the obstruction of the downward-leading fan-out trace FL', the gate drive lead from the second pad P2' has no space to extend left or right to electrically connect with the gate drive circuit. Instead, it needs to connect to a portion of the third pad P3' and be transferred via the internal wiring of the flexible circuit board to a portion of the third pad P3' closer to the left or right bezel (i.e., Figure 21 The third pad (marked as ②) is then led out and electrically connected to the gate drive circuit.

[0130] The above design can narrow the bottom bezel to some extent, but it requires more third pads P3', which increases the width and area of ​​the flexible circuit board, thus increasing the difficulty and cost of manufacturing the flexible circuit board.

[0131] Figure 16 A schematic plan view of an array substrate according to some embodiments of the present disclosure is shown. Figure 19 The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure. Figure 20 Schematic illustration Figure 21 A magnified view of region B in the middle. Figure 19 Schematic illustration Figure 20 A magnified view of region N in the middle.

[0132] Reference Figure 22The array substrate includes a display area AA and a peripheral area NA located around the display area AA. The display area AA has a central axis Y1 extending along a second direction Y. The peripheral area NA may include a first peripheral area NA1 and a second peripheral area NA2 located on both sides of the display area AA along a first direction X, and a third peripheral area NA3 and a fourth peripheral area NA4 located on both sides of the display area AA along the second direction Y.

[0133] It should be noted that the display area AA is symmetrically distributed relative to the central axis Y1. The central axis Y1 is not an actual structure in the display substrate, but a virtual straight line. The central axis Y1 is defined only to more clearly describe the distribution of the relevant structures in the display substrate.

[0134] The array substrate includes a substrate 100 and multiple scan lines L1, multiple signal lines L2, a gate drive circuit GOA, multiple bonding pads Pad, and multiple fan-out traces FL disposed on the substrate 100. At least one of a first peripheral region NA1 and a second peripheral region NA2 is provided with a gate drive circuit GOA; for example, gate drive circuits GOA are respectively disposed in the first peripheral region NA1 and the second peripheral region NA2. The multiple scan lines L1 extend along a first direction X and are arranged along a second direction Y. At least a portion of the scan lines L1 is located in the display region AA and extends to the peripheral region NA and is electrically connected to the gate drive circuit GOA.

[0135] At least a portion of signal line L2 is located in display area AA, and at least a portion of signal line L2 extends along the second direction Y and is arranged along the first direction X. Multiple bonding pads are located in the fourth peripheral area NA4. These bonding pads include multiple first pads P1 and multiple second pads P2. The multiple second pads P2 are located on the side of the multiple first pads P1 away from display area AA. The multiple first pads P1 and multiple second pads P2 are configured to be electrically connected to the driver chip. A portion of the multiple first pads P1 and multiple second pads P2 are used to input signals to the driver chip, and another portion is used to output signals provided by the driver chip to the corresponding traces. Multiple fan-out traces FL are located in the fourth peripheral area NA4. The multiple first pads P1 are electrically connected to the multiple signal lines L2 respectively through the multiple fan-out traces FL, thereby allowing the corresponding signals to be connected to the corresponding signal lines L2.

[0136] When it needs to be explained, Figure 23 The diagram only schematically shows the overall edge outlines of multiple fan-out traces FL, multiple first pads P1, and multiple second pads P2. The specific structures of the fan-out traces FL, first pads P1, and second pads P2 can be found in [reference needed]. Figure 20 , Figure 22 and Figure 22 wait.

[0137] In order to make fuller use of the space in the fourth peripheral area NA4 to arrange multiple fan-out traces FL, a specific design was made for the arrangement of multiple first pads P1.

[0138] Combined with reference Figure 19 and Figure 20 The plurality of first pads P1 include a plurality of first sub-pads P11 and a plurality of second sub-pads P12. The plurality of second sub-pads P12 are located on one side of the plurality of first sub-pads P11 along a first direction X, and in the first direction X, the plurality of second sub-pads P12 are further away from the central axis Y1 than the plurality of first sub-pads P11. The plurality of first pads P1 are arranged in at least one row. Figure 22 The diagram illustrates a two-row arrangement, but multiple first pads P1 can be arranged in three, four, or more rows depending on requirements.

[0139] In a row of first pads P1, multiple first sub-pads P11 are arranged at intervals along a first direction X. The distances between the multiple first sub-pads P11 and the display area AA in the second direction Y are approximately equal. At least one second sub-pad P12 is not equidistant from the first sub-pad P11 in the second direction Y from the display area AA. That is, along the second direction Y, at least one second sub-pad P12 is closer to the display area AA than the first sub-pad P11, or along the second direction Y, at least one second sub-pad P12 is farther away from the display area AA than the first sub-pad P11.

[0140] By offsetting the second sub-pad P12 from the first sub-pad P11 along the second direction Y, the space offset along the second direction Y can be used to set up fan-out traces FL. This allows at least a portion of one fan-out trace FL to be further away from the display area AA than at least one first pad P1 in the second direction Y. This arrangement allows for more efficient use of the space within the fourth peripheral area NA4 to arrange multiple fan-out traces FL, which helps to narrow the bezel width on one side of the fourth peripheral area NA4.

[0141] Figure 20 The diagram schematically illustrates one arrangement of the first pad P1; other arrangements of the first pad P1 are described later. Figure 20 Among the multiple first pads P1 shown in the diagram, along the direction away from the multiple first sub-pads P11, the multiple second sub-pads P12 are arranged in the second direction Y with a trend of gradually moving away from the display area AA. That is, the multiple second sub-pads P12 located on one side of the multiple first sub-pads P11 are arranged in a downward manner.

[0142] Combined with reference Figure 23 , Figure 23 ,Figure 20 and Figure 23 After arranging multiple second sub-pads P12 in a recessed manner, the fan-out traces FL, which connect to both the second sub-pads P12 and the first sub-pads P11, are led out from the end of the pads closest to the display area AA and extended to electrically connect with the signal line L2. A portion of the fan-out traces FL electrically connected to the second sub-pads P12 are further away from the display area AA than the row of first sub-pads P11 closest to the display area AA. In other words, the space near the display area AA of the multiple second sub-pads P12 arranged in a recessed manner, which was originally used to arrange the first pads P1, can be used to arrange the fan-out traces FL after the recessed design. This improves the utilization rate of the wiring space in the fourth peripheral area NA4 and helps to narrow the bezel width on one side of the fourth peripheral area NA4.

[0143] Furthermore, the plurality of second pads P2 include a plurality of third sub-pads P21, and the array substrate also includes a plurality of gate signal leads L3. One end of the gate signal lead L3 is electrically connected to the third sub-pad P21 and the other end extends to be electrically connected to the gate drive circuit GOA. A portion of the gate signal lead L3 is located on the side of the plurality of second sub-pads P12 away from the display area AA. The driver chip can connect the gate drive signal to the gate drive circuit GOA through the third sub-pad P21 and the gate signal lead L3.

[0144] After designing the multiple first pads P1 and fan-out traces FL as described above, without increasing the bezel width on one side of the fourth peripheral area NA4, sufficient space is provided on the side of the multiple second sub-pads P12 away from the display area AA for arranging the gate signal lead L3. The gate signal lead L3, after being led out from the third sub-pad P21, can extend continuously along the second direction Y until it is electrically connected to the gate drive circuit GOA. This eliminates the need to use the bonding pads of the flexible circuit board for transferring the gate drive signal, thereby reducing the cost of the flexible circuit board.

[0145] Furthermore, by reducing the number of bonding pads on the flexible circuit board, the distribution width of the multiple bonding pads on the flexible circuit board along the first direction X is narrowed, and the width of the flexible circuit board along the first direction X is correspondingly narrowed. This results in a narrower width of the printed circuit board electrically connected to the flexible circuit board, which helps to reduce the prohibited component area in the printed circuit board and can save component placement space in the printed circuit board.

[0146] For example, signal line L2 may include multiple data lines DL extending along the second direction Y and arranged along the first direction X. The multiple data lines DL are electrically connected to multiple first pads P1 through multiple fan-out traces FL, so that the first pads P1 can access data signals to the data lines through the fan-out traces FL.

[0147] For example, when it is necessary to integrate touch function, the signal line L2 may also include multiple touch signal lines. The multiple touch signal lines are electrically connected to multiple first pads P1 through multiple fan-out traces FL. The multiple touch signal lines transmit touch signals to the driver chip through multiple fan-out traces FL and multiple first pads P1.

[0148] It should be noted that, due to the relatively dense arrangement of multiple fan-out traces FL, multiple first pads P1, and multiple second pads P2, in order to clearly show the fan-out traces FL, first pads P1, and second pads P2, Figure 22 The diagram illustrates the overall outline of multiple fan-out routing lines FL, and schematically shows nine fan-out routing lines FL within this outline. Similarly, Figure 22 The diagram illustrates the overall outline of multiple first sub-pads P11, and schematically shows six first sub-pads P11 within this outline. Figure 22 The diagram illustrates the overall outline of multiple second sub-pads P12, and schematically shows three second sub-pads P12 within this outline. Figure 22 The diagram illustrates the overall outline of multiple second pads P2, and schematically shows a portion of the second pads P2 within that outline.

[0149] According to some exemplary embodiments, in conjunction with reference to Figure 24 and Figure 25 Multiple second sub-pads P12 are respectively arranged on both sides of multiple first sub-pads P11 along the first direction X. On the side of the multiple first sub-pads P11 near the first peripheral area NA1, the multiple second sub-pads P12 are arranged in the second direction Y, gradually moving away from the display area AA, along the direction away from the multiple first sub-pads P11. Furthermore, on the side of the multiple first sub-pads P11 near the second peripheral area NA2, the multiple second sub-pads P12 are arranged in the second direction Y, gradually moving away from the display area AA, along the direction away from the multiple first sub-pads P11. In other words, the multiple first pads P1 located at both ends of the first direction X can be recessed.

[0150] Figure 24 The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure.

[0151] According to some exemplary embodiments, in conjunction with reference to Figure 26 and Figure 24 Multiple second sub-pads P12 are respectively provided on one side of the multiple first sub-pads P11 along the first direction X. Figure 24This illustration shows that multiple second sub-pads P12 are provided only on the side of the multiple first sub-pads P11 closest to the first peripheral region NA1. Along a direction away from the multiple first sub-pads P11, the multiple second sub-pads P12 are arranged in a trend of gradually moving away from the display area AA in the second direction Y. Furthermore, no second sub-pads P12 are provided on the side of the multiple first sub-pads P11 closest to the second peripheral region NA2. In other words, the multiple first pads P1 located at one end of the first direction X can be designed to be recessed. Of course, multiple second sub-pads P12 can also be provided only on the side of the multiple first sub-pads P11 closest to the second peripheral region NA2, depending on the actual process requirements.

[0152] According to some exemplary embodiments, in conjunction with reference to Figure 25 and Figure 26 Multiple third sub-pads P21 are located on the side of multiple second sub-pads P12 away from the display area AA. One end of the gate signal lead L3 is electrically connected to the end of the third sub-pad P21 away from the display area AA, and the other end extends to be electrically connected to the gate drive circuit GOA. The multiple third sub-pads P21 are placed on the side of the multiple second sub-pads P12 away from the display area AA, and the gate signal lead L3 is led out from the end of the third sub-pad P21 away from the display area AA, so that the led-out gate signal lead L3 can extend into the gate drive circuit GOA within the space of the third sub-pad P21 away from the second sub-pad P12.

[0153] According to some exemplary embodiments, in conjunction with reference to ​ and ​ The multiple bonding pads also include multiple third pads P3, which are located on the side of the multiple second pads P2 away from the multiple first pads P1. The multiple third pads P3 can be arranged in a row along the first direction X, and the multiple third pads P3 are configured to be electrically connected to the flexible circuit board.

[0154] The multiple second pads P2 also include multiple fourth sub-pads P22. Along the first direction X, the multiple fourth sub-pads P22 are located on the side of the multiple third sub-pads P21 near the central axis Y1. The multiple fourth sub-pads P22 are electrically connected to the multiple third pads P3 through multiple bonding connection lines BL.

[0155] For example, multiple third sub-pads P21 are respectively provided on both sides of multiple fourth sub-pads P22 along the first direction X. Among the multiple third sub-pads P21 located near the first peripheral region NA1 of the fourth sub-pad P22, the third sub-pad P21 is electrically connected to the gate drive circuit GOA located in the first peripheral region NA1 through the gate signal lead L3. Among the multiple third sub-pads P21 located near the second peripheral region NA2 of the fourth sub-pad P22, the third sub-pad P21 is electrically connected to the gate drive circuit GOA located in the second peripheral region NA2 through the gate signal lead L3. ​ The diagram only schematically shows the plurality of third sub-pads P21 located near the first peripheral region NA1 of the plurality of fourth sub-pads P22 and the corresponding gate signal leads L3. The plurality of third sub-pads P21 located near the second peripheral region NA2 of the plurality of fourth sub-pads P22 and the corresponding gate signal leads L3 can be arranged in a mirror image along the first direction X with the third sub-pads P21 and the corresponding gate signal leads L3 on the other side.

[0156] Among the multiple second pads P2, the fourth sub-pad P22 is electrically connected to the third pad P3 and is used to receive signals provided by the flexible circuit board and input them into the driver chip. The third sub-pad P21 is used to output the gate drive signal provided by the driver chip to the gate drive circuit GOA.

[0157] In addition, it may also include a portion of the third pad P3 (i.e. ​ The third pad (P3) located on the left side is not electrically connected to the fourth sub-pad (P22). Instead, it is directly connected to the relevant structure on the array substrate via a trace and receives the corresponding signal. This signal can be directly input from the flexible circuit board. For example, the third pad (P3) can be electrically connected to the common electrode in the display area via a trace and receive a common voltage signal from the common electrode.

[0158] It should be noted that, due to the dense arrangement of multiple bonding traces BL and multiple third pads P3, in order to clearly show the bonding traces BL and third pads P3, ​ The diagram illustrates the overall outline of multiple binding connection lines BL, and schematically shows one binding connection line BL within that outline. Similarly, ​ The diagram illustrates the overall outline of multiple third pads P3, and schematically shows a portion of the multiple third pads P3 within that outline.

[0159] According to some exemplary embodiments, in conjunction with reference to ​ and ​A portion of the gate signal lead L3 is located between multiple second sub-pads P12 and multiple third pads P3. Due to the specific design of the multiple second sub-pads P12 and the fan-out traces FL, there is sufficient space between the multiple second sub-pads P12 and multiple third pads P3 to arrange multiple gate signal leads L3. A portion of the gate signal lead L3 located on the side of the multiple second sub-pads P12 away from the display area AA is a straight trace extending along the first direction X. In this way, the trace length of the gate signal lead L3 can be shortened.

[0160] ​ The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure.

[0161] According to some exemplary embodiments, in conjunction with reference to ​ and ​ Multiple second sub-pads P12 include a first sub-pad group PA and a second sub-pad group PB. Along the first direction X, the second sub-pad group PB is located on the side of the first sub-pad group PA away from the multiple first sub-pads P11. In a row of first pads P1, along the direction away from the multiple first sub-pads P11, multiple second sub-pads P12 belonging to the first sub-pad group PA are arranged in a trend of gradually moving away from the display area AA in the second direction Y. In a row of first pads P1, multiple second sub-pads P12 belonging to the second sub-pad group PB are arranged at intervals along the first direction X, and along the second direction Y, the distance between the multiple second sub-pads P12 and the display area AA is basically equal.

[0162] By arranging a portion of the second sub-pads P12 that are far from the central axis Y1 along the first direction X, that is, along the direction far from the multiple first sub-pads P11, the multiple second sub-pads P12 are first sunken and then arranged horizontally, the distribution width of the multiple first pads P1 and multiple second pads P2 along the second direction Y can be shortened, which is beneficial to further narrowing the border width located on the side of the fourth peripheral region NA4.

[0163] It should be noted that when multiple first pads P1 are arranged according to... ​ When arranging the data as shown in the diagram, the multiple fan-out traces FL that are electrically connected to multiple first pads P1 can be referenced. ​ and ​ The layout is illustrated, meaning that all fan-out traces FL are led out from the end of the first pad P1 closest to the display area AA, which will not be elaborated further here.

[0164] Furthermore, based on actual process requirements, multiple first pads P1 can be arranged along both sides of the first direction X according to... ​ The schematic arrangement can be used, or multiple first pads P1 can be arranged along one side of the first direction X.​ Arrange the items according to the illustrated layout.

[0165] ​ The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure. ​ Schematic illustration ​ Another magnified view of region C in the middle.

[0166] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ Multiple first sub-pads P11 extend in a strip along the second direction Y. Multiple second sub-pads P12, located away from the first sub-pads P11, are inclined pads PX. The inclined pads PX extend in a strip along the third direction D3, with the angle β between the third direction D3 and the first direction X being an acute angle. Along the first direction X, a portion of the fan-out traces FL electrically connected to the inclined pads PX are located on the side of the multiple first pads P1 away from the central axis Y1. By designing a portion of the second sub-pads P12 with an inclined shape, the fan-out traces FL leading from the inclined pads PX can be extended towards the side of the multiple first pads P1 away from the central axis Y1. That is, along the first direction X, the area between the peripheral area NA and the multiple first pads P1 is used to arrange the fan-out traces FL, thereby further improving the routing space utilization of the fourth peripheral area NA4, and further narrowing the border width on the side of the fourth peripheral area NA4.

[0167] It should be noted that the orthographic projection of the first pad P1 on the substrate 100 can be a rectangle, the long side of the first sub-pad P11 extends along the second direction Y, and the long side of the tilted pad PX extends along the third direction D3.

[0168] For example, in conjunction with reference ​ and ​ Multiple second sub-pads P12 belonging to the second sub-pad group PB can be set as tilted pads PX. Alternatively, multiple second sub-pads P12 belonging to the second sub-pad group PB and multiple second sub-pads P12 belonging to the first sub-pad group PA can be set as tilted pads PX. Among the multiple second sub-pads P12, except for the tilted pads PX, the other second sub-pads P12 are the same as the first sub-pads P11, and are all set to extend along the second direction Y. ​ The diagram illustrates the case where only multiple second sub-pads P12 belonging to the second sub-pad group PB are set as tilted pads PX. The specific settings can be adjusted according to the actual routing space.

[0169] According to some exemplary embodiments, refer to ​The angle β between the third direction D3 and the first direction X is 45°. By tilting the tilted pad PX along this direction, there can be more space between two adjacent tilted pads PX along the second direction Y, so that more fan-out traces FL can be arranged.

[0170] According to some exemplary embodiments, in conjunction with reference to ​ and ​ In at least two adjacent tilted pads PX along the second direction Y, a portion of a fan-out trace FL electrically connected to one tilted pad PX is located between the two tilted pads PX and extends to one side of a plurality of first pads P1 along the first direction X.

[0171] According to some exemplary embodiments, in conjunction with reference to ​ and ​ The fan-out trace FL can be led out from one end of the tilted pad PX near the display area AA, and then extended along the first direction X towards the side near the gate drive circuit GOA. Specifically, the fan-out trace FL extends from the tilted pads PX located between adjacent tilted pads along the second direction Y to the side of the plurality of first pads P1 away from the central axis Y1, so that a part of the fan-out trace FL can be arranged on one side of the plurality of first pads P1 along the first direction X.

[0172] In this setting, other first pads that are not tilted, such as ​ The second sub-pad P12 shown in the diagram has its fan-out traces drawn from one end near the display area AA, extending to the side of the second sub-pad P12 closest to the display area AA, and then extending towards the first peripheral area NA1 or towards the second peripheral area NA2.

[0173] According to some exemplary embodiments, in conjunction with reference to ​ and ​ The width of the fan-out trace FL electrically connected to the tilted pad PX is greater than the width of the fan-out trace FL electrically connected to the untilted first pad P1 (e.g., including multiple first sub-pads P11 and a portion of the second sub-pad P12).

[0174] The tilted pad PX is the pad located at at least one end of the first pad P1 in the first direction X. The tilted pad PX is electrically connected to the signal line L2 located on at least one side of the first direction X in the display area AA through the fan-out trace FL. Therefore, the extension length of the fan-out trace FL electrically connected to the tilted pad PX is longer than the extension length of the other fan-out traces FL, resulting in a larger voltage drop (IR Drop). Since there is sufficient wiring space on one side of the first pad P1 along the first direction X, the fan-out trace FL can be appropriately thickened in this area, thereby reducing the voltage drop and improving display uniformity.

[0175] ​ The structure of the fan-out routing FL after widening is not specifically shown in the diagram. The width can be appropriately increased according to the actual wiring space.

[0176] For example, the fan-out trace FL electrically connected to the tilted pad PX is set as a non-uniform width trace. It can be thickened only in the space on one side of the multiple first pads P1 along the first direction X, and in other areas it can be consistent with the width of the fan-out trace FL electrically connected to the first pads P1 that are not tilted.

[0177] It should be noted that the trace width should be understood as the width of the trace along its direction of extension.

[0178] ​ The schematic diagram illustrates the arrangement of pads on an array substrate according to some embodiments of the present disclosure. ​ Schematic illustration ​ Another magnified view of region B in the middle.

[0179] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ In a row of first pads P1, multiple second sub-pads P12 are arranged in a direction away from the multiple first sub-pads P11, gradually approaching the display area AA in the second direction Y. The multiple second sub-pads P12 located on the first direction X side are designed to be raised, so that a portion of the space on the side of the multiple second sub-pads P12 away from the display area AA can be used to arrange fan-out traces FL, without occupying the space used for arranging gate signal leads L3.

[0180] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​The multiple fan-out traces FL include multiple first fan-out traces FL1 and multiple second fan-out traces FL2. Multiple first sub-pads P11 are electrically connected to multiple signal lines L2 via the multiple first fan-out traces FL1, and multiple second sub-pads P12 are electrically connected to multiple signal lines L2 via the multiple second fan-out traces FL2. One end of each first fan-out trace FL1 is electrically connected to the end of the first sub-pad P11 closest to the display area AA, and the other end extends to be electrically connected to the signal line L2. One end of each second fan-out trace FL2 is electrically connected to the end of the second sub-pad P12 furthest from the display area AA, and the other end extends to be electrically connected to the signal line L2. A portion of the second fan-out trace FL2 is located on the side of the multiple second sub-pads P12 furthest from the display area AA and on the side of the multiple first sub-pads P11 along the first direction X.

[0181] The second sub-pad P12, which is designed to be raised, is led out from the end away from the display area AA by the second fan-out trace FL2. This makes a part of the second fan-out trace FL2 located on the side of multiple second sub-pads P12 away from the display area AA, thereby improving the wiring space utilization of the fourth peripheral area NA4 and helping to narrow the bezel width on one side of the fourth peripheral area NA4.

[0182] According to some exemplary embodiments, a second sub-pad P12 that is located away from a portion of the plurality of first sub-pads P11 along the first direction X can be configured as an inclined pad. The configuration of the inclined pad can be referred to ​ and ​ This will not be elaborated upon here.

[0183] According to some exemplary embodiments, second sub-pads P12 that are located away from a portion of a plurality of first sub-pads P11 along the first direction X may also be arranged at intervals along the first direction X.

[0184] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The third sub-pad P21 is located on the side of the plurality of second sub-pads P12 away from the display area AA. One end of the gate signal lead L3 is electrically connected to the end of the third sub-pad P21 away from the display area AA, and the other end extends to be electrically connected to the gate drive circuit GOA. A portion of the gate signal lead L3 is located on the side of the second fan-out trace FL2 away from the second sub-pad P12.

[0185] After designing the multiple first pads P1 and fan-out traces FL as described above, without increasing the bezel width on one side of the fourth peripheral area NA4, the space on the side of the multiple second sub-pads P12 away from the display area AA is sufficient to arrange the gate signal lead L3. After being led out from the third sub-pad P21, the gate signal lead L3 can extend continuously along the second direction Y until it is electrically connected to the gate drive circuit GOA.

[0186] It should be noted that multiple first pads P1 located at both ends of the first direction X can be... ​ The illustrated upward design can also be implemented by simply placing multiple first pads P1 located at one end of the first direction X. ​ The design is shown in the illustration.

[0187] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ A portion of the gate signal lead L3 is located between multiple second sub-pads P12 and multiple third pads P3. Due to the specific design of the multiple second sub-pads P12 and fan-out traces FL as described above, the area between the multiple second sub-pads P12 and multiple third pads P3 still has sufficient space to arrange multiple gate signal leads L3 after the second fan-out traces FL2 are arranged. A portion of the gate signal lead L3 located on the side of the multiple second fan-out traces FL2 away from the multiple second sub-pads P12 is a straight trace extending along the first direction X. In this way, the trace length of the gate signal lead L3 can be shortened.

[0188] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The second fan-out trace FL2, which is furthest from the display area AA, can be flush with the side of the second pad P2 furthest from the display area AA. Alternatively, the second fan-out trace FL2, which is furthest from the display area AA, can be closer to the display area AA than the side of the second pad P2 furthest from the display area AA. In this way, even if a part of the second fan-out trace FL2 is set on the side of the second sub-pad P12 furthest from the display area AA, it can still be ensured that the gate signal lead L3 can extend from the area between the second fan-out trace FL2 and the third pad P3 in the direction of the first direction X toward the gate drive circuit GOA.

[0189] According to some exemplary embodiments, refer to ​ , ​ or ​In the fourth peripheral area NA4, multiple virtual pads DP are also set up. The virtual pads DP are configured to connect to the pins of the driver chip and provide support for the pins of the driver chip. This can effectively avoid and prevent the driver chip from warping and shallow bonding indentation caused by bonding stress during the bonding process.

[0190] According to some exemplary embodiments, refer to ​ , ​ or ​ The plurality of virtual pads DP include at least one first virtual pad DP1 and at least one second virtual pad DP2. The first virtual pad DP1 is located between adjacent first sub-pads P11 along the first direction X, and the second virtual pad DP2 is located on one side of the plurality of second pads P2 along the first direction X.

[0191] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The plurality of virtual pads DP also includes at least one third virtual pad DP3, which is located on the side of the second sub-pad P12 closer to the display area AA. The plurality of third virtual pads DP3 can be arranged in a row along the first direction X, or the plurality of third virtual pads DP3 can be arranged in multiple rows.

[0192] It should be noted that the virtual pad DP is set independently on the substrate 100 and is not connected to other leads or other structures. It only serves to support the pins of the driver chip.

[0193] ​ Schematic illustration ​ An enlarged view of region D in the middle. ​ Schematic illustration ​ An enlarged view of region E in the middle.

[0194] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The plurality of first pads P1 include a plurality of first sub-pads P11 and a plurality of second sub-pads P12. The plurality of second sub-pads P12 are located on one side of the plurality of first sub-pads P11 along a first direction X, and in the first direction X, the plurality of second sub-pads P12 are further away from the central axis Y1 than the plurality of first sub-pads P11. The plurality of first pads P1 are arranged in at least one row, and the figure schematically shows the case of being arranged in four rows.

[0195] In a row of first pads P1, multiple first sub-pads P11 are arranged at intervals along the first direction X. The spacing between the multiple first sub-pads P11 and the display area AA in the second direction Y is approximately equal. Along the direction away from the multiple first sub-pads P11, multiple second sub-pads P12 are arranged in the second direction Y with a trend of gradually moving away from the display area AA. That is, the multiple second sub-pads P12 located on one side of the multiple first sub-pads P11 are arranged in a sunken manner.

[0196] The multiple fan-out traces FL include multiple third fan-out traces FL3 and multiple fourth fan-out traces FL4. The ends of multiple first sub-pads P11 closest to the display area AA are electrically connected to multiple signal lines L2 via the multiple third fan-out traces FL3. Among the multiple second sub-pads P12, a portion of the second sub-pads P12 further away from the first sub-pads P11 along the first direction X are electrically connected to the signal lines L2 via the fourth fan-out traces FL4, with the fourth fan-out traces FL4 connected to the end of the connected second sub-pad P12 furthest from the display area AA; and a portion of the second sub-pads P12 closer to the first sub-pads P11 along the first direction X are electrically connected to the signal lines L2 via the third fan-out traces FL3, with the third fan-out traces FL3 connected to the end of the connected second sub-pad P12 closest to the display area AA.

[0197] The fourth fan-out trace FL4, after being led out from the end of the second sub-pad P12 furthest from the display area AA, can first extend towards the first peripheral area NA1 or the second peripheral area NA2, then extend along the direction close to the display area AA to one side of the multiple second sub-pads P12 along the first direction X, and then extend parallel to the multiple third fan-out traces FL3 to be electrically connected to the multiple signal lines L2. That is to say, a portion of the multiple fourth fan-out traces FL4 is located on the side of the multiple second sub-pads P12 furthest from the display area AA, and along the first direction X, a portion of the multiple fourth fan-out traces FL4 is located on the side of the multiple second sub-pads P12 furthest from the central axis Y1.

[0198] By designing the multiple first pads P1 (i.e. multiple second sub-pads P12) located at both ends of the first direction X to be recessed, and by leading out a fan-out trace FL (i.e. fourth fan-out trace FL4) from a side away from the display area AA of a portion of the multiple first sub-pads P11, the wiring space utilization of the fourth peripheral area NA4 can be improved, which is beneficial to narrowing the bezel width on one side of the fourth peripheral area NA4.

[0199] It should be noted that, referring to ​ Multiple virtual pads DP can be set on one side of multiple second sub-pads P12 along the first direction X. These virtual pads DP are not connected to fan-out traces FL.

[0200] ​ Schematic illustration ​ Another magnified view of region D in the middle. ​ Schematic illustration ​ An enlarged view of region F in the middle.

[0201] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The plurality of first pads P1 include a plurality of first sub-pads P11 and a plurality of second sub-pads P12. The plurality of second sub-pads P12 are located on one side of the plurality of first sub-pads P11 along a first direction X, and in the first direction X, the plurality of second sub-pads P12 are further away from the central axis Y1 than the plurality of first sub-pads P11. The plurality of first pads P1 are arranged in at least one row, and the figure schematically shows the case of being arranged in four rows.

[0202] In a row of first pads P1, multiple first sub-pads P11 are arranged at intervals along a first direction X, and the distance between the multiple first sub-pads P11 and the display area AA in a second direction Y is approximately equal. Multiple second sub-pads P12 include a first sub-pad group PA and a second sub-pad group PB. Along the first direction X, the second sub-pad group PB is located on the side of the first sub-pad group PA away from the multiple first sub-pads P11. In a row of first pads P1, along the direction away from the multiple first sub-pads P11, the multiple second sub-pads P12 belonging to the first sub-pad group PA are arranged in a trend of gradually moving away from the display area AA in the second direction Y; and the multiple second sub-pads P12 belonging to the second sub-pad group PB are arranged at intervals along the first direction X, and the distance between the multiple second sub-pads P12 belonging to the second sub-pad group PB and the display area AA in the second direction Y is approximately equal.

[0203] The multiple fan-out traces FL include multiple third fan-out traces FL3 and multiple fourth fan-out traces FL4. The ends of multiple first sub-pads P11 closest to the display area AA are electrically connected to multiple signal lines L2 via the multiple third fan-out traces FL3. In the first sub-pad group PA, the ends of multiple second sub-pads P12 closest to the display area AA are electrically connected to multiple signal lines L2 via the multiple third fan-out traces FL3; in the second sub-pad group PB, the ends of multiple second sub-pads P12 furthest from the display area AA are electrically connected to multiple signal lines L2 via the multiple fourth fan-out traces FL4.

[0204] and ​ and ​ Compared to the schematic array substrate, in ​ and ​In the schematic array substrate, multiple second sub-pads P12 (belonging to the second sub-pad group PB) that lead out the fourth fan-out trace FL4 from the end furthest from the display area AA are arranged at intervals along the first direction X. Then, in a row of first pads P1, the second sub-pad P12 furthest from the multiple first sub-pads P11 is moved a distance H1 in the second direction Y toward the side closer to the display area AA (e.g., ...). ​ The distance indicated in the middle is the difference between the distance of the second sub-pad P12, which is furthest from the first sub-pad P11 in the first sub-pad group PA, from the display area AA, and the distance of the second sub-pad P12, which is furthest from the first sub-pad P11 in the second sub-pad group PB, from the display area AA. This helps to further narrow the border width on the side of the fourth peripheral area NA4.

[0205] ​ Schematic illustration ​ Another magnified view of region D in the middle. ​ Schematic illustration ​ A magnified view of region G in the middle.

[0206] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ In a row of first pads P1, multiple first sub-pads P11 are arranged at intervals along a first direction X. The multiple first sub-pads P11 are spaced approximately equally from the display area AA in a second direction Y. Multiple second sub-pads P12 include a first sub-pad group PA and a second sub-pad group PB. Along the first direction X, the second sub-pad group PB is located on the side of the first sub-pad group PA away from the multiple first sub-pads P11. In a row of first pads P1, along the direction away from the multiple first sub-pads P11, the multiple second sub-pads P12 belonging to the first sub-pad group PA are arranged in the second direction Y with a trend of gradually moving away from the display area AA; and the multiple second sub-pads P12 belonging to the second sub-pad group PB are arranged in the second direction Y with a trend of gradually moving closer to the display area AA.

[0207] The multiple fan-out traces FL include multiple third fan-out traces FL3 and multiple fourth fan-out traces FL4. Multiple first sub-pads P11 are electrically connected to multiple signal lines L2 via multiple third fan-out traces FL3 at their ends near the display area AA. In the first sub-pad group PA, multiple second sub-pads P12 are electrically connected to multiple signal lines L2 via multiple third fan-out traces FL3 at their ends near the display area AA. In the second sub-pad group PB, multiple second sub-pads P12 are electrically connected to multiple signal lines L2 via multiple fourth fan-out traces FL4 at their ends away from the display area AA.

[0208] and ​ and ​ Compared to the schematic array substrate, in ​ and ​ In the schematic array substrate, multiple second sub-pads P12 (belonging to the second sub-pad group PB) that extend from the end furthest from the display area AA, with the fourth fan-out trace FL4, are arranged in a trend of gradually approaching the display area AA in the second direction Y. Then, in a row of first pads P1, the second sub-pad P12 furthest from the multiple first sub-pads P11 is further moved a certain distance in the second direction Y towards the side closer to the display area AA (this distance is less than...). ​ The distance H2 marked in the middle is used to further narrow the border width on the side of the fourth peripheral area NA4.

[0209] According to some exemplary embodiments, refer to ​ In the first sub-pad group PA, the acute angle between the geometric center of the orthographic projection of one second sub-pad P12 onto the substrate 100 and the geometric center of the orthographic projection of another second sub-pad P12 onto the substrate 100, and the first direction X, is the third angle α3. The third angle α3 is greater than 0 degrees and less than or equal to 45 degrees. The larger the third angle α3 is, the better it is for improving the wiring space utilization of the fourth peripheral area NA4. However, since the first sub-pad group PA is arranged into multiple rows of second sub-pads P12, in a row of second sub-pads P12 located further away from the display area AA, the fan-out traces FL need to pass through the area between adjacent second sub-pads P12. The larger the third angle α3 is, the smaller the space between adjacent second sub-pads P12 that can be used to arrange fan-out traces FL. Therefore, the third angle α3 should not be set too large to avoid the problem of short circuit between the fan-out traces FL and the second sub-pads P12 located between adjacent second sub-pads P12.

[0210] For example, in the first sub-pad group PA, the line connecting the geometric centers of the orthographic projections of two second sub-pads P12 on the substrate 100 is parallel to the line connecting the geometric centers of the orthographic projections of the other two second sub-pads P12 on the substrate 100. That is, along the first direction X, the distance between the multiple second sub-pads P12 belonging to the first sub-pad group PA and the display area AA increases linearly, and the geometric centers of the orthographic projections of the multiple second sub-pads P12 on the substrate 100 are located on the same straight line.

[0211] According to some exemplary embodiments, refer to ​The third included angle α3 is greater than or equal to 1 degree and less than or equal to 20 degrees. For example, the third included angle α3 is 1 degree, 2 degrees, 3 degrees, 4 degrees, 5 degrees, 6 degrees, 7 degrees, 8 degrees, 9 degrees, 10 degrees, 11 degrees, 12 degrees, 13 degrees, 14 degrees, 15 degrees, 16 degrees, 17 degrees, 18 degrees, 19 degrees, or 20 degrees, etc.

[0212] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The display area AA has a central axis Y1 extending along the second direction Y. The third fan-out trace FL3 includes a first trace segment FL31 and a second trace segment FL32. One end of the first trace segment FL31 is electrically connected to the end of the first pad P1 near the display area AA and extends along the second direction Y toward the side near the display area AA. One end of the second trace segment FL32 is electrically connected to the end of the first trace segment FL31 near the display area AA and the other end extends along the fourth direction D4 toward the side away from the central axis Y1 and close to the display area AA. The acute angle between the fourth direction D4 and the first direction X is the first angle α1.

[0213] For example, on the side located near the first peripheral region NA1 on the central axis Y1 (i.e. ​ (Illustrated area), the second routing segment FL32 extends towards the first peripheral area NA1 and the display area AA. On the side of the central axis Y1 near the second peripheral area NA2, the second routing segment FL32 extends towards the second peripheral area NA2 and the display area AA. The fourth direction D4 of the second routing segment FL32 extending on the side of the central axis Y1 near the first peripheral area NA1 and the fourth direction D4 of the second routing segment FL32 extending on the side of the central axis Y1 near the second peripheral area NA2 can be symmetrically set with respect to the central axis Y1.

[0214] In the second sub-pad group PB, the acute angle between the line connecting the geometric center of the orthographic projection of one second sub-pad P12 onto the substrate 100 and the geometric center of the orthographic projection of the other second sub-pad P12 onto the substrate 100, and the first direction X, is the second included angle α2. The second included angle α2 is less than or equal to the first included angle α1. ​ This schematically illustrates the case where the second included angle α2 is equal to the first included angle α1. Thus, compared to... ​ In the schematic array substrate, the second sub-pad P12, which is furthest from the plurality of first sub-pads P11, moves a greater distance in the second direction Y toward the side closer to the display area AA, which is the difference between H2 and the safety distance (the distance to avoid short-circuiting the second sub-pad P12 and the second trace segment FL32).

[0215] For example, in the second sub-pad group PB, the line connecting the geometric centers of the orthographic projections of two second sub-pads P12 on the substrate 100 is parallel to the line connecting the geometric centers of the orthographic projections of the other two second sub-pads P12 on the substrate 100. That is, along the first direction X, the distance between the multiple second sub-pads P12 belonging to the second sub-pad group PB and the display area AA decreases linearly. The geometric centers of the orthographic projections of the multiple second sub-pads P12 on the substrate 100 are located on the same straight line, which is parallel to the extension direction of the adjacent second trace segment FL32.

[0216] According to some exemplary embodiments, refer to ​ The size of the second included angle α2 depends on the size of the first included angle α1, and the second included angle α2 is less than or equal to the first included angle α1.

[0217] For example, the second included angle α2 is greater than 0 degrees and less than or equal to 45 degrees.

[0218] For example, the second included angle α2 is greater than or equal to 1 degree and less than or equal to 12 degrees. Exemplarily, the second included angle α2 is 1 degree, 2 degrees, 3 degrees, 4 degrees, 5 degrees, 6 degrees, 7 degrees, 8 degrees, 9 degrees, 10 degrees, 11 degrees, or 12 degrees, etc.

[0219] According to some exemplary embodiments, in conjunction with reference to ​ and ​ Setting the angle (i.e., the third included angle α3) of the multiple second sub-pads P12 in the first sub-pad group PA to be inclined towards the side away from the display area AA is greater than the angle (i.e., the second included angle α2) of the multiple second sub-pads P12 in the second sub-pad group PB to be inclined towards the side closer to the display area AA, which is more conducive to improving the wiring space utilization of the fourth peripheral area NA4.

[0220] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The third sub-pad P21 is located on the side of the plurality of second sub-pads P12 away from the display area AA. One end of the gate signal lead L3 is electrically connected to the end of the third sub-pad P21 away from the display area AA, and the other end extends to be electrically connected to the gate drive circuit GOA. A portion of the gate signal lead L3 is located on the side of the fourth fan-out trace FL4 away from the second sub-pad P12. By setting the third sub-pad P21 on the side of the plurality of second sub-pads P12 away from the display area AA, and extending the gate signal lead L3 from the end of the third sub-pad P21 away from the display area AA around the plurality of fourth fan-out traces FL4 to the side of the plurality of fourth fan-out traces FL4 away from the second sub-pad group PB, and then continuing to extend along the first direction X towards the peripheral area NA until it is electrically connected to the gate drive circuit GOA.

[0221] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ Along the first direction X, a plurality of third sub-pads P21 are located on the side of the fourth fan-out trace FL4 near the central axis Y1. A gate signal lead L3 extends from the end of the third sub-pad P21 away from the display area AA and extends towards the fourth fan-out trace FL4. A portion of the gate signal lead L3 is located on the side of the fourth fan-out trace FL4 away from the peripheral area NA.

[0222] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The multiple bonding pads also include multiple third pads P3. Along the second direction Y, the multiple third pads P3 are located on the side of the multiple second pads P2 away from the multiple first pads P1. The multiple third pads P3 can be arranged in a row along the first direction X. The multiple third pads P3 are configured to be electrically connected to the flexible circuit board. The multiple second pads P2 also include multiple fourth sub-pads P22. Along the first direction X, the multiple fourth sub-pads P22 are located on the side of the multiple third sub-pads P21 closer to the central axis Y1. The multiple fourth sub-pads P22 are electrically connected to the multiple third pads P3 through multiple bonding connection lines BL.

[0223] For example, multiple third sub-pads P21 are respectively provided on both sides of multiple fourth sub-pads P22 along the first direction X. Among the multiple third sub-pads P21 located near the first peripheral region NA1 of the fourth sub-pad P22, the third sub-pad P21 is electrically connected to the gate drive circuit GOA located in the first peripheral region NA1 through the gate signal lead L3. Among the multiple third sub-pads P21 located near the second peripheral region NA2 of the fourth sub-pad P22, the third sub-pad P21 is electrically connected to the gate drive circuit GOA located in the second peripheral region NA2 through the gate signal lead L3.

[0224] In the plurality of second pads P2, the fourth sub-pad P22 is electrically connected to the third pad P3, and is used to receive signals provided by the flexible circuit board and input them into the driver chip. The third sub-pad P21 is used to output the gate drive signal provided by the driver chip to the gate drive circuit GOA. The gate signal lead L3, which is led out from the end of the third sub-pad P21 away from the display area AA, extends from the side of the plurality of third pads P3 near the display area AA to the side of the plurality of third pads P3 along the first direction X, and then continues to extend along the first direction X towards the peripheral area NA until it is electrically connected to the gate drive circuit GOA. In this way, along the first direction X, a portion of the gate signal lead L3 is located on the side of the plurality of third pads P3 away from the central axis Y1. That is, the space between the plurality of third pads P3 and the peripheral area NA along the first direction X can be used to arrange the gate signal lead L3, thereby improving the wiring space utilization of the fourth peripheral area NA4 and helping to narrow the bezel width on the side of the fourth peripheral area NA4.

[0225] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The display area AA has a central axis Y1 extending along the second direction Y. The third pad P3, located on the side of the first direction X, furthest from the central axis Y1, is closer to the central axis Y1 than the first pad P1, located on the same side of the first direction X, furthest from the central axis Y1. The gate signal lead L3 extends from the side of the plurality of third pads P3 near the display area AA, around the edge of the plurality of third pads P3, to the side of the plurality of third pads P3 along the first direction X. That is, the distribution width of the plurality of third pads P3 along the first direction X is set to be narrower than the distribution width of the plurality of first pads P1 along the first direction X, so that the space on the side of the plurality of first pads P1 furthest from the display area AA and on the side of the plurality of third pads P3 along the first direction X can be used to arrange multiple gate signal leads L3, so as to ensure that the gate signal lead L3 can be continuously extended to be electrically connected to the gate drive circuit GOA after being led out from the third sub-pad P21.

[0226] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The third pad P3, located on the side of the first direction X, which is furthest from the central axis Y1, is closer to the central axis Y1 than the second sub-pad P12, which is furthest from the central axis Y1, located on the same side of the first sub-pad group PA on the same side of the first direction X. This allows the space on the side of the second sub-pad group PB furthest from the display area AA to be used to arrange the gate signal lead L3.

[0227] It should be noted that the distribution width of multiple third pads P3 along the first direction X can be narrowed by reducing the size of the third pad P3 along the first direction X and the spacing between adjacent third pads P3 along the first direction X. For example, the size of the third pad P3 along the first direction X can be narrowed to 70 μm, and the spacing between adjacent third pads P3 along the first direction X can be narrowed to 70 μm. Alternatively, some traces that were originally electrically connected to two third pads P3 can be adjusted to be electrically connected to only one third pad P3, thereby reducing the number of third pads P3 and narrowing the distribution width of multiple third pads P3 along the first direction X.

[0228] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The gate signal lead L3 includes a first gate signal lead segment L31, a second gate signal lead segment L32, a third gate signal lead segment L33, and a fourth gate signal lead segment L34 connected in sequence.

[0229] One end of the first gate signal lead segment L31 is electrically connected to the third sub-pad P21, and the other end extends in a direction away from the central axis Y1 and close to multiple third pads P3 (the figure shows the first gate signal lead segment L31 located near the first peripheral area NA1 on the central axis Y1, which extends to the lower left side shown in the figure). The first gate signal lead segment L31 may include two sub-gate signal lead segments connected in sequence, and the extension directions of the two sub-gate signal lead segments at both ends form an obtuse angle.

[0230] One end of the second gate signal lead segment L32 is electrically connected to the end of the first gate signal lead segment L31 away from the third sub-pad P21, and the other end extends along the first direction X toward the side away from the central axis Y1.

[0231] One end of the third gate signal lead segment L33 is electrically connected to the end of the second gate signal lead segment L32 away from the first gate signal lead segment L31, and the other end extends in a direction away from the plurality of first pads P1 and away from the central axis Y1 (the figure shows the third gate signal lead segment L33 located near the first peripheral area NA1 on the central axis Y1, which extends to the lower left side as shown in the figure), until it extends to one side of the plurality of third pads P3 along the first direction X.

[0232] One end of the fourth gate signal lead segment L34 is electrically connected to the end of the third gate signal lead segment L33 away from the second gate signal lead segment L32, and the other end extends along the first direction X toward the side away from the central axis Y1. The fourth gate signal lead segment L34 is located on one side of the plurality of third pads P3 along the first direction X.

[0233] It should be noted that, ​Only a portion of the fourth gate signal lead segment L34 is shown in the diagram. Multiple fourth gate signal lead segments L34 can continue to extend along the first direction X until they are electrically connected to multiple gate drive signal lines extending along the second direction Y in the gate drive circuit GOA.

[0234] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The fourth fan-out trace FL4 includes a first portion FL4A located on the side of the multiple second sub-pads P12 away from the display area AA along the first direction X. The first portion FL4A is located on the side of the third gate signal lead segment L33 away from the central axis Y1, and the first portion FL4A is located on the side of the fourth gate signal lead segment L34 close to the display area AA. Since the gate signal lead L3 extends along the edge of the multiple third pads P3 to the side of the multiple third pads P3 along the first direction X, there is sufficient space between the fourth gate signal lead segment L34 and the multiple second sub-pads P12 to arrange the fourth fan-out trace FL4. In this way, the wiring space utilization of the fourth peripheral area NA4 can be effectively improved, thereby narrowing the bezel width on one side of the fourth peripheral area NA4.

[0235] It should be noted that the number of fourth fan-out traces FL4 (that is, the number of second sub-pads P12 in the second sub-pad group PB) depends on the distance between the end of the second sub-pad group PB away from the display area AA and the end of the third pad P3 away from the display area AA along the second direction Y, the distribution width of the multiple fourth gate signal lead segments L34 in the multiple gate signal leads L3 along the second direction Y, the trace width of the fourth fan-out traces FL4, and the spacing between adjacent fourth fan-out traces FL4. If the wiring space allows, more fourth fan-out traces FL4 can be arranged.

[0236] According to some exemplary embodiments, in conjunction with reference to ​ and ​ The fourth gate signal lead segment L34, which is furthest from the display area AA, is flush with the side of the multiple third pads P3 furthest from the display area AA. This means that the multiple fourth gate signal lead segments L34 are set far away from the display area AA within the space allowed, which is conducive to arranging a larger number of fourth fan-out traces FL4 on the side of the multiple fourth gate signal lead segments L34 close to the display area AA.

[0237] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The fourth outgoing cable FL4 includes the third cable segment FL41, the fourth cable segment FL42, and the fifth cable segment FL43 connected in sequence.

[0238] One end of the third trace segment FL41 is electrically connected to the end of the second sub-pad P12 in the second sub-pad group PB that is away from the display area AA, and the other end extends along the second direction Y toward the side away from the display area AA. When multiple second sub-pads P12 are arranged in multiple rows, in the row of second sub-pads P12 that is farthest from the display area AA, the third trace segment FL41 is connected to the end of the second sub-pad P12 that is farthest from the display area AA; in at least another row of second sub-pads P12 that is closer to the display area AA, after the third trace segment FL41 is connected to the end of the second sub-pad P12 that is farthest from the display area AA, it extends along the gap between adjacent second sub-pads P12 to the side of the row of second sub-pads P12 that is farthest from the display area AA.

[0239] One end of the fourth trace segment FL42 is electrically connected to the end of the third trace segment FL41 away from the second sub-pad P12, and the other end extends in a direction away from the second sub-pad P12 and away from the central axis Y1 (the figure shows the fourth trace segment FL42 located near the first peripheral area NA1 on the central axis Y1, and the fourth trace segment FL42 extends to the lower left side shown in the figure). The fourth trace segment FL42 is located on the side of the third gate signal lead segment L33 along the first direction X, and the fourth trace segment FL42 can be set parallel to the third gate signal lead segment L33.

[0240] One end of the fifth trace segment FL43 is electrically connected to the end of the fourth trace segment FL42 away from the third trace segment FL41, and the other end extends along the first direction X toward the side away from the central axis Y1. Along the second direction Y, the fifth trace segment FL43 is located on the side of the fourth gate signal lead segment L34 close to the display area AA.

[0241] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The fourth outgoing cable FL4 includes the sixth cable segment FL44, the seventh cable segment FL45, and the eighth cable segment FL46 connected in sequence.

[0242] One end of the sixth trace segment FL44 is electrically connected to the end of the fifth trace segment FL43 away from the fourth trace segment FL42, and the other end extends in a direction away from the central axis Y1 and close to the display area AA (the figure shows the sixth trace segment FL44 located on the central axis Y1 close to the first peripheral area NA1, and the sixth trace segment FL44 extends to the upper left side shown in the figure).

[0243] One end of the seventh trace segment FL45 is electrically connected to the end of the sixth trace segment FL44 that is away from the fifth trace segment FL43, and the other end extends along the second direction Y towards the side closer to the display area AA. Along the first direction X, the seventh trace segment FL45 is located on the side of the second sub-pad P12 away from the central axis Y1.

[0244] One end of the eighth routing segment FL46 is electrically connected to the end of the seventh routing segment FL45 away from the sixth routing segment FL44, and the other end extends towards the display area AA and away from the central axis Y1 (the figure shows the eighth routing segment FL46 located near the first peripheral area NA1 on the central axis Y1, and the eighth routing segment FL46 extends towards the upper left side shown in the figure). The eighth routing segment FL46 can be set parallel to the second routing segment FL32 in the third fan-out routing FL3.

[0245] ​ A schematic plan view of an array substrate according to some embodiments of the present disclosure is shown. ​ Schematic illustration ​ A magnified view of region H in the middle. ​ Schematic illustration ​ A magnified view of region I in the middle. ​ Schematic illustration ​ A magnified view of region J in the middle. ​ Schematic illustration ​ A magnified view of region K in the middle.

[0246] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The array substrate also includes a common electrode COM and a common voltage lead CL. The common electrode COM is located in the display area AA, and at least a portion of the common voltage lead CL is located in the peripheral area NA. The common voltage lead CL is electrically connected to the common electrode COM and is used to connect a common voltage signal to the common electrode COM.

[0247] Multiple fan-out traces FL include a first fan-out section FLA and a second fan-out section FLB. The first fan-out section FLA and the second fan-out section FLB are arranged at intervals along a first direction X. Each of the multiple first fan-out section FLA and the multiple second fan-out section FLB includes multiple fan-out traces FL. The first fan-out section FLA is closer to the first peripheral area NA1, and the multiple fan-out traces FL within the first fan-out section FLA can be electrically connected to multiple signal lines L2 that are also closer to the first peripheral area NA1. The second fan-out section FLB is closer to the second peripheral area NA2, and the multiple fan-out traces FL within the second fan-out section FLB can be electrically connected to multiple signal lines L2 that are also closer to the second peripheral area NA2.

[0248] The common voltage lead CL includes a first common voltage lead CL1, a second common voltage lead CL2, and a third common voltage lead CL3 arranged sequentially along the first direction X. At least a portion of the first common voltage lead CL1 is located on the side of the first fan-out section FLA away from the second fan-out section FLB. At least a portion of the third common voltage lead CL3 is located on the side of the second fan-out section FLB away from the first fan-out section FLA. At least a portion of the second common voltage lead CL2 is located between the first fan-out section FLA and the second fan-out section FLB. By setting three common voltage leads CL, which respectively connect the common voltage signal to the common electrode COM from both sides of the first direction X and at a position located in the middle of the first direction X, the uniformity of the distribution of the common voltage signal in the common electrode COM in the display area AA can be effectively improved, thereby improving the display uniformity.

[0249] For example, when a liquid crystal display substrate is prepared using this array substrate, the common electrode COM can be an electrode structure that forms an electric field with the pixel electrode to drive the liquid crystal deflection.

[0250] For example, when an OLED display substrate is fabricated using this array substrate, the common electrode COM can serve as the common cathode for multiple OLED display devices.

[0251] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The multiple bonding pads also include multiple third pads P3, which are located on the side of the multiple second pads P2 away from the multiple first pads P1.

[0252] One end of the first common voltage lead CL1 is electrically connected to at least one third pad P3, and the other end extends between multiple first pads P1 and multiple second pads P2 and around the first fan-out portion FLA to be electrically connected to the common electrode COM. One end of the third common voltage lead CL3 is electrically connected to at least one third pad P3, and the other end extends between multiple first pads P1 and multiple second pads P2 and around the second fan-out portion FLB to be electrically connected to the common electrode COM. The first common voltage leads CL1 and the second common voltage leads CL2 located on both sides of the first direction X are directly electrically connected to the third pad P3 and connect the common voltage signal output by the flexible circuit board to the common electrode COM.

[0253] ​ The diagram illustrates the specific structure at the connection between the first common voltage lead CL1 and the third pad P3. The connection structure between the third common voltage lead CL3 and the third pad P3 can be described as follows: ​ The schematic structure is set up.

[0254] For example, the first common voltage lead CL1 can be electrically connected to the two third pads P3, and the third common voltage lead CL3 can be electrically connected to the two third pads P3.

[0255] It should be noted that the array substrate includes multiple metal layers, including at least one gate metal layer and at least one source / drain metal layer. The common voltage lead CL can be located on the same metal layer as the third pad P3 or on different metal layers. When the common voltage lead CL and the third pad P3 are located on the same metal layer, the first common voltage lead CL1 and the second common voltage lead CL2 are respectively connected to the third pad P3 as a single unit. In actual products, the third pad P3, which is integrated with the first common voltage lead CL1, will not show its outline. ​ The outline of the third pad P3 is shown in the diagram only to make the location of the third pad P3 clearer.

[0256] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ The first common voltage lead CL1 includes a second portion CL11 located between adjacent second pads P2 along the first direction X, wherein the dimension W1 of the second portion CL11 along the first direction X is greater than or equal to the dimension W2 of the second pads P2 along the first direction X.

[0257] The first common voltage lead CL1 extends from the third pad P3 towards the side closest to the display area AA, and passes through multiple second pads P2 to the side of the multiple second pads P2 closest to the multiple first pads P1. To ensure the trace width of the first common voltage lead CL1, the portion passing through the multiple second pads P2 (i.e., the second portion CL11) borrows from at least one second pad P2, for example, ​ The illustration shows the second part CL11 borrowing from three second pads P2. The size W1 of the second part CL11 along the first direction X is three times the size W2 of the second pads P2 along the first direction X plus twice the spacing between adjacent second pads P2 along the first direction X.

[0258] It should be noted that in the actual product, the area where CL11 is located in the second part does not actually have a second pad P2. ​ The diagram illustrates three second pads P2 that overlap with the second part CL11. This is only to show that the second part CL11 borrows space that could have been used to set up the three pads to increase the width of the second part CL11, thereby reducing the resistance of the first common voltage lead CL1.

[0259] The third common voltage lead CL3 includes a third portion located between adjacent second pads P2 along the first direction X, the size of the third portion along the first direction X being greater than or equal to the size of the second pads P2 along the first direction X. ​ The diagram illustrates the specific structure of the second part CL11 of the first common voltage lead CL1. The structure of the third part of the third common voltage lead CL3 can be described as follows: ​ The schematic structure is set up.

[0260] According to some exemplary embodiments, in conjunction with reference to ​ , ​ , ​ and ​ The array substrate may also include a common voltage monitoring trace CL', one end of which is electrically connected to the third pad P3, and the other end extends to be electrically connected to the common electrode COM. The common voltage monitoring trace CL' is used to acquire the common voltage signal on the common electrode COM and transmit it to the flexible circuit board through the third pad P3 to realize the monitoring of the common voltage signal.

[0261] The third pad P3, which is electrically connected to the common voltage monitoring trace CL', is adjacent to the third pad P3, which is electrically connected to the first common voltage lead CL1, and is located on the side closer to the first peripheral area NA1. The common voltage monitoring trace CL' can be electrically connected to two third pads P3, and after being led out from the third pads P3, it extends towards the side closer to the display area AA, and extends to the side of multiple second pads P2 near the display area AA by borrowing one second pad P2.

[0262] After the common voltage monitoring trace CL' extends to the side of the second pad P2 near the display area AA, it extends along the first direction X towards the first peripheral area NA1. After extending to a point closer to the first peripheral area NA1 than the multiple third sub-pads P21, it extends using a second pad P2 to the side of the second pad P2 away from the display area AA, and then continues to extend along the edge of the multiple gate signal leads L3 towards the first peripheral area NA1. After the first common voltage lead CL1 extends to the side of the second pad P2 near the display area AA, it extends parallel to the edge of the adjacent common voltage monitoring trace CL' towards the first peripheral area NA1.

[0263] It should be noted that on the other side of the first direction X, a common voltage monitoring trace CL' adjacent to the third common voltage lead CL3 can also be set. The structure of this common voltage monitoring trace CL' and the common voltage monitoring trace CL' adjacent to the first common voltage lead CL1 can be consistent, and will not be described in detail here.

[0264] According to some exemplary embodiments, in conjunction with reference to ​, ​ , ​ and ​ One end of the second common voltage lead CL2 is directly electrically connected to at least one third pad P3, and extends through multiple second pads P2, along the interval between multiple second pads P2 and multiple third pads P3 and the interval between the first fan-out portion FLA and the second fan-out portion FLB, to be electrically connected to the common electrode COM.

[0265] Combined with reference ​ and ​ The second common voltage lead CL2 includes a fifth portion CL22 located between adjacent second pads P2 along the first direction X. The dimension W3 of the fifth portion CL22 along the first direction X is greater than or equal to the dimension W2 of the second pads P2 along the first direction X. That is, the second common voltage lead CL2 borrows at least one second pad P2 when passing through multiple second pads P2; for example, the fifth portion CL22 borrows two second pads P2.

[0266] It should be noted that in the actual product, the area where CL22 is located in section five does not actually have a second pad P2. ​ The diagram illustrates two second pads P2 that overlap with the fifth part CL22. This is only to show that the fifth part CL22 borrows the space that could have been used to set the two second pads P2 to increase the width of the fifth part CL22, thereby reducing the resistance of the third common voltage lead CL3.

[0267] Combined with reference ​ , ​ and ​ The second common voltage lead CL2 includes a seventh portion CL23 located between a plurality of second pads P2 and a plurality of third pads P3, and a fourth portion CL21 located between a first fan-out portion FLA and a second fan-out portion FLB. One end of the seventh portion CL23 is electrically connected to a fifth portion CL22, and the other end extends along a first direction X to be electrically connected to the fourth portion CL21. One end of the fourth portion CL21 is electrically connected to a common electrode COM, and the other end extends along a second direction Y and passes through a plurality of first pads P1 to be electrically connected to the seventh portion CL23.

[0268] It should be noted that the third pad P3, which is electrically connected to the second common voltage lead CL2, can be located closer to the first peripheral area NA1 or closer to the second peripheral area NA2. ​The diagram schematically illustrates a scenario where the third pad P3, electrically connected to the second common voltage lead CL2, can be located closer to the first peripheral region NA1. Alternatively, the third pad P3, electrically connected to the second common voltage lead CL2, can be located at the midpoint along the first direction X, i.e., with a spacing substantially equal to that between the first peripheral region NA1 and the second peripheral region NA2. In this case, the aforementioned seventh portion CL23 is unnecessary, and the third common voltage lead CL3, after passing through multiple second pads P2, can continue to extend along the second direction Y to between the first fan-out portion FLA and the second fan-out portion FLB.

[0269] According to some exemplary embodiments, refer to ​ Along the second direction Y, the distance D1 between the seventh part CL23 and the row of second pads P2 closest to the display area AA is equal to the distance D2 between the seventh part CL23 and the row of first pads P1 furthest from the display area AA. This ensures that the seventh part CL23 maintains a large distance from both the multiple second pads P2 and the multiple first pads P1, thereby avoiding signal interference between the second common voltage lead CL2 and the multiple second pads P2 and the multiple first pads P1.

[0270] According to some exemplary embodiments, refer to ​ The dimension W4 of the fourth part CL21 along the first direction X is greater than or equal to the dimension W5 of the first pad P1 along the first direction X. That is, the second common voltage lead CL2 borrows at least one first pad P1 when passing through multiple first pads P1. For example, the fourth part CL21 can be a non-uniform width design, and a portion of the fourth part CL21 can borrow four first pads P1, or a portion of the fourth part CL21 can borrow three first pads P1.

[0271] It should be noted that in the actual product, the area where CL21 in the fourth part is located does not actually have a first pad P1. ​ The diagram illustrates multiple first pads P1 that overlap with the fifth part CL22. This is only to show that the fifth part CL22 borrows space that could have been used to set multiple first pads P1 to increase the width of the fourth part CL21, thereby reducing the resistance of the second common voltage lead CL2.

[0272] According to some exemplary embodiments, in conjunction with reference to ​ and ​The multiple first pads P1 include multiple first virtual pads DP1, which are located between the fourth part CL21 and the first fan-out part FLA, and between the fourth part CL21 and the second fan-out part FLB. This configuration ensures that the fourth part CL21 maintains a significant distance from the first fan-out part FLA, the second fan-out part FLB, the multiple first pads P1 electrically connected to the first fan-out part FLA, and the multiple first pads P1 electrically connected to the second fan-out part FLB. This effectively avoids signal interference between the fourth part CL21 and the first fan-out part FLA and the second fan-out part FLB.

[0273] According to some exemplary embodiments, refer to ​ A shielded trace segment LX is provided on at least one side of the second common voltage lead CL2 along the first direction X, and the shielded trace segment LX is spaced apart from the second common voltage lead CL2. One end of the shielded trace segment LX is located between the second common voltage lead CL2 and the third pad P3, and the other end of the shielded trace segment LX is located between the second common voltage lead CL2 and the second pad P2. For example, two shielded trace segments LX are respectively provided on both sides of the second common voltage lead CL2 along the first direction X. The shielded trace segment LX can be used to shield the signal interference between the second common voltage lead CL2 and the adjacent third pad P3, second pad P2, and bonding connection line BL.

[0274] According to some exemplary embodiments, refer to ​ One end of the shielded trace segment LX can be electrically connected to at least one third pad P3, and the flexible circuit board can connect to the ground signal (GND) through the third pad P3 to the shielded trace segment LX.

[0275] According to some exemplary embodiments, refer to ​ The shielded trace segment LX includes a sixth portion LX1 located between adjacent second pads P2 along the first direction X. The dimension W6 of the sixth portion LX1 along the first direction X is greater than or equal to the dimension W2 of the second pads P2 along the first direction X. The end of the sixth portion LX1 closest to the display area AA can be configured using at least one second pad P2, for example... ​ This illustrates the situation where the sixth part LX1, near the display area AA, borrows two second pads P2.

[0276] ​ A schematic plan view of an array substrate according to some embodiments of the present disclosure is shown. ​ Schematic illustration ​ A magnified view of the central region L. ​ Schematic illustration ​ A magnified view of region M in the middle.

[0277] According to some exemplary embodiments, in conjunction with reference to ​ , ​ and ​ In some cases, when there is no second pad P2 available for the second common voltage lead CL2 to use, the second common voltage lead CL2 may not be directly electrically connected to the third pad P3. Instead, the second common voltage lead CL2 may be electrically connected to at least one of the first common voltage lead CL1 and the third common voltage lead CL3, and then extend along the interval between the first fan-out portion FLA and the second fan-out portion FLB to be electrically connected to the common electrode COM.

[0278] Specifically, the second common voltage lead CL2 includes a fourth portion CL21 and an eighth portion CL24. One end of the fourth portion CL21 is electrically connected to the common electrode COM, and the other end extends along the second direction Y and passes through multiple first pads P1 to be electrically connected to the eighth portion CL24. The eighth portion CL24 is located between the multiple first pads P1 and multiple second pads P2. The eighth portion CL24 extends along the first direction X, with one end extending to be electrically connected to the first common voltage lead CL1 and the other end extending to be electrically connected to the third common voltage lead CL3.

[0279] It should be noted that the specific structures of the fourth part CL21, the first common voltage lead CL1, and the third common voltage lead CL3 can be described as above, and will not be repeated here.

[0280] At least some embodiments of this disclosure also provide a display substrate, which includes the array substrate described above. The display substrate may include a liquid crystal display substrate, an OLED display substrate, a sub-millimeter light-emitting diode (Mini LED) display substrate, and a micro light-emitting diode (Micro LED) display substrate, etc.

[0281] At least some embodiments of this disclosure also provide a display device comprising the display substrate described above. The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0282] It should be understood that the display device according to some exemplary embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be referred to in the above description of the display substrate and will not be repeated here.

[0283] As used herein, the terms “substantially,” “approximately,” “about,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “about” as used herein includes the stated value and indicates that the particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0284] While some embodiments based on the general inventive concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate comprising a display area and a peripheral area surrounding the display area, the display area having a central axis extending along a second direction, wherein, The array substrate includes: Substrate; Multiple scan lines are located on the substrate, at least a portion of the scan lines are located in the display area, the multiple scan lines extend along a first direction and are arranged along a second direction, the first direction and the second direction intersect; Multiple signal lines are located on the substrate, at least a portion of the signal lines are located in the display area, and at least a portion of the signal lines extend along the second direction and are arranged along the first direction; A gate driving circuit, located on the substrate, is situated in the peripheral region and at least one side of the display area along the first direction, and is electrically connected to a plurality of the scan lines; and Multiple bonding pads are located on the substrate, and the multiple bonding pads are located in the peripheral region and on one side of the display region along the second direction. The plurality of bonding pads include a plurality of first pads and a plurality of second pads, the plurality of second pads being located on the side of the plurality of first pads away from the display area, and the plurality of first pads and the plurality of second pads being configured to be electrically connected to the driver chip. The plurality of first pads include a plurality of first sub-pads and a plurality of second sub-pads, wherein along the first direction, the plurality of second sub-pads are located on the side of the plurality of first sub-pads away from the central axis; A plurality of first pads are arranged in at least one row, and in one row of first pads, a plurality of first sub-pads are spaced apart along the first direction, and at least one second sub-pad is not equidistant from the display area from the first sub-pad in the second direction; and The second pad includes a plurality of third sub-pads, and the array substrate also includes a plurality of gate signal leads, one end of which is electrically connected to the third sub-pad and the other end extends to be electrically connected to the gate drive circuit.

2. The array substrate according to claim 1, wherein, The array substrate also includes multiple fan-out traces, and multiple first pads are electrically connected to multiple signal lines through the multiple fan-out traces. In the second direction, a portion of at least one fan-out trace is further away from the display area than at least one first pad.

3. The array substrate according to claim 2, wherein, Along the second direction, a plurality of third sub-pads are located on the side of a plurality of second sub-pads away from the display area. One end of the gate signal lead is electrically connected to the end of the third sub-pad away from the display area, and the other end extends to be electrically connected to the gate drive circuit. A portion of the gate signal lead along the second direction is located on the side of a plurality of second sub-pads away from the display area.

4. The array substrate according to claim 3, wherein, The plurality of bonding pads further include a plurality of third pads, the plurality of third pads being located on the side of the plurality of second pads away from the plurality of first pads; The plurality of second pads further include a plurality of fourth sub-pads, which are located on the side of the plurality of third sub-pads away from the central axis along the first direction, and are electrically connected to the plurality of third pads respectively via a plurality of bonding wires; and A portion of the gate signal lead is located between a plurality of second sub-pads and a plurality of third pads.

5. The array substrate according to claim 4, wherein, The line connecting the geometric centers of the orthographic projections of the plurality of second sub-pads, which are close to the plurality of first sub-pads, onto the substrate forms an acute angle with the first direction.

6. The array substrate according to claim 5, wherein, In a row of first pads, along the first direction away from the plurality of first sub-pads, the plurality of second sub-pads are arranged in the second direction in a trend of gradually moving away from the display area.

7. The array substrate according to claim 5, wherein, In a row of first pads, along the first direction away from the plurality of first sub-pads, the plurality of second sub-pads are arranged in the second direction with a tendency to gradually approach the display area.

8. The array substrate according to claim 6, wherein, The plurality of second sub-pads include a first sub-pad group and a second sub-pad group, wherein along the first direction, the second sub-pad group is located on the side of the first sub-pad group away from the plurality of first sub-pads; In a row of first pads, along the first direction away from the plurality of first sub-pads, the plurality of second sub-pads belonging to the first sub-pad group are arranged in the second direction in a trend of gradually moving away from the display area; as well as In a row of the first pad, multiple second sub-pads belonging to the second sub-pad group are arranged at intervals along the first direction.

9. The array substrate according to claim 6, wherein, The plurality of second sub-pads include a first sub-pad group and a second sub-pad group, wherein along the first direction, the second sub-pad group is located on the side of the first sub-pad group away from the plurality of first sub-pads; In a row of first pads, along the first direction away from the plurality of first sub-pads, the plurality of second sub-pads belonging to the first sub-pad group are arranged in the second direction in a trend of gradually moving away from the display area; as well as In a row of first pads, along the first direction away from the plurality of first sub-pads, the plurality of second sub-pads belonging to the first sub-pad group are arranged in the second direction with a trend of gradually approaching the display area.

10. The array substrate according to claim 6 or 8, wherein, One end of the fan-out trace is electrically connected to the side of the first pad near the display area, and the other end extends to be electrically connected to the signal line; and A portion of the fan-out trace electrically connected to the second sub-pad is further away from the display area than the first sub-pad that is closest to the display area.

11. The array substrate according to claim 8, wherein, The plurality of first sub-pads are in the form of strips extending along the second direction, and the plurality of second sub-pads in the first sub-pad group are in the form of strips extending along the second direction; In the second sub-pad group, the second sub-pads on the side away from the first sub-pads along the first direction are inclined pads, and the inclined pads are strips extending along a third direction, with the angle between the third direction and the first direction being an acute angle. as well as Along the first direction, a portion of the fan-out trace electrically connected to the tilted pad is located on the side of the plurality of first pads away from the central axis.

12. The array substrate according to claim 11, wherein, In at least two adjacent tilted pads along the second direction, a portion of the fan-out trace electrically connected to one of the tilted pads is located between the two tilted pads and extends to the side of the plurality of first pads away from the central axis.

13. The array substrate according to claim 11 or 12, wherein, The width of the fan-out trace electrically connected to the tilted pad is greater than the width of the fan-out trace electrically connected to the first sub-pad.

14. The array substrate according to claim 7, wherein, The multiple fan-out traces include multiple first fan-out traces and multiple second fan-out traces. Multiple first sub-pads are electrically connected to multiple signal lines through multiple first fan-out traces, and multiple second sub-pads are electrically connected to multiple signal lines through multiple second fan-out traces. One end of the first fan-out trace is electrically connected to the end of the first sub-pad near the display area, and the other end extends to be electrically connected to the signal line; one end of the second fan-out trace is electrically connected to the end of the second sub-pad away from the display area, and the other end extends to be electrically connected to the signal line; and A portion of the second fan-out trace is located on the side of the plurality of second sub-pads away from the display area and on the side of the plurality of first sub-pads along the first direction.

15. The array substrate according to claim 14, wherein, A portion of the gate signal lead is located on the side of the second fan-out trace away from the second sub-pad.

16. The array substrate according to any one of claims 11-12 and 14-15, wherein, The gate signal lead is located on a portion of the second sub-pads on the side away from the display area, and is a straight trace extending along the first direction.

17. The array substrate according to claim 6, wherein, The multiple fan-out routing lines include multiple third fan-out routing lines and multiple fourth fan-out routing lines; In at least a portion of the second sub-pad, the end of the second sub-pad away from the display area is electrically connected to the signal line via the fourth fan-out trace; In the remaining first pads, the end of the first pad closest to the display area is electrically connected to the signal line via the third fan-out trace; and A portion of the multiple fourth fan-out traces is located on the side of multiple second sub-pads away from the display area.

18. The array substrate according to claim 8, wherein, The multiple fan-out routing lines include multiple third fan-out routing lines and multiple fourth fan-out routing lines; The ends of the multiple first sub-pads near the display area are respectively electrically connected to the multiple signal lines through the multiple third fan-out traces; In the first sub-pad group, the end of the second sub-pad near the display area is electrically connected to the signal line via the third fan-out trace; and In the second sub-pad group, the end of the second sub-pad away from the display area is electrically connected to the signal line through the fourth fan-out trace.

19. The array substrate according to claim 9, wherein, The multiple fan-out routing lines include multiple third fan-out routing lines and multiple fourth fan-out routing lines; The ends of the multiple first sub-pads near the display area are respectively electrically connected to the multiple signal lines through the multiple third fan-out traces; In the first sub-pad group, the end of the second sub-pad near the display area is electrically connected to the signal line via the third fan-out trace; and In the second sub-pad group, the end of the second sub-pad away from the display area is electrically connected to the signal line through the fourth fan-out trace.

20. The array substrate according to claim 19, wherein, The third fan-out trace includes a first trace segment and a second trace segment. One end of the first trace segment is electrically connected to the end of the first pad near the display area and extends along the second direction toward the side near the display area. One end of the second trace segment is electrically connected to the end of the first trace segment near the display area, and the other end extends along the fourth direction toward the side away from the central axis and near the display area. The acute angle between the fourth direction and the first direction is the first angle. In the second sub-pad group, the acute angle between the line connecting the geometric center of the orthographic projection of one second sub-pad on the substrate and the geometric center of the orthographic projection of the other second sub-pad on the substrate and the first direction is the second angle, and the second angle is less than or equal to the first angle.

21. The array substrate according to claim 20, wherein, The second included angle is greater than 0 degrees and less than or equal to 45 degrees.

22. The array substrate according to any one of claims 6-9, 11-12, and 17-21, wherein, The acute angle between the line connecting the geometric center of the orthographic projection of one second sub-pad on the substrate and the geometric center of the orthographic projection of the other second sub-pad on the substrate and the first direction is a third angle, wherein the third angle is greater than 0 degrees and less than or equal to 45 degrees.

23. The array substrate according to any one of claims 17-21, wherein, A portion of the gate signal lead is located on the side of the fourth fan-out trace away from the second sub-pad.

24. The array substrate according to claim 23, wherein, Along the first direction, a portion of the gate signal lead is located on the side of the fourth fan-out trace closer to the peripheral region.

25. The array substrate according to claim 23, wherein, Along the first direction, a portion of the gate signal lead is located on the side of the plurality of third pads away from the central axis.

26. The array substrate according to claim 25, wherein, The third pad located on one side of the first direction that is furthest from the central axis is closer to the central axis than the first pad located on the same side of the first direction that is furthest from the central axis. as well as The gate signal lead extends from the side of the plurality of third pads near the display area around the edge of the plurality of third pads to the side of the plurality of third pads away from the central axis.

27. The array substrate according to claim 26, wherein, The gate signal lead includes a first gate signal lead segment, a second gate signal lead segment, a third gate signal lead segment, and a fourth gate signal lead segment; One end of the first gate signal lead segment is electrically connected to the third sub-pad, and the other end extends in a direction away from the central axis and close to the plurality of third pads; One end of the second gate signal lead segment is electrically connected to the end of the first gate signal lead segment away from the third sub-pad, and the other end extends along the first direction toward the side away from the central axis; One end of the third gate signal lead segment is electrically connected to the end of the second gate signal lead segment away from the first gate signal lead segment, and the other end extends in a direction away from the plurality of first pads and away from the central axis; and One end of the fourth gate signal lead segment is electrically connected to the end of the third gate signal lead segment away from the second gate signal lead segment, and the other end extends along the first direction toward the side away from the central axis. The fourth gate signal lead segment is located on one side of the plurality of third pads along the first direction.

28. The array substrate according to claim 27, wherein, The fourth fan-out trace includes a first portion located away from the display area from a plurality of second sub-pads; as well as Along the first direction, the first portion is located on the side of the third gate signal lead segment away from the central axis, and / or, the first portion is located on the side of the fourth gate signal lead segment closer to the display area.

29. The array substrate according to claim 28, wherein, The fourth outgoing cable includes the third cable segment, the fourth cable segment, and the fifth cable segment; One end of the third trace segment is electrically connected to the end of the second sub-pad away from the display area and extends along the second direction toward the side away from the display area; One end of the fourth trace segment is electrically connected to the end of the third trace segment away from the second sub-pad, and the other end extends in a direction away from the second sub-pad and away from the central axis. The fourth trace segment is located on one side of the third gate signal lead segment along the first direction; and One end of the fifth trace is electrically connected to the end of the fourth trace away from the third trace, and the other end extends along the first direction toward the side away from the central axis. The fifth trace is located on the side of the fourth gate signal lead segment closer to the display area.

30. The array substrate according to any one of claims 2-9, 11-12, 14-15, 17-21, and 24-29, wherein, The array substrate further includes a common electrode and a common voltage lead. The common electrode is located in the display area, and at least a portion of the common voltage lead is located in the peripheral area. The common voltage lead is electrically connected to the common electrode. The fan-out routing includes a first fan-out section and a second fan-out section, the first fan-out section and the second fan-out section being arranged at intervals along the first direction; and The common voltage lead includes a first common voltage lead, a second common voltage lead, and a third common voltage lead arranged sequentially along the first direction. At least a portion of the first common voltage lead is located on the side of the first fan-out portion away from the second fan-out portion. At least a portion of the third common voltage lead is located on the side of the second fan-out portion away from the first fan-out portion. At least a portion of the second common voltage lead is located between the first fan-out portion and the second fan-out portion.

31. The array substrate according to claim 30, wherein, The plurality of bonding pads further include a plurality of third pads, the plurality of third pads being located on the side of the plurality of second pads away from the plurality of first pads; The plurality of second pads further include a plurality of fourth sub-pads, which are located on the side of the plurality of third sub-pads near the central axis along the first direction. The plurality of fourth sub-pads are electrically connected to the plurality of third pads via a plurality of bonding connection lines. The second common voltage lead includes a fourth portion located between the first fan-out portion and the second fan-out portion. One end of the fourth portion is electrically connected to the common electrode, and the other end extends along the second direction to the side of the plurality of first pads away from the display area. The size of the fourth portion along the first direction is greater than or equal to the size of the first pads along the first direction.

32. The array substrate according to claim 31, wherein, The plurality of first pads include a plurality of first virtual pads, the plurality of first virtual pads being located between the fourth portion and the first fan-out portion, and the plurality of first virtual pads being located between the fourth portion and the second fan-out portion.

33. The array substrate according to claim 31 or 32, wherein, One end of the first common voltage lead is electrically connected to at least one of the third pads, and the other end extends between the plurality of first pads and the plurality of second pads and extends around the first fan-out portion to be electrically connected to the common electrode; and / or, one end of the third common voltage lead is electrically connected to at least one of the third pads, and the other end extends between the plurality of first pads and the plurality of second pads and extends around the second fan-out portion to be electrically connected to the common electrode.

34. The array substrate according to claim 33, wherein, The first common voltage lead includes a second portion located between adjacent second pads along the first direction, the second portion having a dimension along the first direction greater than or equal to the dimension of the second pads along the first direction; And / or, The third common voltage lead includes a third portion located between adjacent second pads along the first direction, the third portion having a dimension along the first direction greater than or equal to the dimension of the second pads along the first direction.

35. The array substrate according to claim 33, wherein, The end of the second common voltage lead away from the display area is electrically connected to at least one of the third pads.

36. The array substrate according to claim 35, wherein, The second common voltage lead has a shielded trace segment provided on at least one side along the first direction, and the shielded trace segment is spaced apart from the second common voltage lead; and One end of the shielded trace is located between the second common voltage lead and the third pad, and the other end of the shielded trace is located between the second common voltage lead and the second pad.

37. The array substrate according to claim 36, wherein, The second common voltage lead includes a fifth portion located between adjacent second pads along the first direction, the fifth portion having a dimension along the first direction greater than or equal to the dimension of the second pads along the first direction; and / or, The shielded trace segment includes a sixth portion located between adjacent second pads along the first direction, the size of the sixth portion along the first direction being greater than or equal to the size of the second pads along the first direction.

38. The array substrate according to claim 37, wherein, The second common voltage lead includes a seventh portion located between a plurality of first pads and a plurality of second pads, the seventh portion extending along the first direction, one end of the seventh portion being electrically connected to the fourth portion, and the other end of the seventh portion being electrically connected to the fifth portion.

39. The array substrate according to claim 38, wherein, Along the second direction, the distance between the seventh portion and the row of second pads closest to the display area is equal to the distance between the seventh portion and the row of first pads furthest from the display area.

40. The array substrate according to claim 33, wherein, The second common voltage lead further includes an eighth portion located between a plurality of first pads and a plurality of second pads, the eighth portion extending along the first direction, one end of the eighth portion being electrically connected to the first common voltage lead, and / or, one end of the eighth portion being electrically connected to the third common voltage lead; as well as The fourth part extends away from the display area and is electrically connected to the eighth part.

41. A display substrate, wherein, The display substrate includes an array substrate according to any one of claims 1-40.

42. A display device, wherein, The display substrate includes the display substrate according to claim 41.

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