Display device

Abstract

The application provides a display device. The display device comprises a display panel, a data driving module, and a timing control module, wherein the display panel comprises scan lines, data lines, and sub-pixels, and a connection node is arranged between a driving unit and a liquid crystal unit in the sub-pixel. The display panel further comprises a collection driving line, and at least part of the sub-pixels further comprises a switching unit. The control end of the switching unit is electrically connected to the collection driving line, the first end is electrically connected to the connection node, and the second end is electrically connected to the data driving module. When the control end receives a collection signal, the pixel voltage of the connection node is transmitted to the data driving module. The data driving module is used for transmitting the pixel voltage to the timing control module after preprocessing the pixel voltage. The timing control module is used for adjusting the next frame data signal according to the preprocessed pixel voltage, so that the pixel voltage reaches a preset target value. The display device can effectively improve the color deviation problem of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the display technical field, in particular to a display device. BACKGROUND

[0002] With the development of the display technical field, the display device is applied more and more widely, and the requirement for the display device is higher and higher. Among them, the liquid crystal display device (LCD) has the characteristics of small volume, low power consumption, no radiation, relatively low manufacturing cost, etc., and occupies the dominant position in the display field market.

[0003] Generally, in the liquid crystal display device, the display panel includes a scan line, a data line and a sub-pixel, the sub-pixel includes a driving unit and a liquid crystal unit; when the driving unit is turned on, the liquid crystal unit is charged within the turn-on time. Due to the impedance of the data line itself and the coupling capacitance with other wires, it is easy to cause the delay of charging, that is, the so-called RC charging delay.

[0004] However, in order to achieve high-end visual effect, the effective charging time of the liquid crystal unit is getting shorter and shorter, and the difference between the pixel voltage received by the liquid crystal unit close to the data driving module on the panel and the pixel voltage received by the liquid crystal unit far away from the data driving module is getting larger and larger, resulting in the difference in display color or gray scale at different positions of the panel, causing color deviation problem. SUMMARY

[0005] The present application provides a display device, aiming at solving the problem of color deviation at different positions of the display panel caused by RC charging delay of the data line in the prior art.

[0006] In order to solve the above technical problem, one of the technical solutions provided by the present application is to provide a display device. The display device comprises:

[0007] A display panel, comprising a scan line, a data line and a sub-pixel; the sub-pixel comprises a driving unit and a liquid crystal unit, and the driving unit and the liquid crystal unit have a connection node therebetween;

[0008] A data driving module, electrically connected to the data line;

[0009] A timing control module, configured to provide a data signal to the data driving module;

[0010] Among them, the display panel further comprises a collection driving line, and at least part of the sub-pixels further comprises a switching unit; the control end of the switching unit is electrically connected to the collection driving line, the first end is electrically connected to the connection node, and the second end is electrically connected to the data driving module;

[0011] The control end transmits the pixel voltage of the connection node to the data driving module when receiving the collection signal; the data driving module is used for transmitting the pixel voltage after preprocessing; the timing control module is used for adjusting the data signal of the next frame according to the pixel voltage after preprocessing, so that the pixel voltage reaches the preset target value.

[0012] The display panel further comprises a collection line, and the second end of the switch unit is electrically connected to the data driving module through the collection line.

[0013] The data driving module comprises an analog-to-digital conversion unit, which is used for converting the pixel voltage into a digital voltage to complete the preprocessing of the pixel voltage.

[0014] The timing control module is used for calculating the ratio of the data signal to the data signal to obtain a compensation parameter, and multiplying the data signal by the compensation parameter as the adjusted data signal of the next frame to adjust the data signal of the next frame.

[0015] The display panel comprises a display area, and the sub-pixels are arranged in an array manner in the display area.

[0016] The display area is divided into a plurality of compensation areas, each compensation area comprising at least two sub-pixels, one of which is used as a collection point; the timing control module obtains a compensation parameter according to the pixel voltage of the collection point after preprocessing, and all the sub-pixels in the compensation area share the compensation parameter.

[0017] The sub-pixels between adjacent compensation areas are target sub-pixels, and the timing control module is further used for calculating a weighted average value of the compensation parameters of adjacent collection points according to the distance between the target sub-pixel and the adjacent collection points, to be used as the compensation parameter of the target sub-pixel.

[0018] The connection node is connected to the corresponding data line to be electrically connected to the data driving module through the data line.

[0019] The data driving module comprises a multiplexing switch, an analog-to-digital conversion unit and an output buffer unit; the multiplexing switch comprises an access end, a data signal end and a signal conversion end, the data line is electrically connected to the access end, the data signal end is electrically connected to the output buffer unit, and the signal conversion end is electrically connected to the analog-to-digital conversion unit.

[0020] In the display stage, the multiplexing switch is used to connect the access end and the data signal end, so that the output buffer unit transmits data signal to the data line; in the collection stage, the multiplexing switch is used to connect the access end and the signal conversion end, so that the pixel voltage of the connection node is transmitted to the analog-digital conversion unit through the data line, and the analog-digital conversion unit is used to convert the pixel voltage into digital voltage, so as to complete the preprocessing of the pixel voltage.

[0021] The data driving module comprises a comparator and a data buffer, the comparator comprises a first input end, a second input end and an output end, the data line is electrically connected with the first input end through the data buffer, the connection node is electrically connected with the second input end, and the output end is electrically connected with the timing control module.

[0022] In the collection stage, the pixel voltage of the connection node is transmitted to the second input end, the data signal of the current frame stored by the data buffer is transmitted to the first input end, the comparator is used to compare the data signal and the pixel voltage, so as to complete the preprocessing of the pixel voltage, and the comparison result is transmitted to the timing control module.

[0023] The timing control module is used to adjust the data signal of the next frame according to the comparison result, so that the pixel voltage reaches the preset target value.

[0024] The display panel further comprises a collection control module, the collection control module is electrically connected with the collection driving line, and is used to provide a collection signal to control the switch unit to be turned on in the collection stage; the collection stage is arranged in the black-out area of each frame signal.

[0025] After the display panel is turned on, a plurality of compensation stages arranged in time sequence are arranged; in each compensation stage, the timing control module adjusts the data signal of the same sub-pixel by using the same compensation parameter.

[0026] The beneficial effects of the present application: different from the prior art, the present application provides a display device, the display device includes a display panel, a data driving module and a timing control module. Among them, the display panel includes a scan line, a data line and a sub-pixel; the sub-pixel includes a driving unit and a liquid crystal unit, the driving unit is used to drive the liquid crystal unit, and the driving unit and the liquid crystal unit have a connection node. The present application is by making at least part of the sub-pixel further includes a switching unit, and the control end of the switching unit is electrically connected to the acquisition driving line, the first end is electrically connected to the connection node, and the second end is electrically connected to the data driving module, so that when the control end of the switching unit receives the acquisition signal transmitted by the acquisition driving line, the switching unit is opened, the pixel voltage of the connection node is transmitted to the data driving module, so as to complete the acquisition of the pixel voltage of the sub-pixel on the display panel. And by making the data driving module pre-processes the acquired pixel voltage, and transmitting the pre-processed pixel voltage to the timing control module, so as to complete the pre-processing of the acquired pixel voltage by the data driving module, and obtain the pre-processing result required by the timing control module; the timing control module obtains the adjustment parameter according to the pre-processing result, so as to adjust the data signal of the next frame, so that the pixel voltage reaching the connection node reaches the preset target value, thereby reversely compensating the pressure difference between the actual received pixel voltage of the sub-pixel and the original data signal, so as to improve the color deviation phenomenon, thereby overcoming the different RC impedance of the sub-pixel caused by the different data line lengths of the sub-pixel at different pixel positions, and solving the color deviation problem between the near-end sub-pixel and the far-end sub-pixel. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative labor.

[0028] Figure 1 is the overall structure schematic diagram of the display device provided by an embodiment of the present application;

[0029] Figure 2 is the structure schematic diagram of the display device provided by the first embodiment of the present application;

[0030] Figure 3 is Figure 2 is the structure schematic diagram of the data driving module and the timing control module provided in the embodiment;

[0031] Figure 4 is the timing control waveform diagram of the display panel provided by an embodiment of the present application;

[0032] Figure 5 is the structure schematic diagram of the display panel provided by the second embodiment of the present application;

[0033] Figure 6 is a structural schematic diagram of a display device provided by a third embodiment of the present application;

[0034] Figure 7 is Figure 6 is a structural schematic diagram of a data driving module and a timing control module provided in the embodiment;

[0035] Figure 8 is a structural schematic diagram of a data driving module and a timing control module provided by a fourth embodiment of the present application;

[0036] Figure 9 is a structural schematic diagram of a data driving module and a timing control module provided by a fifth embodiment of the present application.

[0037] Reference signs:

[0038] 100 - display device; 10 - display panel; 101 - compensation area; 11 - sub-pixel; 111 - liquid crystal cell; 210 - control terminal; 121 - first terminal; 122 - second terminal; 20 - data driving module; 21 - output buffer unit; 211 - data buffer; 22 - digital-to-analog conversion unit; 23 - data latch; 24 - shift register; 25 - logic processor; 26 - receiving unit; 27 - analog-to-digital conversion unit; 28 - multiplexing switch; 281 - access terminal; 282 - data signal terminal; 283 - signal conversion terminal; 284 - signal control terminal; 29 - comparator; 291 - first input terminal; 292 - second input terminal; 293 - output terminal; 30 - timing control module; 40 - gate driving module; 50 - acquisition control module;

[0039] G1-Gn - scan lines; D1-Dn - data lines; E1-En - acquisition driving lines; B1-Bn - acquisition lines; Q1 - driving unit; M1 - switching unit; N1 - connection node; S - acquisition point; X - first direction; Y - second direction. DETAILED DESCRIPTION

[0040] The scheme of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0041] In the following description, specific details are set forth in order to provide a thorough understanding of the present application. The present application may, however, be practiced without these details. In other instances, well-known methods, structures and techniques have not been described in detail in order to avoid obscuring the present application.

[0042] With reference to the drawings and embodiments, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0043] The terms "first", "second", "third" in the present application are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0044] In this document, reference to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. Those skilled in the art will appreciate that embodiments described herein can be combined with other embodiments.

[0045] The present application will be described in detail below with reference to the drawings and embodiments.

[0046] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of the overall structure of a display device provided by an embodiment of the present application, Figure 2 is a schematic diagram of the structure of a display device provided by a first embodiment of the present application. In the present embodiment, a display device 100 is provided, which includes a display panel 10, a gate drive module 40, a data drive module 20 and a timing control module 30.

[0047] The display panel 10 includes a plurality of scan lines G1-Gn, a plurality of data lines D1-Dn and a plurality of sub-pixels 11. The plurality of scan lines G1-Gn extend along a first direction X and are arranged at intervals along a second direction Y, and are used to transmit a scan signal to the sub-pixels 11; the plurality of data lines D1-Dn extend along the second direction Y and are arranged at intervals along the first direction X, form a grid with the scan lines G1-Gn, and define the area of the sub-pixels 11, one sub-pixel 11 is arranged in each grid area, and the data lines D1-Dn are used to transmit a data signal to the sub-pixels 11; wherein the first direction X is perpendicular to the second direction Y, and in this embodiment, the row direction of the sub-pixel 11 matrix is defined as the first direction X, and the column direction of the sub-pixel 11 matrix is defined as the second direction Y.

[0048] Each sub-pixel 11 includes a driving unit Q1 and a liquid crystal unit 111, the driving unit Q1 includes a driving transistor, the gate of the driving transistor is electrically connected to the corresponding scan line G1-Gn, the source is electrically connected to the data line D1-Dn, and the drain is electrically connected to the liquid crystal unit 111, specifically to the pixel electrode of the liquid crystal unit 111. The liquid crystal unit 111 includes a pixel electrode, a liquid crystal layer common electrode and a color filter layer, wherein the pixel electrode, the liquid crystal layer and the common electrode form a liquid crystal capacitor, which is used to drive the liquid crystal molecules in the liquid crystal layer to deflect to control the amount of light transmission, and the color filter layer is used to filter light into corresponding color light. Wherein, the driving unit Q1 and the liquid crystal unit 111 have a connection node N1.

[0049] The display panel 10 further includes a plurality of acquisition driving lines E1-En, the plurality of driving lines extend along the first direction X and are arranged at intervals along the second direction Y, and are used to transmit an acquisition signal, and at least part of the sub-pixels 11 further include a switching unit M1, the control end 210 of the switching unit M1 is electrically connected to the acquisition driving lines E1-En, the first end 121 is electrically connected to the connection node N1, and the second end 122 is electrically connected to the data driving module 20, so that the acquisition signal is transmitted through the acquisition driving lines E1-En to control the switching unit M1 to be turned on, thereby realizing the acquisition of the pixel voltage at the connection node N1 of the sub-pixel 11.

[0050] Specifically, the display panel 10 further includes an acquisition control module 50, the acquisition control module 50 is electrically connected to the acquisition driving lines E1-En, and is used to provide an acquisition signal to control the switching unit M1 to be turned on in the acquisition stage; the input end of the acquisition control module 50 is electrically connected to the timing control module 30, so that the timing control module 30 transmits corresponding timing signals to the acquisition control module 50, the acquisition control module 50 processes the received timing signals to form an acquisition signal and transmits it to the acquisition driving lines E1-En, so as to control the switching unit M1 to be turned on in the acquisition stage, thereby acquiring the pixel voltage at the connection node N1 in the sub-pixel 11.

[0051] In the first embodiment, the display panel 10 further comprises a plurality of collection lines B1-Bn extending along the second direction Y and arranged at intervals along the first direction X, the second end 122 of the switch unit M1 in the sub-pixel 11 is electrically connected to the corresponding collection line B1-Bn, and the other end of the collection line B1-Bn is electrically connected to the data driving module 20, so that the second end 122 of the switch unit M1 in the sub-pixel 11 is electrically connected to the data driving module 20 through the collection line B1-Bn, and when the switch unit M1 is turned on, the pixel voltage at the connection node N1 can be transmitted to the data driving module 20 through the collection line B1-Bn, so as to realize the collection of the pixel voltage.

[0052] In the first embodiment, one switch unit M1 is arranged in each sub-pixel 11, so as to realize the collection of the pixel voltage of each sub-pixel 11. Specifically, the switch unit M1 comprises a switch transistor, the gate electrode of the switch transistor is electrically connected to the corresponding collection driving line E1-En, the source electrode is electrically connected to the connection node N1, and the drain electrode is electrically connected to the data driving module 20 through the collection line B1-Bn, so as to realize the collection of the pixel voltage of each sub-pixel 11.

[0053] Specifically, when the control end 210 receives the collection signal, the pixel voltage of the connection node N1 is transmitted to the data driving module 20; the data driving module 20 is used for transmitting the pixel voltage to the timing control module 30 after preprocessing, and the timing control module 30 is used for adjusting the next frame data signal according to the preprocessed pixel voltage, so as to make the pixel voltage reach the preset target value.

[0054] It can be understood that in specific embodiments, by providing the collection signal to the control end 210 of the switch unit M1, the switch unit M1 is turned on after receiving the collection signal, so that the pixel voltage at the connection node N1 is transmitted to the data driving module 20, so as to realize the collection of the pixel voltage. After the data driving module 20 receives the collected pixel voltage, the collected pixel voltage is preprocessed, and the preprocessing result is transmitted to the timing control module 30, and the timing control module 30 adjusts the data signal to be transmitted to the sub-pixel 11 according to the preprocessing result, so as to make the pixel voltage actually received by the connection node N1 of the sub-pixel 11 reach the preset target value, i.e. reach the voltage value of the original data signal, so as to realize the accurate compensation of the pixel voltage of the sub-pixel 11, improve the color deviation phenomenon, and make the display panel 10 overcome the color deviation problem between the near-end sub-pixel 11 and the far-end sub-pixel 11 caused by the different RC impedances of the sub-pixels 11 due to the different lengths of the data lines D1-Dn, i.e. overcome the color deviation problem caused by the length difference of the data lines D1-Dn.

[0055] Please refer to Figure 3 , Figure 3 isFigure 2 The structural diagram of the data driving module and the timing control module provided in the embodiment is shown. In the embodiment, the data processing module comprises a receiving unit 26, a logic processor 25, a shift register 24, a data latch 23, a digital-analog conversion unit 22 and an output buffer unit 21. The receiving unit 26 is configured to receive the timing signal transmitted by the timing control module 30 and transmit the timing signal to the logic processor 25 and the data latch 23. The logic processor 25 is configured to perform corresponding logical operation processing on the timing signal and transmit the processed signal to the shift register 24. The shift register 24 is configured to transmit the signal to the data latch 23. The data latch 23 is configured to transmit the signal to the digital-analog conversion unit 22 for analog-digital conversion processing, so as to convert the signal into a digital signal and then transmit the digital signal to the output buffer unit 21 for buffering. The output buffer unit 21 is configured to transmit the corresponding data signal to the corresponding sub-pixel 11 through the data lines D1-Dn.

[0056] Specifically, the data driving module 20 further comprises a plurality of analog-digital conversion units 27 configured to convert the collected pixel voltage into a digital voltage, so as to complete the preprocessing of the pixel voltage. In the embodiment, the collection lines B1-Bn are electrically connected to the input end of the analog-digital conversion unit 27. The output port of the analog-digital conversion unit 27 is electrically connected to the logic processor 25. The logic processor 25 is configured to transmit the preprocessed pixel voltage to the timing control module 30. The timing control module 30 is configured to calculate the ratio of the data signal and the digital voltage, so as to obtain the compensation parameter. The timing control module 30 is further configured to multiply the next frame data signal by the compensation parameter, and take the product as the adjusted next frame data signal, so as to adjust the next frame data signal.

[0057] Please refer to Figure 4 , Figure 4 is the timing control waveform diagram of the display panel provided in an embodiment of the present application. In combination with Figure 2 , in the effective display area in each frame, the scan lines G1-Gn transmit the scan signal in sequence, so that the driving transistor of the driving unit Q1 is turned on row by row, and the data lines D1-Dn transmit the data signal to the sub-pixel 11 row by row, so as to realize the image display function of the display panel 10. In the non-display area of each frame, the collection driving lines E1-En transmit the collection signal in sequence, so that the switching transistor of the switching unit M1 is turned on row by row, so that the pixel voltage at the connection node N1 of each sub-pixel 11 is transmitted to the data driving module 20 through the collection lines B1-Bn, so as to complete the collection of the pixel voltage of the sub-pixel 11 in the frame signal. Further, the data driving module 20 and the timing control module 30 calculate the compensation parameter of the sub-pixel 11 according to the collected pixel voltage and the voltage of the data signal of the frame signal, and adjust the next frame data signal according to the compensation parameter, so that the pixel voltage received at the connection node N1 reaches the preset target value, thereby improving the color cast phenomenon. Figure 4In the embodiment, only the time sequence waveforms of the scan lines G1-G3, the data line D1, the collection driving lines E1-E3 and the collection line B1 are shown to explain the time sequence of the pixel voltage collection. In the embodiment, the waveforms of the other scan lines G4-Gn, the data lines D2-Dn, the collection driving lines and the collection lines B2-Bn are similar to those shown in the figure, and will not be described herein.

[0058] In the embodiment, the collection stage is arranged in the black-out area of each frame signal, so that the pixel voltage is collected without affecting the image display of the display panel 10 and the refresh rate of the display panel 10, and the refresh rate is not reduced due to the addition of the collection stage.

[0059] Please refer to Figure 5 , Figure 5 is a structural schematic diagram of a display panel provided by the second embodiment. In the embodiment, the display panel 10 includes a display area, and the sub-pixels 11 are arranged in the display area in an array manner. The display area is divided into a plurality of compensation areas 101, each of which includes at least two sub-pixels 11, one of which is a collection point S. The time sequence control module 30 obtains a compensation parameter according to the pixel voltage of the collection point S after preprocessing, and all the sub-pixels 11 in the compensation area 101 share the compensation parameter.

[0060] It should be noted that, in each frame signal, the time length of the black-out area is shorter than that of the effective display area, and a long time is required for collection of each row. In order to ensure that the pixel voltage of each sub-pixel 11 on the display panel 10 is completely collected, the display area is divided into a plurality of compensation areas 101 in the embodiment, and the pixel voltage of only one sub-pixel 11 is collected in each compensation area 101.

[0061] Specifically, one row of sub-pixels 11 can be collected every several rows in the column direction, and one column of sub-pixels 11 can be collected every several columns in the row direction. Then, the compensation parameter of each collection point S is obtained by the data driving module 20 and the time sequence control module 30, all the sub-pixels 11 in the same compensation area 101 as the collection point S share the compensation parameter of the collection point S, and the time sequence control module 30 performs compensation processing on the sub-pixels 11 in the same compensation area 101 with the same compensation parameter.

[0062] Such a configuration not only reduces the collection time, but also can not set the switch unit M1 in the sub-pixels 11 that are not collection points S, effectively reduces the number of switch transistors, reduces the production cost, and also reduces the number of analog-to-digital conversion units 27 in the data driving module 20, further reducing the production cost. Furthermore, the reduction of the collection points S also reduces the number of preprocessing of the data voltage collected by the data driving module 20 and the calculation amount of the compensation parameter by the time sequence control module 30, improves the operation rate, and reduces the delay of compensation.

[0063] Specifically, in each compensation region 101, the sub-pixel 11 located at the center of the compensation region 101 can be used as the sampling point S, and the compensation parameter of the sampling point S can be used as the compensation parameter for the entire compensation region 101. All sub-pixels 11 in the compensation region 101 share this compensation parameter. By using the sub-pixel 11 at the center of the compensation region 101 as the sampling point S and the compensation parameter of the sampling point S as the compensation parameter for the compensation region 101, the compensation parameter becomes more representative, thereby making the compensation effect on the pixel voltage of each sub-pixel 11 in the compensation region 101 more balanced.

[0064] Furthermore, in this embodiment, in order to ensure the pixel voltage compensation effect of sub-pixel 11, the area of ​​compensation region 101 can be reduced. The compensation parameters of sub-pixels 11 between adjacent compensation regions 101 are obtained by using the centroid algorithm based on the compensation parameters of the surrounding adjacent compensation regions 101.

[0065] Specifically, the sub-pixels 11 between adjacent compensation areas 101 are designated as target sub-pixels 11. The timing control module 30 is also used to calculate the weighted average of the compensation parameters of adjacent acquisition points S based on the distance between the target sub-pixel 11 and the adjacent acquisition points S, so as to use the compensation parameters of the target sub-pixel 11.

[0066] For example, if the compensation parameter for compensation area A is K1, the compensation parameter for compensation area B is K2, the distance between the target sub-pixel 11 and the acquisition point S in compensation area A is two rows, and the distance between the target sub-pixel 11 and the acquisition point S in compensation area B is four rows, then the compensation coefficient for the target sub-pixel 11 is: K = (4*K1 + 2*K2) / 6. This can be understood as follows: the acquisition points S of the adjacent compensation areas 101 surrounding the target sub-pixel 11 form a region, with the target sub-pixel 11 as the centroid of this region. Then, using the centroid algorithm, the weighted average of the compensation coefficients of the surrounding acquisition points S is calculated, with the distance between the target sub-pixel 11 and the surrounding acquisition points S as the weight. This weighted average is then used as the compensation parameter for the target sub-pixel 11.

[0067] For example, such as Figure 5 As shown, the compensation parameter for compensation zone A1 is K1, the compensation parameter for compensation zone A2 is K2, the compensation parameter for compensation zone A3 is K3, and the compensation parameter for compensation zone A4 is K4. Each of the compensation zones A1 to A4 has a sampling point S.

[0068] Among them, the target sub-pixel P is adjacent to the compensation areas A1 and A2. The distance between the target sub-pixel P and the sampling point S of the compensation area A1 is 2, and the distance between the target sub-pixel P and the sampling point S of the compensation area A2 is 1. Using the centroid algorithm, the compensation parameter of the target sub-pixel P is: Kp=(1*K1+2*K2) / 3.

[0069] In this context, target sub-pixel Q is adjacent to compensation areas A1 to A4, and target sub-pixel P is separated from the acquisition point S of compensation area A1 by two rows and two columns. The distance between P and acquisition point S of compensation area A1 is... The target sub-pixel P is located two rows and one column away from the acquisition point S in the compensation area A2, and the distance between it and the acquisition point S in the compensation area A2 is... The target sub-pixel P is located one row and two columns away from the acquisition point S in the compensation area A3, and the distance between it and the acquisition point S in the compensation area A3 is... The target sub-pixel P is separated from the acquisition point S of the compensation area A4 by one row and one column, and the distance between it and the acquisition point S of the compensation area A4 is... Using the centroid algorithm, the compensation parameters for the target sub-pixel P are:

[0070]

[0071] Please see Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the structure of the display device provided in the third embodiment of this application. Figure 7 yes Figure 6 The schematic diagram of the data driving module and timing control module provided in this embodiment is shown. In this embodiment, the connection node N1 of sub-pixel 11 is connected to the corresponding data lines D1 to Dn, so as to be electrically connected to the data driving module 20 through the data lines D1 to Dn. During the pixel voltage acquisition stage, the pixel voltage at the connection node N1 of sub-pixel 11 is transmitted to the data driving module 20 through the data lines D1 to Dn. During the display stage, the data lines D1 to Dn transmit data signals to sub-pixel 11 to realize image display. In this embodiment, by multiplexing the data lines D1 to Dn as acquisition lines B1 to Bn, it is not necessary to set additional acquisition lines B1 to Bn on both sides of sub-pixel 11, which can ensure the aperture ratio of sub-pixel 11 and avoid the decrease in the aperture ratio of sub-pixel 11; at the same time, it can also avoid the parasitic capacitance generated between the data lines D1 to Dn and the acquisition lines B1 to Bn, which would cause serious RC delay in the waveform of the acquired pixel voltage, resulting in deviation in the pixel voltage acquisition result and insufficient compensation accuracy.

[0072] In this embodiment, as Figure 7 As shown, the data driving module 20 also includes a multiplexer 28, which includes an access terminal 281, a data signal terminal 282, and a signal conversion terminal 283. Data lines D1 to Dn are electrically connected to the access terminal 281, the data signal terminal 282 is electrically connected to the output buffer unit 21, and the signal conversion terminal 283 is electrically connected to the analog-to-digital conversion unit 27.

[0073] Specifically, in the display stage, the multiplexing switch 28 is used to connect the access end 281 with the data signal end 282, so that the data buffer unit transmits the data signal to the data lines D1~Dn; in the collection stage, the multiplexing switch 28 is used to connect the access end 281 with the signal conversion end 283, so that the pixel voltage of the connection node N1 is transmitted to the analog-digital conversion unit 27 through the data lines D1~Dn, and the analog-digital conversion unit 27 is used to convert the pixel voltage into a digital voltage, so as to complete the preprocessing of the pixel voltage.

[0074] The multiplexing switch 28 further comprises a control signal end connected with the ABK signal, in the display stage, the ABK signal is high, so as to control the multiplexing switch 28 to connect the data lines D1~Dn with the output buffer unit 21, so that the output buffer unit 21 transmits the data signal to the data lines D1~Dn, and then transmits the data signal to the sub-pixel 11 through the data lines D1~Dn, so as to realize the image display; in the collection stage, the ABK signal is low, so as to control the multiplexing switch 28 to connect the data lines D1~Dn with the analog-digital conversion unit 27, so that the pixel voltage is transmitted to the analog-digital conversion unit 27 through the data lines D1~Dn for analog-digital conversion, so as to complete the preprocessing of the collected data.

[0075] Please refer to Figure 8 , Figure 8 is the structural schematic diagram of the data driving module and the timing control module provided in the fourth embodiment of the present application. In the present embodiment, the data driving module 20 comprises a comparator 29 and a data buffer 211, the comparator 29 comprises a first input end 291, a second input end 292 and an output end 293, the data lines D1~Dn are electrically connected with the first input end 291 through the data buffer 211, the connection node N1 is electrically connected with the second input end 292, and the output end 293 is electrically connected with the timing control module 30.

[0076] Specifically, in the collection stage, the pixel voltage of the connection node N1 is transmitted to the second input end 292, the current frame data signal stored in the data buffer 211 is transmitted to the first input end 291, the comparator 29 is used to compare the data signal with the pixel voltage, so as to complete the preprocessing of the pixel voltage, and the comparison result is transmitted to the timing control module 30 through the logic processor 25; the timing control module 30 is used to adjust the next frame data signal according to the comparison result, so that the pixel voltage reaches the preset target value.

[0077] It can be understood that, in the acquisition stage, the voltage of the sub-pixel 11 connecting node N1 is transmitted to the second input end 292 of the comparator 29, and the data buffer 211 is used to store the data signal transmitted to the data line D1-Dn by the current frame output buffer, so as to transmit the buffered data signal to the first input end 291 of the comparator 29 in the acquisition stage, so as to compare the pixel voltage with the data signal through the comparator 29. Specifically, the first input end 291 can be a positive input end, and the second input end 292 can be a negative input end. If the acquired pixel voltage is lower than the data signal, the comparison result is high level, and the timing control module 30 adjusts the next frame timing signal to be high according to the comparison result, so as to adjust the next frame data signal to be high, so that the pixel voltage is increased to the preset target value. If the acquired pixel voltage is higher than the data signal, the comparison result is low level, and the timing control module 30 adjusts the next frame timing signal to be low according to the comparison result, so as to adjust the next frame data signal to be low, so that the pixel voltage is decreased to the preset target value.

[0078] In the embodiment, the comparator 29 is arranged in the data driving module 20 to complete the preprocessing of the acquired pixel voltage. Compared with the processing through the analog-digital conversion and then returning to the timing control module 30 for further processing, the processing rate can be effectively improved, and the response rate of compensation can be improved.

[0079] Specifically, the timing control module 30 can pre-store adjustment parameters, then select the corresponding adjustment parameters according to the comparison result, adjust the next frame timing signal by using the adjustment parameters, and then transmit the next frame timing signal to the data driving module 20. The data driving module 20 processes the adjusted timing signal to form the next frame data signal, and then transmits the next frame data signal to the data line D1-Dn, so that the pixel voltage received at the connecting node N1 reaches the preset target value. In this way, the timing control module 30 does not need to calculate the compensation parameters, so that the response rate of compensation is improved, and the delay is reduced.

[0080] Please refer to Figure 9 , Figure 9 is a structural schematic diagram of the data driving module 20 and the timing control module provided in the fifth embodiment of the application. Different from the fourth embodiment, the data driving module 20 provided in the embodiment further includes a multiplexing switch 28. Similar to the third embodiment, if the data line D1-Dn is multiplexed as the acquisition line B1-Bn in the display panel 10, the data driving module 20 provided in the embodiment is matched.

[0081] Specifically, in the display stage, the ABK signal is high to control the multiplexing switch 28 to connect the data lines D1-Dn and the data buffer 211, so that the data buffer transmits the data signal to the data lines D1-Dn, and the data signal is transmitted to the sub-pixel 11 through the data lines D1-Dn to realize image display, and the data buffer 211 buffers the data signal transmitted to the data lines D1-Dn; in the collection stage, the ABK signal is low to control the multiplexing switch 28 to connect the data lines D1-Dn and the second input end 292 of the comparator 29, so that the collected pixel electrode is transmitted to the second input end 292 of the comparator 29 through the data lines D1-Dn, at this time, the data buffer 211 transmits the previously buffered data signal to the first input end 291 of the comparator 29, so that the comparator 29 compares the pixel voltage with the output data signal, and transmits the comparison result to the timing control module 30 through the logic processor 25, and then the timing control module 30 adjusts the next frame data signal accordingly, so that the pixel voltage received at the connection node N1 of the sub-pixel 11 reaches the preset target value, thereby improving the color deviation phenomenon caused by RC charging delay due to the different lengths of the data lines D1-Dn.

[0082] In other specific embodiments, the display panel 10 has a plurality of compensation stages arranged in time sequence after being turned on; in each compensation stage, the timing control module 30 adjusts the data signal of the same sub-pixel 11 using the same compensation parameter. It can be understood that, when the display panel 10 is working, it does not collect the pixel voltage and then compensate the next frame pixel voltage every frame, but in the use process of the display panel 10, a plurality of compensation stages T1-Tn are arranged in time sequence, for example, the time zone of the compensation stage T1 is (t0, t1), the time zone of the compensation stage T2 is (t1, t2), and so on, and the time zone of the compensation stage Tn is (t(n-1), tn), and the time zones of the compensation stages are continuous. The collection stage is set at the initial time of each compensation stage to collect the pixel voltage, and then the compensation parameter is calculated by processing and calculating the collected data through the data driving module 20 and the timing control module 30, and the compensation parameter is used as the compensation parameter of the compensation stage. The pixel voltage is compensated using the compensation parameter in the time zone.

[0083] In this embodiment, by using the above compensation method, the corresponding compensation parameter is not collected and processed for each frame of pixel voltage, which effectively reduces the operation and processing amount of the data driving module 20 and the timing control module 30, and the compensation is more timely, and the compensation delay is reduced.

[0084] It can be understood that, since the length of the data lines D1-Dn on the display panel 10 does not change with the use time of the display panel 10, the RC charging delay degree of the data lines D1-Dn to the sub-pixels 11 at different positions generally does not change with the use time of the panel, that is, the color cast problem caused by the RC charging delay of the data lines D1-Dn does not change with the use time of the panel. Therefore, only the corresponding compensation parameter needs to be calculated for each sub-pixel 11 at the beginning of each compensation stage, and the pixel voltage is compensated using the compensation parameter in each compensation stage to improve the above color cast problem of the display panel 10.

[0085] Specifically, a leading data frame stream can be imported each time the machine is started, and the collection of the pixel voltage and the obtaining of the compensation parameter can be completed during the display period of the leading data frame stream, and then the compensation parameter is used to compensate the pixel voltage in the subsequent display work of the display panel 10. Specifically, when collecting the data voltage, the collection stage can still be arranged in the blacking-out area of each frame, or can also be arranged after the effective display area of each frame.

[0086] Alternatively, a leading data frame stream is imported each time the machine is started, and the pixel voltage of a plurality of rows of sub-pixels 11 can be collected in a frame, and then the compensation parameter is calculated, and the pixel voltage of a plurality of rows of sub-pixels 11 after the next frame is collected, and then the compensation parameter is calculated, and so on, so as to obtain the compensation parameters corresponding to all sub-pixels 11 in a plurality of frames, so as to match the refresh rate of the leading data frame stream. For example, in the first frame, the pixel voltage of the first to twentieth rows of sub-pixels 11 is collected to obtain the compensation parameters corresponding to the first to twentieth rows of sub-pixels 11, in the second frame, the pixel voltage of the twenty-first to fortieth rows of sub-pixels 11 is collected to obtain the compensation parameters corresponding to the twenty-first to fortieth rows of sub-pixels 11, and so on, in the kth frame, the pixel voltage of the (n-19)th to nth rows of sub-pixels 11 is collected to obtain the compensation parameters corresponding to the (n-19)th to nth rows of sub-pixels 11, so that the compensation parameters corresponding to all sub-pixels 11 can be obtained through k frame time, and then the obtained compensation parameters are used to compensate the pixel voltage of the corresponding sub-pixels 11 in the subsequent display.

[0087] In this way, not only the color cast problem can be improved, but also the refresh rate of the display panel 10 can be improved. The collection method of the pixel voltage and the calculation method of the compensation parameter are the same as or similar to those in the above embodiment, and the same technical effects can be achieved. For details, refer to the specific description in the above embodiment, which will not be repeated here.

[0088] In specific embodiments, the display device 100 further comprises a backlight assembly (not shown in the figure) disposed at one side of the display panel 10 opposite to the display panel 10, for providing backlight to the display panel 10 to enable the display panel 10 to realize image display function. Specifically, the backlight assembly can be a direct type backlight assembly or an edge type backlight assembly, which can be specifically set according to actual needs.

[0089] The above is only the embodiment of the present application, and does not limit the patent protection scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A display device, comprising: The display panel includes scan lines, data lines, and subpixels; The sub-pixel includes a driving unit and a liquid crystal unit, and there is a connection node between the driving unit and the liquid crystal unit; The data driver module is electrically connected to the data line; The timing control module is used to provide data signals to the data driving module; The display panel is characterized in that it further includes a data acquisition driving line, and at least some of the sub-pixels further include a switching unit; the control terminal of the switching unit is electrically connected to the data acquisition driving line, the first terminal is electrically connected to the connection node, and the second terminal is electrically connected to the data driving module. When the control terminal receives the acquisition signal, the pixel voltage of the connection node is transmitted to the data driving module. The data driving module is used to preprocess the pixel voltage and then transmit it to the timing control module. The timing control module is used to adjust the data signal of the next frame according to the preprocessed pixel voltage so that the pixel voltage reaches a preset target value.

2. The display device according to claim 1, characterized in that, The display panel also includes a data acquisition line, and the second end of the switch unit is electrically connected to the data driving module through the data acquisition line.

3. The display device according to claim 1, characterized in that, The data driving module includes an analog-to-digital conversion unit, used to convert the pixel voltage into a digital voltage to complete the preprocessing of the pixel voltage; The timing control module is used to calculate the ratio of the data signal to the digital voltage to obtain a compensation parameter, and to use the product of the data signal of the next frame and the compensation parameter as the adjusted data signal of the next frame to adjust the data signal of the next frame.

4. The display device according to claim 1, characterized in that, The display panel includes a display area, and the sub-pixels are disposed in the display area and arranged in an array; The display area is divided into multiple compensation areas, each compensation area including at least two sub-pixels, one of which is a sampling point; The timing control module obtains compensation parameters based on the pixel voltage of the preprocessed acquisition point, and all sub-pixels in the compensation area share the compensation parameters.

5. The display device according to claim 4, characterized in that, The sub-pixels between adjacent compensation areas are target sub-pixels. The timing control module is further used to calculate the weighted average of the compensation parameters of adjacent acquisition points based on the distance between the target sub-pixel and the adjacent acquisition points, so as to use the compensation parameters of the target sub-pixel.

6. The display device according to claim 1, characterized in that, The connection node is connected to the corresponding data line to be electrically connected to the data driver module via the data line.

7. The display device according to claim 6, characterized in that, The data driving module includes a multiplexer, an analog-to-digital converter, and an output buffer unit; the multiplexer includes an access terminal, a data signal terminal, and a signal conversion terminal, the data line is electrically connected to the access terminal, the data signal terminal is electrically connected to the output buffer unit, and the signal conversion terminal is electrically connected to the analog-to-digital converter; In the display phase, the multiplexer is used to connect the access terminal and the data signal terminal, so that the output buffer unit transmits data signals to the data line; in the acquisition phase, the multiplexer is used to connect the access terminal and the signal conversion terminal, so that the pixel voltage of the connection node is transmitted to the analog-to-digital conversion unit through the data line, and the analog-to-digital conversion unit is used to convert the pixel voltage into digital voltage to complete the preprocessing of the pixel voltage.

8. The display device according to claim 2 or 6, characterized in that, The data driving module includes a comparator and a data buffer. The comparator includes a first input terminal, a second input terminal, and an output terminal. The data line is electrically connected to the first input terminal through the data buffer. The connection node is electrically connected to the second input terminal. The output terminal is electrically connected to the timing control module. During the acquisition phase, the pixel voltage of the connection node is transmitted to the second input terminal, the data signal of the current frame stored in the data buffer is transmitted to the first input terminal, and the comparator is used to compare the data signal with the pixel voltage to complete the preprocessing of the pixel voltage and transmit the comparison result to the timing control module. The timing control module is used to adjust the data signal of the next frame according to the comparison result so that the pixel voltage reaches the preset target value.

9. The display device according to claim 1, characterized in that, The display panel also includes a data acquisition control module, which is electrically connected to the data acquisition drive line and is used to provide acquisition signals to control the switching unit to turn on during the acquisition phase; the acquisition phase is set in the cancellation zone of each frame of signal.

10. The display device according to claim 9, characterized in that, After being turned on, the display panel has multiple compensation stages arranged in chronological order; within each compensation stage, the timing control module uses the same compensation parameter to adjust the data signal of the same sub-pixel.

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