Piezoelectric mems resonator and electronic component

Abstract

The application relates to the field of semiconductor devices and provides a piezoelectric MEMS resonator and an electronic component. The resonator comprises a cap wafer and a device wafer, the cap wafer comprises a cap layer, and the device wafer comprises: a substrate layer; a resonant cavity arranged on the substrate layer; a device silicon layer located on the upper side of the resonant cavity; a piezoelectric layer located on the upper side of the device silicon layer; a top electrode located on the upper side of the piezoelectric layer; and a first dielectric layer located on the upper side of the top electrode and covering the top electrode, the first dielectric layer is bonded to the cap layer, at least a part of the first dielectric layer bonded to the cap layer projects on the vertical direction and overlaps the projection of the top electrode on the vertical direction, and the upper surface of the at least part of the first dielectric layer bonded to the cap layer is in the same plane. In this way, the bonding properties of the cap wafer and the device wafer are improved by flattening the surface of the dielectric layer covering the top electrode, and a good bonding effect is ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more particularly to a piezoelectric MEMS resonator and electronic components. Background Technology

[0002] The resonator is the core component of an oscillator. Due to the smaller size, lower manufacturing cost and higher reliability of electrostatically driven silicon-based MEMS resonators, MEMS oscillators with electrostatically driven silicon-based MEMS resonators as the core component are expected to become a replacement for traditional quartz oscillators as the technology matures.

[0003] With the development of piezoelectric thin film materials, compared with electrostatically driven silicon-based MEMS resonators, piezoelectrically driven silicon-based MEMS resonators (referred to as "piezoelectrically driven silicon-based MEMS resonators") exhibit superior performance such as lower motional impedance and higher electromechanical coupling coefficient, which is more conducive to reducing the power consumption and phase noise of the oscillator.

[0004] Since piezoelectrically driven silicon-based MEMS resonators do not require the application of electrostatic bias voltage, they reduce the error term in the output signal caused by power supply jitter. In addition, piezoelectrically driven silicon-based MEMS resonators do not require the formation of submicron-level silicon layer slits during fabrication, which reduces the difficulty of the process, improves the device yield, and facilitates further miniaturization of the device.

[0005] Piezoelectric driven silicon-based MEMS resonators often employ wafer-level packaging structures. To ensure that the piezoelectric driven silicon-based MEMS resonators have a small size, the device wafer signal is usually brought out through conductive via structures in the cap wafer. That is, conductive via structures for signal outgoing are formed in the silicon cap, thereby bringing the electrodes in the device layer out to the outside of the package.

[0006] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0007] The inventors discovered that in the above-mentioned packaging structure, the process of fabricating the silicon cap with conductive vias is relatively complex and involves many steps, resulting in higher manufacturing costs and lower yield, thereby increasing the cost per chip.

[0008] In addition, the method of extracting device wafer signals through conductive vias in capped wafers can affect device performance before and after bonding, thus significantly impacting device frequency, impedance characteristics, and other properties. This makes it difficult to control these properties and maintain device performance consistency during production, increasing on-chip performance variability.

[0009] In addition, because there is a patterned electrode layer inside the device wafer, the surface of the dielectric layer deposited on the electrode layer is usually uneven, which affects the bonding characteristics between the cap wafer and the device wafer.

[0010] To address at least one of the above-mentioned problems or other similar issues, embodiments of this application provide a piezoelectric MEMS resonator and an electronic component.

[0011] According to one aspect of the embodiments of this application, a piezoelectric MEMS resonator is provided, the resonator comprising a cap wafer and a device wafer, the cap wafer comprising a cap layer.

[0012] The device wafer includes:

[0013] Substrate layer;

[0014] The resonant cavity is disposed in the substrate layer;

[0015] The device silicon layer located on the upper side of the resonant cavity;

[0016] A piezoelectric layer located on top of the silicon layer of the device;

[0017] The top electrode located on the upper side of the piezoelectric layer; and

[0018] The first dielectric layer located above and covering the top electrode.

[0019] The first dielectric layer is bonded to the capping layer, and the projection of at least a portion of the first dielectric layer bonded to the capping layer in the vertical direction overlaps with the projection of the top electrode in the vertical direction. The upper surface of at least the portion of the first dielectric layer bonded to the capping layer is in the same plane.

[0020] According to another aspect of the embodiments of this application, an electronic component is provided, the electronic component including the resonator described in the above embodiments.

[0021] One of the beneficial effects of the embodiments of this application is that by planarizing the surface of the dielectric layer covering the top electrode, the bonding characteristics of the cap wafer and the device wafer are improved, ensuring a good bonding effect. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is a top view schematic diagram of a piezoelectric MEMS resonator according to an embodiment of this application.

[0024] Figure 2 yes Figure 1 The image shows a cross-sectional view of the piezoelectric MEMS resonator along the A-A' direction.

[0025] Figure 3 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0026] Figure 4 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0027] Figure 5 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0028] Figure 6 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0029] Figure 7 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0030] Figure 8 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0031] Figure 9 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0032] Figure 10 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0033] Figure 11 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0034] Figure 12 This is a schematic diagram of another embodiment of the piezoelectric MEMS resonator of this application.

[0035] Figure 13 yes Figure 12 The image shows a cross-sectional view of the piezoelectric MEMS resonator along the A-A' direction.

[0036] Figure 14 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0037] Figure 15 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0038] Figure 16 This is a top view schematic diagram of another embodiment of the piezoelectric MEMS resonator of this application.

[0039] Figure 17 yes Figure 16 The image shows a cross-sectional view of the piezoelectric MEMS resonator along the B-B' direction. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of this application are used to explain this application, but are not intended to limit this application.

[0041] In the embodiments of this application, the terms "first," "second," "upper," "lower," etc., are used to distinguish different elements by their names, but do not indicate the spatial arrangement or temporal order of these elements, and these elements should not be limited by these terms. The term "and / or" includes any one or more of the terms listed in connection with the application and all combinations thereof. The terms "comprising," "including," "having," etc., refer to the presence of the stated features, elements, components, or assemblies, but do not exclude the presence or addition of one or more other features, elements, components, or assemblies.

[0042] In the embodiments of this application, the singular forms "a," "the," etc., including the plural forms, should be broadly understood as "a kind" or "a class" rather than limited to the meaning of "an." Furthermore, the term "the" should be understood to include both the singular and plural forms, unless the context explicitly indicates otherwise. Additionally, the term "according to" should be understood as "at least partially based on…," and the term "based on" should be understood as "at least partially based on…," unless the context explicitly indicates otherwise.

[0043] The embodiments of this application will now be described with reference to the accompanying drawings.

[0044] This application provides a piezoelectric MEMS resonator, which can be a silicon-based MEMS resonator driven by piezoelectricity. However, this application does not limit this. The piezoelectric MEMS resonator of this application will be described below using a silicon-based MEMS resonator driven by piezoelectricity as an example.

[0045] Figure 1 This is a top view schematic diagram of a piezoelectric MEMS resonator according to an embodiment of this application. Figure 2 yes Figure 1 The image shows a cross-sectional view of the piezoelectric MEMS resonator along the A-A' direction.

[0046] like Figure 2As shown, the piezoelectric MEMS resonator (hereinafter referred to as "resonator") 1 includes a cap wafer 30 and a device wafer 20. The cap wafer 30 includes a cap layer 301. The device wafer 20 includes a substrate layer 101, a resonant cavity 102 disposed on the substrate layer, a piezoelectric layer 202 located on the resonant cavity 102, a top electrode 203 located on the piezoelectric layer 202, and a first dielectric layer 204 located on the top electrode 203 and covering the top electrode 203. In addition, for the convenience of explanation, without causing ambiguity, the other layers in the device wafer 20 besides the substrate layer 101 are sometimes collectively referred to as "device layers".

[0047] In some embodiments, such as Figure 2 As shown, the first dielectric layer 204 is bonded to the capping layer 301. The vertical projection of at least a portion of the first dielectric layer 204 bonded to the capping layer 301 overlaps with the vertical projection of the top electrode 203. The upper surface of at least a portion of the first dielectric layer 301 bonded to the capping layer 301 is in the same plane. In other words, the area of ​​the upper surface of the first dielectric layer 301 bonded to the capping layer 301 is flat.

[0048] Therefore, by planarizing the surface of the dielectric layer covering the top electrode, the bonding characteristics of the cap wafer and the device wafer are improved, ensuring good bonding results.

[0049] like Figure 1 As shown, the cap wafer 30 and the device wafer 20 are bonded in the first direction z. In the embodiments of this application, the first direction z, the second direction x, and the third direction y are perpendicular to each other. In addition, without causing ambiguity, the first direction z is sometimes referred to as the "vertical direction", and the second direction x and the third direction y are referred to as the "horizontal direction". In addition, for the convenience of description, unless otherwise specified, the dimension in the first direction z is referred to as the "thickness", the dimension in the second direction x is referred to as the "width", and the dimension in the third direction y is referred to as the "length". For the first direction z, the direction from the device wafer 20 to the cap wafer 30 is referred to as "up", the direction from the cap wafer 30 to the device wafer 20 is referred to as "down", the surface located "up" is referred to as the "upper surface", and the surface located "down" is referred to as the "lower surface".

[0050] In some embodiments, the capping layer 301 of the capping wafer 30 may be formed of a material such as silicon or glass to protect the effective device area of ​​the device wafer 20. Additionally, for ease of explanation, the "capping layer" is sometimes referred to as a "silicon cap".

[0051] In some embodiments, "effective device region" refers, for example, to the region where the effective acoustic regions of the resonant cavity 102 and the piezoelectric layer 202 coincide in the first direction z, such as... Figure 2As shown, the effective acoustic region of the piezoelectric layer 202 is, for example, the region of the piezoelectric layer 202 covered by the top electrode 203, and the "device effective region" is, for example, the portion of the resonant cavity 102 that overlaps with the top electrode 203 in the first direction z.

[0052] In some embodiments, the substrate 101 may be formed of a semiconductor material or a multilayer composite material, and this application embodiment does not limit this. For example, the substrate 101 may be formed of single-crystal silicon, or a high-resistivity silicon material, for example, with a resistivity greater than 1000 Ω·cm, or for example, a resistivity > 5000 Ω·cm, and this application embodiment does not limit this. For example, the substrate 101 may also be formed of materials such as lithium niobate, lithium tantalate, silicon carbide (SiC), sapphire, or quartz. Alternatively, the substrate 101 may also be formed of semiconductor materials such as silicon dioxide, silicon nitride, polycrystalline silicon, or amorphous silicon, and this application embodiment does not limit this.

[0053] In some embodiments, the resonant cavity 102 is a recess formed in the substrate layer 101, and the formation process of this application is not limited. Furthermore, although the term "cavity" is used, it can also be an acoustic reflection layer with similar or close acoustic impedance characteristics to the "cavity," such as a Bragg reflector layer. This application does not limit the choice of acoustic reflection structure and can design it according to actual needs. For example, when a high Q value is required for the resonator, a cavity can be chosen as the acoustic reflection layer; when high heat dissipation performance or power requirements are required for the resonator, a Bragg reflector layer can be chosen as the acoustic reflection layer. The following description uses a cavity as an example; those skilled in the art should understand that the embodiments of this application are also applicable to acoustic reflection layers of other structures.

[0054] In some embodiments, the piezoelectric layer 202 can be formed of a piezoelectric thin film, for example, a piezoelectric thin film formed of a single-crystal piezoelectric material. This application embodiment does not limit the specific material and can select it according to actual needs or performance requirements. For example, a material with a large piezoelectric coupling coefficient corresponding to a large transverse electric field excitation can be selected, such as single-crystal piezoelectric materials like lithium niobate or lithium tantalate. This application embodiment can, by selecting a suitable cut and the angle between the in-plane interdigitated electrode and the crystal axis, make lithium niobate or lithium tantalate have large d11 (or e11), d15 (or e15), and d16 (or e16) piezoelectric coupling coefficients. This allows the resonator to excite a zero-order symmetric Lamb Wave mode (S0 mode), a first-order antisymmetric Lamb Wave mode (A1 mode), a zero-order shearhorizontal mode (SH0 mode), and higher-order or lower-order modes of the above modes, respectively.

[0055] Furthermore, the wafer-level packaging structure of this application embodiment is applicable to piezoelectrically driven silicon-based MEMS resonators with different vibration modes. The planar structure of a piezoelectrically driven silicon-based MEMS resonator can be varied, and the corresponding electrode arrangements also differ. Its vibration modes can also be varied, such as in-plane flexural mode, out-of-plane flexural mode, width extensional mode (WE mode), length extensional mode (LE mode), Lamé mode, etc., but not limited to the above vibration modes. In addition, the resonant frequency achievable by the resonator of this application embodiment can, for example, cover a range from tens of kHz to hundreds of MHz.

[0056] In some embodiments, the top electrode 203 can be formed of a metal, such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr), or other elemental metals or their alloys or composite layers; the top electrode 203 can also be made of doped polycrystalline silicon, and the doping element can be boron (B), phosphorus (P), arsenic (As), etc., with a doping concentration of, for example, 10. 19 cm -3 As shown above, the higher the doping concentration, the lower the sheet resistance and electrical loss of the polycrystalline silicon electrode. The choice of material to form the top electrode 203 can be determined according to actual needs, and this application embodiment does not impose any restrictions on this.

[0057] In some embodiments, the material forming the first dielectric layer 204 may be silicon dioxide, fluorine-doped silicon dioxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, titanium oxide, tantalum pentoxide, etc., and may be a single layer or a combination of multiple layers of different dielectric materials. The first dielectric layer 204 may serve as a passivation layer for the resonator 1 or as an isolation layer between the signal line and the cap.

[0058] When the first dielectric layer 204 covers the surface of the resonant cavity, the first dielectric layer 204 also participates in the vibration of the resonant cavity. Therefore, the first dielectric layer 204 will affect the frequency, temperature drift characteristics and quality factor of the resonator. For example, the first dielectric layer 204 is formed of silicon dioxide material, which can simultaneously play a temperature compensation role in the performance of the resonator.

[0059] In some embodiments, a first dielectric layer 204 can be formed on the upper surface of the piezoelectric layer 202 containing the top electrode 203 by a deposition process. At locations with metal leads, the surface of the first dielectric layer 204 will be higher than other locations. If the thickness of the top electrode 203 is less than 1000 Å, this height difference will have little impact on bonding characteristics; however, if the thickness of the top electrode 203 is greater than 1000 Å, this height difference will affect bonding characteristics. Therefore, after depositing the first dielectric layer 204, a chemical mechanical polishing (CMP) process can be performed on the first dielectric layer 204 to eliminate its surface height difference and ensure good subsequent bonding performance. For example, the entire upper surface of the first dielectric layer 204 can be flat.

[0060] In some embodiments, such as Figure 1 As shown, at least a portion of the projection of the top electrode 203 in the vertical direction z does not overlap with the projection of the capping layer 301 in the vertical direction z, such as... Figure 2 As shown, the device wafer 20 also includes at least one first lead-out electrode P1 electrically connected to the top electrode 203. The at least one first lead-out electrode P1 extends from the portion of the top electrode 203 that does not overlap with the capping layer 301 through the first dielectric layer 204 and covers the area of ​​the upper surface of the first dielectric layer 204 that is not covered by the capping layer.

[0061] This avoids the need to fabricate complex conductive via structures in the silicon cap, reducing manufacturing costs while improving chip manufacturing yield, thus enabling the production of low-cost resonator chips.

[0062] On the other hand, because the electrodes are laterally led out, the test pins and leads remain unchanged before and after bonding the cap wafer to the device wafer. Therefore, the device performance is almost unaffected by bonding, improving the on-chip stability of the device performance. In contrast, in traditional structures, the device layer signals are led out through conductive vias in the cap wafer. The device performance before and after bonding is affected by the process of forming the conductive vias. The process of forming the conductive vias has a significant impact on the device frequency and impedance characteristics, which is not conducive to maintaining good consistency in the device performance, thereby increasing the on-chip variability of the device performance.

[0063] In some embodiments, the material for forming the first lead electrode P1 is, for example, gold, aluminum, copper, or an aluminum-copper alloy or an aluminum-silicon-copper alloy. This application embodiment does not limit this.

[0064] In some embodiments, such as Figure 2As shown, the device wafer 20 also includes a device silicon layer 201 located between the piezoelectric layer 202 and the substrate layer. The device silicon layer 201 is a doped silicon layer. This improves the device's frequency-temperature characteristics. The device silicon layer 201 can be, for example, monocrystalline silicon or polycrystalline silicon. Furthermore, to further improve the device's frequency-temperature characteristics, the device silicon layer 201 can be heavily doped silicon, with doping elements such as boron (B), phosphorus (P), and arsenic (As), and a doping concentration of, for example, 10. 19 cm -3 Optionally, the doping concentration is 10. 20 cm -3 This results in a resistivity of less than 1 mΩ·cm.

[0065] In some embodiments, at least a portion of the projection of the device silicon layer 201 in the vertical direction z does not overlap with the projection of the cap layer 301 in the vertical direction z, such as... Figure 2 As shown, the device wafer 20 also includes a second lead electrode P2 electrically connected to the upper surface of the device silicon layer 201. The second lead electrode P2 extends from the portion of the device silicon layer 201 that does not overlap with the capping layer 301, passing through the piezoelectric layer 202 and the first dielectric layer 204, and covers the area of ​​the upper surface of the first dielectric layer 204 not covered by the capping layer 301. Thus, the device silicon layer 201 realizes the function of the bottom electrode of the piezoelectric layer 202. In addition, the forming material of the second lead electrode P2 can be the same as or different from the forming material of the first lead electrode P1, and this embodiment of the application does not limit this.

[0066] Figure 3 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0067] In some embodiments, such as Figure 2 As shown, the device wafer 20 also includes a silicon oxide layer 207 located between the device silicon layer 201 and the substrate layer 101, with the portion of the silicon oxide layer 207 corresponding to the resonant cavity 102 located on the lower surface of the device silicon layer 201. Alternatively, as... Figure 3 As shown, the portion of the silicon oxide layer 103 corresponding to the resonant cavity 102 is formed on the upper surface of the substrate layer 101.

[0068] For example, when forming a pre-defined cavity SOI wafer (Cavity SOI, or CSOI for short), the silicon oxide layer 207 for bonding is formed below the device silicon layer 201. In this case, the silicon oxide layer 207 exists below the finally formed device suspended region. Optionally, when forming CSOI, the silicon oxide layer 103 for bonding is formed on the surface of the substrate 101. In this case, the silicon oxide layer 103 does not exist below the finally formed device suspended region.

[0069] In addition, the silicon oxide layer 207 or silicon oxide layer 103 can be formed by thermal oxidation method, or by other methods such as low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). The specific formation method can be referred to the relevant technology, and the embodiments of this application do not limit it.

[0070] Figure 4 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0071] In some embodiments, such as Figure 4 As shown, the device wafer 20 also includes a bottom electrode 208 located below the piezoelectric layer 202 and at least one second lead electrode P2 electrically connected to the bottom electrode 208. At least a portion of the projection of the bottom electrode 202 in the vertical direction z does not overlap with the projection of the capping layer 301 in the vertical direction z. At least one second lead electrode P2 passes through the piezoelectric layer 202 and the first dielectric layer 204 from the portion of the bottom electrode 208 that does not overlap with the capping layer 301 and covers the upper surface of the first dielectric layer 204.

[0072] For example, the bottom electrode 208 is located between the piezoelectric layer 202 and the device silicon layer 201, thereby further reducing the motion impedance of the device and improving the reliability of the connection between the second lead electrode P2 and the device silicon layer 201.

[0073] In addition, the bottom electrode 208 may be a metal layer, for example, it may be made of a single metal such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr) or its alloys or composite layers, and the embodiments of this application do not limit this.

[0074] In addition, with Figure 3 The structure of the capped wafer 30 shown is different. Figure 4 The edge of the cap wafer 30 shown has an eave structure that protrudes outward in the horizontal direction. This is formed by different processing techniques, and the embodiments of this application do not limit this.

[0075] In some embodiments, such as Figure 2As shown, the device wafer also includes a sealing ring 205. The first dielectric layer 204 is bonded to the cap layer 301 through the sealing ring 205. The sealing ring 205 is formed of at least one layer of metal material and / or dielectric material. For example, the metal material can be gold, aluminum, germanium, tin, copper, etc., used to form metal-silicon bonding or metal-metal bonding. It can also include at least one layer of adhesion layer or barrier layer material, such as titanium (Ti), titanium tungsten (TiW), chromium (Cr), etc. The dielectric material can be silicon dioxide, glass frit, etc., which can be used to bond with silicon wafers and glass wafers, respectively. In addition, the material forming the sealing ring 205 can be the same as the material of the first electrode P1 or the second electrode P2. For example, the sealing ring 205 and the first electrode P1 or the second electrode P2 can be formed simultaneously by the same process. Alternatively, the material forming the sealing ring 205 can be different from the material of the first electrode P1 or the second electrode P2. This embodiment of the application does not limit this.

[0076] Figure 5 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0077] In some embodiments, such as Figure 5 As shown, the thickness of the portion of the first dielectric layer 204 bonded to the capping layer 301 is greater than the thickness of the portion not bonded to the capping layer 301.

[0078] For example, the first dielectric layer 204 is bonded to the cap layer 301 via a sealing ring 205. The cap wafer 30 and the device wafer 20 can be bonded together via gold-silicon bonding. After the device layer is manufactured but before bonding with the cap wafer, sometimes the thickness of the first dielectric layer 204 needs to be adjusted to adjust the frequency of the resonator. For example, the first dielectric layer 204 is silicon dioxide or aluminum nitride, or a combination of the two materials. The first dielectric layer 204 can be subjected to ion beam frequency correction treatment, that is, the first dielectric layer 204 is thinned by ion beam bombardment. At this time, the first dielectric layer 204 below the sealing ring 205 is protected by the sealing ring 205 and its thickness remains unchanged, while the thickness of the first dielectric layer 204 not covered by the sealing ring 205 is reduced.

[0079] In some embodiments, such as Figures 1 to 5 As shown, the cap layer 301 and the first dielectric layer 204 form an upper cavity 302. The upper cavity 302 can be a single cavity or include multiple sub-cavities. The dimension (or depth) of the upper cavity 302 in the first direction z can be set according to the vibration amplitude of the resonator, and this embodiment does not limit this.

[0080] In addition, such as Figures 1 to 5As shown, the resonator 1 has a groove H that connects the upper cavity 302 and the resonant cavity 102, thereby achieving a sealed encapsulation of the resonator 1. Furthermore, the sealing vacuum level can be adjusted by changing the bonding parameters to achieve encapsulation at different pressures. For example, it can achieve atmospheric pressure encapsulation, i.e., the same as or slightly less than atmospheric pressure; or high vacuum encapsulation, such as less than 10 Pa, less than 1 Pa, less than 0.1 Pa, etc.; or general vacuum encapsulation, such as less than 100 Pa, less than 1 kPa, etc. The appropriate vacuum level can be selected according to actual needs, and this application embodiment does not impose any limitations on this.

[0081] Figure 6 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0082] and Figure 4 The resonator shown has a different structure. Figure 6 The piezoelectric layer 202 or the first dielectric layer 204 of the resonator 1 shown is located on a different plane from the end face of the device silicon layer 201 on the trench H side. That is, the end face of the piezoelectric layer 202 or the first dielectric layer 204 is not flush with the end face of the device silicon layer 201 on the trench H side.

[0083] In some embodiments, such as Figure 6 As shown, the end faces of the first dielectric layer 204 and the piezoelectric layer 202 on the trench H side can be flush. For example, the end faces of the first dielectric layer 204 and the piezoelectric layer 202 on the trench H side can be parallel to the vertical direction or inclined relative to the vertical direction. The end faces of the device silicon layer 201 and the silicon oxide layer 207 on the trench H side can also be flush, for example, parallel to the vertical direction. The end face of the bottom electrode 208 on the trench H side is not flush with the end faces of the piezoelectric layer 202 and the device silicon layer 201 on its upper and lower sides.

[0084] For example, when forming trench H using an etching process, a distributed shell etching method can be used. For instance, the piezoelectric layer 202 and the first dielectric layer 204 are formed by the same photolithography etching, and the bottom electrode 208 is formed by wet etching. Compared to the piezoelectric layer 202, the size is reduced by 0 to 5 μm. Optionally, it is reduced by 1 to 2.5 μm compared to the piezoelectric layer 202. Finally, the device silicon layer 201 and silicon oxide layer 207 are etched using the Bosch deep silicon etching process, so that the device silicon layer 201 and silicon oxide layer 207 have a high perpendicularity feature of nearly 90° at the end face of trench H.

[0085] Furthermore, the embodiments of this application are not limited to this. For example, the first dielectric layer 204 and the piezoelectric layer 202 may not be flush with each other on the end face of the trench H, and the device silicon layer 201 and the silicon oxide layer 207 may not be flush with each other on the end face of the trench H; additionally, for example, such as Figures 2 to 5As shown, all layers can also be flush with the end face of trench H, for example, trench H can be formed by a continuous etching method. This application does not limit this approach.

[0086] Figure 7 and Figure 8 These are cross-sectional views of another embodiment of the piezoelectric MEMS resonator according to the present application.

[0087] In some embodiments, the first dielectric layer 204 located in the effective region of the device can be removed by etching, thereby preventing the first dielectric layer 204 from affecting device performance and allowing it to serve only as an isolation layer between the signal line and the cap. For example... Figure 7 and Figure 2 The difference is, such as Figure 7 As shown, the effective region of the device, for example, at least the suspended portion of the device layer, is etched away by the corresponding first dielectric layer 204.

[0088] In some embodiments, such as Figure 8 As shown, the resonator 1 also has a second dielectric layer 209 located between the first dielectric layer 204 and the top electrode 203. The materials used to form the second dielectric layer 209 and the first dielectric layer 204 can be different. Therefore, the second dielectric layer 209 can serve as a passivation layer for the top electrode 203 and a barrier layer for etching the first dielectric layer 204, as well as a temperature compensation layer for the resonator. For example, if the first dielectric layer 204 is formed of silicon dioxide and the second dielectric layer 209 is formed of aluminum nitride, then the second dielectric layer 209 can serve as a passivation layer protecting the metal top electrode 203, and also as a barrier layer during the etching of the first dielectric layer 204. As another example, if the first dielectric layer 204 is formed of silicon nitride and the second dielectric layer 209 is formed of silicon dioxide, then in addition to the above functions, the second dielectric layer 209 can also serve as a temperature compensation layer for the resonator. This application does not limit the scope of the embodiments.

[0089] Figure 9 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0090] In some embodiments, the first dielectric layer 204 located in the effective region of the device can be patterned by etching. This allows for simultaneous adjustment of the temperature coefficient and frequency characteristics.

[0091] For example, Figure 9 and Figure 8 The difference is, such as Figure 9As shown, the first dielectric layer 204 is etched into a predetermined pattern in the effective region of the device, for example, at least in the suspended portion of the device layer. This predetermined pattern can be set according to the required temperature coefficient and frequency characteristics. For example, the material density, stiffness, and temperature coefficient of the first dielectric layer 204 are different from those of the second dielectric layer 209, and the removal rates of the two layers during ion beam bombardment are different. Therefore, it is advantageous to simultaneously adjust the temperature coefficient and frequency characteristics through ion beam bombardment.

[0092] Figure 10 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0093] In some embodiments, such as Figure 10 As shown, the capped wafer 30 also includes a metal layer 304. The capped layer 301 is bonded to the sealing ring 205 through the metal layer 304, and the metal layer 304 is formed of at least one layer of metal material. This achieves metal-metal bonding in various ways, such as gold-gold bonding, aluminum-germanium bonding, and gold-tin-copper bonding.

[0094] In some embodiments, such as Figure 10 As shown, the cap wafer 30 also includes a first insulating layer 303 covering the outer surface of the cap layer 301, and a metal layer 304 is formed on the lower surface of the first insulating layer 303. For example, the cap wafer 30 is formed of single-crystal silicon, and the first insulating layer 303 can be a silicon dioxide layer formed by thermal oxidation, thereby further reducing the parasitic capacitance generated by the cap wafer, or improving bonding reliability and extending device life.

[0095] Figure 11 This is a cross-sectional view of another embodiment of the piezoelectric MEMS resonator of this application.

[0096] In some embodiments, the device wafer 20 further includes a second insulating layer 215 located on the lower surface of the bottom electrode 208. For example, as Figure 11 As shown, with Figure 4 Compared to the resonator shown, a second insulating layer 215 is added below the bottom electrode 208. The second insulating layer 215 can be formed of materials such as silicon dioxide, doped silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, and tantalum pentoxide. The second insulating layer 215 can be a single layer or a combination of multiple layers of different dielectric materials. Since the bottom electrode 208 is insulated from the device silicon layer 201 through the second insulating layer 215, the bottom electrode 208 can be patterned into multiple electrode shapes to connect electrical signals of different polarities.

[0097] Figure 12 This is a schematic diagram of another embodiment of the piezoelectric MEMS resonator of this application. Figure 13 yes Figure 12The image shows a cross-sectional view of the piezoelectric MEMS resonator along the A-A' direction. Figure 14 and Figure 15 These are cross-sectional views of another embodiment of the piezoelectric MEMS resonator according to the present application.

[0098] In some embodiments, such as Figure 13 As shown, the device silicon layer 201 also includes a trench-shaped isolation layer 210 that penetrates the device silicon layer 201. The isolation layer 210 extends from a portion of the device silicon layer 201 located in the effective region of the device to a portion corresponding to the second lead electrode P2.

[0099] like Figure 13 As shown, the isolation layer 210 includes a third insulating layer 211 filled within the trench. For example, a trench-like structure is etched into the device silicon layer 201, and the trench-like structure is filled with an insulating material such as silicon dioxide or a combination of silicon dioxide and polysilicon. Finally, excess insulating layer is removed by etching or CMP. For example, by CMP, only the excess insulating layer is retained. Figure 13 The trench shown contains a third insulating layer 211, while no insulating layer is retained on the surface of the device silicon layer 201.

[0100] like Figure 14 and Figure 15 As shown, the isolation layer 210 may also include a fourth insulating layer 212 located on the upper surface of the device silicon layer 201, the fourth insulating layer 212 being located on the portion of the upper surface of the device silicon layer 201 that is not covered by the second lead electrode P2 and the piezoelectric layer 202.

[0101] For example, after filling the trench with insulating material, an etching method is used to remove the insulating layer on the surface of the device silicon layer 201 where the piezoelectric layer 202 needs to be grown and where it needs to be connected to the second lead electrode P2, while retaining the insulating layer in other areas of the surface of the device silicon layer 201, thereby forming Figure 14 The fourth insulating layer 212 is shown.

[0102] For example, after filling the trench with insulating material, the insulating layer at the location where the piezoelectric layer 202 needs to be grown on the surface of the device silicon layer 201 is first etched away using an etching method, while retaining the insulating layer in other areas on the surface of the device silicon layer 201. When forming the second lead electrode P2 to connect with the bottom electrode, the insulating layer at the exposed location is etched away after etching the first dielectric layer 204 and the piezoelectric layer 202, thereby exposing the device silicon layer 201 or the bottom electrode.

[0103] Figure 16 This is a top view schematic diagram of another embodiment of the piezoelectric MEMS resonator of this application. Figure 17 yes Figure 16 The image shows a cross-sectional view of the piezoelectric MEMS resonator along the B-B' direction.

[0104] In some embodiments, the sealing ring 205 may also be electrically connected to the bottom electrode of the piezoelectric layer 202, thereby reducing the parasitic capacitance effect of the metal sealing ring 205 and the cap wafer 30 on the resonator, and thus improving the performance of the resonator.

[0105] For example, when the device silicon layer 201 serves as the bottom electrode of the piezoelectric layer 202, the sealing ring 205 can be electrically connected to the device silicon layer 201 through at least one conductive hole. For example, as Figure 17 As shown, the conductive hole P3 passes through at least the first dielectric layer 204 and the piezoelectric layer 202, and is electrically connected to the upper surface of the device silicon layer 201. Figure 16 and 17 Only one conductive hole is shown, but the embodiments of this application are not limited to this, and multiple conductive holes can be provided as needed.

[0106] Alternatively, if the device wafer 20 includes a bottom electrode 208, the sealing ring 205 may be electrically connected to the bottom electrode 208 through at least one conductive hole, which passes through at least the first dielectric layer 204 and the piezoelectric layer 202 and is electrically connected to the upper surface of the bottom electrode 208. Alternatively, the at least one conductive hole may also pass through the first dielectric layer 204, the piezoelectric layer 202 and the bottom electrode 208 and be electrically connected to the device silicon layer 201.

[0107] In addition, the projection of the aforementioned conductive hole in the vertical direction can overlap with the sealing ring 205, or it can be located inside the annular region of the sealing ring 205, or it can be located outside the annular region of the sealing ring 205. The embodiments of this application do not limit the setting position of the conductive hole.

[0108] As can be seen from the above embodiments, the bonding characteristics of the cap wafer and the device wafer are improved by planarizing the surface of the dielectric layer covering the top electrode, thus ensuring a good bonding effect.

[0109] This application also provides an electronic component, which includes the piezoelectric MEMS resonator described in the foregoing embodiments. Since the structure and features of the piezoelectric MEMS resonator have been described in detail in the above embodiments, the details are incorporated herein and omitted here.

[0110] The electronic components in the embodiments of this application are, for example, oscillators, including the piezoelectric MEMS resonators described in any of the foregoing embodiments, the contents of which are incorporated herein and are omitted here.

[0111] In addition, the electronic components in the embodiments of this application may be applied to communication devices that comply with the fifth generation mobile communication standard or may be included in the communication device. For details, please refer to the relevant technology. The embodiments of this application do not limit this.

[0112] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A piezoelectric MEMS resonator, the resonator comprising a cap wafer and a device wafer, characterized in that, The capped wafer includes a capping layer. The device wafer includes: Substrate layer; The resonant cavity is disposed in the substrate layer; The device silicon layer located on the upper side of the resonant cavity; A piezoelectric layer located on top of the silicon layer of the device; The top electrode located on the upper side of the piezoelectric layer; and The first dielectric layer located above and covering the top electrode. The first dielectric layer is bonded to the capping layer, and the vertical projection of at least a portion of the first dielectric layer bonded to the capping layer overlaps with the vertical projection of the top electrode. The upper surface of at least the portion of the first dielectric layer bonded to the capping layer is in the same plane. The device wafer also includes at least one first lead-out electrode electrically connected to the top electrode. At least a portion of the vertical projection of the top electrode does not overlap with the vertical projection of the cap layer. The at least one first lead-out electrode passes through the first dielectric layer from the portion of the top electrode that does not overlap with the capping layer and covers the area of ​​the upper surface of the first dielectric layer that is not covered by the capping layer.

2. The resonator according to claim 1, characterized in that, The upper surface of the first dielectric layer is flat.

3. The resonator according to claim 1, characterized in that, The device wafer also includes a metal bottom electrode located below the piezoelectric layer and at least one second lead electrode electrically connected to the bottom electrode. At least a portion of the vertical projection of the bottom electrode does not overlap with the vertical projection of the cap layer. The at least one second lead electrode extends from the portion of the bottom electrode that does not overlap with the capping layer, through the piezoelectric layer and the first dielectric layer, and covers the upper surface of the first dielectric layer.

4. The resonator according to claim 1, characterized in that, The silicon layer of the device is a doped silicon layer, and the doping concentration of the silicon layer of the device is 10. 19 cm -3 above.

5. The resonator according to claim 1, characterized in that, The cap layer and the first dielectric layer form an upper cavity. The resonator has a groove that connects the upper cavity and the resonant cavity.

6. The resonator according to claim 5, characterized in that, The piezoelectric layer or the first dielectric layer and the device silicon layer are located on different planes on the end face of the trench side.

7. The resonator according to claim 1, characterized in that, The device wafer also includes a silicon oxide layer located between the device silicon layer and the substrate layer. The portion of the silicon oxide layer corresponding to the resonant cavity is located on the lower surface of the silicon layer of the device, or... The portion of the silicon oxide layer corresponding to the resonant cavity is formed on the upper surface of the substrate layer.

8. The resonator according to claim 1, characterized in that, The resonator also has a second dielectric layer located between the first dielectric layer and the top electrode.

9. The resonator according to claim 1 or 8, characterized in that, The first dielectric layer located in the effective region of the device is removed.

10. The resonator according to claim 1 or 8, characterized in that, The first dielectric layer located in the effective region of the device is patterned.

11. The resonator according to claim 1, characterized in that, The device wafer also includes a sealing ring, through which the first dielectric layer is bonded to the cap layer, and the sealing ring is formed of at least one layer of metal material and / or dielectric material.

12. The resonator according to claim 11, characterized in that, The thickness of the portion of the first dielectric layer bonded to the capping layer is greater than the thickness of the portion not bonded to the capping layer.

13. The resonator according to claim 11, characterized in that, The capped wafer also includes a metal layer, which is bonded to the sealing ring via the metal layer, and the metal layer is formed of at least one layer of metal material.

14. The resonator according to claim 13, characterized in that, The capped wafer also includes a first insulating layer covering the outer surface of the capping layer, and the metal layer is formed on the lower surface of the first insulating layer.

15. The resonator according to claim 3, characterized in that, The device wafer also includes a second insulating layer located on the lower surface of the bottom electrode.

16. The resonator according to claim 1 or 4, characterized in that, The device wafer also includes a second lead electrode electrically connected to the upper surface of the device silicon layer. At least a portion of the vertical projection of the silicon layer of the device does not overlap with the vertical projection of the capping layer. The second lead electrode extends from the portion of the device silicon layer that does not overlap with the capping layer, through the piezoelectric layer and the first dielectric layer, and covers the area of ​​the upper surface of the first dielectric layer that is not covered by the capping layer.

17. The resonator according to claim 16, characterized in that, The device silicon layer further includes a trench-shaped isolation layer that extends through the device silicon layer from a portion of the device silicon layer located in the effective region of the device to a portion corresponding to the second lead electrode.

18. The resonator according to claim 17, characterized in that, The insulating layer includes a third insulating layer that fills the trench.

19. The resonator according to claim 18, characterized in that, The isolation layer also includes a fourth insulating layer located on the upper surface of the silicon layer of the device. The fourth insulating layer is located on the upper surface of the device silicon layer, excluding the portion covered by the second lead-out electrode and the piezoelectric layer.

20. The resonator according to claim 11, characterized in that, The sealing ring is electrically connected to the silicon layer of the device through at least one conductive hole.

21. The resonator according to claim 3, characterized in that, The device wafer also includes a sealing ring, through which the first dielectric layer is bonded to the cap layer. The sealing ring is formed of at least one layer of metallic material and / or dielectric material. The sealing ring is electrically connected to the bottom electrode through at least one conductive hole.

22. An electronic component, characterized in that, The electronic component includes the resonator according to any one of claims 1 to 21.

Images