An isolation drive chip and PWM drive signal consistency check circuit

Abstract

The present application provides an isolation driver chip and a PWM drive signal consistency check circuit, which are applied to the technical field of isolation driver chips, wherein a gate voltage sampling circuit and a comparison filter circuit are added to the isolation driver chip, and the encoder, digital isolator, and decoder of the isolation feedback channel are reused, so that the sampling, feedback, and comparison modules originally implemented by the system are completely integrated into the isolation driver chip, thereby realizing a simple, accurate, and fast consistency check circuit by multiplexing the encoding and decoding isolation feedback channel, thereby greatly reducing the cost and complexity of the system.

Description

Technical Field

[0001] The present application relates to the technical field of isolation drive chips, and in particular to an isolation drive chip and a PWM drive signal consistency check circuit. Background Art

[0002] In the electric drive system, the isolated driver chip is responsible for transmitting the control signal from the controller (such as MCU microcontroller, DSP digital processor, etc.) on the control side to the drive side, driving the external power device and providing sufficient current driving capability. Since the signal between the control side and the drive side cannot be transmitted directly, it needs to be electrically isolated through an isolator. If the transmitted signal is wrong, it may cause abnormal motor torque and affect the normal driving of the car; in extreme cases, it may cause the power tube to explode and the car to lose power. Therefore, ensuring the correctness of the control signal transmission of the isolated driver chip is an important part of achieving functional safety and ensuring personal safety of the electric drive system.

[0003] The existing solution is to add additional devices and circuits outside the isolation driver chip, sample the gate-level signal of the power tube on the driver side, isolate and transmit it back to the controller on the control side, and monitor it by the controller. This not only increases a lot of material costs, but also increases the software complexity of the controller. Summary of the invention

[0004] In view of this, the present application proposes an isolated driver chip and a PWM drive signal consistency verification circuit. By integrating sampling, feedback, comparison and other circuits into the isolated driver chip, a fast and accurate PWM consistency verification function can be achieved, thereby effectively saving the cost of the electric drive system and reducing the system complexity.

[0005] This application provides the following technical solutions:

[0006] The present application provides a PWM drive signal consistency check circuit, which is integrated into an isolation drive chip. The PWM drive signal consistency check circuit includes:

[0007] Gate voltage sampling circuit: integrated design on the driving side of the isolation driver chip, used to sample the voltage of the driving output signal output from the driving side of the isolation driver chip to the power device and form a sampling result;

[0008] Multiplexed encoder: multiplex the encoder located on the drive side of the isolation driver chip to encode the sampling results;

[0009] Multiplexing digital isolator: Multiplexing the digital isolator located in the isolation barrier inside the isolation driver chip to isolate and transmit the encoded sampling results from the driver side to the control side.

[0010] Multiplexing decoder: multiplexing the decoder located at the control side of the isolation driver chip to decode the sampling results isolated and transmitted back by the digital isolator;

[0011] Comparison filter circuit: integrated design on the control side inside the isolation driver chip, used to perform consistency check on the sampling result output by the decoder and the PWM signal input to the control side of the isolation driver chip, and when the sampling result output by the decoder is inconsistent with the PWM signal input to the control side of the isolation driver chip, the comparison result of the gate signal failure is output, otherwise the comparison result of the gate signal is normal is output.

[0012] Preferably, the comparison filtering circuit includes: a digital circuit and a timer, wherein the digital circuit is used to determine whether the sampling result output by the decoder is the same as the PWM signal input to the control side of the isolation driver chip, and if they are the same, the timer is reset; if they are not the same, the timer is started for timing.

[0013] Preferably, the comparison filter circuit further comprises: a control logic redundancy unit, which is a redundant unit corresponding to an existing control logic unit on the control side in the isolation driver chip, wherein the input of the control logic redundancy unit is the same as the input of the existing control logic unit, so as to: if the existing control logic unit fails, the output of the control logic redundancy unit is different from the output of the existing control logic unit, thereby detecting the failure of the existing control logic unit;

[0014] And / or, the comparison filter circuit further includes: a delay matching unit, used for performing delay matching on the PWM signal input from the controller to the control side of the isolation driver chip, so as to match the transmission delay time of the sampling result relative to the PWM signal inside the isolation driver chip;

[0015] And / or, the timer is configured as follows: if the timer timing exceeds a preset time, it is determined that a PWM consistency check detection failure occurs, otherwise the timer continues timing.

[0016] Preferably, the preset time setting range is 300ns-600ns;

[0017] And / or, the delay time setting range of the delay matching unit is 300ns-600ns.

[0018] Preferably, in the PWM drive signal consistency check circuit described in any one of the present applications, the gate voltage sampling circuit includes a first hysteresis comparator and a second hysteresis comparator, the non-inverting input terminal of the first hysteresis comparator and the non-inverting input terminal of the second hysteresis comparator are used to input the gate signal to be sampled, the inverting input terminal of the first hysteresis comparator is used to set the high level detection threshold, the output terminal of the first hysteresis comparator is used to output a first comparison result, the inverting input terminal of the second hysteresis comparator is used to set the low level detection threshold, and the output terminal of the second hysteresis comparator is used to output a second comparison result, wherein when the first comparison result is a high level, it indicates that the gate signal is high, and when the second comparison result is a high level, it indicates that the gate signal is low.

[0019] Preferably, the multiplexing encoder adopts a pulse width modulation encoding method, and the multiplexing decoder adopts a pulse width counting decoding method.

[0020] Preferably, a high level pulse width is used to encode and decode the fault signal driven by the isolation driver chip, and a low level pulse width is used to encode and decode the first comparison result and the second comparison result.

[0021] Preferably, the fault signal includes the following signal types: a general alarm signal and a serious alarm signal; wherein, when both the general alarm signal and the serious alarm signal are fault-free, the pulse width using the high-level encoding method is set to the first width, and the pulse width count of the high-level decoding is set to the first count; when the general alarm signal is faulty and the serious alarm signal is fault-free, the pulse width using the high-level encoding method is set to the second width, and the pulse width count of the high-level decoding is set to the second count; when the general alarm signal is fault-free and the serious alarm signal is faulty, the pulse width using the high-level encoding method is set to the third width, and the pulse width count of the high-level decoding is set to the third count; when both the general alarm signal and the serious alarm signal are faulty, the pulse width using the high-level encoding method is set to the fourth width, and the pulse width count of the high-level decoding is set to the fourth count;

[0022] And / or, when the first comparison result and the second comparison result are both low levels, the pulse width of the low-level encoding method is set to the fifth width, and the pulse width count of the high-level decoding method is set to the fifth count; when the first comparison result is a low level and the second comparison result is a high level, the pulse width of the low-level encoding method is set to the sixth width, and the pulse width count of the low-level decoding method is set to the sixth count; when the first comparison result is a high level and the second comparison result is a low level, the pulse width of the low-level encoding method is set to the seventh width, and the pulse width count of the low-level decoding method is set to the seventh count; when the first comparison result and the second comparison result are both high levels, the pulse width of the low-level encoding method is set to the eighth width, and the pulse width count of the low-level decoding method is set to the eighth count.

[0023] Preferably, the first width and / or the fifth width is set to 3 clock cycles, and the first count and / or the fifth count is set to 2-4 clock cycles; the second width and / or the sixth width is set to 6 clock cycles, and the second count and / or the sixth count is set to 5-7 clock cycles; the third width and / or the seventh width is set to 9 clock cycles, and the third count and / or the seventh count is set to 8-10 clock cycles; the fourth width and / or the eighth width is set to 12 clock cycles, and the fourth count and / or the eighth count is set to 11-13 clock cycles.

[0024] The present application also provides an isolation driver chip, including a control logic unit, a digital isolator 1, a drive logic unit, an encoder, a digital isolator 2, and a decoder. After the PWM signal is input to the control logic unit for processing, it is transmitted to the drive logic unit through the digital isolator 1, and is processed by the drive logic unit as a gate signal of the power device to be driven. The isolation driver chip also includes: a verification circuit, the verification circuit is a PWM drive signal consistency verification circuit as described in any one of the present applications, wherein the PWM signal is input to the verification circuit at the same time as the control logic unit, and the verification circuit is used to compare the PWM signal and the feedback sampling result to form a consistency verification result output, and the feedback sampling result is a sampling result obtained by sampling the gate signal through the gate signal sampling circuit of the verification circuit, encoding by the multiplexing encoder, isolation feedback by the multiplexing digital isolator 2, and decoding by the multiplexing decoder.

[0025] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the present application include at least:

[0026] (1) The additional circuits required for the system to monitor the drive signal, such as sampling, feedback, comparison and other hardware and software resources, are integrated into the isolation driver chip, and the existing isolation feedback channel inside the driver chip is reused for transmission, which can save a lot of costs and reduce system complexity;

[0027] (2) Through the use of encoding and decoding technology, and multiplexing of isolation channel related circuits (such as encoders, digital isolators, decoders, etc.) transmitted from the drive side to the control side, the cost of the isolation driver chip is almost not increased;

[0028] (3) The consistency check function of the PWM drive signal is realized, with a simple solution, high detection accuracy and fast response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 It is a schematic diagram of the structure of an isolation driver chip;

[0031] Figure 2 It is a schematic diagram of a structure based on the isolation feedback of the external circuit of the isolation driver chip;

[0032] Figure 3 This is a schematic diagram of the overall structure of the isolation driver chip that integrates the PWM signal consistency check function in this application;

[0033] Figure 4 This is a structural schematic diagram of an isolation driver chip in the present application that has a PWM signal consistency check function by reusing existing circuits and adding new circuits;

[0034] Figure 5 It is a structural schematic diagram of a comparison filter circuit based on a comparator in the present application for implementing gate signal sampling and digital processing. DETAILED DESCRIPTION

[0035] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0036] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0037] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0038] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0039] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0040] In the electric drive system, the driver chip plays an important role. On the one hand, the driver chip needs to receive the control signal from the controller (such as MCU, DSP, etc.) on the control side and transmit it to the drive side to control the on and off of the power device. On the other hand, the driver chip needs to monitor the working status of the peripheral circuit (such as power device) on the drive side and report the fault information to the controller in a timely manner.

[0041] In a basic electric drive system, the isolated driver chip needs to use isolation technology to achieve at least the transmission of the following signals:

[0042] 1. Drive PWM signal. This signal directly controls the on and off of the power device and requires extremely low transmission delay.

[0043] 2. Serious alarm signal. This signal is generally used to indicate busbar overcurrent / short circuit, requiring a quick response, usually referred to as FLT fault.

[0044] 3. General alarm signal. This signal is used to indicate other faults that require a quick response and is usually called a RDY fault.

[0045] Figure 1The basic functional block diagram of an isolation driver chip given in the existing solution is shown as follows: the isolation driver chip 100 can be divided into two functional blocks, the control side 101 and the drive side 103, and the medium for communication between the two is the isolation barrier 102; wherein the PWM drive signal of the control side 101 (which can come from a controller such as an MCU or a DSP), namely the PWM in-phase input 104 and the PWM inverted input 105, is transmitted to the digital isolator 1 202 after passing through the control logic unit 201, and is sent to the drive side 103; after receiving the PWM signal, the drive side 103 obtains the drive output 109 through the drive logic unit 203 to control the gate of the external power device 106; in addition, the drive side fault 207 is encoded by the encoder 204, sent to the digital isolator 2 205, and transmitted back to the control side 101. After receiving the fault information, the control side 101 obtains the fault data (such as the RDY fault 107 and the FLT fault 108) after demodulation through the decoder 206, and sends it to the controller (such as the MCU) for processing.

[0046] In the electric drive system, if the PWM signal transmission inside the isolated driver chip is wrong, it will directly affect the operation of the motor, and in turn have a very large impact on the reliability of the system and even the safety of the entire vehicle.

[0047] Therefore, in automotive electric drive systems with high safety requirements, high requirements are usually placed on the consistency of the PWM signals input and output in the isolation driver chip.

[0048] Figure 2 It illustrates a common practice at present: an additional digital isolator is used outside the isolation driver chip to sample the gate signal of the driving power device and then isolate and transmit it back. An additional power supply circuit is also needed to provide power for the sampling, transmission and other circuits. After the signal is transmitted back to the controller (such as MCU), the controller uses additional software resources to complete the comparison processing. Therefore, the added digital isolator, the 5V power supply circuit on the driver side, etc. are all additional hardware, and the comparison processing of the controller will also consume additional software resources, resulting in the addition of more hardware, software and other system resources, which is not only costly, but also highly complex.

[0049] In view of this, through in-depth research and improvement exploration of the drive isolation chip and PWM drive signal, it was found that:

[0050] On the one hand, the driver isolation chip already has isolation transmission and encoding and decoding circuits for transmitting signals, as mentioned above Figure 1In the illustrated isolation driver chip, the isolated transmission of the fault signal from the driver side 103 to the control side 101 is realized through the encoder 204, the digital isolator 205 and the decoder 206. Therefore, if the control side 101 needs to monitor whether the drive output 109 drives the power device 106 correctly, that is, the control side 101 needs to monitor the gate signal of the power device 106, the isolation feedback of the monitoring signal involved can multiplex these circuits to complete the isolated transmission, so there is no need to Figure 2 Adding additional circuitry such as digital isolators can save the circuitry required for isolated backhaul.

[0051] In other words, it is only necessary to isolate the internal driver chip and integrate the sampling circuit of the gate signal on the driver side, and reuse Figure 1 The encoder 204 , the digital isolator 205 , the decoder 206 and other isolation feedback circuits shown in the figure can isolate and transmit the sampling results from the driving side 103 back to the control side 101 .

[0052] Therefore, the design idea can be: just integrate the sampling circuit for sampling the gate signal on the driving side of the isolated driver chip, and reuse the existing encoder, digital isolator, decoder and other circuits on the driving side, so as to realize the encoding, isolated transmission and decoding of the sampling signal inside the isolated driver chip.

[0053] Secondly, based on the above-mentioned multiplexing circuit, the decoded sampling signal is obtained on the control side 101 inside the isolation driver chip. If the relevant functional modules for signal comparison (such as hardware, software and other comparison modules) can be integrated and designed inside the isolation driver chip (i.e., inside the control side 101), there is no need to return the decoded sampling signal to the controller for comparison and processing. That is, the controller only needs to obtain the comparison result given by the isolation driver chip, and there is no need to compare and process the returned sampling signal. This can release more controller resources (such as hardware, software and other resources), thereby simplifying the control system design.

[0054] Thirdly, since the sampling, isolation feedback and other related circuits are integrated and designed inside the isolation driver chip, there is no need to add additional related power supply circuits outside the isolation driver chip to provide working power for these circuits, that is, these circuits can directly use the related power supply inside the isolation driver chip to obtain working power. For example, if the sampling circuit integrated on the driving side of the isolation driver chip needs power supply, it can use the related power supply on the driving side for power supply; similarly, if the comparison circuit integrated on the control side of the isolation driver chip needs power supply, it can use the related power supply on the control side for power supply.

[0055] Four aspects, as mentioned above Figure 1The isolated driver chip shown in the figure, the driver output is the PWM signal output by the controller, after being processed by the control logic unit 201 of the control side 101, it is transmitted from the control side 101 to the driver logic unit 203 of the driver side 103 through the digital isolator 202, and finally the driver logic unit 203 forms the driver output 109 to control the gate of the power device 106. Therefore, once a logic error occurs in the control logic unit 201, the driver logic unit 203, etc., it will inevitably cause the gate of the power device 106 to operate under the wrong logic, so the PWM signal check refers to the consistency comparison of the PWM signal input to the control logic unit 201 and the PWM signal output to the gate of the power device 106 by the driver logic unit 203. In other words, the inputs in the aforementioned comparison circuit are respectively the PWM signal input to the control logic unit 201 and the PWM signal obtained after the gate signal of the power device 106 is sampled from the driver side 103 and transmitted back to the control side 101 for decoding.

[0056] Therefore, the design idea can be: in order to simplify the overall design, the risk of logic errors in the control logic unit 201 and the drive logic unit 203 can be monitored from the final result, that is, the gate signal finally input to the power device 106 is sampled and transmitted back for monitoring. In addition, in terms of interface design, the input interface for inputting the gate signal in the sampling circuit can be set as an independent external interface, or it can be set as a drive output 109 connected to the output of the drive logic unit 203 (that is, integrated in the isolated driver chip); similarly, the input interface for inputting the PWM signal (that is, the PWM signal input by the controller to the control side) in the comparison circuit can be set as an independent external interface, or it can be set as a port connected to the control logic unit 201 input PWM signal (that is, integrated in the isolated driver chip). It should be noted that whether the interface is an external or integrated design can be determined according to application needs. For example, the integrated design can simplify the external connection relationship of the isolated driver chip, such as the independent design facilitates the connection of the external circuit to the interface.

[0057] In summary, by integrating a small amount of related circuits (such as sampling circuits, comparison circuits, etc.) inside the isolation driver chip and partially reusing existing circuits (such as encoders, digital isolation, decoders, etc.), not only can the drive signal consistency check of the power device gate signal be achieved, but also a large amount of resources (such as hardware circuits, software functions, etc.) can be saved, reducing costs and simplifying the system structure.

[0058] Based on this, the present application proposes a PWM drive signal consistency check circuit solution: Figure 3 As shown, the aforementioned Figure 2The sampling, digital isolation transmission, comparison and other functional modules shown in the diagram are integrated and designed inside the isolation driver chip, among which the sampling circuit for sampling the gate signal is integrated and designed on the driving side of the isolation driver chip, and the encoder, digital isolator and decoder circuits that need to be isolated and fed back for the fault signal are reused to realize the isolated feedback of the sampling result from the driving side to the control side, and then the comparison circuit for comparing the sampling signal is integrated and designed on the control side of the isolation driver chip, and then after the decoder demodulates the sampling result, the comparison circuit compares the PWM drive signal for consistency, and the comparison result is returned to the controller as fault data for processing.

[0059] Some embodiments provided by the present application are described below in conjunction with the accompanying drawings.

[0060] like Figure 3 As shown, in the present invention, all sampling, feedback, and comparison are completed autonomously by the isolation driver chip, and the fault signal is directly transmitted to the controller (such as MCU), which greatly saves system cost and reduces system complexity.

[0061] like Figure 4 As shown, a functional block diagram of an isolation driver chip with an integrated PWM drive signal consistency check circuit is shown.

[0062] refer to Figure 4 Schematically, the PWM drive signal consistency check circuit includes: a gate voltage sampling circuit 301, a control logic redundancy unit 302, a delay matching unit 303 and a comparison filter circuit 304 (see Figure 4 medium-dark modules).

[0063] From the perspective of the driving side 103 , the gate voltage sampling circuit 301 directly samples the gate signal voltage of the power device 106 to obtain a driving side sampling result 305 , and sends it to the control side 101 together with the driving side fault 207 through the encoder 204 (i.e., the encoder is multiplexed for encoding).

[0064] From the control side 101, the decoder 206 of the control side decodes and obtains the control side sampling result 307, which is the real-time value of the drive output. At the same time, the PWM in-phase input 104 and the PWM inverting input 105 from the controller (such as MCU) pass through the control logic redundancy unit 302 and the delay matching unit 303 to obtain the reference signal 306, which is the theoretical value of the drive output. Finally, the comparison filter circuit 304 compares the control side sampling result 307 with the reference signal 306, that is, compares the real-time value of the drive output with the theoretical value, and obtains the PWM verification result 308.

[0065] The following is a schematic and supplementary description of the main modules in the PWM consistency check path circuit:

[0066] The gate voltage sampling circuit 301 can usually be implemented by a high voltage delay comparator to sample the output pin voltage and convert it into a digital value. Figure 5 As shown in FIG. 1 , a separate pin can be used to sample the driver output to obtain an accurate output voltage value.

[0067] The control logic redundancy unit 302 is identical to the control logic unit 201 and serves as a hardware backup to prevent PWM consistency check failure caused by an error in the control logic unit 201. Therefore, if the control logic unit 201 fails, the output of the control logic redundancy unit 302 will be different from the output of the control logic unit 201, and further different from the drive output 109. In this way, this abnormality can also be detected by the PWM drive signal consistency check circuit proposed by the present invention.

[0068] The delay matching unit 303 is used to match the delay caused by the feedback of the isolation drive output, gate voltage sampling, encoding and decoding circuits, and offset the impact of these delays on the verification circuit. In implementation, the circuit is mainly used to offset the sampling and transmission delays caused by the digital isolator 1 202, the drive logic unit 203, the gate voltage sampling circuit 301, the encoder 204, the digital isolator 2 205, and the decoder 206. In addition, the delay value can be set at 300-600ns, and the typical value can be about 500ns.

[0069] The comparison filter circuit 304 is implemented by a digital circuit, which compares the similarities and differences of the two digital signals. It can also have a certain filtering ability to prevent false fault triggering. In implementation, a digital circuit and a timer can be used to compare the reference signal 306 with the control side sampling result 307. If the reference signal is the same as the sampling result, the timer is in a reset state. If the reference signal is different from the sampling result, or the sampling result is in an abnormal state, the timer starts timing. In addition, if the timer timing exceeds the filtering time, it is considered that the PWM consistency check has detected a fault. The filtering time is mainly to prevent false faults, and can usually be set at 300-600ns, and the typical value can be about 500ns. With this setting, the PWM consistency check module can detect PWM transmission faults within 1us.

[0070] The encoder 204, the digital isolator 205 and the decoder 206 can reuse the hardware resources in the original basic isolation driver chip. Figure 1 In comparison, there is almost no additional cost.

[0071] The encoder 204 and the decoder 206 can use an improved pulse width modulation encoding method to simultaneously transmit the driver side fault and the gate level sampling result, which is simple to implement and fast.

[0072] In implementation, the new encoding and decoding method is as follows: the encoder 204 adopts a pulse width modulation encoding method, and correspondingly, the decoder 206 adopts a pulse width counting decoding method.

[0073] Specifically, a simple implementation method is as follows:

[0074] Use high level pulse width to encode and decode PG fault and NFLT fault:

[0075]

[0076] Use low level pulse width to encode and decode OUT_High and OUT_Low:

[0077]

[0078] In this way, the structure of the encoder-decoder is simple, the fault signal and the sampling signal are encoded and decoded using high-level and low-level pulse widths respectively, and the channel utilization rate is high and the speed is fast.

[0079] In addition, the gate voltage sampling circuit 301 is implemented as shown in FIG. Figure 5 Schematic diagram: VCC2 is the positive power supply of the isolated driver chip, and VEE2 is the negative power supply of the driver. GATEVCCH V is the gate-level high-level detection threshold, with a typical value of VCC2 -2.1V. GATEVEEL is the gate-level low-level detection threshold, and its typical value is VEE2 + 2.1V. The gate-level sampling circuit mainly uses an independent gate-level sampling pin and two high-voltage hysteresis comparators to realize the sampling function. One of the comparators compares the sampling voltage of the gate-level sampling pin with the gate-level high-level detection threshold to obtain the OUT_High signal, whose high level represents that the drive output is high; the other comparator compares the sampling voltage of the gate-level sampling pin with the gate-level low-level detection threshold to obtain the OUT_Low signal, whose high level represents that the drive output is low. Under normal circumstances, only one of OUT_High and OUT_Low will be high at the same time. If both are low or high at the same time, it means that the drive sampling is in an abnormal state.

[0080] In summary, the present invention proposes a PWM consistency check circuit for an isolated driver chip, which completely integrates the sampling, feedback, and comparison modules originally implemented by the system into the chip, and realizes simple, accurate, and fast verification through multiplexing encoding and decoding technology, greatly reducing the cost and complexity of the system.

[0081] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0082] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A PWM drive signal consistency check circuit, characterized in that: Integrated in the isolation driver chip, the PWM drive signal consistency check circuit includes: Gate voltage sampling circuit: integrated design on the driving side of the isolation driver chip, used to sample the voltage of the driving output signal output from the driving side of the isolation driver chip to the power device and form a sampling result; Multiplexed encoder: multiplex the encoder located on the drive side of the isolation driver chip to encode the sampling results; Multiplexing digital isolator: Multiplexing the digital isolator located in the isolation barrier inside the isolation driver chip to isolate and transmit the encoded sampling results from the driver side to the control side. Multiplexing decoder: multiplexing the decoder located at the control side of the isolation driver chip to decode the sampling results isolated and transmitted back by the digital isolator; Comparison filter circuit: integrated design on the control side inside the isolation driver chip, used to perform consistency check on the sampling result output by the decoder and the PWM signal input to the control side of the isolation driver chip, and when the sampling result output by the decoder is inconsistent with the PWM signal input to the control side of the isolation driver chip, the comparison result of the gate signal failure is output, otherwise the comparison result of the gate signal is normal is output.

2. The PWM drive signal consistency check circuit according to claim 1, characterized in that: The comparison filter circuit includes: a digital circuit and a timer. The digital circuit is used to determine whether the sampling result output by the decoder is the same as the PWM signal input to the control side of the isolation driver chip. If they are the same, the timer is reset; if they are not the same, the timer is started for timing.

3. The PWM drive signal consistency check circuit according to claim 2, characterized in that: The comparison filter circuit further includes: a control logic redundancy unit, which is a redundant unit corresponding to an existing control logic unit on the control side of the isolation driver chip, wherein an input of the control logic redundancy unit is the same as an input of the existing control logic unit, so as to: if the existing control logic unit fails, an output of the control logic redundancy unit is different from an output of the existing control logic unit, thereby detecting a failure of the existing control logic unit; And / or, the comparison filter circuit further includes: a delay matching unit, used for performing delay matching on the PWM signal input from the controller to the control side of the isolation driver chip, so as to match the transmission delay time of the sampling result relative to the PWM signal inside the isolation driver chip; And / or, the timer is configured as follows: if the timer timing exceeds a preset time, it is determined that a PWM consistency check detection failure occurs, otherwise the timer continues timing.

4. The PWM drive signal consistency check circuit according to claim 3, characterized in that: The preset time setting range is 300ns-600ns; And / or, the delay time setting range of the delay matching unit is 300ns-600ns.

5. The PWM drive signal consistency check circuit according to any one of claims 1 to 4, characterized in that: The gate voltage sampling circuit includes a first hysteresis comparator and a second hysteresis comparator, the non-inverting input terminal of the first hysteresis comparator and the non-inverting input terminal of the second hysteresis comparator are used to input the gate signal to be sampled, the inverting input terminal of the first hysteresis comparator is used to set the high level detection threshold, the output terminal of the first hysteresis comparator is used to output a first comparison result, the inverting input terminal of the second hysteresis comparator is used to set the low level detection threshold, and the output terminal of the second hysteresis comparator is used to output a second comparison result, wherein when the first comparison result is a high level, it indicates that the gate signal is high, and when the second comparison result is a high level, it indicates that the gate signal is low.

6. The PWM drive signal consistency check circuit according to claim 5, characterized in that: The multiplex encoder adopts pulse width modulation encoding method, and the multiplex decoder adopts pulse width counting decoding method.

7. The PWM drive signal consistency check circuit according to claim 6, characterized in that: The fault signal driven by the isolation driver chip is encoded and decoded using a high-level pulse width, and the first comparison result and the second comparison result are encoded and decoded using a low-level pulse width.

8. The PWM drive signal consistency check circuit according to claim 7, characterized in that: The fault signal includes the following signal types: a general alarm signal and a serious alarm signal; wherein, when both the general alarm signal and the serious alarm signal are fault-free, the pulse width using the high-level encoding method is set to the first width, and the pulse width count of the high-level decoding is set to the first count; when the general alarm signal is faulty and the serious alarm signal is fault-free, the pulse width using the high-level encoding method is set to the second width, and the pulse width count of the high-level decoding is set to the second count; when the general alarm signal is fault-free and the serious alarm signal is faulty, the pulse width using the high-level encoding method is set to the third width, and the pulse width count of the high-level decoding is set to the third count; when both the general alarm signal and the serious alarm signal are faulty, the pulse width using the high-level encoding method is set to the fourth width, and the pulse width count of the high-level decoding is set to the fourth count; And / or, when the first comparison result and the second comparison result are both low levels, the pulse width of the low-level encoding method is set to the fifth width, and the pulse width count of the high-level decoding method is set to the fifth count; when the first comparison result is a low level and the second comparison result is a high level, the pulse width of the low-level encoding method is set to the sixth width, and the pulse width count of the low-level decoding method is set to the sixth count; when the first comparison result is a high level and the second comparison result is a low level, the pulse width of the low-level encoding method is set to the seventh width, and the pulse width count of the low-level decoding method is set to the seventh count; when the first comparison result and the second comparison result are both high levels, the pulse width of the low-level encoding method is set to the eighth width, and the pulse width count of the low-level decoding method is set to the eighth count.

9. The PWM drive signal consistency check circuit according to claim 8, characterized in that: The first width and / or the fifth width is set to 3 clock cycles, and the first count and / or the fifth count is set to 2-4 clock cycles; the second width and / or the sixth width is set to 6 clock cycles, and the second count and / or the sixth count is set to 5-7 clock cycles; the third width and / or the seventh width is set to 9 clock cycles, and the third count and / or the seventh count is set to 8-10 clock cycles; the fourth width and / or the eighth width is set to 12 clock cycles, and the fourth count and / or the eighth count is set to 11-13 clock cycles.

10. An isolation driver chip, comprising a control logic unit, a digital isolator 1, a drive logic unit, an encoder, a digital isolator 2, and a decoder, wherein the PWM signal is input to the control logic unit for processing, and then transmitted to the drive logic unit via the digital isolator 1, and then processed by the drive logic unit as a gate signal of a power device to be driven, characterized in that: The isolation drive chip also includes: a verification circuit, which is a PWM drive signal consistency verification circuit as described in any one of claims 1 to 9, wherein the PWM signal is input into the verification circuit at the same time as the input control logic unit, and the verification circuit is used to compare the PWM signal and the feedback sampling result to form a consistency verification result output, and the feedback sampling result is a sampling result obtained by sampling the gate signal through the gate signal sampling circuit of the verification circuit, encoding by the multiplexing encoder, isolation feedback by the multiplexing digital isolator 2, and decoding by the multiplexing decoder.

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