High-performance full-precision in-memory search method and device oriented to ultra-long dimension vector sorting

Abstract

The invention provides a high-performance full-precision in-memory search method and device oriented to ultra-long dimension vector sorting, and the method comprises the steps: firstly carrying out the first search operation on each segment of input feature data, and judging whether the Hamming distance between the input feature data and the corresponding segment of storage data is within a computable range or not; and when the second search operation is carried out, if the Hamming distance is within the calculable range during the first search operation, the segment input feature data are not changed, otherwise, the segment input feature data are negated bit by bit, and then the Hamming distance between the current segment input feature data and the segment storage feature data is calculated. The Hamming distance of each segment of input feature data and the Hamming distance of the corresponding segment of storage feature data are fused, the matching number result of comparison between the ultra-long-dimension input feature vector data and the storage category data can be calculated, and low-difference ultra-long-dimension vector similarity sorting is achieved.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit design, and in particular to a high-performance full-precision in-memory search method and device for sorting very long dimensional vectors. Background Art

[0002] The rapid development of big data-driven applications and the dramatic increase in data volume have brought about the storage wall problem to traditional computing architectures, that is, the data transmission bottleneck between storage units and computing units. In order to overcome this problem, in-memory computing technology has emerged. In-memory computing eliminates the bottleneck of data transmission by directly integrating computing operations into storage units, improving computing efficiency and system performance. This technology solves the storage wall problem under the von Neumann architecture, enabling storage and computing to be performed simultaneously, greatly improving data processing speed.

[0003] However, when applying in-memory computing design to perform classification tasks, the exact matching or threshold matching of each vector segment may affect the reasoning accuracy of the entire circuit. In particular, when the number of categories increases, the traditional in-memory search design method may have difficulty accurately distinguishing input data with extremely low Hamming distance. In traditional in-memory search design, there are problems with exact matching and threshold matching, especially when there are many categories, small vector differences may be ignored. This may lead to classification errors or inaccurate recognition results.

[0004] These challenges indicate that in the design of in-memory computing, especially when processing large-scale data, it is necessary to consider how to effectively distinguish tiny differences between multiple categories of ultra-long dimensional vectors to ensure accurate classification and inference results, which will have a significant impact on the performance and accuracy of the system. Summary of the invention

[0005] The purpose of the present invention is to provide a high-performance, fully accurate in-memory search method and device for ultra-long dimensional vector sorting, which can calculate the number of matches between ultra-long dimensional input feature vector data and stored category data, and achieve low-difference ultra-long dimensional vector similarity sorting.

[0006] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0007] In a first aspect, the present invention discloses a high-performance fully accurate in-memory search method for sorting very long dimensional vectors, the high-performance fully accurate in-memory search method comprising the following steps:

[0008] In the process of counting the number of matches of the ultra-long dimensional vector, when searching for input feature data of length M bits in the memory, a first search operation is performed on each segment of the M-bit input feature data to determine whether the Hamming distance with the corresponding segment of the stored data is within a computable range;

[0009] If the Hamming distance is within the distinguishable range, the number of matches is greater than The second search operation maintains the original input feature data; if the Hamming distance is not within the distinguishable range, the number of matches is determined to be less than or equal to The second search operation inverts the original input feature data bit by bit, and then calculates the Hamming distance between the current segment input feature data and the segment storage feature data;

[0010] The Hamming distance between each segment of input feature data and the corresponding segment of stored feature data is integrated to calculate the number of matches between the ultra-long dimensional input feature vector data and the stored category data; wherein, the maximum calculable Hamming distance between each segment of input feature data and the corresponding segment of stored data in any search operation is

[0011] Furthermore, an array circuit is used to store and search the input feature data, which specifically includes the following steps:

[0012] Constructing a memory cell array of N rows and M columns, wherein each memory cell in the same row is connected to the same word line, each memory cell in the same column is connected to the same bit line, and each memory cell in each column is connected to the matching line through a search circuit;

[0013] When searching for input feature data in memory, the matching line appears after each segment of input feature data is searched once. If the input characteristic data is not inverted, the matching number range corresponding to the voltage from high to low after the matching line is discharged is M to If the input characteristic data is inverted, the matching number corresponding to the voltage from high to low after the matching line is discharged ranges from 0 to

[0014] After obtaining the result of the first search operation, if the voltage maintained after the match line is discharged is not the lowest, the Hamming distance is within the distinguishable range; if the voltage maintained after the match line is discharged is the lowest, the Hamming distance is not within the distinguishable range.

[0015] Furthermore, the process of completing the matching number statistics of the input feature data and the corresponding segment storage data includes the following steps:

[0016] After the first search, A precharge read amplifier circuit samples the voltage value maintained by the match line to generate bit coded signal;

[0017] according to The bit-coded signal generates a control signal for performing a logic operation with the input feature data of the current segment, and according to the result of judging whether the Hamming distance is within the calculable range, the input feature data is bit-inverted or unchanged;

[0018] Output The number of matches of the input feature data is represented in the form of a bit binary digital signal, and the number of matches of each segment of input feature data is counted during the validity period of the search result data of the segment of input feature data.

[0019] In a second aspect, the present invention discloses a high-performance full-precision in-memory search device for ultra-long dimensional vector sorting, characterized in that the high-performance full-precision in-memory search device comprises a register, an N-bit decoder, an array circuit module, a coding control output module and a summary module;

[0020] The register is equal in length to the input feature data and is used to store external input feature data of M bits each time;

[0021] The N-bit decoder is used to generate a row selection signal;

[0022] The array circuit module stores the N*M dimensional storage long vector in N rows and M columns;

[0023] The coding control output module receives M bits of input feature data serially outputted in N working cycles, and completes the matching number statistics of the input feature data through two consecutive search operation cycles for each segment of input feature data;

[0024] The summary module counts the number of matches on the input long vector of N*M dimensions after 2N search operation cycles.

[0025] Furthermore, the array circuit module includes N rows and M columns of storage cells; wherein each storage cell in the same row is connected to the same word line, each storage cell in the same column is connected to the same bit line, and each column of storage cells is connected to the matching line through a search circuit;

[0026] When searching for input feature data in memory, the matching line appears after each segment of input feature data is searched once. If the input characteristic data is not inverted, the matching number range corresponding to the voltage from high to low after the matching line is discharged is M to If the input characteristic data is inverted, the matching number corresponding to the voltage from high to low after the matching line is discharged ranges from 0 to

[0027] After obtaining the result of the first search operation, if the voltage maintained after the match line is discharged is not the lowest, the Hamming distance is within the distinguishable range; if the voltage maintained after the match line is discharged is the lowest, the Hamming distance is not within the distinguishable range.

[0028] Furthermore, the coding control output module includes a coding module, a control module and an output module

[0029] The encoding module consists of A pre-charged read amplifier circuit and D latches; in each search cycle, after the search is completed, A precharge read amplifier circuit samples the voltage value maintained by the match line to generate bit coded signal, D latches are sent to the control module; after the first search is completed, if the number of matches is And below, The bit-coded signal is all 0, otherwise There is 1 in the bit-coded signal;

[0030] The control module outputs the first post-search encoding module according to The bit-coded signal generates a control signal for performing a logic operation with the current input feature data, and according to the result of judging whether the Hamming distance is within the calculable range, the input feature data is bit-inverted or unchanged;

[0031] The output module receives the output of the encoding module The bit coded signal and the control signal output by the control module are output in The current segment length represented in the form of a bit binary digital signal is the number of matches for the M-bit input feature data.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The high-performance, fully accurate in-memory search method and device for ultra-long dimensional vector sorting of the present invention can calculate the number of matches between ultra-long dimensional input feature vector data and stored category data, and achieve low-difference ultra-long dimensional vector similarity sorting. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of a basic storage unit provided by an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of a search operation on a single storage unit provided by an embodiment of the present invention;

[0036] Figure 3A diagram of a storage array architecture with a word length of 8 bits provided in an embodiment of the present invention;

[0037] Figure 4 A schematic diagram of a coding control output module provided in an embodiment of the present invention;

[0038] Figure 5 A memory timing definition diagram provided by an embodiment of the present invention;

[0039] Figure 6 An in-memory search architecture diagram for an embodiment of the present invention that provides a comparison word length of 8 bits and implements matching number statistics for a type of input data;

[0040] Figure 7 A flow chart of a high-performance, fully accurate in-memory search method for sorting very long dimensional vectors provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0042] See also Figure 7 The present invention discloses a high-performance full-precision in-memory search method for sorting ultra-long dimensional vectors, the high-performance full-precision in-memory search method comprising the following steps:

[0043] In the process of counting the number of matches of the ultra-long dimensional vector, when searching for input feature data of length M bits in the memory, a first search operation is performed on each segment of the M-bit input feature data to determine whether the Hamming distance with the corresponding segment of the stored data is within a computable range;

[0044] If the Hamming distance is within the distinguishable range, the number of matches is greater than The second search operation maintains the original input feature data; if the Hamming distance is not within the distinguishable range, the number of matches is determined to be less than or equal to The second search operation inverts the original input feature data bit by bit, and then calculates the Hamming distance between the current segment input feature data and the segment storage feature data;

[0045] The Hamming distance between each segment of input feature data and the corresponding segment of stored feature data is integrated to calculate the number of matches between the ultra-long dimensional input feature vector data and the stored category data; wherein, the maximum calculable Hamming distance between each segment of input feature data and the corresponding segment of stored data in any search operation is

[0046] The method comprises:

[0047] Step S101, constructing storage units under the matching line.

[0048] In this step, the magnetic tunnel junction is used as an example to store the stored data through the magnetic tunnel junction device. One bit of data is stored using two magnetic tunnel junctions. This method can not only effectively store information, but also has high reliability and stability. By using the pre-charge search signal method, the magnetic tunnel junctions in different states can be effectively distinguished, thereby constructing the basic storage unit structure. Figure 1 , Figure 1 This is a basic storage unit diagram.

[0049] Step S102, constructing a search circuit for the storage unit.

[0050] In this step, the storage unit is searched using a latch structure composed of a pre-charged N-channel field effect transistor, see Figure 2 , Figure 2 This is a schematic diagram of the search operation for a single storage cell. The input data is a pair of complementary SL and SLB signals. When the PRE signal is at a low level, VDD charges the Q and QB points. When the PRE signal is at a high level, it indicates that the charging is completed. At this time, the Q and QB points begin to discharge through N1 and N2. Since the magnetic tunnel junctions of the two discharge paths are in different high and low resistance states, there will be differences in discharge speed. The voltage on the branch with faster discharge will drop to '0' first, and the branch with slower discharge will be cut off from discharge. In this process, one of Q and QB will be '0', and the other will maintain a certain voltage value.

[0051] The role of N9 and N10 is to set a suitable VON voltage value and utilize the cut-off characteristics of the field effect tube to make N9 or N10 of the branch where the Q or QB point maintains a higher voltage in the cut-off state, and N9 or N10 of the branch where the voltage is lower in the non-cut-off state. In this way, the voltage difference between N9 and N10 can be controlled, thereby affecting the discharge speed and the final output state.

[0052] After the above process is completed, the SAMPLE signal will be set to a high level. If the match line discharges, it is considered a mismatch, and if the match line does not discharge, it is considered a match. The operation of this stage controls the behavior of the discharge path and combines the voltage and current changes between various components to achieve the search and judgment of the storage cell state.

[0053] The implementation of this technology can improve the accuracy and efficiency of data search, retrieval and writing. It shows how to use this pre-charging technology to distinguish between magnetic tunnel junctions in different states, thereby achieving reliable data storage and retrieval.

[0054] Step S103, completing the search process for an M-bit comparison word.

[0055] In this step, taking M=8 as an example, a storage cell structure of 1 row and 8 columns and 8 corresponding search circuit structures are mounted on a matching line to perform a search. Figure 3 , Figure 3 This is a diagram of a memory array architecture with a word length of 8 bits. The structure shows how these memory cells are connected under the match line for search.

[0056] Encoding control output module see Figure 4 , Figure 4 Schematic diagram of the coding control output module. In this step, the comparison word length of 8 bits is still taken as an example. The coding control output module takes the match line as input, the matching number Q<0:3> of the current search data and a control signal ReInput as output.

[0057] At the end of each search cycle, the coding control output module circuit will compare according to the voltage value maintained by the match line, encode the comparison result D<0:3>, and generate a 4-bit coding signal M<0:3>.

[0058] The control signal ReInput is an enable signal for determining whether the input feature data is bit-inverted during the second search operation. If the coding signals M<0:3> are all 0 at the end of the first search cycle, it means that the input feature data needs to be bit-inverted during the second search operation. If the coding signals M<0:3> are not all 0 at the end of the first search cycle, it means that the input feature data does not need to be bit-inverted during the second search operation, and the original input feature data is maintained.

[0059] At the end of the first search cycle, the coding control output module circuit generates a control signal ReInput according to the 4-bit coding signal M<0:3>; at the end of the second search cycle, the coding control output module circuit performs combinational logic according to the 4-bit coding signal M<0:3> and the control signal ReInput to generate a 4-bit binary signal Q<0:3> indicating the number of matches of the current input 8-bit comparison word;

[0060] The complete memory timing definition in this step is shown in Figure 5 , Figure 5 Therefore, it takes two search cycles to complete the search operation for a comparison word. The data validity period is after the search time in the second search cycle. The output Q<0:3> of the encoding control output module indicates the number of matches of the current 8-bit comparison word.

[0061] Step S104, completing the in-memory search architecture for matching statistics of the N×M dimensional long vector.

[0062] In this step, we take the implementation of the matching number statistics of a class of ultra-long dimensional vectors with M=8 as an example. The principle of the in-memory search architecture is shown in Figure 6 , Figure 6 This is a diagram of the in-memory search architecture for a comparison word length of 8 bits and for matching number statistics for a type of input data. It includes a complete search circuit, a coding control output module MRPM, and some peripheral circuit decoders, I / O buffers, and a Merge summary module for matching numbers.

[0063] The register is equal in length to the input feature data and is used to store the M (here 8) bit comparison word data input from the I / O port. In each clock cycle, the register gradually receives and stores the 8-bit comparison word data from the I / O port.

[0064] The N-bit decoder is used to generate the 2 N The decoder is responsible for decoding the input address signal and generating a corresponding row select signal to select the enable of a specific row in the array. The input of the N-bit decoder is an address signal with a length of N bits. According to different address signal combinations, the decoder will activate the corresponding row select signal accordingly. In the system, the address signal of this N-bit decoder is updated every two search cycles. This means that after every two search cycles, the address signal will change, and the decoder will generate a new row select signal accordingly. This update frequency ensures the synchronization of the address signal and the row select signal, so that the data in the array can be selected and processed according to the correct address.

[0065] The input of the Merge module is (Here is a 4-bit binary signal, and the output is a binary form corresponding to the final number of matches of the input data. This summary module is used to count the number of matches in a class of input data. In the form of a pipeline, the output of the MRPM coding control output module is counted in sequence in the form of a pipeline of N clock cycles. This means that in each clock cycle, the matching results of each input feature data are counted in sequence in accordance with the pipeline order. The output of the MRPM coding control output module is sequentially counted through the data full addition operation. (Here is 4)-bit binary data full addition operation. Update and store calculation results: According to the input order of the pipeline, in each data validity period, the currently calculated matching result is updated and stored as the number of matches in a class of input vectors. After N data validity periods, the matching results are gradually calculated and updated, and finally the number of matches in a class of input data is obtained.

[0066] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0067] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0068] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0069] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0070] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0071] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A high-performance fully accurate in-memory search method for sorting very long dimensional vectors, characterized in that: The high-performance fully accurate in-memory search method comprises the following steps: In the process of counting the number of matches of the ultra-long dimensional vector, when searching for input feature data of length M bits in the memory, a first search operation is performed on each segment of the M-bit input feature data to determine whether the Hamming distance with the corresponding segment of the stored data is within a computable range; If the Hamming distance is within the distinguishable range, the number of matches is greater than The second search operation maintains the original input feature data; if the Hamming distance is not within the distinguishable range, the number of matches is determined to be less than or equal to The second search operation inverts the original input feature data bit by bit, and then calculates the Hamming distance between the current segment input feature data and the segment storage feature data; The Hamming distance between each segment of input feature data and the corresponding segment of stored feature data is integrated to calculate the number of matches between the ultra-long dimensional input feature vector data and the stored category data; wherein, the maximum calculable Hamming distance between each segment of input feature data and the corresponding segment of stored data in any search operation is 2. The high-performance full-precision in-memory search method for sorting very long dimensional vectors according to claim 1, characterized in that: The array circuit is used to store and search the input feature data, which specifically includes the following steps: Constructing a memory cell array of N rows and M columns, wherein each memory cell in the same row is connected to the same word line, each memory cell in the same column is connected to the same bit line, and each memory cell in each column is connected to the matching line through a search circuit; When searching for input feature data in memory, the matching line appears after each segment of input feature data is searched once. If the input characteristic data is not inverted, the matching number range corresponding to the voltage from high to low after the matching line is discharged is M to If the input characteristic data is inverted, the matching number corresponding to the voltage from high to low after the matching line is discharged ranges from 0 to After obtaining the result of the first search operation, if the voltage maintained after the match line is discharged is not the lowest, the Hamming distance is within the distinguishable range; if the voltage maintained after the match line is discharged is the lowest, the Hamming distance is not within the distinguishable range.

3. The high-performance full-precision in-memory search method for sorting very long dimensional vectors according to claim 1, characterized in that: The process of completing the matching number statistics of input feature data compared with the corresponding segment storage data includes the following steps: After the first search, A precharge read amplifier circuit samples the voltage value maintained by the match line to generate bit coded signal; according to The bit-coded signal generates a control signal for performing a logic operation with the input feature data of the current segment, and according to the result of judging whether the Hamming distance is within the calculable range, the input feature data is bit-inverted or unchanged; Output The number of matches of the input feature data is represented in the form of a bit binary digital signal, and the number of matches of each segment of input feature data is counted during the validity period of the search result data of the segment of input feature data.

4. A high-performance fully accurate in-memory search device for sorting very long dimensional vectors, characterized in that: The high-performance fully accurate in-memory search device comprises a register, an N-bit decoder, an array circuit module, a coding control output module and a summarization module; The register is equal in length to the input feature data and is used to store external input feature data of M bits each time; The N-bit decoder is used to generate a row selection signal; The array circuit module stores the N*M dimensional storage long vector in N rows and M columns; The coding control output module receives M bits of input feature data serially outputted in N working cycles, and for each segment of input feature data, uses the method as claimed in claim 1 to complete the matching number statistics of the input feature data through two consecutive search operation cycles; The summary module counts the number of matches on the input long vector of N*M dimensions after 2N search operation cycles.

5. The high-performance full-precision in-memory search device for sorting very long dimensional vectors according to claim 4, characterized in that: The array circuit module comprises N rows and M columns of storage cells; wherein each storage cell in the same row is connected to the same word line, each storage cell in the same column is connected to the same bit line, and each column of storage cells is connected to the matching line through a search circuit; When searching for input feature data in memory, the matching line appears after each segment of input feature data is searched once. If the input characteristic data is not inverted, the matching number range corresponding to the voltage from high to low after the matching line is discharged is M to If the input characteristic data is inverted, the matching number corresponding to the voltage from high to low after the matching line is discharged ranges from 0 to After obtaining the result of the first search operation, if the voltage maintained after the match line is discharged is not the lowest, the Hamming distance is within the distinguishable range; if the voltage maintained after the match line is discharged is the lowest, the Hamming distance is not within the distinguishable range.

6. The high-performance full-precision in-memory search device for sorting very long dimensional vectors according to claim 4, characterized in that: The coding control output module includes a coding module, a control module and an output module The encoding module consists of A pre-charged read amplifier circuit and D latches; in each search cycle, after the search is completed, A precharge read amplifier circuit samples the voltage value maintained by the match line to generate bit coded signal, D latches are sent to the control module; after the first search is completed, if the number of matches is And below, The bit-coded signal is all 0, otherwise There is 1 in the bit-coded signal; The control module outputs the first post-search encoding module according to The bit-coded signal generates a control signal for performing a logic operation with the current input feature data, and according to the result of judging whether the Hamming distance is within the calculable range, the input feature data is bit-inverted or unchanged; The output module receives the output of the encoding module The bit coded signal and the control signal output by the control module are output in The current segment length represented in the form of a bit binary digital signal is the number of matches for the M-bit input feature data.

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