Display panel and display device

Abstract

The present application relates to a display panel and a display device; a first metal layer is arranged on one side of a substrate, and the first metal layer includes a plurality of first fan-out lines located in a display area of ​​the display panel; a second metal layer is arranged on a side of the first metal layer away from the substrate, and the second metal layer includes a plurality of first data lines corresponding to at least some of the plurality of first fan-out lines; wherein, a plurality of first contact holes corresponding to the plurality of first data lines are opened in the display panel, the first data lines extend into the first contact holes and are connected to the pixel driving circuit, and the first fan-out lines extend into the first contact holes and are connected to the corresponding first data lines; the present application can reduce the load of the first fan-out lines and increase the wiring space in the display panel, so that the spacing between the signal lines becomes larger, the probability of short circuit between the signal lines is reduced, and the stability of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to better achieve a narrow bezel for display products, the related technology adopts the technology of setting part of the fan-out lines in the display area (Fanout in aa, FIAA). FIAA sets part of the fan-out lines in the display area, structurally saving the fan-out area wiring space required for the lower bezel, and further compressing the lower bezel.

[0003] Currently, if Figure 1 As shown, in a display panel with a FIAA architecture, in order to connect the laterally extending fan-out trace FIAA with the data line DATA, a lap protrusion TU is often reserved on the data line DATA and connected to the laterally extending fan-out trace FIAA through a sleeve hole, and the data line DATA is connected to the semiconductor layer BA through a contact hole KO at the position of the switching transistor; this will increase the load of the laterally extending fan-out trace FIAA and reduce the spacing between the traces, thereby increasing the risk of short circuit between the traces. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a display device, which reduce the load of a first fan-out line, increase wiring space, and reduce the probability of a short circuit.

[0005] An embodiment of the present application provides a display panel, comprising a plurality of pixel regions and a plurality of pixel driving circuits arranged corresponding to the plurality of pixel regions;

[0006] The display panel further includes:

[0007] substrate;

[0008] a first metal layer disposed on one side of the substrate, the first metal layer comprising a plurality of first fan-out lines located in a display area of ​​the display panel;

[0009] a second metal layer disposed on a side of the first metal layer away from the substrate, the second metal layer comprising a plurality of first data lines correspondingly connected to at least some of the plurality of first fan-out lines;

[0010] Among them, the display panel is provided with multiple first contact holes corresponding to multiple first data lines, the first data lines extend into the first contact holes and are connected to the pixel driving circuit, and the first fan-out lines extend into the first contact holes and are connected to the corresponding first data lines.

[0011] In one embodiment of the present application, the pixel driving circuit includes a switching transistor, and the display panel further includes:

[0012] A semiconductor layer is provided between the substrate and the first metal layer. The semiconductor layer includes a switch active portion of the switch transistor. The first data line extends into the first contact hole and is connected to the switch active portion.

[0013] In one embodiment of the present application, the plurality of pixel areas are arranged along a first direction and a second direction, the first direction and the second direction intersect, the plurality of first data lines are arranged along the first direction, the first data lines extend along the second direction, and the switch active portion extends along the second direction;

[0014] The fan-out line includes the first fan-out line segment extending along the first direction, the orthographic projection of the first fan-out line segment on the substrate overlaps with the orthographic projection of the corresponding first data line on the substrate, and the orthographic projection of the switch active portion on the substrate partially overlaps with the orthographic projection of the corresponding first data line on the substrate.

[0015] In one embodiment of the present application, the fan-out line also includes a second fan-out line segment extending along the second direction, one end of the second fan-out line segment is connected to the first fan-out line segment, and the other end of the second fan-out line segment extends into the first contact hole and is connected to the corresponding first data line.

[0016] In one embodiment of the present application, the second fan-out line segment at least partially overlaps with the switch active portion along the second direction, and the orthographic projection of the second fan-out line segment on the substrate partially overlaps with the orthographic projection of the first data line on the substrate.

[0017] In one embodiment of the present application, the pixel driving circuit further includes a driving transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first node, a second node, a third node, and a fourth node;

[0018] the semiconductor layer including a driving active portion of the driving transistor, a first light emission control active portion of the first light emission control transistor, a second light emission control active portion of the second light emission control transistor, a first reset active portion of the first reset transistor, a second reset active portion of the second reset transistor, and a third reset active portion of the third reset transistor;

[0019] Among them, the first light-emitting control active part extends along the second direction and is connected to the switch active part at the first node, one end of the driving active part is connected to the first node, and the other end of the driving active part along the first direction is connected to the second node, the first reset active part and the second light-emitting control active part are located on opposite sides of the second node along the second direction and are both connected to the second node, the side of the second light-emitting control active part away from the second node is connected to the third node, the third reset active part is connected to the third node, the second reset active part is located along the second direction on the side of the first reset active part away from the second node, and the end of the first reset active part away from the second node is connected to the second reset active part and to the fourth node, and the gate of the driving active part is electrically connected to the fourth node.

[0020] In one embodiment of the present application, the first metal layer further includes a first control signal line extending along the first direction, an orthographic projection of the first control signal line on the substrate overlaps with an orthographic projection of the switch active portion on the substrate, and an orthographic projection of the first control signal line on the substrate overlaps with an orthographic projection of the first reset active portion on the substrate;

[0021] The orthographic projection of the first contact hole on the substrate is located between the orthographic projection of the first fan-out line segment on the substrate and the orthographic projection of the first control signal line on the substrate.

[0022] In one embodiment of the present application, the first metal layer further includes a first reset signal line extending along the first direction, the first reset signal line is connected to the second reset active portion, and the first fan-out line segment is located between the first control signal line and the first reset signal line.

[0023] In one embodiment of the present application, the display panel further includes:

[0024] a third metal layer, disposed between the second metal layer and the first metal layer, the third metal layer comprising a second fan-out line, one end of the first fan-out line segment being connected to the second fan-out line segment, and the other end of the first fan-out line segment being connected to the second fan-out line;

[0025] a signal terminal disposed in a non-display area of ​​the display panel, wherein one end of the second fan-out line is connected to the first fan-out line segment, and the other end of the second fan-out line is connected to the signal terminal;

[0026] The second fan-out line extends along the second direction, and an orthographic projection of the second fan-out line on the substrate is located between an orthographic projection of the switch active portion on the substrate and an orthographic projection of the first reset active portion on the substrate.

[0027] In an embodiment of the present application, corresponding to the same pixel area, the first node and the second node are located on opposite sides of the second fan-out line, and the second node, the third node and the fourth node are located on the same side of the second fan-out line.

[0028] In one embodiment of the present application, the third metal layer also includes a second data line extending along the second direction, the switch active portion in part of the pixel driving circuit is connected to the first data line, and the switch active portion in another part of the pixel driving circuit is connected to the second data line.

[0029] In one embodiment of the present application, some of the plurality of first fan-out lines are connected to the second data line;

[0030] The display panel further includes a second contact hole corresponding to the second data line, the second data line is connected to the switch active portion through the second contact hole, and the first fan-out line extends into the second contact hole and is connected to the second data line.

[0031] In one embodiment of the present application, in the second contact hole, the first fan-out line covers a side of the switch active portion away from the substrate, and the second data line covers a side of the first fan-out line away from the switch active portion.

[0032] In one embodiment of the present application, in the first contact hole, the first fan-out line covers a side of the switch active portion away from the substrate, and the first data line covers a side of the first fan-out line away from the switch active portion.

[0033] In an embodiment of the present application, in two adjacent pixel areas along the first direction, the corresponding two pixel driving circuits are arranged in an axisymmetric manner.

[0034] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a display device, which includes the display panel.

[0035] An embodiment of the present application provides a display panel and a display device, wherein a first fan-out line is extended into a first contact hole between a first data line and a pixel driving circuit and connected to the first data line to achieve signal transmission, without requiring additional overlapping protrusions and sleeve holes to be provided on the corresponding data line. This can reduce the load on the first fan-out line and increase the wiring space in the display panel, thereby increasing the spacing between signal lines, reducing the probability of short circuits between signal lines, and improving the stability of the display panel.

[0036] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0038] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0039] Figure 1 A schematic diagram of a planar wiring distribution structure of a display panel provided by an embodiment;

[0040] Figure 2 A schematic diagram of a planar distribution structure of a display panel provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of a connection structure between a first fan-out line and a first data line provided in an embodiment of the present application;

[0042] Figure 4 Provided in the embodiments of this application Figure 3 Schematic diagram of the cross-section structure taken along line aa;

[0043] Figure 5 A circuit structure diagram of a pixel driving circuit provided in an embodiment of the present application;

[0044] Figure 6 Provided in the embodiments of this application Figure 2 A schematic diagram of a planar distribution structure of a pixel driving circuit at position Z in the middle;

[0045] Figure 7 A schematic diagram of a planar distribution structure of a semiconductor layer provided in an embodiment of the present application;

[0046] Figure 8A schematic diagram of a planar distribution structure of the second metal layer and the third metal layer provided in an embodiment of the present application;

[0047] Figure 9 Schematic diagram of a connection structure between the first fan-out line and the second data line in an embodiment of the present application.

[0048] Description of reference numerals:

[0049] 10. Substrate; 101. Display area; 102. Non-display area; 1101. Pixel area; 11. Pixel driving circuit; 12. First spacer layer; 13. Second spacer layer; 14. Third spacer layer;

[0050] 20. Semiconductor layer; 201. First contact hole; 202. Second contact hole; 21. Switch active portion; 22. Driving active portion; 23. First light-emitting control active portion; 24. First reset active portion; 25. Second light-emitting control active portion; 26. Second reset active portion; 27. Third reset active portion;

[0051] 30. First metal layer; 31. First fan-out line; 311. First fan-out line segment; 312. Second fan-out line segment; 32. First control signal line; 33. First reset signal line; 34. Second reset signal line; 35. Second control signal line; 36. Power signal line;

[0052] 40. Second metal layer; 41. First data line;

[0053] 50. Third metal layer; 51. Second fan-out line; 52. Second data line; 53. Transfer portion;

[0054] 60. Gate layer; 61. Light-emitting control signal line; 62. Gate; 63. Connecting portion;

[0055] 70. Signal terminal. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0057] Please combine Figure 2 、 Figure 3 as well as Figure 4 An embodiment of the present application provides a display panel, which includes a plurality of pixel areas 1011 and a plurality of pixel driving circuits 11 arranged corresponding to the plurality of pixel areas 1011.

[0058] The display panel also includes a substrate 10, a first metal layer 30 and a second metal layer 40; the first metal layer 30 is arranged on one side of the substrate 10, and the first metal layer 30 includes a plurality of first fan-out lines 31 located in the display area 101 of the display panel; the second metal layer 40 is arranged on the side of the first metal layer 30 away from the substrate 10, and the second metal layer 40 includes a plurality of first data lines 41 correspondingly connected to the plurality of first fan-out lines 31.

[0059] In which, the display panel is provided with multiple first contact holes 201 corresponding to multiple first data lines 41, the first data lines 41 extend into the first contact holes 201 and are connected to the pixel driving circuit 11, and the first fan-out lines 31 extend into the first contact holes 201 and are connected to the corresponding first data lines 41.

[0060] During the implementation and application process, the embodiment of the present application enables the first fan-out line 31 to extend into the first contact hole 201 of the first data line 41 and the pixel driving circuit 11, and be connected to the first data line 41 to realize signal transmission, and there is no need to additionally set up overlapping protrusions and sleeve holes for the corresponding data lines. This can reduce the load of the first fan-out line 31 and increase the wiring space in the display panel, so that the spacing between the signal lines becomes larger, reducing the probability of short circuits between the signal lines and improving the stability of the display panel.

[0061] Specifically, please continue to combine Figure 2 、 Figure 3 as well as Figure 4 The display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101; a plurality of pixel areas 1011 are arranged in the display area 101, and the plurality of pixel areas 1011 can be arranged in an array along a first direction X and a second direction Y, and the first direction X intersects the second direction Y.

[0062] In some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0063] Furthermore, the display panel includes a substrate 10 and a thin film transistor layer disposed on the substrate 10 , and the thin film transistor layer includes a semiconductor layer 20 , a gate layer, a first metal layer 30 , a second metal layer 40 and a third metal layer 50 disposed on the substrate 10 .

[0064] In some embodiments, the first metal layer 30 is located on the side of the semiconductor layer 20 away from the substrate 10, the second metal layer 40 is located on the side of the first metal layer 30 away from the semiconductor layer 20, and the third metal layer 50 is located between the first metal layer 30 and the second metal layer 40; the display panel also includes a first spacer layer 12 arranged between the semiconductor layer 20 and the first metal layer 30, a second spacer layer 13 arranged between the first metal layer 30 and the third metal layer 50, and a third spacer layer 14 arranged between the third metal layer 50 and the second metal layer 40.

[0065] It can be understood that the gate layer can be located between the semiconductor layer 20 and the substrate 10; or the gate layer is located between the semiconductor layer 20 and the first metal layer 30; or the gate layer includes a first gate sublayer and a second gate sublayer, and the first gate sublayer is located between the semiconductor layer 20 and the substrate 10, and the second gate sublayer is located between the semiconductor layer 20 and the first metal layer 30; or the gate layer includes a first gate sublayer and a second gate sublayer, and both the first gate sublayer and the second gate sublayer are located between the semiconductor layer 20 and the first metal layer 30.

[0066] In the embodiment of the present application, the second metal layer 40 includes a plurality of first data lines 41 arranged along the first direction, each of the first data lines 41 extends along the second direction Y, and each of the data lines 41 transmits a signal to a corresponding column of pixel areas 1011 arranged along the second direction Y.

[0067] It should be noted that the display panel provided in the embodiment of the present application adopts the FIAA architecture, that is, the fan-out line connecting the first data line 41 is arranged in the display area 101 to achieve a narrow frame; wherein, the first metal layer 30 includes multiple first fan-out lines 31, the third metal layer 50 includes multiple second fan-out lines 51, and at least part of the first fan-out lines 31 extends along the first direction X, the second fan-out lines 51 can extend along the second direction Y, and one first fan-out line 31 is connected to one second fan-out line 52, and the connected first fan-out line 31 and one second fan-out line 52 are connected to a corresponding first data line 41.

[0068] In some embodiments, the display panel also includes a signal terminal 70 arranged in the non-display area 102, and one end of the second fan-out line 52 is connected to the signal terminal 61, the other end of the second fan-out line 51 is connected to the first fan-out line 31, one end of the first fan-out line 31 is connected to the second fan-out line 51, and the other end of the first fan-out line 31 is connected to the corresponding first data line 41; so as to transmit the data signal to the corresponding first data line 41, and further transmit the data signal to the corresponding pixel area 1011 through the first data line 41.

[0069] The display panel includes a pixel driving circuit 11 arranged corresponding to the plurality of pixel areas 101, and the first data line 41 is connected to the pixel driving circuit 11 in the corresponding pixel area 1011 to transmit the data signal to the corresponding pixel driving circuit 11; for example, one pixel driving circuit 11 is provided in each pixel area 101, and the pixel driving circuit 11 is provided with a plurality of thin film transistors located in the thin film transistor layer, and the thin film transistor layer also includes a signal line connecting the plurality of thin film transistors.

[0070] In which, the gate layer 60 includes a light-emitting control signal line 61 extending along the first direction X, and the first metal layer 30 includes a first control signal line 32 extending along the first direction X, a first reset signal line 33 extending along the first direction X, a second reset signal line 34 extending along the first direction X, a second control signal line 35 extending along the first direction X, and a power signal line 36 extending along the first direction X.

[0071] For details, please refer to Figure 5 The pixel driving circuit 11 includes a switching transistor T1, a driving transistor T2, a first reset transistor T3, a second reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a third reset transistor T7, a first node A, a second node B, a third node C and a fourth node Q.

[0072] The display panel includes a light-emitting device layer arranged in each pixel area 101, and the light-emitting device layer is located on the side of the thin film transistor layer away from the substrate 10. The light-emitting device layer includes a stacked anode, a light-emitting layer and a cathode, and the anode is connected to the thin film transistor.

[0073] The gate of the switch transistor T1 is connected to the first control signal line 32 and receives the first control signal SCAN. The switch transistor T1 is also connected to the first data line 41 and the first node A.

[0074] The gate of the driving transistor T2 is connected to the fourth node Q. The driving transistor T2 is also connected to the first node A and the second node B.

[0075] The gate of the first reset transistor T3 is connected to the first control signal line 32 and receives the first control signal SCAN. The first reset transistor T3 is also connected to the second node B and the fourth node Q.

[0076] The gate of the second reset transistor T4 is connected to the second control signal line 35 and receives the second control signal SCAN_RST. The second reset transistor T4 is also connected to the fourth node Q and the first reset signal line 33 and receives the first reset signal VI_Gate from the first reset signal line 33 .

[0077] The gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line 61 and receives the light-emitting control signal EM. The first light-emitting control transistor T5 is also connected to the power signal line 36 and the first node, and receives the power signal VDD from the power signal line 36 .

[0078] The gate of the second light emitting control transistor T6 is connected to the light emitting control signal 61 and is connected to the light emitting control signal EM. The second light emitting control transistor T6 is also connected to the second node B and the third node C.

[0079] The gate of the third reset transistor T7 is connected to the second control signal line 35 and receives the second control signal SCAN_RST. The third reset transistor T7 is also connected to the second reset signal line 34 and the third node C, and receives the second reset signal VI_Ano from the second reset signal line 34 .

[0080] The anode is connected to the third node C.

[0081] The pixel driving circuit 11 further includes a storage capacitor Cst connected between the power signal VDD and the fourth node Q.

[0082] In some embodiments, the first reset transistor T3 and the second reset transistor T4 may be dual-gate thin film transistors to reduce leakage current of the first reset transistor T3 and the second reset transistor T4.

[0083] Furthermore, please combine Figure 5 、 Figure 6 、 Figure 7 as well as Figure 8 , to describe in detail the wiring structure of the pixel driving circuit 11 in the embodiment of the present application.

[0084] In which, the semiconductor layer 20 includes a switching active part 21 of the switching transistor T1, a driving active part 22 of the driving transistor T2, a first light-emitting control active part 25 of the first light-emitting control transistor T5, a second light-emitting control active part 26 of the second light-emitting control transistor T6, a first reset active part 23 of the first reset transistor T3, a second reset active part 24 of the second reset transistor T4, and a third reset active part 27 of the third reset transistor T7.

[0085] The switch active portion 21 and the first light-emission control active portion 25 both extend along the second direction Y, and are connected at the first node A. The orthographic projection of the first control signal line 32 on the substrate 10 overlaps with the orthographic projection of the switch active portion 21 on the substrate 10, and the overlapping portion of the first control signal line 32 is reused as the gate of the switch transistor T1. The light-emission control signal line 61 overlaps with the first light-emission control active portion 25, and the overlapping portion of the light-emission control signal line 61 is reused as the gate of the first light-emission control transistor T5.

[0086] One end of the switch active portion 21 away from the first node A is connected to the first data line 41 and receives a data signal.

[0087] One end of the first light emitting control active portion 25 away from the first node A is connected to the power signal line 36 and receives a power signal VDD.

[0088] One end of the driving active portion 22 is connected to the first node A, and the other end of the driving active portion 22 along the first direction X is connected to the second node B, and the portion of the driving active portion 22 located between the first node A and the second node B is arranged in a U shape, and the gate layer 60 includes a gate 62 of the driving transistor T1, and the U-shaped portion can be arranged in alignment with the gate 62 of the driving transistor T1 to form a channel; and the gate 62 of the driving transistor T1 is connected to the fourth node Q.

[0089] The first reset active portion 23 and the second light-emitting control active portion 26 are located on opposite sides of the second node B along the second direction Y and are both connected to the second node B. The first reset active portion 23 is connected between the second node B and the fourth node Q, and has a U-shaped portion. The orthographic projection of the first reset active portion 23 on the substrate 10 overlaps with the orthographic projection of the first control signal line 32 on the substrate 10. The overlapping portion of the first control signal line 32 is reused as the gate of the first reset transistor T3. Because the first control signal line 32 and the U-shaped first reset active portion 23 have two overlapping portions, the first reset transistor T3 has a dual-gate structure.

[0090] The side of the second light-emitting control active portion 26 away from the second node B is connected to the third node C, and the orthographic projection of the second light-emitting control active portion 26 on the substrate 10 overlaps with the orthographic projection of the light-emitting control signal line 61 on the substrate 10, and the overlapping part of the light-emitting control signal line 61 is reused as the gate of the second light-emitting control transistor T6.

[0091] The third reset active portion 27 is connected to the third node C. The third reset active portion 27 is located on the side of the second light-emitting control active portion 26 away from the second node B along the second direction Y. The orthographic projection of the third reset active portion 27 on the substrate 10 overlaps with the orthographic projection of the second control signal line 35 on the substrate 10, and the overlapping part of the second control signal line 35 is reused as the gate of the third reset transistor T7.

[0092] One end of the third reset active portion 27 away from the fourth node Q is connected to the second reset signal line 34 and receives the second reset signal VI_Ano.

[0093] One end of the first reset active portion 23 away from the second node B is connected to the second reset active portion 24 and to the fourth node Q. The second reset active portion 24 is located on a side of the first reset active portion 23 away from the fourth node Q. The gate layer 60 further includes a connecting portion 63, one end of which is connected to the second control signal line 35, and the other end of which extends along the first direction X and overlaps with the second reset active portion 23. The portion of the connecting portion 63 that overlaps with the second reset active portion 24 serves as the gate of the second reset transistor T4. Part of the second reset active portion 24 is U-shaped, and the U-shaped second reset active portion 24 overlaps with the connecting portion 63 at two locations. Therefore, the second reset transistor T4 has a dual-gate structure.

[0094] One end of the second reset active portion 24 is connected to the first reset active portion 23 , and the other end of the second reset active portion 24 is connected to the first reset signal line 33 so as to input the first reset signal VI_Gate to the second reset active portion 24 .

[0095] The gate 62 of the driving active portion 22 is electrically connected to the fourth node Q.

[0096] It should be noted that, in some embodiments, the third metal layer 50 also includes a second data line 52 extending along the second direction Y, and for multiple pixel driving circuits 11, the switch active part 21 in some of the pixel driving circuits 11 is connected to the first data line 41, and the switch active part 21 in some of the pixel driving circuits 11 is connected to the second data line 52; for example, multiple pixel areas 1011 include a red pixel area, a green pixel area and a blue pixel area, wherein the switch active part 21 of the pixel driving circuit 11 in the red pixel area and the green pixel area is connected to the first data line 41, and the switch active part 21 of the pixel driving circuit 11 in the blue pixel area is connected to the second data line 52; thereby, the wiring space of the second metal layer 40 can be saved, so as to increase the spacing between adjacent traces in the second metal layer 40 and reduce the probability of signal interference and short circuit; and the subsequent description in the embodiment of the present application takes the first data line 41 as an example.

[0097] In the embodiment of the present application, both the first data line 41 and the second data line 52 receive signals through the first fan-out line 31 and the second fan-out line 51 .

[0098] Regarding the routing connection structure of the first data line 41 , the display panel includes a plurality of first contact holes 201 corresponding to the plurality of first data lines 41 , and the first data line 41 extends into the corresponding first contact holes 201 and is connected to the switch active portion 21 in the pixel driving circuit 11 .

[0099] Furthermore, the first fan-out line 31 includes a first fan-out line segment 311 extending along the first direction X and a second fan-out line segment 312 extending along the second direction Y, and one end of the first fan-out line segment 311 is connected to the second fan-out line 51, the other end of the first fan-out line segment 311 is connected to the second fan-out line segment 312, one end of the second fan-out line segment 312 is connected to the first fan-out line segment 311, and the other end of the second fan-out line segment 312 extends into the first contact hole 201 and is connected to the first data line 41; that is, the embodiment of the present application changes the position of the first fan-out line 31 so that the first fan-out line 51 is connected to the second fan-out line 51. The line 31 is arranged close to the first contact hole 201, and can be connected to the first contact hole 201 by adding a second fan-out line segment 312 extending along the second direction Y, sharing the first data line 41 and the first contact hole 201 of the switch active part 21 to realize the connection between the first fan-out line 31 and the first data line 41. Compared with the existing technology, the setting of vias can be reduced, the signal transmission path can be reduced, and the load of the first fan-out line 31 can be reduced; and the setting of the overlapping protrusion can be reduced, the wiring space can be increased, the spacing between the signal lines can be increased, the probability of short circuit between the signal lines can be reduced, and the stability of the display panel can be improved.

[0100] It should be noted that, in the first contact hole 201 , the first fan-out line 31 covers the side of the switch active portion 21 away from the substrate 10 , and the first data line 41 covers the side of the first fan-out line 31 away from the switch active portion 21 .

[0101] In some embodiments, the third metal layer 50 is located between the first metal layer 30 and the second metal layer 40, and the third metal layer 50 also includes a transition portion 53, the transition portion 53 extends into the first contact hole 201, and in the first contact hole 201, the first fan-out line 31 covers the side of the switch active portion 21 away from the substrate 10, the transition portion 53 covers the side of the first fan-out line 31 away from the switch active portion 21, and the first data line 41 covers the side of the transition portion 53 away from the first fan-out line 31; in the embodiment of the present application, the transition portion 53 can be added to improve the overlap yield of the first data line 41 in the first contact hole 201, and reduce the probability of the first data line 41 being broken or other defects due to the depth of the first contact hole 201.

[0102] In some embodiments, the orthographic projection of the first fan-out line segment 311 on the substrate 10 overlaps with the orthographic projection of the corresponding first data line 41 on the substrate 10; the second fan-out line segment 312 at least partially overlaps with the active switch portion 21 along the second direction Y, and the orthographic projection of the second fan-out line segment 312 on the substrate 10 partially overlaps with the orthographic projection of the first data line 41 on the substrate 10. That is, one end of the first fan-out line 31 is connected to the second fan-out line 51, and the other end of the first fan-out line 31 first extends along the first direction X to the intersection with the first data line 41, and then extends along the second direction Y into the first contact hole 201 to connect to the first data line 41.

[0103] In some embodiments, an orthographic projection of the first data line 41 on the substrate 10 partially overlaps with an orthographic projection of the switch active portion 21 on the substrate 10 .

[0104] In some embodiments, the orthographic projection of the first contact hole 201 on the substrate 10 is located between the orthographic projection of the first fan-out line segment 311 on the substrate 10 and the orthographic projection of the first control signal line 32 on the substrate 10; the first fan-out line segment 311 is located between the first control signal line 32 and the first reset signal line 33.

[0105] In some embodiments, the second fan-out line 51 extends along the second direction Y, and the orthographic projection of the second fan-out line 51 on the substrate 10 is located between the orthographic projection of the switch active portion 21 on the substrate 10 and the orthographic projection of the first reset active portion 23 on the substrate 10. Furthermore, corresponding to the same pixel region 101, the first node A and the second node B are located on opposite sides of the second fan-out line 52, and the second node B, the third node C, and the fourth node Q are located on the same side of the second fan-out line 52.

[0106] In addition, in some embodiments, please refer to Figure 9, for the connection between the first fan-out line 31 and the second data line 52; similarly, the display panel includes a second contact hole 202 set corresponding to the second data line 52, and the second data line 52 is connected to the switch active part 21 through the second contact hole 202; wherein, the second fan-out line 52 extends along the second direction Y and is connected to the first fan-out line 31, and the first fan-out line 31 can be extended to the second data line 52 through the first fan-out line segment 311 extending along the first direction X, and then extended by the second fan-out line segment 312 extending along the second direction Y to the second contact hole 202 connecting the second data line 52 and the switch active part 21, so as to realize the connection between the first fan-out line 31 and the second data line 52 in the second contact hole 202.

[0107] In the second contact hole 202 , the first fan-out line 31 covers a side of the switch active portion 21 away from the substrate 10 , and the second data line 52 covers a side of the first fan-out line 31 away from the switch active portion 21 .

[0108] In some embodiments, in two adjacent pixel areas 101 along the first direction X, the corresponding two pixel driving circuits 11 are arranged axially symmetrically; further, the two pixel driving circuits 11 adjacent along the first direction X and both connected to the first data line 41 are arranged axially symmetrically.

[0109] In the examples of this application, comparative examples and embodiments are provided to Figure 1 The pixel driving circuit structure shown and Figure 6 The structure of the pixel driving circuit shown in FIG. 1 is verified, wherein the comparative example is Figure 1 The pixel driving circuit structure shown in the embodiment is Figure 6 The pixel driving circuit 11 shown is used, and the load and line spacing of the fan-out lines (first fan-out lines 31, second fan-out lines 51 or FIAA lines) in the comparative example and the embodiment are verified to obtain the following Table 1.

[0110] Table 1

[0111]

[0112] As can be seen from Table 1, the embodiment of the present application can effectively reduce the load on the first fan-out line 31 and the second fan-out line 51, and can increase the wiring space and increase the line spacing in the first metal layer 30 and the third metal layer 50.

[0113] To sum up, the embodiment of the present application enables the first fan-out line 31 to extend into the first contact hole 201 between the first data line 41 and the switch active part 21, and to be connected to the first data line 41 to realize signal transmission, and does not require additional overlapping protrusions and sleeve holes for the corresponding data lines. This can reduce the load of the first fan-out line 31 and increase the wiring space in the display panel, thereby increasing the spacing between the signal lines, reducing the probability of short circuits between the signal lines, and improving the stability of the display panel.

[0114] In addition, an embodiment of the present application further provides a display device, which includes the display panel described in the above embodiment.

[0115] It can be understood that, since the display device has the same display panel as that in the above embodiment, the display device has the same beneficial effects as the display panel in the above embodiment, which will not be described in detail here.

[0116] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0117] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0118] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0119] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel areas and a plurality of pixel driving circuits arranged corresponding to the plurality of pixel areas; The display panel further includes: substrate; a first metal layer disposed on one side of the substrate, the first metal layer comprising a plurality of first fan-out lines located in a display area of ​​the display panel; a second metal layer disposed on a side of the first metal layer away from the substrate, the second metal layer comprising a plurality of first data lines correspondingly connected to at least some of the plurality of first fan-out lines; Among them, the display panel is provided with multiple first contact holes corresponding to multiple first data lines, the first data lines extend into the first contact holes and are connected to the pixel driving circuit, and the first fan-out lines extend into the first contact holes and are connected to the corresponding first data lines.

2. The display panel according to claim 1, wherein: The pixel driving circuit includes a switching transistor, and the display panel further includes: A semiconductor layer is provided between the substrate and the first metal layer. The semiconductor layer includes a switch active portion of the switch transistor. The first data line extends into the first contact hole and is connected to the switch active portion.

3. The display panel according to claim 2, wherein: The plurality of pixel areas are arranged along a first direction and a second direction, the first direction and the second direction intersect, a plurality of the first data lines are arranged along the first direction, the first data lines extend along the second direction, and the switch active portion extends along the second direction; The fan-out line includes a first fan-out line segment extending along the first direction, the orthographic projection of the first fan-out line segment on the substrate overlaps with the orthographic projection of the corresponding first data line on the substrate, and the orthographic projection of the switch active portion on the substrate partially overlaps with the orthographic projection of the corresponding first data line on the substrate.

4. The display panel according to claim 3, wherein: The fan-out line further includes a second fan-out line segment extending along the second direction, one end of the second fan-out line segment is connected to the first fan-out line segment, and the other end of the second fan-out line segment extends into the first contact hole and is connected to the corresponding first data line.

5. The display panel according to claim 4, wherein: The second fan-out line segment at least partially overlaps with the switch active portion along the second direction, and an orthographic projection of the second fan-out line segment on the substrate partially overlaps with an orthographic projection of the first data line on the substrate.

6. The display panel according to claim 5, wherein: The pixel driving circuit further includes a driving transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first node, a second node, a third node and a fourth node; the semiconductor layer including a driving active portion of the driving transistor, a first light emission control active portion of the first light emission control transistor, a second light emission control active portion of the second light emission control transistor, a first reset active portion of the first reset transistor, a second reset active portion of the second reset transistor, and a third reset active portion of the third reset transistor; Among them, the first light-emitting control active part extends along the second direction and is connected to the switch active part at the first node, one end of the driving active part is connected to the first node, and the other end of the driving active part along the first direction is connected to the second node, the first reset active part and the second light-emitting control active part are located on opposite sides of the second node along the second direction and are both connected to the second node, the side of the second light-emitting control active part away from the second node is connected to the third node, the third reset active part is connected to the third node, the second reset active part is located along the second direction on the side of the first reset active part away from the second node, and the end of the first reset active part away from the second node is connected to the second reset active part and to the fourth node, and the gate of the driving active part is electrically connected to the fourth node.

7. The display panel according to claim 6, wherein: The first metal layer further includes a first control signal line extending along the first direction, an orthographic projection of the first control signal line on the substrate overlaps with an orthographic projection of the switch active portion on the substrate, and an orthographic projection of the first control signal line on the substrate overlaps with an orthographic projection of the first reset active portion on the substrate; The orthographic projection of the first contact hole on the substrate is located between the orthographic projection of the first fan-out line segment on the substrate and the orthographic projection of the first control signal line on the substrate.

8. The display panel according to claim 7, wherein: The first metal layer further includes a first reset signal line extending along the first direction, the first reset signal line is connected to the second reset active portion, and the first fan-out line segment is located between the first control signal line and the first reset signal line.

9. The display panel according to claim 6, wherein: The display panel further includes: a third metal layer, disposed between the second metal layer and the first metal layer, the third metal layer comprising a second fan-out line, one end of the first fan-out line segment being connected to the second fan-out line segment, and the other end of the first fan-out line segment being connected to the second fan-out line; a signal terminal disposed in a non-display area of ​​the display panel, wherein one end of the second fan-out line is connected to the first fan-out line segment, and the other end of the second fan-out line is connected to the signal terminal; The second fan-out line extends along the second direction, and an orthographic projection of the second fan-out line on the substrate is located between an orthographic projection of the switch active portion on the substrate and an orthographic projection of the first reset active portion on the substrate.

10. The display panel according to claim 9, wherein: Corresponding to the same pixel area, the first node and the second node are located on opposite sides of the second fan-out line, and the second node, the third node and the fourth node are located on the same side of the second fan-out line.

11. The display panel according to claim 9, wherein The third metal layer further includes a second data line extending along the second direction, the switch active portion in part of the pixel driving circuit is connected to the first data line, and the switch active portion in another part of the pixel driving circuit is connected to the second data line.

12. The display panel according to claim 11, wherein: Some of the plurality of first fan-out lines are connected to the second data line; The display panel further includes a second contact hole corresponding to the second data line, the second data line is connected to the switch active portion through the second contact hole, and the first fan-out line extends into the second contact hole and is connected to the second data line.

13. The display panel according to claim 12, wherein: In the second contact hole, the first fan-out line covers a side of the switch active portion away from the substrate, and the second data line covers a side of the first fan-out line away from the switch active portion.

14. The display panel according to any one of claims 3 to 13, characterized in that: In two adjacent pixel areas along the first direction, the corresponding two pixel driving circuits are arranged in an axisymmetric manner.

15. The display panel according to claim 2, wherein: In the first contact hole, the first fan-out line covers a side of the switch active portion away from the substrate, and the first data line covers a side of the first fan-out line away from the switch active portion.

16. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 15.

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