Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a substrate, a light shielding layer, a first semiconductor layer and a second semiconductor layer arranged on the substrate. The first semiconductor layer is provided with a first active part of a driving transistor. The second semiconductor layer is provided with a third active part of a compensation transistor and a fourth active part of a first initialization transistor. The light shielding layer comprises a first light shielding part corresponding to the first active part, a second light shielding part corresponding to the third active part and a third light shielding part corresponding to the fourth active part. The second light shielding part can shield the third active part from light. The third light shielding part can shield the fourth active part from light. The third active part of the compensation transistor and the fourth active part of the first initialization transistor are prevented from being affected by light, thereby improving the light sensitivity and electrical properties of the compensation transistor and the first initialization transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display devices, the requirements of existing display devices for power consumption and screen ratio are higher and higher. In order to reduce power consumption and improve screen ratio, the existing display devices will adopt low temperature polysilicon oxide (LTPO) technology. The LTPO technology refers to the use of low temperature polysilicon thin film transistor and oxide thin film transistor at the same time, so that the driving circuit takes into account the advantages of low temperature polysilicon thin film transistor and oxide thin film transistor, thereby reducing power consumption and reducing leakage current.

[0003] The existing display device using the LTPO technology has a large number of film layers, and accordingly a large number of mask plates are required, resulting in a complex process and high cost. In order to reduce the number of mask plates, the existing display device will remove some gate layers and insulating layers, but this will cause the bottom gate of the oxide thin film transistor to be missing, and the photosensitivity and electrical properties of the thin film transistor to be poor.

[0004] Therefore, the existing display device using the LTPO technology has the technical problem of poor photosensitivity and electrical properties caused by the missing bottom gate of the oxide thin film transistor. SUMMARY

[0005] The present application provides a display panel and a display device to alleviate the technical problem of poor photosensitivity and electrical properties caused by the missing bottom gate of the oxide thin film transistor in the existing display device using the LTPO technology.

[0006] To solve the above problems, the technical solutions provided by the present application are as follows:

[0007] In a first aspect, the embodiments of the present application provide a display panel, which comprises a substrate and a plurality of sub-pixels arranged on the substrate, each of the sub-pixels comprising a driving transistor, a switching transistor, a compensation transistor and a first initialization transistor, the switching transistor and the driving transistor being connected to a first node, one electrode of the compensation transistor and one electrode of the first initialization transistor being connected to a second node with the driving transistor, the other electrode of the compensation transistor being connected to a third node with the driving transistor; the display panel further comprises:

[0008] a light shielding layer arranged on one side of the substrate;

[0009] a first semiconductor layer arranged on the side of the light shielding layer away from the substrate, the first semiconductor layer comprising a first active part of the driving transistor and a second active part of the switching transistor;

[0010] a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate, the second semiconductor layer comprising a third active part of the compensation transistor and a fourth active part of the first initialization transistor;

[0011] The light shielding layer comprises a first light shielding part corresponding to the first active part, a second light shielding part corresponding to the third active part, and a third light shielding part corresponding to the fourth active part; the light shielding layer further comprises a first connecting line extending in a first direction and a second connecting line extending in a second direction, the first direction being different from the second direction, the first connecting line being connected to two first light shielding parts disposed adjacent in the first direction, and the second connecting line being connected to two first light shielding parts disposed adjacent in the second direction.

[0012] In a second aspect, the embodiments of the present application further provide a display device, which comprises the display panel as described in any one of the preceding embodiments.

[0013] The display panel and the display device provided by the present application have the following beneficial effects: the display panel comprises a substrate and a light shielding layer, a first semiconductor layer, and a second semiconductor layer disposed on the substrate, the first semiconductor layer forms a first active part of a driving transistor, the second semiconductor layer forms a third active part of a compensation transistor and a fourth active part of a first initialization transistor, the light shielding layer comprises a first light shielding part corresponding to the first active part, a second light shielding part corresponding to the third active part, and a third light shielding part corresponding to the fourth active part, the second light shielding part can shield the third active part, and the third light shielding part can shield the fourth active part, thereby avoiding the third active part of the compensation transistor and the fourth active part of the first initialization transistor from being affected by light, and improving the photosensitivity and electrical properties of the compensation transistor and the first initialization transistor, so as to solve the problem of poor photosensitivity and electrical properties caused by the absence of a bottom gate of an oxide thin film transistor in the existing display device using the LTPO technology. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0015] Figure 1 The first comparative display device provided by the embodiments of the present application is shown in the schematic diagram.

[0016] Figure 2A second comparative display device schematic diagram provided for the embodiments of the present application.

[0017] Figure 3 A third comparative display device schematic diagram provided for the embodiments of the present application.

[0018] Figure 4 A film layer schematic diagram of a display panel provided for the embodiments of the present application.

[0019] Figure 5 A circuit diagram of a sub-pixel of a display panel provided for the embodiments of the present application.

[0020] Figure 6 A first kind of layer diagram of each film layer of a display panel provided for the embodiments of the present application.

[0021] Figure 7 A second kind of layer diagram of each film layer of a display panel provided for the embodiments of the present application.

[0022] Figure 8 A display panel in Figure 6 A light shielding layer exploded view of the display panel in

[0023] Figure 9 A display panel in Figure 7 A light shielding layer exploded view of the display panel in

[0024] Figure 10 A first semiconductor layer exploded view of the display panel in Figure 6

[0025] Figure 11 A first gate layer exploded view of the display panel in Figure 6

[0026] Figure 12 A second semiconductor layer exploded view of the display panel in Figure 6

[0027] Figure 13 A second gate layer exploded view of the display panel in Figure 6

[0028] Figure 14 A first source-drain layer exploded view of the display panel in Figure 6

[0029] Figure 15 A second source-drain layer exploded view of the display panel in Figure 6

[0030] Figure 16 A first via hole exploded view of the display panel in Figure 6

[0031] ​​​​​​​Figure 17 is a cross-sectional view of a second via hole of the display panel in Figure 6

[0032] Figure 18 is a cross-sectional view of a third via hole of the display panel in Figure 6

[0033] Figure 19 is a cross-sectional view of a fourth via hole of the display panel in Figure 6 DETAILED DESCRIPTION

[0034] The following description of the embodiments is provided as an enabling teaching of the application. Expressions of direction, such as [up], [down], [front], [back], [left], [right], [inward], [outward], [side], and the like, as can be used in the description which follows, are only relative expressions and thus are used to describe the application by reference to the accompanying drawings. Absolute positions of the various elements can thus be determined by using positive coordinates, and the use of directional expressions is to facilitate understanding of the application without restricting the application thereto. In the drawings, like reference numerals designate like elements throughout the several views. In the drawings, the thicknesses of some layers and regions are exaggerated for clarity and convenience of description. That is, the sizes and the thicknesses of the components shown in the drawings are arbitrarily shown but the application is not limited thereto.

[0035] Referring to Figures 1 to 3 , as a lead-in to the embodiments of the application, some comparative display devices are provided, Figure 1 is a schematic view of a first comparative display device provided as a lead-in to the embodiments of the application, Figure 2 is a schematic view of a second comparative display device provided as a lead-in to the embodiments of the application, Figure 3 is a schematic view of a third comparative display device provided as a lead-in to the embodiments of the application. Referring to Figure 1 , a comparative display device employing LTPO technology includes a substrate 101, a light-blocking film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarization film 117, a second source-drain film 118, a second planarization film 119, a third source-drain film 121, a third planarization film 122, an anode film 123, a pixel definition film 124, and a support film 125. As can be seen from Figure 1 , the comparative display device includes three layers of source-drain films and three layers of gate films, so that the comparative display device needs to be formed using 16 mask plates, which is relatively complex and costly.

[0036] ​​​To address the complexity of the manufacturing process in contrast display devices, another type of contrast display device removes one of the gate film and insulating films, such as... Figure 2 As shown, by removing the second gate film 109 and the second gate insulating film 108 from the comparison display device, the number of mask layers can be reduced to 14. However, the problem of a large number of mask layers, complex process, and high cost still exists.

[0037] To address the complexity of the manufacturing process in contrast display devices, another type of contrast display device further removes a source / drain film and an insulating film, such as... Figure 3 As shown, by removing the third source / drain film 121 and the third planarization film 122, the number of mask layers can be reduced to 13; however, from Figure 2 , Figure 3 As can be seen, the lack of shielding under the oxide semiconductor film 112 leads to the absence of the bottom gate of the oxide thin film transistor, resulting in a deterioration in the photosensitivity and electrical properties of the thin film transistor.

[0038] Therefore, this application provides a display panel and a display device, please refer to... Figures 1 to 19 , Figure 4 This is a schematic diagram of the film layer of the display panel provided in an embodiment of this application. Figure 5 A circuit diagram of a sub-pixel of a display panel provided in an embodiment of this application. Figure 6 This is a first stacking diagram of the film layers of the display panel provided in the embodiments of this application. Figure 7 This is a second layered diagram of a display panel provided in an embodiment of this application. Figure 8 for Figure 6 An exploded view of the light-shielding layer of the display panel. Figure 9 for Figure 7 An exploded view of the light-shielding layer of the display panel. Figure 10 for Figure 6 An exploded view of the first semiconductor layer of the display panel. Figure 11 for Figure 6 An exploded view of the first gate layer of the display panel. Figure 12 for Figure 6 An exploded view of the second semiconductor layer of the display panel. Figure 13 for Figure 6 An exploded view of the second gate layer of the display panel. Figure 14 for Figure 6 An exploded view of the first source-drain layer of the display panel. Figure 15 for Figure 6 An exploded view of the second source-drain layer of the display panel. Figure 16 for Figure 6 An exploded view of the first via of the display panel. Figure 17 for Figure 6 An exploded view of the second via of the display panel.Figure 18 for Figure 6 An exploded view of the third via in the display panel. Figure 19 for Figure 6 An exploded view of the fourth via on the display panel.

[0039] It should be noted that, in the embodiments of this application... Figure 6 The display panel and Figure 7 The difference between the display panels lies in the design of the light-shielding layer; the designs of other film layers on the display panel can be the same. Therefore, the following... Figure 6 In the exploded view, apart from the different light-shielding layers, the exploded views of other film layers can also be used as... Figure 7 An exploded view of the corresponding film layer of the display panel, for example Figure 7 An exploded view of the light-shielding layer of the display panel can be seen as Figure 9 As shown, the other films are similar and can be found in other exploded diagrams, which will not be repeated here.

[0040] This application provides a display panel, such as... Figures 4 to 19 As shown, the display panel 2 includes a substrate 201 and a plurality of sub-pixels 31 disposed on the substrate 201. Each sub-pixel 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4. The switching transistor T2 and the driving transistor T1 are connected to a first node A. One electrode of the compensation transistor T3 and one electrode of the first initialization transistor T4 are connected to the driving transistor T1 at a second node Q. The other electrode of the compensation transistor T3 is connected to the driving transistor T1 at a third node B.

[0041] The display panel 2 also includes a light-shielding layer 202, a first semiconductor layer 207 and a second semiconductor layer 212 disposed on a substrate 201. The light-shielding layer 202 is disposed between the substrate 201 and the first semiconductor layer 207, and the first semiconductor layer 207 is disposed between the light-shielding layer 202 and the second semiconductor layer 212.

[0042] The first semiconductor layer 207 is disposed on the side of the light-shielding layer 202 away from the substrate 201. The first semiconductor layer 207 includes a first active portion T1A of the driving transistor T1 and a second active portion T2A of the switching transistor T2.

[0043] The second semiconductor layer 212 is disposed on the side of the first semiconductor layer 207 away from the substrate 201. The second semiconductor layer 212 includes the third active portion T3A of the compensation transistor T3 and the fourth active portion T4A of the first initialization transistor T4.

[0044] The light shielding layer 202 includes a first light shielding portion 202a corresponding to the first active portion T1A, a second light shielding portion 202b corresponding to the third active portion T3A, and a third light shielding portion 202c corresponding to the fourth active portion T4A; the light shielding layer 202 further includes a first connecting line 202e extending along the first direction X and a second connecting line 202d extending along the second direction Y, the first connecting line 202e is connected to two first light shielding portions 202a arranged adjacent in the first direction X, and the second connecting line 202d is connected to two first light shielding portions 202a arranged adjacent in the second direction Y, so that the light shielding layer 202 forms a grid structure. The second light shielding portion 202b and the third light shielding portion 202c are located in the area surrounded by the two adjacent first connecting lines 202e, the two adjacent second connecting lines 202d and the four first light shielding portions 202a, that is, the second light shielding portion 202b and the third light shielding portion 202c are located in part of the mesh of the grid structure formed by the light shielding layer 202. The first direction X and the second direction Y are different, for example, the first direction X is the horizontal direction, and the second direction Y is the vertical direction, that is, the first direction X is the row direction, and the second direction Y is the column direction, of course, the present application is not limited to this, and the first direction X and the second direction Y in the present application can also be at other angles.

[0045] The display panel provided by the embodiment of the present application includes a substrate and a light shielding layer, a first semiconductor layer and a second semiconductor layer arranged on the substrate, the first semiconductor layer forms a first active portion of a driving transistor, the second semiconductor layer forms a third active portion of a compensation transistor and a fourth active portion of a first initialization transistor, the light shielding layer includes a first light shielding portion corresponding to the first active portion, a second light shielding portion corresponding to the third active portion and a third light shielding portion corresponding to the fourth active portion, the second light shielding portion can shield the third active portion, and the third light shielding portion can shield the fourth active portion, thereby avoiding the third active portion of the compensation transistor and the fourth active portion of the first initialization transistor from being affected by light, and improving the photosensitivity and electrical properties of the compensation transistor and the first initialization transistor, so as to solve the problem of poor photosensitivity and electrical properties caused by the absence of the bottom gate of the oxide thin film transistor in the display device using the LTPO technology.

[0046] Specifically, in the embodiment of the present application, the light shielding portion formed by the light shielding layer is arranged corresponding to the active portion of the transistor, which means that the light shielding portion is arranged corresponding to at least the channel portion of the active portion of the transistor, and the projection of the light shielding portion on the substrate overlaps the projection of the channel portion of the transistor on the substrate. It can be understood that the active portion of each transistor includes a doped portion and a channel portion, and the channel portion is easily affected by light to cause performance changes. Therefore, the light shielding portion can be arranged corresponding to the channel portion of the transistor. Specifically, for example, the second light shielding portion is arranged corresponding to the third active portion of the compensation transistor, which means that the second light shielding portion is arranged corresponding to at least the third channel portion of the compensation transistor.

[0047] In some embodiments, as shown in Figure 6 and Figure 8 , the light shielding layer 202 includes a first light shielding portion 202a, a second light shielding portion 202b, and a third light shielding portion 202c. The first light shielding portion 202a is arranged corresponding to the first active portion T1A of the driving transistor T1, the second light shielding portion 202b is arranged corresponding to the third active portion T3A of the compensation transistor T3, and the third light shielding portion 202c is arranged corresponding to the fourth active portion T4A of the first initialization transistor T4.

[0048] Specifically, the orthographic projection of the first active portion of the driving transistor on the substrate is located within the orthographic projection of the first light shielding portion on the substrate, the orthographic projection of the third active portion of the compensation transistor on the substrate is located within the orthographic projection of the second light shielding portion on the substrate, and the orthographic projection of the fourth active portion of the first initialization transistor on the substrate is located within the orthographic projection of the third light shielding portion on the substrate, so that the light can be prevented from irradiating onto the first active portion of the driving transistor, the third active portion of the compensation transistor, and the fourth active portion of the first initialization transistor, thereby improving the electrical properties and light sensitivity of the driving transistor, the compensation transistor, and the first initialization transistor.

[0049] Specifically, the area of the first light shielding portion can be greater than or equal to the area of the first active portion of the driving transistor, the area of the second light shielding portion can be greater than or equal to the area of the third active portion of the compensation transistor, and the area of the third light shielding portion can be greater than or equal to the area of the fourth active portion of the first initialization transistor.

[0050] In some embodiments, as shown in Figure 4 , Figure 6 , Figure 8 , the display panel includes a plurality of repeating units 30 arranged on the array substrate, each repeating unit 30 includes two sub-pixels 31 arranged in mirror symmetry, and within the repeating unit 30, the light shielding layer 202 includes two first light shielding portions 202a, two second light shielding portions 202b, two third light shielding portions 202c, and a first connecting line 202e and a second connecting line 202d connecting the two first light shielding portions 202a, which are symmetrically arranged in the corresponding regions of the two sub-pixels 31. The second light shielding portion 202b is located between the third light shielding portion 202c and the first light shielding portion 202a, and is also arranged corresponding to the gap between the two first light shielding portions 202a. The two first light shielding portions 202a are mirror symmetric about the two second light shielding portions 202b. Moreover, the second light shielding portion 202b partially overlaps the first light shielding portion 202a in the first direction X. The third light shielding portion 202c is located between the two second connecting lines 202d, and in the second direction Y, the third light shielding portion 202c partially overlaps the first light shielding portion 202a.

[0051] The first connection line 202e is arranged along the first direction X, the second connection line 202d is arranged along the second direction Y, the first light shielding part 202a is provided with a notch on the side away from the second light shielding part 202b, and the first connection line 202e is arranged at the notch. Adjacent two first connection lines 202e coincide in the first direction X. The second connection line 202d is located on the side of the center line of the first light shielding part 202a in the second direction Y close to the second light shielding part 202b, and adjacent two second connection lines 202d coincide in the second direction Y. The second light shielding part 202b has a gap with the first light shielding part 202a, the first connection line 202e and the second connection line 202d, so as to be insulated from the first light shielding part 202a. The third light shielding part 202c has a gap with the first light shielding part 202a, the first connection line 202e and the second connection line 202d, so as to be insulated from the first light shielding part 202a. Optionally, adjacent second light shielding parts 202b have a gap, adjacent third light shielding parts 202c have a gap, and adjacent second light shielding parts 202b and third light shielding parts 202c also have a gap. The second light shielding part 202b and / or the third light shielding part 202c are in a floating state, that is, the second light shielding part 202b and / or the third light shielding part 202c are not connected to an electrical signal, and the second light shielding part 202b and / or the third light shielding part 202c will not be applied to an electrical signal. At least one of the first light shielding part 202a, the first connection line 202e and the second connection line 202d is connected to a high potential power line.

[0052] Specifically, it can be understood that the display panel will include a plurality of repeating units arranged in an array, and the sub-pixels in each repeating unit can refer to the design of a repeating unit in an embodiment of the present application.

[0053] Specifically, it can be understood that in the display panel, two adjacent sub-pixels are symmetrically arranged to improve the aperture ratio. The present application embodiment realizes the mesh structure of the first light shielding part by symmetrically arranging each light shielding part and realizing the connection of each row and each column of the first light shielding part through the arrangement of the first connection line and the second connection line, so that the voltage drop of each part of the first light shielding part is similar or even the same when signal input is performed, thereby making the uniformity of the signal better and improving the display effect.

[0054] Specifically, as Figure 8As shown, the first connecting line 202e connects multiple first light-shielding parts 202a in the first direction X, and the second connecting line 202d connects multiple first light-shielding parts 202a in the second direction Y. The second connecting line 202d connects the first light-shielding part 202a in the current row of sub-pixels 31 with the first light-shielding part 202a in the previous row of sub-pixels 31. Adjacent second connecting lines 202d connect the first light-shielding part 202a in the current row of sub-pixels 31 with the first light-shielding part 202a in the next row of sub-pixels 31. The two first light-shielding parts 202a in the repeating unit 30 are connected to each other (not shown in the figure, because the two first light-shielding parts 202a in some repeating units can achieve a grid design by connecting them to each other), thereby realizing the connection of the first light-shielding parts 202a in each row and column, so that the light-shielding layer 202 forms a mesh structure, thereby achieving uniformity during signal transmission.

[0055] In some embodiments, such as Figure 4 , Figure 7 , Figure 9 As shown, with Figure 8 Unlike the illustrated embodiment, the light-shielding layer 202 also includes a third connecting line (such as...). Figure 9 (Illustrated 202f1, 202f2) In a repeating unit, at least one of the second light-shielding part 202b and the third light-shielding part 202c is connected to at least one of the first light-shielding part 202a, the first connecting line 202e, and the second connecting line 202d via a third connecting line, as shown. Figure 9 As illustrated, the second light-shielding part 202b is connected to the first light-shielding part 202a and the second connecting line 202d via the third connecting line 202f1, and the third light-shielding part 202c is connected to the second connecting line 202d via the third connecting line 202f2. Adjacent second light-shielding parts 202b and / or adjacent third light-shielding parts 202c are connected via the fourth connecting line 202g. Thus, the second light-shielding parts 202b, the third light-shielding parts 202c, the third connecting lines 202f1 and 202f2, and the fourth connecting line 202g, together with the first light-shielding parts 202a, the first connecting line 202e, and the second connecting line 202d, form a grid structure, further achieving uniformity in signal transmission; moreover, it can replace the first connecting line 202e connecting two adjacent first light-shielding parts 202a within the repeating unit, thereby reducing the number of first connecting lines 202e. Meanwhile, in the second direction Y, the linewidths of the second light-shielding part 202b, the third light-shielding part 202c, the third connecting lines 202f1, 202f2, and the fourth connecting line 202g are all greater than the linewidth of the first connecting line 202e, which can further reduce the overall impedance of the light-shielding layer 202 and further improve the uniformity of the signal.

[0056] Optionally, at least one of the first light-shielding part 202a, the second light-shielding part 202b, the third light-shielding part 202c, the first connecting line 202e, the second connecting line 202d, and the third connecting lines 202f1 and 202f2 is connected to a high-potential power line.

[0057] In some embodiments, such as Figure 5 As shown, the gate of switching transistor T2 is connected to the first scan signal line Pscan, the first electrode of switching transistor T2 is connected to the data line DATA, and the second electrode of switching transistor T2 is connected to the first electrode of driving transistor T1 at the first node A; the gate of compensation transistor T3 is connected to the second scan signal line Nscan1, the first electrode of compensation transistor T3 is connected to the gate of driving transistor T1 at the second node Q, and the second electrode of compensation transistor T3 is connected to the second electrode of driving transistor T1; the gate of first initialization transistor T4 is connected to the third scan signal line Nscan2, the first electrode of first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of first initialization transistor T4 is connected to the gate of driving transistor T1 at the second node B; sub-pixel 31 further includes:

[0058] The first light-emitting control transistor T5 has its gate connected to the light-emitting control signal line EM, its first electrode connected to the high-potential power supply line VDD, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0059] The second light-emitting control transistor T6 has its gate connected to the light-emitting control signal line EM, and its first electrode is connected to the second electrode of the driving transistor T1 at the third node B.

[0060] The second initialization transistor T7 has its gate connected to the fourth scan signal line Pscan2, its first electrode connected to the second initialization signal line VI-ANO, and its second electrode connected to the second electrode of the second light-emitting control transistor T6 at the fourth node C.

[0061] The third initialization transistor T8 has its gate connected to the fourth scan signal line Pscan2, its first electrode connected to the third initialization signal line VI3, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0062] Storage capacitor Cst, one plate of storage capacitor Cst is connected to the high potential power line VDD, and the other plate of storage capacitor Cst is connected to the gate of driving transistor T1 at the second node Q;

[0063] The boost capacitor Cboost has one plate connected to the first scan signal line Pscan, and the other plate connected to the second electrode of the first initialization transistor T4.

[0064] Specifically, such as Figure 4 , Figure 5 As shown, the display panel 2 also includes a light-emitting layer 23, which includes a light-emitting device LED. The positive electrode of the light-emitting device LED is connected to the second electrode of the second initialization transistor T7, and the negative electrode of the light-emitting device LED is connected to the low-potential power line VSS.

[0065] In some embodiments, such as Figure 4 As shown, the display panel 2 further includes a first gate layer 209, a second gate layer 214, a first source-drain layer 216, and a second source-drain layer 218. The first gate layer 209 is disposed between the first semiconductor layer 207 and the second semiconductor layer 212, the second gate layer 214 is disposed between the second semiconductor layer 212 and the first source-drain layer 216, and the first source-drain layer 216 is disposed between the second gate layer 214 and the second source-drain layer 218. By including the first gate layer, the second gate layer, the first source-drain layer, and the second source-drain layer in the display panel, the number of process steps in the display panel can be reduced, and the number of photomasks required to form the display panel can be reduced.

[0066] In some embodiments, such as Figures 4 to 6 , Figure 10As shown, the first semiconductor layer 207 includes a first active part T1A of the driving transistor T1, a second active part T2A of the switching transistor T2, a fifth active part T5A of the first light emitting control transistor T5, a sixth active part T6A of the second light emitting control transistor T6, a seventh active part T7A of the second initialization transistor T7, and an eighth active part T8A of the third initialization transistor T8, the first active part T1A of the driving transistor T1 is arranged along the first direction X, and the first active part T1A of the driving transistor T1 is connected with the second active part T2A of the switching transistor T2, the fifth active part T5A of the first light emitting control transistor T5, and the sixth active part T6A of the second light emitting control transistor T6, the second active part T2A of the switching transistor T2 and the fifth active part T5A of the first light emitting control transistor T5 are arranged along the second direction Y, the sixth active part T6A of the second light emitting control transistor T6 and the seventh active part T7A of the second initialization transistor T7 are arranged along the second direction Y, and the sixth active part T6A of the second light emitting control transistor T6 and the seventh active part T7A of the second initialization transistor T7 are connected, the eighth active part T8A of the third initialization transistor T8 is arranged apart from the first active part T1A of the driving transistor T1, the second active part T2A of the switching transistor T2, the fifth active part T5A of the first light emitting control transistor T5, the sixth active part T6A of the second light emitting control transistor T6, and the seventh active part T7A of the second initialization transistor T7.

[0067] Specifically, as can be seen in one repeating unit, the seventh active part T7A of the second initialization transistor T7 of the two adjacent sub-pixels 31 is connected.

[0068] In some embodiments, as shown in FIG. 1, the first semiconductor layer 207 includes a first active part T1A of the driving transistor T1, a second active part T2A of the switching transistor T2, a fifth active part T5A of the first light emitting control transistor T5, a sixth active part T6A of the second light emitting control transistor T6, a seventh active part T7A of the second initialization transistor T7, and an eighth active part T8A of the third initialization transistor T8, the first active part T1A of the driving transistor T1 is arranged along the first direction X, and the first active part T1A of the driving transistor T1 is connected with the second active part T2A of the switching transistor T2, the fifth active part T5A of the first light emitting control transistor T5, and the sixth active part T6A of the second light emitting control transistor T6, the second active part T2A of the switching transistor T2 and the fifth active part T5A of the first light emitting control transistor T5 are arranged along the second direction Y, the sixth active part T6A of the second light emitting control transistor T6 and the seventh active part T7A of the second initialization transistor T7 are arranged along the second direction Y, and the sixth active part T6A of the second light emitting control transistor T6 and the seventh active part T7A of the second initialization transistor T7 are connected, the eighth active part T8A of the third initialization transistor T8 is arranged apart from the first active part T1A of the driving transistor T1, the second active part T2A of the switching transistor T2, the fifth active part T5A of the first light emitting control transistor T5, the sixth active part T6A of the second light emitting control transistor T6, and the seventh active part T7A of the second initialization transistor T7. Figures 4 to 7 , Figure 11 As shown, the first gate layer 209 includes a first initialization signal line VI-G, a first scan signal line Pscan, a light emitting control signal line EM, a fourth scan signal line Pscan2, a gate T1G of the driving transistor T1, a gate T2G of the switching transistor T2, a gate T5G of the first light emitting control transistor T5, a gate T6G of the second light emitting control transistor T6, a gate T7G of the second initialization transistor T7, a gate T8G of the third initialization transistor T8, and a first plate Cst1 of the storage capacitor Cst, the first initialization signal line VI-G, the first scan signal line Pscan, the first plate Cst1 of the storage capacitor Cst, the light emitting control signal line EM, and the fourth scan signal line Pscan2 are sequentially and spacedly arranged along the second direction Y.

[0069] Specifically, as shown in FIG. 1, the first gate layer 209 includes a first initialization signal line VI-G, a first scan signal line Pscan, a light emitting control signal line EM, a fourth scan signal line Pscan2, a gate T1G of the driving transistor T1, a gate T2G of the switching transistor T2, a gate T5G of the first light emitting control transistor T5, a gate T6G of the second light emitting control transistor T6, a gate T7G of the second initialization transistor T7, a gate T8G of the third initialization transistor T8, and a first plate Cst1 of the storage capacitor Cst, the first initialization signal line VI-G, the first scan signal line Pscan, the first plate Cst1 of the storage capacitor Cst, the light emitting control signal line EM, and the fourth scan signal line Pscan2 are sequentially and spacedly arranged along the second direction Y. Figure 11As can be seen, the gate T2G of the switch transistor T2 is part of the first scan signal line Pscan, and it can be understood that, since the gates T2G of all the switch transistors T2 in a row of sub-pixels are connected to the same first scan signal line Pscan, when the first scan signal line Pscan is formed, the part of the first scan signal line Pscan corresponding to the channel of the switch transistor T2 of each sub-pixel serves as the gate of the switch transistor T2 of each pixel unit, therefore, the same structure is identified by two labels, and by analogy, the gate T1G of the drive transistor T1 serves as both the gate and the first plate Cst1 of the storage capacitor Cst, the part of the emission control signal line EM corresponding to the channel of the first emission control transistor T5 serves as the gate T5G of the first emission control transistor T5, the part of the emission control signal line EM corresponding to the channel of the second emission control transistor T6 serves as the gate T6G of the second emission control transistor T6, the part of the fourth scan signal line Pscan2 corresponding to the channel of the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and the part of the fourth scan signal line Pscan2 corresponding to the channel of the third initialization transistor T8 serves as the gate T8G of the third initialization transistor T8.

[0070] In some embodiments, as shown in FIGS. 1A and 1B, the second semiconductor layer 212 includes the third active part T3A of the compensation transistor T3, the fourth active part T4A of the first initialization transistor T4, and the second plate Cst2 of the storage capacitor Cst, the third active part T3A of the compensation transistor T3 is connected to the fourth active part T4A of the first initialization transistor T4, the second plate Cst2 of the storage capacitor Cst is disposed on one side of the third active part T3A of the compensation transistor T3 along the first direction X, and a through hole 331 is provided on the second plate Cst2 of the storage capacitor Cst. Figures 4 to 7 、 Figure 12 As can be seen, the gate T2G of the switch transistor T2 is part of the first scan signal line Pscan, and it can be understood that, since the gates T2G of all the switch transistors T2 in a row of sub-pixels are connected to the same first scan signal line Pscan, when the first scan signal line Pscan is formed, the part of the first scan signal line Pscan corresponding to the channel of the switch transistor T2 of each sub-pixel serves as the gate of the switch transistor T2 of each pixel unit, therefore, the same structure is identified by two labels, and by analogy, the gate T1G of the drive transistor T1 serves as both the gate and the first plate Cst1 of the storage capacitor Cst, the part of the emission control signal line EM corresponding to the channel of the first emission control transistor T5 serves as the gate T5G of the first emission control transistor T5, the part of the emission control signal line EM corresponding to the channel of the second emission control transistor T6 serves as the gate T6G of the second emission control transistor T6, the part of the fourth scan signal line Pscan2 corresponding to the channel of the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and the part of the fourth scan signal line Pscan2 corresponding to the channel of the third initialization transistor T8 serves as the gate T8G of the third initialization transistor T8.

[0071] Specifically, it can be understood that the second semiconductor layer forms the second plate of the storage capacitor, therefore, it is necessary to make the second plate of the storage capacitor have good electrical properties, the second plate of the storage capacitor can be doped, the electrical properties of the second plate of the storage capacitor are kept consistent with or even exceed the electrical properties of the doped part of the active part, so that the electrical properties of the storage capacitor are good.

[0072] Specifically, by providing a through hole on the second plate of the storage capacitor, the first electrode of the compensation transistor can be connected to the gate of the drive transistor through the second plate of the storage capacitor, so that the sub-pixel 31 can work normally.

[0073] Specifically, as shown in Figure 11 , Figure 12 , the first gate layer 209 further includes a first plate Cboost1 of a boost capacitor Cboost, the second semiconductor layer 212 further includes a second plate Cboost2 of the boost capacitor Cboost, and an overlapping portion of the first scan signal line Pscan and the fourth active portion T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and an overlapping portion of the fourth active portion T4A of the first initialization transistor T4 and the first scan signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0074] In some embodiments, as shown in Figures 4 to 7 , Figure 13 , the second gate layer 214 includes the second scan signal line Nscan1, the third scan signal line Nscan2, the third initialization signal line VI3, the gate T3G of the compensation transistor T3, and the gate T4G of the first initialization transistor T4, and the third scan signal line Nscan2, the second scan signal line Nscan1, and the third initialization signal line VI3 are sequentially arranged along the second direction Y.

[0075] In some embodiments, as shown in Figures 4 to 7 , Figure 14 , the first source-drain layer 216 includes the first data connection line L1, the first electrode T2S of the switch transistor T2, the first electrode T3S of the compensation transistor T3, the second electrode T3D of the compensation transistor T3, the first electrode T4S of the first initialization transistor T4, the second electrode T4D of the first initialization transistor T4, the first electrode T5S of the first light-emitting control transistor T5, the second electrode T5D of the first light-emitting control transistor T5, the first electrode T6S of the second light-emitting control transistor T6, the second electrode T6D of the second light-emitting control transistor T6, the first electrode T7S of the second initialization transistor T7, the second electrode T7D of the second initialization transistor T7, the first electrode T8S of the third initialization transistor T8, the second electrode T8D of the third initialization transistor T8, and the second initialization signal line VI-ANO.

[0076] Specifically, as shown in Figure 14 , it can be understood that the electrodes of the transistors are connected together, but in actual design, in order to improve the aperture ratio, the electrodes of the transistors share the same structure, so in Figure 14 , the same structure is identified by multiple labels, for example, a structure is both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4, and from Figure 5As can be seen, this is the location where the second node Q is connected. Similarly, other structures will also serve as multiple electrodes, and the positions of each node can be determined accordingly.

[0077] Specifically, such as Figure 11 , Figure 14 As shown, the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4 are connected through the first connection terminal K1. Given the small distance between the projections of the first initialization signal line VI-G and the third scan signal line Nscan2 on the substrate, directly forming vias in the corresponding region of the first electrode of the first initialization transistor to connect the first initialization signal line would result in vias being formed on the third scan signal line Nscan2. Therefore, the first connection terminal K1 can be set on the first source-drain layer, connecting the first electrode of the first initialization transistor T4 through the first connection terminal K1. Simultaneously, a via is formed in the corresponding region of the first connection terminal K1, connecting the first connection terminal K1 to the first initialization signal line VI-G. This achieves the connection between the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4. Furthermore, the first connection terminal K1 is positioned on the axis of symmetry of the two symmetrically arranged sub-pixels 31, allowing the first electrodes of the first initialization transistor T4 in the two symmetrically arranged sub-pixels 31 to be connected to the first initialization signal line through the same first connection terminal K1, reducing the number of vias and improving yield.

[0078] Specifically, such as Figure 6 , Figure 7 , Figure 14 , Figure 15 As shown, since the high-potential power line VDD does not overlap with the first electrode T5S of the first light-emitting control transistor T5, and the high-potential power line VDD will connect to one plate of the storage capacitor, a second connection terminal K2 needs to be set so that the second connection terminal K2 is connected to the high-potential power line VDD, thereby transmitting the signal of the high-potential power line VDD to the first electrode T5S of the first light-emitting control transistor T5. A third connection terminal K3 can also be set so that the third connection terminal K3 is connected to the second plate Cst2 of the storage capacitor Cst, thereby realizing the connection of one plate of the storage capacitor Cst, the first light-emitting control transistor T5, and the high-potential power line VDD.

[0079] Specifically, such as Figures 6 to 14 As shown, the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, a fourth connection terminal K4 can be provided in the first source-drain layer. The fourth connection terminal K4 passes through the via 331 and is connected to the gate T1G of the driving transistor T1, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0080] In some embodiments, such as Figures 4 to 15As shown, within the repeating unit 30, the second source-drain layer 218 includes two data lines DATA, an initialization signal connection line L3, two high-potential power lines VDD, and a second data connection line L2. The two data lines DATA are arranged in a mirror symmetrical configuration, the two high-potential power lines VDD are arranged in a mirror symmetrical configuration, and the initialization signal connection line L3 and the second data connection line L2 are arranged in a mirror symmetrical configuration.

[0081] Specifically, the high-potential power line VDD can be connected to the second connection terminal K2 through a via, and the data line can be connected to the first electrode T2S of the switching transistor T2 through a via.

[0082] Specifically, such as Figure 15 As shown, the second source-drain layer 218 also includes a fifth connection terminal K5, which connects the second electrode T6D of the second light-emitting control transistor T6 and the first electrode of the light-emitting device.

[0083] Specifically, it is understood that due to the design of the sub-pixel 31 in the display area shown in the embodiments of this application, and the connection points of some traces located in the non-display area, some traces may not be connected together. However, in reality, they will be connected. For example, in order to adopt the technique of setting the fanout line in the display area (Fanout In AA, FIAA), the data line DATA will be provided with a first data connection line L1 set along the first direction and a second data connection line L2 set along the second direction, and will be connected to the data line outside the display area. However, the embodiments of this application show the design of the sub-pixel 31, so its connection point is not shown, but in reality, it will be connected.

[0084] Meanwhile, in order to realize the mesh structure design of the initialization signal line, the embodiments of this application will set an initialization signal connection line L3. The initialization signal connection line L3 can realize the mesh structure design of at least one of the first initialization signal line, the second initialization signal line and the third initialization signal line. Similarly, the initialization signal connection line will be connected to the initialization signal line.

[0085] For example, the first initialization signal line can be connected to the initialization signal connection line outside the display area to achieve a mesh structure design for the first initialization signal line. Similarly, a mesh structure design for the second and third initialization signal lines can be achieved. However, the embodiments of this application are not limited to this. Some initialization signal connection lines can be connected to one of the first, second, and third initialization signal lines, and some initialization signal connection lines can be connected to the other one of the first, second, and third initialization signal lines. Alternatively, some initialization signal connection lines can be connected to the other one of the first, second, and third initialization signal lines to achieve a mesh structure design for each initialization signal line.

[0086] In some embodiments, such as Figure 16 As shown, Figure 16 The location of the first via 341 is shown. The first via 341 refers to a via etched from the first source / drain layer to the first semiconductor layer or the first gate layer.

[0087] In some embodiments, such as Figure 17 As shown, Figure 17 The location of the second via 342 is shown. The second via 342 refers to a via etched from the first source / drain layer to the second semiconductor layer or the second gate layer.

[0088] In some embodiments, such as Figure 18 As shown, Figure 18 The location of the third via 343 is shown. The third via 343 refers to the via etched from the second source-drain layer to the first source-drain layer.

[0089] In some embodiments, such as Figure 19 As shown, Figure 19 The location of the fourth via 344 is shown. The fourth via 344 refers to the via etched from the anode of the light-emitting layer to the second source / drain layer.

[0090] Specifically, such as Figure 4 As shown, the display panel 2 also includes a first barrier layer 203, a second barrier layer 205, a buffer layer 206, a first gate insulating layer 208, a first interlayer insulating layer 211, a second gate insulating layer 213, a second interlayer insulating layer 215, a first planarization layer 217, and a second planarization layer 219.

[0091] Specifically, such as Figure 4 As shown, the display panel 2 also includes a light-emitting layer 23, which includes a pixel electrode layer 221, a pixel definition layer 222, a light-emitting material layer, a common electrode layer, and a support pillar 223.

[0092] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0093] Specifically, the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM can be connected to different gate driving circuits. Specifically, five sets of gate driving circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM, respectively. Among them, the gate driving circuit connected to the first scan signal line Pscan can use double-sided driving, while the other gate driving circuits use single-sided driving.

[0094] Specifically, the material of the first semiconductor layer includes silicon semiconductor materials, specifically low-temperature polycrystalline silicon.

[0095] Specifically, the material of the second semiconductor layer includes oxide semiconductor materials, specifically metal oxide semiconductor materials, and more specifically, indium gallium zinc oxide.

[0096] Specifically, the materials used for the light-shielding layer include metallic materials.

[0097] Specifically, the driving transistor, the switching transistor, the first light-emitting transistor, the second light-emitting transistor, the second initialization transistor, and the third initialization transistor are P-type transistors, while the first initialization transistor and the compensation transistor are N-type transistors.

[0098] Specifically, the above embodiments have provided a detailed description of the display panel from the aspects of sub-pixel structure, film layer structure, specific structure of each layer, material, and potential. It is understood that when there is no conflict between the embodiments, the embodiments can be combined.

[0099] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0100] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0101] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized by, Each of the plurality of sub-pixels includes a driving transistor, a compensation transistor, a first initialization transistor, and a storage capacitor, a first active part of the driving transistor is located in a first semiconductor layer, a third active part of the compensation transistor, a fourth active part of the first initialization transistor, and one plate of the storage capacitor are all located in a second semiconductor layer, the other plate of the storage capacitor is located in a first gate layer, and the first semiconductor layer, the second semiconductor layer, and the first gate layer are all arranged in different layers. The display panel further includes a light shielding layer, the light shielding layer includes a first light shielding part arranged corresponding to the first active part, a second light shielding part arranged corresponding to the third active part, and a third light shielding part arranged corresponding to the fourth active part; the light shielding layer further includes a first connecting line and a second connecting line, and at least part of adjacent first light shielding parts are connected through the first connecting line or the second connecting line. The display panel includes a plurality of repetitive units arranged in an array, each of the repetitive units includes two sub-pixels arranged in mirror symmetry, and in the repetitive unit, the light shielding layer includes two first light shielding parts, two second light shielding parts, two third light shielding parts, and the first connecting line and the second connecting line connecting adjacent two first light shielding parts, the second light shielding part is located between the third light shielding part and the first light shielding part, and the second light shielding part is further arranged corresponding to the gap between adjacent two first light shielding parts, and two first light shielding parts are mirror symmetric about two second light shielding parts.

2. The display panel of claim 1, wherein, The first connecting line extends along a first direction, the second connecting line extends along a second direction, the first direction and the second direction are different, the first connecting line is connected with two first light shielding parts arranged adjacent in the first direction, and the second connecting line is connected with two first light shielding parts arranged adjacent in the second direction; the second light shielding part and the third light shielding part are both located in a region surrounded by adjacent two first connecting lines, adjacent two second connecting lines, and four first light shielding parts.

3. The display panel of claim 1, wherein, The second light shielding part and the third light shielding part each have a gap between the first light shielding part, the first connecting line, and the second connecting line, and the second light shielding part and / or the third light shielding part are in a floating state.

4. The display panel of claim 1, wherein, The light shielding layer further includes a third connecting line, and at least one of the second light shielding part and the third light shielding part is connected with at least one of the first light shielding part, the first connecting line, and the second connecting line through the third connecting line.

5. The display panel of claim 4, wherein, At least one of the first light shielding part, the second light shielding part, the third light shielding part, the first connecting line, the second connecting line, and the third connecting line is connected with a high-potential power line.

6. The display panel of claim 4, wherein, The second light shielding part is connected with the first light shielding part and the second connecting line through the third connecting line, and the third light shielding part is connected with the second connecting line through the third connecting line; the light shielding layer further comprises a fourth connecting line, and adjacent second light shielding parts and / or adjacent third light shielding parts are connected through the fourth connecting line.

7. The display panel of claim 2, wherein, The second light shielding part partially overlaps with the first light shielding part in the first direction, and the third light shielding part is located between two adjacent second connecting lines, and the third light shielding part partially overlaps with the first light shielding part in the second direction.

8. The display panel of claim 7, wherein, The first light shielding part is provided with a notch on the side away from the second light shielding part, and the first connecting line is arranged at the notch.

9. The display panel of claim 1, wherein, Each of the sub-pixels further comprises: a switch transistor connected with the driving transistor at a first node; one electrode of the compensation transistor, one electrode of the first initialization transistor and the driving transistor are connected at a second node, another electrode of the compensation transistor and the driving transistor are connected at a third node, a gate of the switch transistor is connected with a first scan signal line, a first electrode of the switch transistor is connected with a data line, and a second electrode of the switch transistor and the first electrode of the driving transistor are connected at the first node; a gate of the compensation transistor is connected with a second scan signal line, a first electrode of the compensation transistor and the gate of the driving transistor are connected at the second node, and a second electrode of the compensation transistor is connected with a second electrode of the driving transistor; a gate of the first initialization transistor is connected with a third scan signal line, a first electrode of the first initialization transistor is connected with a first initialization signal line, and a second electrode of the first initialization transistor and the gate of the driving transistor are connected at the second node; a first light emitting control transistor, a gate of the first light emitting control transistor is connected with a light emitting control signal line, a first electrode of the first light emitting control transistor is connected with a high potential power supply line, and a second electrode of the first light emitting control transistor and the first electrode of the driving transistor are connected at the first node; a second light emitting control transistor, a gate of the second light emitting control transistor is connected with the light emitting control signal line, and a first electrode of the second light emitting control transistor is connected with the second electrode of the driving transistor at the third node; a second initialization transistor, a gate of the second initialization transistor is connected with a fourth scan signal line, a first electrode of the second initialization transistor is connected with a second initialization signal line, and a second electrode of the second initialization transistor and a second electrode of the second light emitting control transistor are connected at a fourth node; a third initialization transistor, a gate of the third initialization transistor is connected with the fourth scan signal line, a first electrode of the third initialization transistor is connected with a third initialization signal line, and a second electrode of the third initialization transistor and the first electrode of the driving transistor are connected at the first node; One pole plate of the storage capacitor is connected with the high potential power line, the other pole plate of the storage capacitor is connected with the gate of the driving transistor and the second node, and a through hole is arranged on the one pole plate connected with the high potential power line; A boost capacitor, one pole plate of the boost capacitor is connected with the first scan signal line, and the other pole plate of the boost capacitor is connected with the second electrode of the first initialization transistor.

10. The display panel of claim 9, wherein, The first semiconductor layer further comprises a fifth active part of the first light-emitting control transistor, a sixth active part of the second light-emitting control transistor, a seventh active part of the second initialization transistor, and an eighth active part of the third initialization transistor, the first active part is arranged along a first direction, and the first active part is connected with a second active part, the fifth active part and the sixth active part, the second active part and the fifth active part are arranged along a second direction, the sixth active part and the seventh active part are arranged along the second direction, and the sixth active part and the seventh active part are connected, and the eighth active part is arranged apart from the first active part, the third active part, the fifth active part, the sixth active part and the seventh active part; the display panel further comprises: The first gate layer is arranged between the first semiconductor layer and the second semiconductor layer, and comprises the first initialization signal line, the first scan signal line, the light-emitting control signal line, the fourth scan signal line, the gate of the driving transistor, the gate of the switch transistor, the gate of the first light-emitting control transistor, the gate of the second light-emitting control transistor, the gate of the second initialization transistor, the gate of the third initialization transistor, and the first pole plate of the storage capacitor, and the first initialization signal line, the first scan signal line, the first pole plate of the storage capacitor, the light-emitting control signal line and the fourth scan signal line are sequentially arranged apart along the second direction; The second gate layer is arranged on the side of the second semiconductor layer away from the first gate layer, and comprises the second scan signal line, the third scan signal line, the third initialization signal line, the gate of the compensation transistor, and the gate of the first initialization transistor, and the third scan signal line, the second scan signal line and the third initialization signal line are sequentially arranged along the second direction; The first source-drain layer is arranged on the side of the second gate layer away from the second semiconductor layer, and comprises the first data connection line, the first electrode of the switch transistor, the first electrode and the second electrode of the compensation transistor, the first electrode and the second electrode of the first initialization transistor, the first electrode and the second electrode of the first light-emitting control transistor, the first electrode and the second electrode of the second light-emitting control transistor, the first electrode and the second electrode of the second initialization transistor, the first electrode and the second electrode of the third initialization transistor, and the second initialization signal line. A second source-drain layer is disposed on a side of the first source-drain layer away from the second gate layer, and the second source-drain layer comprises the data line, the high-potential power line, a second data connection line and an initialization signal connection line extending along the second direction; Each of the repeating units further comprises two mirror-symmetrical data lines, two mirror-symmetrical high-potential power lines, and mirror-symmetrical second data connection lines and initialization signal connection lines. In the repeating unit, the high-potential power line is located between the second data connection line and the initialization signal connection line, and the second data connection line and the initialization signal connection line are both located between the high-potential power line and the data line.

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