SM3 algorithm-based IP core generation method and device

Abstract

The invention provides an IP core generation method and device based on an SM3 algorithm, and relates to the technical field of information security, and the method comprises the steps: firstly carrying out pure soft implementation on the SM3 algorithm based on a high-level programming language, then carrying out algorithm optimization in multiple modes on an SM3 software code level, and finally generating an IP core with improved performance based on an SM3 optimization code. According to the IP core generation method based on the SM3 algorithm provided by the invention, the operation efficiency of the SM3 algorithm is improved, and the time cost and labor cost of development are reduced, so that the operation performance and efficiency of the SM3 algorithm on an FPGA (Field Programmable Gate Array) can be improved on the basis of reducing the IP core area and reducing the power consumption.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and in particular to an IP core generation method and device based on an SM3 algorithm. Background Art

[0002] The national cryptographic algorithm is a series of algorithms standardized by the National Cryptography Bureau, also known as the national cryptographic algorithm, which includes symmetric encryption algorithms, hash algorithms, and asymmetric encryption algorithms. The SM3 algorithm in the existing national cryptographic algorithm is mainly used for digital signature and verification, message authentication code generation and verification, random number generation, etc.

[0003] However, the SM3 algorithm based on the traditional Register Transfer Level (RTL) hardware implementation requires a large number of computing and processing modules, and has a series of defects such as long development time, low fault tolerance and high human resource requirements. In addition, the simulated IP core has the disadvantages of large area, high power consumption and slow performance rate. Summary of the invention

[0004] The present invention provides an IP core generation method and device based on SM3 algorithm, which are used to solve the above problems existing in the prior art.

[0005] The present invention provides an IP core generation method based on the SM3 algorithm, comprising the following steps: Generate SM3 software code corresponding to SM3 algorithm based on high-level programming language; Optimizing the SM3 software code to generate SM3 optimized code; Based on the SM3 optimized code, an IP core is generated.

[0006] According to a method for generating an IP core based on an SM3 algorithm provided by the present invention, the SM3 software code is optimized to generate an SM3 optimized code, comprising: Revising the SM3 software code to obtain a revised SM3 software code; Compiling and simulating the revised SM3 software code to generate a comprehensive report; The revised SM3 software code is optimized according to the comprehensive report to generate SM3 optimized code.

[0007] According to a method for generating an IP core based on an SM3 algorithm provided by the present invention, the manner of optimizing the SM3 software code includes one or more of the following: The result of message expansion is calculated through a three-stage pipeline; Reduce the number of times intermediate variables are used; The initial vectors and constants in the SM3 algorithm are pre-stored through a lookup table.

[0008] According to an IP core generation method based on the SM3 algorithm provided by the present invention, the method of reducing the number of times the intermediate variables are used includes one or more of the following: Update state variables through local variables; Directly update state variables; Compute and cache the results of intermediate variables in advance.

[0009] According to a method for generating an IP core based on an SM3 algorithm provided by the present invention, the IP core is generated based on the SM3 optimization code, comprising: Based on the SM3 optimized code, generate SM3 hardware code through VIVADO-HLS software; Based on the SM3 hardware code, perform collaborative simulation; Based on the result of the co-simulation, an IP core corresponding to the SM3 optimized code is generated.

[0010] According to a method for generating an IP core based on the SM3 algorithm provided by the present invention, the method further includes: After the IP core is generated, the IP core is encapsulated as an encryption function HMAC-SM3 with a message authentication function; Based on the encryption function HMAC-SM3, an encryption operation corresponding to the security requirements is performed; the encryption operation includes an HMAC-SM3 operation and an SM3 operation.

[0011] According to a method for generating an IP core based on the SM3 algorithm provided by the present invention, the execution of encryption operations corresponding to security requirements includes: When the security requirement is the first security requirement, at least one HMAC-SM3 operation and one SM3 operation are performed, and the HMAC-SM3 operation is performed preferentially; When the safety requirement is the second safety requirement, the SM3 operation is performed at least once.

[0012] The present invention also provides an IP core generation device based on the SM3 algorithm, comprising the following modules: An initial module, used to generate SM3 software code corresponding to the SM3 algorithm based on a high-level programming language; An optimization module, used for optimizing the SM3 software code and generating an SM3 optimized code; A generation module is used to generate an IP core based on the SM3 optimized code.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the IP core generation method based on the SM3 algorithm as described above is implemented.

[0014] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the IP core generation method based on the SM3 algorithm as described above is implemented.

[0015] The present invention provides an IP core generation method based on the SM3 algorithm. First, the SM3 algorithm is implemented purely in software based on a high-level programming language. Then, the algorithm is optimized in multiple ways at the SM3 software code level, thereby improving the operation efficiency of the SM3 algorithm and reducing the time and labor costs of development. Finally, the IP core with improved performance is generated based on the SM3 optimized code. The method can improve the running performance and efficiency of the SM3 algorithm on the FPGA on the basis of reducing the IP core area and reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 This is one of the flow charts of an IP core generation method based on the SM3 algorithm provided by the present invention.

[0018] Figure 2 It is a schematic diagram of the collaborative simulation process in the IP core generation method based on the SM3 algorithm provided by the present invention.

[0019] Figure 3 This is the second flow chart of an IP core generation method based on the SM3 algorithm provided by the present invention.

[0020] Figure 4 It is a structural schematic diagram of an IP core generation device based on the SM3 algorithm provided by the present invention.

[0021] Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0022] With the advent of the information age, information transmission and data transmission are ongoing all the time, and the links between various devices are becoming more numerous and complex, leading to widespread information leakage and theft. Therefore, many fields have begun to pay attention to information security, such as information security in areas such as secure information transmission, device connection, data link, and cloud transmission.

[0023] The IP core generation method based on the SM3 algorithm provided by the present invention develops an IP core of a dedicated encryption and decryption algorithm inside a chip according to the specific protocols of the national cryptographic algorithm and the international cryptographic algorithm. Among them, the national cryptographic algorithm is a series of algorithms formulated by the National Cryptography Bureau, also known as the national secret algorithm, including symmetric encryption algorithms, hash algorithms, and asymmetric encryption algorithms. The SM3 algorithm in the national secret algorithm is a hash function used to perform summary operations on messages of any length, and can generate a message summary of a fixed length, and ensure the strength and uniqueness of the summary, which is suitable for digital signatures and verifications, the generation and verification of message authentication codes, and the generation of random numbers.

[0024] For the IP core development of the SM3 algorithm in the national secret algorithm, traditional development is hardware-implemented through the Verilog language. However, using HLS (High-Level Synthesis, HLS) software for development, the FPGA development time will be greatly reduced compared to the traditional development time, and the entire development process will be more flexible and efficient. Specifically, the algorithm IP core developed by traditional hardware has the disadvantages of being too large in area, too high in power consumption, low in performance, and too slow in running speed. However, HLS software can accelerate the processing of the algorithm and greatly improve the running efficiency. Therefore, the algorithm IP core implemented based on high-level synthesis can improve its performance while ensuring the minimum area.

[0025] The present invention uses VIVADO-HLS software to simulate the SM3 algorithm, and uses C / C++ high-level programming language to compile and generate RTL-level HDL modules. Compared with the hardwareization of traditional encryption and decryption algorithms, it can save a lot of development time and labor costs. In addition, the present invention performs algorithm optimization processing such as algorithm internal loop optimization, pipeline optimization, array partition optimization, data flow optimization, state variable optimization, parameterization optimization and compression function calculation optimization on the SM3 algorithm to ensure that the rate at which the hash algorithm can run on FPGA is greatly enhanced, and the area of ​​the corresponding IP core is minimized.

[0026] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Combine the following Figures 1 to 5 The present invention describes an IP core generation method and device based on the SM3 algorithm.

[0028] Figure 1 FIG. 1 is one of the flow charts of an IP core generation method based on the SM3 algorithm provided by the present invention, such as Figure 1 As shown, the method includes step 101, step 102 and step 103.

[0029] Step 101: Generate SM3 software code corresponding to the SM3 algorithm based on a high-level programming language.

[0030] Based on high-level programming language, compile according to SM3 algorithm to generate corresponding SM3 software code.

[0031] High-level programming languages ​​include C, C++, Python and other languages, and any one of these languages ​​can be selected to compile the SM3 software code corresponding to the SM3 algorithm. In the embodiment of the present invention, C language is used as an example for description.

[0032] The embodiment of the present invention uses C language to compile the SM3 software code (i.e., C language code) corresponding to the SM3 algorithm, so that the algorithm can be optimized directly based on the C language code. Compared with traditional hardware languages ​​(such as Verilog and VHDL), the C language code is less complex, thereby saving development time and labor costs and improving fault tolerance.

[0033] Step 102: Optimize the SM3 software code to generate SM3 optimized code.

[0034] Based on the SM3 software code, the corresponding C language code is optimized to generate SM3 optimized code. The optimization methods include: interface type selection optimization, internal loop optimization, pipeline optimization, array partition optimization, data flow optimization, state variable optimization, parameterization optimization, and compression function calculation optimization.

[0035] Interface type selection optimization. You can use the #pragma HLS INTERFACE instruction to define the interface type (for the SM3 algorithm, you can consider using the s_axilite interface type) to make it compatible with the AXI LITE bus of the PYNQ platform. In this way, when calling the IP core later, you can directly call the library function in the third-party library inside PYNQ, which is convenient and fast.

[0036] Internal loop optimization refers to expanding the calculation of the for loop in the algorithm to minimize the number of loop iterations and improve the parallelism of the hardware.

[0037] Pipeline optimization, pipeline optimization includes calculating the message expansion results in the SM3 algorithm through a three-level pipeline. It is an optimization specifically for calculating the message expansion results in the SM3 algorithm. A three-level pipeline is used to calculate the message expansion results to improve instruction-level parallelism, thereby improving the operating efficiency of the SM3 algorithm.

[0038] The three-stage pipeline structure consists of five components: IF, ID, EX, MEM, and WB. IF (Instruction Fetch) is responsible for reading instructions from memory; ID (Instruction Decode) is responsible for decoding instructions; EX (Execution) is responsible for executing instructions; MEM (Memory) is responsible for accessing memory; and WB (Write Back) is responsible for writing calculation results back to registers.

[0039] The three-stage pipeline uses instruction pipeline technology to divide the instruction processing process into multiple stages, each of which can process different instructions at the same time. In the three-stage pipeline structure, since each stage can process different instructions at the same time, the processing efficiency is improved.

[0040] Array partition optimization refers to partitioning the arrays in the SM3 software code, which can greatly improve parallelism and reduce data dependencies, thereby improving the processing efficiency of the SM3 algorithm.

[0041] Data flow optimization refers to converting the dependencies between function calls in the SM3 algorithm into data flow so that instructions can be executed in parallel.

[0042] State variable optimization, state variable optimization includes reducing the number of times intermediate variables are used to reduce the operation time of the compression function. State variables include original variables and intermediate variables used in the operation process of the SM3 algorithm. In the existing SM3 algorithm, the intermediate variables need to be used multiple times to perform multiple shift operations and multiple registers during the operation. Among them, since the intermediate variables are used multiple times for assignment, it is necessary to read and write data in the registers multiple times, which increases a lot of operation time.

[0043] Therefore, by reducing the number of times intermediate variables are used to optimize state variables, the calculation time can be reduced by reducing the number of times data in registers are read and written. This method will not destroy the original function structure while making improvements, thus ensuring the credibility of the results.

[0044] For example, the message expansion in the SM3 algorithm operation process is merged into the compression function, and the word expansion of the message is performed when it is used, thereby reducing the multiple assignment operations to multiple intermediate variables and reducing the operation time of the compression function. It can also be achieved by: (1) using local variables to optimize the use of state variables. If certain state variables are no longer used in subsequent operations, they can be overwritten as new local variables without the need to use additional intermediate variables to save storage space; (2) in the iterative compression process, directly update the original state variables instead of using intermediate variables to store the updated values, thereby reducing the number of times the intermediate variables are used; (3) splitting the compression function algorithm in the SM3 algorithm and reasonably arranging the calculation order so that the intermediate variables can be calculated in advance and the results can be pre-cached, so that the intermediate variables do not need to be used again during the real-time calculation, reducing the need to use intermediate variables during the real-time calculation, saving calculation time, and thus improving the calculation efficiency of the SM3 algorithm.

[0045] For example, for the calculation of TT1←FFj(A, B, C)+D+SS2+W′, since the calculation of FFj(A, B, C) is independent of the previous calculation results, the intermediate variable FFj(A, B, C) can be calculated in advance and pre-cached, and then when calculating TT1, the cached calculation result can be directly called, thereby saving the time of immediate calculation.

[0046] Parameterized optimization, that is, using macro-defined template parameters, allows the SM3 algorithm to be configured through template parameters and adapt to different hardware requirements more flexibly.

[0047] Compression function calculation optimization, compression function optimization includes pre-storing the initial vectors and constants in the SM3 algorithm through a lookup table to optimize the calculation process of the compression function.

[0048] The compression function is responsible for compressing the input group into a fixed hash value. In the compression function, intermediate variables SS1, SS2, TT1, and TT2 are used for calculation. The specific calculation process is as follows: (1) Initialize the buffers A, B, C, D, E, F, G, and H as 32-bit registers.

[0049] (2) In each round of iteration, use the intermediate variables for shift operations and update the values in the buffers.

[0050] (3) The values in the finally output buffer form a 256-bit message digest of 32 * 8 = 256 bits.

[0051] By using the initial vector IV value of the SM3 algorithm and the constant T j can be pre-stored in the lookup table and directly called during the operation, thus saving the operation time and improving the operation speed. T j The expression of is as follows: For example, in the compression function, loop 64 times, and it is necessary to calculate (T j << j) << 7, that is, the constant is circularly shifted left by j bits and then circularly shifted left by 7 bits. This step can be pre-calculated and put into the lookup table, and it does not affect other operations of SM3, thus saving the calculation time of the compression function. When j is 0, directly call the data at the corresponding position in the lookup table; and so on, corresponding data can be provided for each shift of j bits transformation, reducing the calculation complexity of the compression function and accelerating the calculation process.

[0052] In the embodiment of the present invention, the SM3 algorithm is optimized in various ways such as interface type selection optimization, internal loop optimization, pipeline optimization, array partitioning optimization, data flow optimization, state variable optimization, parameterization optimization, and compression function calculation optimization, modify the corresponding SM3 software code, and generate the SM3 optimized code, thereby providing a basis for subsequent generation of high-performance and low-area IP cores.

[0053] Step 103, generate an IP core based on the SM3 optimized code.

[0054] Based on the SM3 optimized code, through co-simulation with the VIVADO-HLS software, generate the IP core corresponding to the SM3 optimized code. Through the optimization and hardware implementation of the SM3 algorithm, generate the corresponding IP core. The subsequent IP core can be applied to various hardware or chips to execute the SM3 algorithm possessed by the IP core, and can perform encryption, digital signature and verification, message authentication code generation and verification, random number generation, etc.

[0055] IP cores include three levels of classification: behavioral level, structural level and physical level, corresponding to three types of IP cores, namely, soft cores designed by hardware description language, solid cores with completed structural description and hard cores based on physical description and process verification. In the embodiment of the present invention, the soft core in the IP core is generated as an example for explanation.

[0056] Figure 2 FIG. 1 is a flow chart of collaborative simulation in an IP core generation method based on the SM3 algorithm provided by the present invention, such as Figure 2 VIVADO-HLS software is a high-level synthesis tool that can simulate the code corresponding to the high-level programming language (the embodiment of the present invention is described by taking C language code as an example), verify the correctness of the code, and then convert the C language into the hardware language (the embodiment of the present invention is described by taking RTL language as an example) through high-level synthesis, and perform co-simulation of C language and RTL language to generate a corresponding synthesis report, and at the same time generate an IP core containing appropriate interfaces and configuration options, thereby reducing the time required for development.

[0057] For example, VIVADO-HLS software is used to convert the SM3 optimized code into RTL language, and then the SM3 optimized code and RTL language are co-simulated to export the IP core containing the appropriate interface and configuration options.

[0058] The embodiment of the present invention is developed by adopting VIVADO-HLS software, so that the SM3 algorithm can be optimized based on a high-level programming language with lower complexity and converted into a corresponding hardware language, and then co-simulation is performed to generate an IP core. The optimization process is clearer and more direct, which reduces the difficulty and complexity of development, thereby ensuring that the generated IP core can improve performance while reducing the area, and reduce the time and labor costs of development.

[0059] The IP core generation method based on the SM3 algorithm provided by the present invention first implements the SM3 algorithm in pure software based on a high-level programming language, then optimizes the algorithm in multiple ways at the SM3 software code level, thereby improving the operation efficiency of the SM3 algorithm and reducing the time cost and labor cost of development. Finally, an IP core with improved performance is generated based on the SM3 optimized code, thereby improving the operation efficiency of the SM3 algorithm on the FPGA on the basis of reducing the IP core area and reducing power consumption.

[0060] Optionally, the optimizing the SM3 software code to generate the SM3 optimized code includes: Revising the SM3 software code to obtain a revised SM3 software code; Compiling and simulating the revised SM3 software code to generate a comprehensive report; The revised SM3 software code is optimized according to the comprehensive report to generate SM3 optimized code.

[0061] Specifically, Figure 3 FIG. 2 is a flow chart of an IP core generation method based on the SM3 algorithm provided by the present invention. Figure 3 The SM3 software code directly generated based on the SM3 algorithm also needs to be initially revised to adapt to the compilation syntax and compilation environment of VIVADO-HLS, and generate an SM3 performance comprehensive report to verify the correctness of the SM3 software code.

[0062] The embodiment of the present invention uses VIVADO-HLS software to compile the code corresponding to the SM3 algorithm. The compilation under the VIVADO-HLS software environment is different from the traditional pure software implementation of C language. Before compiling, the SM3 software code directly generated by the SM3 algorithm needs to be modified to be suitable for the compilation syntax and compilation environment of VIVADO-HLS, and then the simulation can be performed after the VIVADO-HLS software is successfully compiled. After the simulation process passes normally, a comprehensive report is obtained. Finally, through the comprehensive report, not only can the performance of the SM3 algorithm be clearly checked, but also the performance of the SM3 algorithm can be targetedly improved according to the comprehensive report, that is, the revised SM3 software code is targetedly optimized to obtain the SM3 optimized code.

[0063] If the VIVADO-HLS software compiles successfully but fails during simulation, the cause of the failure will be detected and an error report will be generated instead of a comprehensive report. At this time, you need to return to modify the SM3 software code according to the error report to ensure that the SM3 software code can properly implement the functions of the SM3 algorithm, and simulate again to obtain a comprehensive report, and check the performance of the IP core based on the comprehensive report.

[0064] The embodiment of the present invention compiles and simulates the SM3 software code through the VIVADO-HLS software to ensure that the SM3 software code is successfully compiled in the VIVADO-HLS software, and then generates a comprehensive report through simulation to ensure the correctness of the SM3 software code, and checks the performance of the SM3 algorithm according to the comprehensive report, thereby achieving targeted optimization of the SM3 software code and improving optimization efficiency and reliability.

[0065] Optionally, the manner of improving the SM3 software code includes one or more of the following: The result of message expansion is calculated through a three-stage pipeline; Reduce the number of times intermediate variables are used; The initial vectors and constants in the SM3 algorithm are pre-stored through a lookup table.

[0066] Specifically, the methods for improving the SM3 software code include one or more of the following: 1. Calculate the result of message expansion through a three-stage pipeline. That is, when calculating the message expansion result of the SM3 algorithm, pipeline optimization is performed. By using a three-stage pipeline to calculate the message expansion result, the instruction-level parallelism is improved, thereby improving the SM3 operation efficiency.

[0067] 2. Reduce the number of times intermediate variables are used. In the existing SM3 algorithm, intermediate variables need to be used multiple times to perform multiple shift operations and multiple registers. Since intermediate variables are used multiple times for assignment, the data in the register needs to be read and written multiple times, which increases a lot of computing time.

[0068] Therefore, by reducing the number of times intermediate variables are used to optimize state variables, the calculation time can be reduced by reducing the number of times data in registers are read and written. This method will not destroy the original function structure while making improvements, thus ensuring the credibility of the results.

[0069] For example, the message expansion in the SM3 algorithm operation process is merged into the compression function, and the word expansion of the message is performed when it is used, thereby reducing the multiple assignment operations to multiple intermediate variables and reducing the operation time of the compression function. It is also possible to: (1) use local variables to optimize the use of state variables. If certain state variables are no longer used in the subsequent operation process, they can be overwritten as new local variables without the need to use additional intermediate variables to save storage space; (2) in the iterative compression process, directly update the original state variables instead of using intermediate variables to store the updated values, thereby reducing the number of times the intermediate variables are used; (3) split the compression function algorithm in the SM3 algorithm and arrange the calculation order reasonably, so that the intermediate variables can be calculated in advance and the results can be pre-cached, so that the intermediate variables do not need to be used again during the real-time calculation, reducing the need to use intermediate variables during the real-time calculation, saving calculation time, and thus improving the calculation efficiency of the SM3 algorithm.

[0070] 3. Pre-store the initial vectors and constants in the SM3 algorithm through a lookup table to optimize the calculation process of the compression function.

[0071] The compression function is responsible for compressing the input group into a fixed hash value. In the compression function, intermediate variables SS1, SS2, TT1 and TT2 are used for calculation. The specific calculation process is as follows: (1) Initialize buffers A, B, C, D, E, F, G, and H to 32-bit registers.

[0072] (2) In each iteration, the intermediate variable is used to perform shift operations and update the value in the buffer.

[0073] (3) The values in the finally output buffer form a 256-bit message digest of 32 * 8 = 256 bits.

[0074] By pre-storing the initial vector IV value and the constant Tj of the SM3 algorithm into the lookup table, they can be directly called during the operation, thus saving the operation time and improving the operation speed.

[0075] For example, in the compression function, it loops 64 times, and it is necessary to calculate (T j << j) << 7, that is, the constant is circularly shifted left by j bits and then circularly shifted left by 7 bits. This step can be pre-calculated and put into the lookup table, and it does not affect other operations of SM3, thus saving the calculation time of the compression function. When j is 0, directly call the data at the corresponding position in the lookup table; and so on, corresponding data can be provided each time it is shifted by j bits, reducing the calculation complexity of the compression function and accelerating the calculation process.

[0076] In the embodiment of the present invention, through various methods such as calculating the result of message expansion by a three-stage pipeline, reducing the number of times of using intermediate variables, and pre-storing the initial vector and constants in the SM3 algorithm through a lookup table, targeted improvement is made to the software code corresponding to the SM3 algorithm, which not only effectively accelerates the calculation process of the SM3 algorithm, but also ensures the credibility of the calculation result, thereby improving the operation efficiency of the SM3 algorithm and the performance and reliability of the subsequent generated IP core.

[0077] Optionally, the method of reducing the number of times of using intermediate variables includes one or more of the following: Updating the state variable through a local variable; Directly updating the state variable; Pre-calculating and caching the result of the intermediate variable in advance.

[0078] Specifically, in the existing SM3 algorithm, intermediate variables need to be used multiple times for multiple shift operations and operations with multiple registers during the operation. Among them, due to the multiple use of intermediate variables for assignment, it is necessary to read and write the data in the registers multiple times, resulting in a large increase in the operation time.

[0079] Therefore, by reducing the number of times of using intermediate variables to optimize the state variable, the operation time can be reduced by reducing the number of times of reading and writing the data in the register, and the original function structure will not be damaged when using this method for improvement, ensuring the credibility of the result.

[0080] The method of reducing the number of times of using intermediate variables specifically includes: (1) Use local variables to update state variables. If certain state variables are no longer used in subsequent operations, they can be overwritten with new local variables without using additional intermediate variables, thus saving storage space.

[0081] (2) During the iterative compression process, updates are made directly on the original state variables instead of using intermediate variables to store the updated values, thereby reducing the number of times the intermediate variables are used.

[0082] (3) The compression function algorithm in the SM3 algorithm is split and the calculation order is arranged reasonably, so that the intermediate variables can be calculated in advance and the results can be cached in advance, so that the intermediate variables do not need to be used again during the real-time calculation, which reduces the need to use intermediate variables during the real-time calculation, saves calculation time, and thus improves the calculation efficiency of the SM3 algorithm.

[0083] The embodiments of the present invention reduce the number of times intermediate variables are used in various ways, thereby saving storage space and computing time while ensuring the credibility of calculation results, thereby reducing the area and power consumption of subsequently generated IP cores and improving the computing efficiency and performance of the SM3 algorithm.

[0084] Optionally, generating an IP core based on the SM3 optimization code includes: Based on the SM3 optimized code, generate SM3 hardware code through VIVADO-HLS software; Based on the SM3 hardware code, perform collaborative simulation; Based on the result of the co-simulation, an IP core corresponding to the SM3 optimized code is generated.

[0085] Specifically, VIVADO-HLS software is used to convert the C language code corresponding to the SM3 algorithm, that is, the C language is converted into RTL language (hardware code) through high-level synthesis, and co-simulation of C language and RTL language is performed to generate the corresponding synthesis report. At the same time, the IP core containing appropriate interfaces and configuration options is directly exported, thereby reducing the time required for development.

[0086] The embodiment of the present invention is developed by adopting VIVADO-HLS software, so that the SM3 algorithm can be optimized based on a high-level programming language with lower complexity and converted into a corresponding hardware language, and then co-simulation is performed to generate an IP core, thereby reducing the difficulty and complexity of development and reducing the time and labor costs of development.

[0087] Optionally, the method further comprises: After the IP core is generated, the IP core is encapsulated as an encryption function HMAC-SM3 with a message authentication function; Based on the encryption function HMAC-SM3, an encryption operation corresponding to the security requirements is performed; the encryption operation includes an HMAC-SM3 operation and an SM3 operation.

[0088] Specifically, the IP core generated based on the optimized SM3 algorithm has the advantages of high performance and low area compared to the IP core generated by the traditional SM3 algorithm. It can also be further improved during the packaging process, so that it can add message authentication function on the basis of the original SM3 operation function, that is, to obtain the encryption function HMAC-SM3.

[0089] The encryption function HMAC-SM3 can perform both SM3 and HMAC-SM3 operations. The SM3 operation is used to generate a key-based message authentication code to ensure that data is not tampered with during transmission and storage; the HMAC-SM3 operation can perform message authentication, detect whether the key length meets security requirements, and detect the strength and uniqueness of the summary information generated after the encryption operation of any fixed string.

[0090] During the packaging process, the IP core is further improved to add the message authentication function on the basis of the original SM3 computing function. The specific steps include: (1) Check whether the key length meets the security requirements. For example, if the key length is 256 bits, it needs to be padded to 512 bits first. (2) Fill the fixed string 0x36 to 512 bits and XOR it with the message in step (1), then send it to the encapsulated IP interface for calculation; (3) Fill the fixed string 0x5C to 512 bits, XOR it with step (1), and concatenate it with the result of step (2) to generate its summary information.

[0091] Furthermore, in step (2), the fixed string 0x36 is padded to 512 bits. This operation is performed only when the instruction transmitted by the interface information is to perform the HMAC-SM3 operation. Otherwise, the content of step (2) is to send the message to the encapsulated IP interface for SM3 operation. Furthermore, in step (3), the step is executed only when the instruction transmitted by the interface information is to perform the HMAC-SM3 operation. Otherwise, the step is not executed, and the IP directly outputs the result of step (2) as the summary value.

[0092] The embodiment of the present invention encapsulates the IP core into the encryption function HMAC-SM3, and adds the HMAC-SM3 operation function on the basis of the SM3 operation function of the original SM3 algorithm, so that the encryption function HMAC-SM3 can be called to perform corresponding encryption operations in scenarios with different IP security requirements.

[0093] Optionally, the performing of encryption operations corresponding to the security requirements includes: When the security requirement is the first security requirement, at least one HMAC-SM3 operation and one SM3 operation are performed, and the HMAC-SM3 operation is performed preferentially; When the safety requirement is the second safety requirement, the SM3 operation is performed at least once.

[0094] Specifically, different application scenarios correspond to different IP security requirements, wherein the first security requirement refers to a higher IP security requirement, and the second security requirement refers to a lower IP security requirement.

[0095] For example, when the application scenario is identity authentication, the IP security requirement is message authentication, which has higher IP security requirements. At this time, at least one HMAC-SM3 operation and one SM3 operation need to be performed, and the HMAC-SM3 operation is performed first to detect the security strength and uniqueness of the identity information generated after the encryption operation.

[0096] For another example, when the application scenario is data signature, the IP security requirement is to generate and verify the signature in the data signature system to ensure that the data is not tampered with during transmission and storage, which has lower IP security requirements. At this time, an SM3 operation is performed to generate a key-based message authentication code and encrypt the signature, thereby ensuring that the signature is not tampered with during transmission and storage.

[0097] The embodiment of the present invention calls the encapsulated encryption function HMAC-SM3 in different application scenarios according to different IP security requirements to perform different encryption operations, thereby meeting different IP security requirements.

[0098] An IP core generation device based on the SM3 algorithm provided by the present invention is described below. The IP core generation device based on the SM3 algorithm described below and the IP core generation method based on the SM3 algorithm described above can correspond to each other.

[0099] Based on any of the above embodiments, Figure 4 This is a schematic diagram of the structure of an IP core generation device based on the SM3 algorithm provided in this article. Figure 4 The embodiment of the present invention provides an IP core generation device based on the SM3 algorithm, including an initial module 401, an optimization module 402 and a generation module 403, wherein: The initial module 401 is used to generate the SM3 software code corresponding to the SM3 algorithm based on a high-level programming language; the optimization module 402 is used to optimize the SM3 software code and generate the SM3 optimized code; the generation module 403 is used to generate the IP core based on the SM3 optimized code.

[0100] The present invention provides an IP core generation device based on the SM3 algorithm. The device is developed by adopting VIVADO-HLS software. First, the SM3 algorithm is implemented purely by software based on a high-level programming language. Then, the algorithm is optimized in various ways at the SM3 software code level, thereby improving the operation efficiency of the SM3 algorithm and reducing the time and labor costs of development. Finally, an IP core with improved performance is generated based on the SM3 optimized code, thereby improving the running performance and efficiency of the SM3 algorithm on FPGA on the basis of reducing the IP core area and reducing power consumption.

[0101] Figure 5 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 5 As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the IP core generation method based on the SM3 algorithm, and the method includes: Generate SM3 software code corresponding to SM3 algorithm based on high-level programming language; Optimizing the SM3 software code to generate SM3 optimized code; Based on the SM3 optimized code, an IP core is generated.

[0102] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0103] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer can execute the IP core generation method based on the SM3 algorithm provided by the above methods, the method comprising: Generate SM3 software code corresponding to SM3 algorithm based on high-level programming language; Optimizing the SM3 software code to generate SM3 optimized code; Based on the SM3 optimized code, an IP core is generated.

[0104] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the IP core generation method based on the SM3 algorithm provided by the above methods, the method comprising: Generate SM3 software code corresponding to SM3 algorithm based on high-level programming language; Optimizing the SM3 software code to generate SM3 optimized code; Based on the SM3 optimized code, an IP core is generated.

[0105] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0106] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0107] It should be noted that, in this article, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0108] It should also be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0109] "Determine B based on A" in the embodiments of the present application means that the factor A should be considered when determining B. It is not limited to "B can be determined based on A alone", but should also include: "Determine B based on A and C", "Determine B based on A, C and E", "Determine C based on A, and further determine B based on C", etc. In addition, it can also include taking A as a condition for determining B, for example, "When A meets the first condition, use the first method to determine B"; for another example, "When A meets the second condition, determine B", etc.; for another example, "When A meets the third condition, determine B based on the first parameter", etc. Of course, it can also be a condition that takes A as a factor for determining B, for example, "When A meets the first condition, use the first method to determine C, and further determine B based on C", etc.

[0110] In the present invention, the term "plurality" refers to two or more than two, and other quantifiers are similar to them.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating an IP core based on the SM3 algorithm, characterized in that: include: Generate SM3 software code corresponding to SM3 algorithm based on high-level programming language; Optimizing the SM3 software code to generate SM3 optimized code; Based on the SM3 optimized code, an IP core is generated.

2. The IP core generation method based on the SM3 algorithm according to claim 1, characterized in that: The step of optimizing the SM3 software code to generate the SM3 optimized code includes: Revising the SM3 software code to obtain a revised SM3 software code; Compiling and simulating the revised SM3 software code to generate a comprehensive report; The revised SM3 software code is optimized according to the comprehensive report to generate SM3 optimized code.

3. The IP core generation method based on the SM3 algorithm according to claim 2, characterized in that: The method of optimizing the revised SM3 software code includes one or more of the following: The result of message expansion is calculated through a three-stage pipeline; Reduce the number of times intermediate variables are used; The initial vectors and constants in the SM3 algorithm are pre-stored through a lookup table.

4. The IP core generation method based on the SM3 algorithm according to claim 3 is characterized in that: The method of reducing the number of times the intermediate variables are used includes one or more of the following: Update state variables through local variables; Directly update state variables; Compute and cache the results of intermediate variables in advance.

5. The IP core generation method based on the SM3 algorithm according to claim 1, characterized in that: The generating of IP core based on the SM3 optimized code comprises: Based on the SM3 optimized code, generate SM3 hardware code through VIVADO-HLS software; Based on the SM3 hardware code, perform collaborative simulation; Based on the result of the co-simulation, an IP core corresponding to the SM3 optimized code is generated.

6. The IP core generation method based on the SM3 algorithm according to claim 1, characterized in that: The method further comprises: After the IP core is generated, the IP core is encapsulated as an encryption function HMAC-SM3 with a message authentication function; Based on the encryption function HMAC-SM3, an encryption operation corresponding to the security requirements is performed; the encryption operation includes an HMAC-SM3 operation and an SM3 operation.

7. The IP core generation method based on the SM3 algorithm according to claim 6, characterized in that: The performing of encryption operations corresponding to the security requirements includes: When the security requirement is the first security requirement, at least one HMAC-SM3 operation and one SM3 operation are performed, and the HMAC-SM3 operation is performed preferentially; When the safety requirement is the second safety requirement, the SM3 operation is performed at least once.

8. An IP core generation device based on SM3 algorithm, characterized in that: include: An initial module, used to generate SM3 software code corresponding to the SM3 algorithm based on a high-level programming language; An optimization module, used for optimizing the SM3 software code and generating an SM3 optimized code; A generation module is used to generate an IP core based on the SM3 optimized code.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the IP core generation method based on the SM3 algorithm as described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the IP core generation method based on the SM3 algorithm as claimed in any one of claims 1 to 7 is implemented.

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