A DSP-based self-correcting chain computing device and method for on-chip quantized vector MAC operations

Abstract

The present invention discloses a DSP-based self-correcting chained computing device and method for on-chip quantized vector MAC operations. The device comprises: a cascade structure formed by a plurality of cascade-connected DSP48E2 units; each DSP48E2 unit cascades the calculation results of the upper and lower DSP48E2 units and accumulates the input; each DSP48E2 unit, upon receiving the sign of the upper-level input data, also detects the sign of the lower half calculation result of the upper-level DSP48E2 unit; and generates correction data for the upper half calculation result of the upper-level DSP48E2 unit for packed calculation based on a pre-established correction mechanism; the obtained upper half calculation result correction data is input into the ALU subunit within the DSP48E2 unit of the current level to participate in the upper half addition stage, thereby achieving self-correction of the upper half calculation result of the upper-level DSP48E2 unit. By improving the connection method of the DSP calculation chain and adding an error correction mechanism, the present invention enables the device to process packed MAC calculations of signed low-precision input data without generating errors.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA data processing, and more particularly, relates to a DSP-based self-correcting chain computing device and method for on-chip quantized vector MAC operations. Background Art

[0002] In neural network computing scenarios, vector-matrix multiplication operations frequently occur in the computational data stream, and these operations place high demands on hardware computing power. When performing such calculations on FPGA devices, a large number of digital signal processors (DSPs) are typically called upon to perform processing, but the available DSP resources on-chip are often quite limited. Therefore, fully utilizing DSP resources is crucial for FPGA hardware computing performance, power consumption, and area. However, the DSPs available in Xilinx devices are all implemented as large-bitwidth operators (such as 48-bit accumulators or 18-by-27-bit multipliers). Directly using such DSPs to process relatively low-precision input data results in inadequate utilization of the DSP's computing resources. Therefore, for lower-precision fixed-point multiplication and addition operations, existing technologies have proposed methods for packing and computing two or more multiplication operations, as well as two addition operations, within a single DSP clock cycle.

[0003] However, despite its widespread use, this packing approach still has drawbacks. Existing solutions for handling packed calculations of signed numbers can cause the sign bit of the lower half of the result to overflow, leading to deviations in the upper half. When several such DSPs are cascaded into a calculation chain and performing packed calculations, the resulting deviations accumulate, resulting in significant errors in the final result.

[0004] Existing technologies have also proposed methods for correcting such computational errors. However, these solutions analyze the generation mechanisms and correction methods for packed multiplication and packed addition errors separately, without fully analyzing the error generation mechanisms and correction methods for packed MAC operations, which are more common in neural network computations. Furthermore, these proposed error correction methods are only applicable to error correction for single-stage DSP multiplication or addition packing operations. The proposed error correction scheme for addition calculations is not applicable to packed DSP MAC calculations and cannot be extended to error correction for cascaded DSP chain calculations. Therefore, there is currently a lack of a DSP packed MAC calculation error correction method and corresponding computational structure that is applicable to cascade-scale DSPs. Summary of the Invention

[0005] The present invention aims to overcome the problem in the prior art that packed MAC calculation of signed low-precision input data cannot be processed without generating errors, and provides a DSP-based self-correcting chain calculation device and method for on-chip quantized vector MAC operations.

[0006] The primary purpose of the present invention is to solve the above technical problems, and the technical solutions of the present invention are as follows:

[0007] The first aspect of the present invention provides a DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations, comprising: a plurality of cascade-connected DSP48E2 units, each level of DSP48E2 units comprising a correction data input terminal, a cascade data input terminal, a DSP48E2 module, a cascade data output terminal, a correction generation logic module, a weight data input terminal, and an activation value data input terminal; the specific connection relationship is: the calculation result of the upper level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level are respectively input into the cascade data of the DSP48E2 module of the current level; Input terminal and correction data input terminal, input the weight data and activation value data of this level into the weight data input terminal and activation value data input terminal of the DSP48E2 module of this level respectively, and the output of the DSP48E2 module of this level is obtained through the cascade data output terminal to obtain the calculation result of this level; input the calculation result of this level, the weight data of this level, and the activation value data of this level into the correction generation logic module to obtain the correction data of the upper half of the calculation result of the DSP48E2 unit of this level; input the correction data and the calculation result of this level into the correction data input terminal and the cascade data input terminal of the lower-level DSP48E2 unit respectively.

[0008] Furthermore, the PCIN port of each stage DSP48E2 unit is cascade-connected to the PCOUT port of the upper stage DSP48E2 unit for inputting the calculation results of the upper stage DSP48E2 unit.

[0009] Furthermore, the correction data of the calculation result of the upper half of the upper level is input into the ALU subunit inside the DSP48E2 unit of this level through the C port of the DSP48E2 unit of this level to participate in the addition stage of the upper half.

[0010] Furthermore, the device also includes: a weight buffer and an activation value buffer; the weight values ​​in the neural network calculation are input into the weight buffer, and the weight buffer inputs the weight values ​​of each level into the DSP48E2 unit through the first weight data input terminal (A) and the second weight data input port (D) of the DSP48E2 unit at each level and participates in the package calculation; the activation values ​​in the neural network calculation are input into the activation value buffer, and the activation value buffer inputs the activation values ​​of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

[0011] Furthermore, the device further includes: a final correction unit; the final correction unit is connected to the cascade data output end of the last stage DSP48E2 unit, and the last stage DSP48E2 unit is corrected by the final correction unit.

[0012] The second aspect of the present invention provides a DSP-based self-correcting chain calculation method for on-chip quantized vector MAC operations. The method is applied to a DSP-based self-correcting chain calculation device for on-chip quantized vector MAC operations. The method includes the following steps: inputting the first weight input data (W0) and the second weight input data (W1) of this level into the first-level adder of the DSP48E2 unit of this level for shift addition, inputting the addition result and the activation value data (ACTSHare) of this level into the multiplier for multiplication, inputting the multiplication result and the calculation result of the upper-level DSP48E2 unit and the correction data of the upper-level upper half calculation result generated by a preset correction mechanism into the second-level adder, and outputting the calculation result of the DSP48E2 unit of this level.

[0013] Furthermore, the specific method of using the preset correction mechanism to generate correction data for the upper half calculation result of the upper level is: using the upper level symbol situation and the current level symbol situation to determine in turn whether the upper level DSP48E2 unit generates a +1 error, whether the upper level DSP48E2 unit generates a -1 error, whether there is an error in the upper half calculation of the upper level DSP48E2 unit, and the current level DSP48E2 unit calculates the correction data for the upper half calculation of the upper level DSP48E2 unit.

[0014] Furthermore, the symbol conditions include:

[0015] The first flag is based on the positive or negative sign of the multiplication result of the second half of the multiplication stage calculated by each DSP48E2 unit. If the result sign is negative, it is recorded as the first flag; if the result sign is positive, it is recorded as the second flag.

[0016] The second flag is calculated based on the result of the sign of another addend in addition to the multiplication result in the second half of the addition stage by each DSP48E2 unit. If the result is negative, it is recorded as the first flag; if the result is positive, it is recorded as the second flag.

[0017] Furthermore, in a cascade structure composed of several cascade-connected DSP48E2 units, the DSP48E2 unit at the first stage is not corrected.

[0018] Furthermore, the method also includes: calculating the neural network calculation load by accessing the corresponding weight buffer and activation value buffer; inputting the weight value in the neural network calculation into the weight buffer, and the weight buffer inputs the weight value of each level into the DSP48E2 unit through the first weight data input terminal (A) and the second weight data input port (D) of the DSP48E2 unit at each level and participates in the package calculation; inputting the activation value in the neural network calculation into the activation value buffer, and the activation value buffer inputs the activation value of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

[0019] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0020] The present invention improves the connection mode of the DSP calculation chain and adds an error correction mechanism, so that it can process the packed MAC calculation of signed low-precision input data without generating errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the purpose and technical solution of the present invention clearer, the present invention provides the following drawings and descriptions:

[0022] Figure 1 This is the DSP48E2 unit framework diagram.

[0023] Figure 2 This is a schematic diagram of the conventional quantitative data packaging calculation method.

[0024] Figure 3 This is a schematic diagram of the calculation error generated during the quantized data multiplication and packing calculation process.

[0025] Figure 4 This is a schematic diagram of the calculation error generated during the quantized data addition and packaging calculation process.

[0026] Figure 5 It is a schematic diagram of the self-correcting chain computing device for on-chip quantized vector MAC operations proposed by the present invention.

[0027] Figure 6 This is a schematic diagram of the principle of a single DSP48E2 computing unit.

[0028] Figure 7 This is a schematic diagram of the computational data flow for quantized vector inner product calculations in neural networks.

[0029] Figure 8 It is a schematic diagram of the principle of using a self-correcting chain computing device to realize the inner product calculation of quantized vectors. DETAILED DESCRIPTION

[0030] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0031] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0032] Example 1:

[0033] In FPGA devices, the architecture diagram of DSP48E2 in MACC (Multiply-Accumulate) mode is as follows Figure 1 As shown in , after the data of ports A and D are added, they are multiplied with the data of port B, and then added with the data of port C, and finally the 48-bit result is output from port P. In order to efficiently process the MAC calculation of low-precision data, two or more multiplication and addition operations are usually packaged into a single group of inputs to complete multiple multiplication and addition operations in a single DSP within a single cycle; for example, the calculation of two 8-bit data, c×b=X and c×a=Y, is done with c×(a×2 18 +b)=(Y×2 18 +X) and sent to the corresponding data port, and finally the two calculation results are obtained at the corresponding position of the output port, such as Figure 2 In addition, in some accelerated calculations, the addition part will be packaged into the above calculations according to the needs; for example, based on the above calculations, if we continue to complete the calculations X+B=P0 and Y+A=P1, we will package the addition calculations into the formula: (A×2 18 +X)+c×(a×2 18 + b) = (A × 2 18 +B)+(Y×2 18 +X)=P1×2 18 +P0, and (A×2 18 +B) After being packaged, it is sent from the C port of the DSP to the 48-bit ALU in the DSP for addition, so as to make full use of the computing unit in the DSP to realize DSP chain calculation.

[0034] However, conventional packing calculation methods may cause calculation errors when processing signed data. The calculation errors generated are analyzed as follows:

[0035] The calculation in the above packing calculation formula can be divided into two steps: the packing multiplication stage c×(a×2 18 +b) and the packed addition stage (A×218 +B)+(Y×2 18 +X); the calculation error generated in the packed multiplication stage is as follows: Figure 3 As shown, when the b input, which serves as the lower half of the packing, is non-negative, direct packing calculations present no issues. However, if the lower half of the data is negative, its sign bit overflows into the upper half during the packing calculation, causing errors in the upper half of the data during the addition phase. Furthermore, if the data at multiplication input port B is signed, if the multiplier generates a negative result for the lower half of the multiplication, this will also result in errors in the upper half of the multiplication calculation. Binary multiplication rules show that a negative result for the lower half of the multiplication will cause a -1 deviation in the upper half of the multiplication result.

[0036] In addition, in the packing addition phase, if Figure 4 As shown, if the addition of the lower half generates a carry, this carry will cause the result of the addition of the upper half to deviate by +1. Assuming sufficient bit width is reserved for accumulation, this carry will only be caused by a carry from the sign bit, not by data overflow. Therefore, when both addends in the lower half are positive, no carry overflow will occur. When both addends in the lower half are negative, a carry will definitely occur because their highest sign bits are both 1. When one addend is positive and the other negative, the binary addition carry rule shows that a carry will occur if and only if the result of the addition is positive or 0. Conversely, if the result of the addition is negative, no carry will occur.

[0037] Therefore, to implement complete DSP packed MAC calculation, it is necessary to process the errors of the two parts of calculation, but the existing packed calculation error processing solution cannot handle this situation.

[0038] To this end, the present invention provides a self-correcting chain computing device for on-chip quantized vector MAC operations based on DSP, such as Figure 5As shown, the device includes: a number of cascade-connected DSP48E2 units, each level of DSP48E2 unit includes a correction data input terminal, a cascade data input terminal, a DSP48E2 module, a cascade data output terminal, a correction generation logic module, a weight data input terminal and an activation value data input terminal; the specific connection relationship is: the calculation result of the upper-level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level are respectively input into the cascade data input terminal and the correction data input terminal of the DSP48E2 module of this level, the weight data and activation value data of this level are respectively input into the weight data input terminal and the activation value data input terminal of the DSP48E2 module of this level, and the output of the DSP48E2 module of this level is obtained through the cascade data output terminal to obtain the calculation result of this level; the calculation result of this level, the weight data of this level, and the activation value data of this level are input into the correction generation logic module to obtain the correction data of the upper half of the calculation result of the DSP48E2 unit of this level; the correction data and the calculation result of this level are respectively input into the correction data input terminal and the cascade data input terminal of the lower-level DSP48E2 unit.

[0039] More specifically, the PCIN port of each DSP48E2 unit is cascaded to the PCOUT port of the upper-level DSP48E2 unit for inputting the calculation results of the upper-level DSP48E2 unit. Through the C port of the DSP48E2 unit at this level, the correction data of the upper-half calculation result of the upper-level unit is input into the ALU subunit inside the DSP48E2 unit at this level to participate in the addition stage of the upper half.

[0040] The self-correcting chained computing device described in this invention maintains the original packed data input unchanged by inputting the generated upper half of the calculation result correction data through the DSP's C input port, thereby maximizing the use of DSP unit internal resources to solve the correction problem without using additional computing units. Furthermore, the self-correcting computing device described in this invention can be cascaded into a chain structure, using the DSP unit's PCIN and PCOUT ports to cascade the calculation results and accumulated inputs of the upper and lower calculation stages, and designing a corresponding pipeline structure, ultimately achieving error-free and efficient packed MAC calculations for low-precision signed input data.

[0041] More specifically, the device also includes: a weight buffer and an activation value buffer; the weight values ​​in the neural network calculation are input into the weight buffer, and the weight buffer inputs the weight values ​​of each level into the DSP48E2 unit through the first weight data input terminal (A) and the second weight data input port (D) of the DSP48E2 unit at each level and participates in the package calculation; the activation values ​​in the neural network calculation are input into the activation value buffer, and the activation value buffer inputs the activation values ​​of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

[0042] More specifically, the device further includes: a final correction unit; the final correction unit is connected to the cascade data output terminal of the last stage DSP48E2 unit, and the last stage DSP48E2 unit is corrected by the final correction unit.

[0043] Example 2:

[0044] This embodiment provides a DSP-based self-correcting chained calculation method for on-chip quantized vector MAC operations. Based on the above-mentioned DSP-based self-correcting chained calculation device for on-chip quantized vector MAC operations, the calculation method includes the following steps:

[0045] The first weight input data (W0) and the second weight input data (W1) of this level are input into the first-level adder of the DSP48E2 unit of this level for shift addition, the addition result and the activation value data (ACT SHare) of this level are input into the multiplier for multiplication, the multiplication result and the calculation result of the upper-level DSP48E2 unit and the correction data of the upper half calculation result of the upper level generated by the preset correction mechanism are input into the second-level adder, and the calculation result of the DSP48E2 unit of this level is output.

[0046] More specifically, the specific method of using the preset correction mechanism to generate correction data for the upper half calculation result of the upper level is: using the upper level symbol situation and the current level symbol situation to determine in turn whether the upper level DSP48E2 unit generates a +1 error, whether the upper level DSP48E2 unit generates a -1 error, whether there is an error in the upper half calculation of the upper level DSP48E2 unit, and the current level DSP48E2 unit calculates the correction data for the upper half calculation of the upper level DSP48E2 unit.

[0047] The symbol conditions include:

[0048] The first flag is based on the positive or negative sign of the multiplication result of the second half of the multiplication stage calculated by each DSP48E2 unit. If the result sign is negative, it is recorded as the first flag; if the result sign is positive, it is recorded as the second flag.

[0049] The second flag is calculated based on the result of the sign of another addend in addition to the multiplication result in the second half of the addition stage by each DSP48E2 unit. If the result is negative, it is recorded as the first flag; if the result is positive, it is recorded as the second flag.

[0050] In a specific embodiment, the calculation (A×2 18 +B)+c×(a×2 18 + b) = (A × 2 18 +B)+(Y×2 18 +X)=P1×2 18Taking +P0 as an example, let's consider analyzing and correcting the computational errors. Specifically, consider the impact of the two-part calculation on the error in the result of the first half. As mentioned above, in the packed multiplication phase, if the result of the second half multiplication is negative, the result of the first half will have an error of -1. In the packed addition phase, if the second half addition results in a carry, the result of the first half will have an error of +1.

[0051] Therefore, the error analysis should consider the sign of the multiplication result of the lower half of the multiplication part and the sign of the other addend in addition to the multiplication result in the lower half of the addition part. For convenience of expression, the sign is represented by {last_negative, local_negative}; when the sign of the multiplication result of the lower half of the multiplication part calculated at this level is negative, local_negative is marked as 1, otherwise local_negative is marked as 0; when the sign of the other addend in addition to the multiplication result in the lower half of the addition part of this level is negative, last_negative is marked as 1, otherwise last_negative is marked as 0.

[0052] Therefore, at each level, the errors in the calculation results of the upper half caused by the calculation of the lower half can be summarized as follows: Table 1 is an analysis of the errors in the calculation results of the upper half of each level:

[0053] Table 1

[0054]

[0055]

[0056] Based on the above analysis, if we need to know whether a carry-up error, resulting in a +1 error, occurs in the cases {01} and {10}, we can determine this by looking at the sign of the addition result in the lower half. Therefore, while minimizing the number of additional computing units, in the self-correcting chained computing device of the present invention, the calculation results of the upper-level DSP unit are corrected in the lower-level DSP unit.

[0057] Because the DSP48E2 unit at the first stage of a cascaded structure composed of multiple cascaded DSP48E2 units does not perform correction, in the self-correcting chain computing device proposed by the present invention, the data input symbol status of the upper-stage DSP48E2 unit is transmitted to the lower stage, and the lower stage corrects the upper-stage result.

[0058] The present invention proposes a correction mechanism for a DSP-based self-correcting chained computing structure for on-chip quantized vector MAC operations. Table 2 below shows an error analysis of the previous-stage calculation results under the cascade structure. For ease of presentation, X represents a don't care situation, i.e., it has no effect on the generation of the previous-stage correction input. (X) represents an impossible situation.

[0059] Table 2

[0060]

[0061]

[0062] In Table 2, for a DSP stage, the input to this stage indicates whether the multiplication result is negative (of course, this multiplication result also serves as an addend in the addition stage) and whether the other addend in the addition stage is negative. Based on these two sign conditions, for this stage, sign_situation = {a, b} can be derived. When the multiplication result of this stage is negative, b = 1; when the other addend in the addition stage is negative, a = 1. Therefore, "last_negative" here refers to the sign_situation of the previous stage, while "local_negative" refers to the sign_situation of this stage.

[0063] The following is to calculate PIN+ACT Share×(W1×2 18 + W0) as an example to illustrate the calculation process implemented by the present invention. PIN is the result of the upper level package calculation, which is cascaded to the current level for the package MAC operation.

[0064] like Figure 6 The figure shows a block diagram of a single computational unit. Its operating principle is as follows: "sign situation" represents the sign of the input data. In the first-stage adder, W0 and W1 are shifted and added to achieve concatenation. This is then multiplied by ACT SHARE in the multiplier. In the second-stage adder, this is then added to the PIN input from the previous stage to achieve accumulation. Simultaneously, the correction input generated by the sign situation also participates in this stage's addition, achieving computational correction. Finally, the computational output of this stage is connected to the next stage via the P and PCOUT ports. The sign situation of the input data at this stage is then passed as the sign situation to the next stage to generate the correction input.

[0065] In a specific embodiment, considering the limited number of computing resources in FPGA devices and to avoid adding computing units beyond the DSP slice, the present invention's design transmits the sign of the input data of the current stage to the next stage. The next stage then analyzes the actual error generated by the current stage's packaged calculations based on the sign of the results of the lower half of the current stage, generates corresponding correction data, and inputs it into the DSP's internal ALU unit through the DSP device's C port to participate in the addition of the upper half, thereby correcting the upper half of the calculation results of the upper DSP48E2 unit. The calculation results of the previous stage are cascaded through the PCOUT and PCIN cascade ports and fed into the DSP's ALU unit to perform the PIN+mult MAC calculation.

[0066] In a specific embodiment, the device further includes a final addition correction unit located at the PCOUT port of the last-stage DSP48E2 unit in the cascade structure composed of several cascade-connected DSP48E2 units, and the last-stage DSP48E2 unit is corrected by the final addition correction unit.

[0067] Based on a single computing unit, the present invention expands the computing device into Figure 5 As shown, assuming that the computing device has N stages, the computing device can self-correct the calculation results of the first N-1 stages of computing units without consuming additional computing resources. Only the upper half of the calculation results of the last stage DSP48E2 unit remain uncorrected, with a probability of a calculation error of ±1. The present invention only requires an additional final addition correction unit to eliminate this error, achieving correction without consuming additional computing resources to the greatest extent possible.

[0068] In a specific embodiment, in the FPGA computing acceleration scenario, facing the neural network computing load, vector-matrix multiplication operations will appear frequently in the calculation, which can be decomposed into several N-dimensional vector inner product operations. When facing this computing load, the self-correcting chain computing device for on-chip quantized vector MAC operations with a length of N proposed by the present invention can be implemented, such as Figure 7 、 Figure 8As shown, the method also includes: calculating the neural network computing load by accessing the corresponding weight buffer and activation value buffer; inputting the weight value in the neural network calculation into the weight buffer, and the weight buffer inputs the weight value of each level into the DSP48E2 unit through the first weight data input terminal (A) and the second weight data input port (D) of the DSP48E2 unit at each level and participates in the package calculation; inputting the activation value in the neural network calculation into the activation value buffer, and the activation value buffer inputs the activation value of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation. Assume that the current computing load is the activation values ​​of the N-dimensional vectors A0, A1, A2, ..., A after calculation quantization. i The inner product of two columns of N-dimensional vector weights W0 and W1, for convenience of expression, A ij With W ij That is, the jth element of the corresponding vector i, and A i W j It means A i With W j The inner product result of X represents the data bubble in the pipeline, and the calculation data flow can be as shown in the following Figure 7 As shown in Figure 1. Each element in the weight and activation value vector is input into the calculation chain in time sequence, and then the vector inner product result of W and A is output at the end of the calculation chain.

[0069] By accessing the corresponding weight buffer area and activation value buffer area, the present invention can use the self-correcting chain computing device for on-chip quantized vector MAC operation based on DSP48E2 proposed by the present invention for processing, and its calculation results will not have errors caused by sign bit overflow in signed number packing calculation, nor will there be error accumulation of conventional chain computing devices.

[0070] Table 3 below is a horizontal comparison with related prior art:

[0071] Table 3

[0072]

[0073]

[0074] The comparison results show that the self-correcting chain calculation method proposed in the present invention can completely eliminate the calculation errors of packed MAC calculations with a very small consumption of hardware resources. At the same time, it supports cascading into a chain calculation structure, and can further support packed MAC operations such as vector inner products that are common in neural network calculations. This can increase the calculation throughput of each DSP by 1.75x to 2x, greatly improving calculation efficiency.

[0075] Table 4 below shows the change in resource usage of the self-correcting chain computing device proposed by the present invention as the computing chain grows:

[0076] Table 4

[0077] Calculate chain level LUT Usage FF usage 1 5 3 4 6 7 8 18 7 16 34 7 32 66 7

[0078] It can be concluded from the test results that the growth rate of the hardware resource usage of the self-correcting chain computing device proposed in the present invention is basically linearly related to the growth rate of its computing level, which proves that the self-correcting chain computing device proposed in the present invention has strong scalability and can be expanded to larger computing devices within a relatively low hardware budget.

[0079] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations, characterized in that: include: Several cascade-connected DSP48E2 units, each level of DSP48E2 unit includes a correction data input terminal, a cascade data input terminal, a DSP48E2 module, a cascade data output terminal, a correction generation logic module, a weight data input terminal and an activation value data input terminal; the specific connection relationship is: the calculation result of the upper-level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level are respectively input into the cascade data input terminal and the correction data input terminal of the DSP48E2 module of this level, and the weight data and activation value data of this level are respectively input into the weight data input terminal and the activation value data input terminal of the DSP48E2 module of this level, and the output of the DSP48E2 module of this level is obtained through the cascade data output terminal to obtain the calculation result of this level; The calculation results of this level, the weight data of this level, and the activation value data of this level are input into the correction generation logic module to obtain the correction data of the upper half of the calculation results of the DSP48E2 unit of this level; the correction data and the calculation results of this level are respectively input into the correction data input terminal and the cascade data input terminal of the lower-level DSP48E2 unit.

2. A DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations according to claim 1, characterized in that: The PCIN port of each level of DSP48E2 unit is cascade-connected to the PCOUT port of the upper level DSP48E2 unit for inputting the calculation results of the upper level DSP48E2 unit.

3. The DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations according to claim 1, characterized in that: Through the C port of the DSP48E2 unit at this level, the correction data of the calculation result of the upper half of the upper level is input into the ALU subunit inside the DSP48E2 unit at this level to participate in the addition stage of the upper half.

4. The DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations according to claim 1, characterized in that: The device also includes: a weight buffer and an activation value buffer; the weight values ​​in the neural network calculation are input into the weight buffer, and the weight buffer inputs the weight values ​​of each level into the DSP48E2 unit through the first weight data input terminal and the second weight data input port of the DSP48E2 unit at each level and participates in the package calculation; the activation values ​​in the neural network calculation are input into the activation value buffer, and the activation value buffer inputs the activation values ​​of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

5. The DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations according to claim 1, characterized in that: The device further comprises: a final correction unit; the final correction unit is connected to the cascade data output end of the last stage DSP48E2 unit, and the last stage DSP48E2 unit is corrected by the final correction unit.

6. A DSP-based self-correcting chained computing method for on-chip quantized vector MAC operations, using a DSP-based self-correcting chained computing device for on-chip quantized vector MAC operations according to any one of claims 1 to 5, characterized in that: The following steps are involved: The first weight input data and the second weight input data of this level are input into the first-level adder of the DSP48E2 unit of this level for shift addition, the addition result and the activation value data of this level are input into the multiplier for multiplication, the multiplication result and the calculation result of the upper-level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level generated by the preset correction mechanism are input into the second-level adder, and the calculation result of the DSP48E2 unit of this level is output.

7. The self-correcting chain calculation method for on-chip quantized vector MAC operation based on DSP according to claim 6, characterized in that: The specific method of using the preset correction mechanism to generate correction data for the upper half calculation result of the upper level is: using the upper level symbol situation and the current level symbol situation to determine in turn whether the upper level DSP48E2 unit generates a +1 error, whether the upper level DSP48E2 unit generates a -1 error, whether there is an error in the upper half calculation of the upper level DSP48E2 unit, and the current level DSP48E2 unit calculates the correction data for the upper half calculation of the upper level DSP48E2 unit.

8. The self-correcting chain calculation method for on-chip quantized vector MAC operation based on DSP according to claim 7, characterized in that: The symbol conditions include: The first flag is based on the positive or negative sign of the multiplication result of the second half of the multiplication stage calculated by each DSP48E2 unit. If the result sign is negative, it is recorded as the first flag; if the result sign is positive, it is recorded as the second flag. The second flag is calculated based on the result of the sign of another addend in addition to the multiplication result in the second half of the addition stage by each DSP48E2 unit. If the result is negative, it is recorded as the first flag; if the result is positive, it is recorded as the second flag.

9. The self-correcting chain calculation method for on-chip quantized vector MAC operation based on DSP according to claim 6, characterized in that: In a cascade structure composed of several cascade-connected DSP48E2 units, the DSP48E2 unit at the first stage is not corrected.

10. The self-correcting chain calculation method for on-chip quantized vector MAC operation based on DSP according to claim 6, characterized in that: The method also includes: calculating the neural network calculation load by accessing the corresponding weight buffer and activation value buffer; inputting the weight value in the neural network calculation into the weight buffer, and the weight buffer inputs the weight value of each level into the DSP48E2 unit through the first weight data input terminal and the second weight data input port of the DSP48E2 unit at each level and participates in the package calculation; inputting the activation value in the neural network calculation into the activation value buffer, and the activation value buffer inputs the activation value of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

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