Pixel and display device including same

Abstract

The invention relates to a pixel and a display device including the same. The pixel includes: a light emitting element; a pulse width modulator controlling an emission duration of the light emitting element based on the data voltage; and a constant current generator that supplies a driving current having a constant level to the light emitting element based on the constant current generation voltage. The pulse width modulator includes: a first driving transistor; and an N-type transistor connected to the gate electrode of the first driving transistor, the first electrode, and the second electrode. The constant current generator includes: a second driving transistor; and an N-type transistor connected to the gate electrode, the first electrode, and the second electrode of the second driving transistor.

Description

Technical Field

[0001] Embodiments relate to a pixel and a display device including the pixel. More particularly, embodiments relate to a pixel driven by a pulse width modulation scheme and a display device including the pixel. Background Art

[0002] The display device may include a plurality of pixels, and each of the pixels may include a self-luminous element. The self-luminous element may include an organic light emitting diode, a quantum dot light emitting diode, a micro light emitting diode, and the like.

[0003] Typically, an organic light emitting diode may be driven by a pulse amplitude modulation ("PAM") scheme, which controls the brightness of light emitted from a pixel by controlling the magnitude of a driving current flowing through the organic light emitting diode.

[0004] When the micro-LED is driven by a pulse amplitude modulation scheme, the wavelength of light emitted from the micro-LED may shift according to the magnitude of the driving current flowing through the micro-LED. Therefore, the micro-LED may be driven by a pulse width modulation scheme that controls the brightness of light emitted from a pixel by controlling the emission duration of the micro-LED while maintaining the magnitude of the driving current flowing through the micro-LED constant. Summary of the invention

[0005] Embodiments provide a pixel having relatively low power consumption and a display device including the pixel.

[0006] Embodiments provide a pixel in which leakage current of a light emitting element is reduced and a display device including the pixel.

[0007] The pixel in the embodiment includes: a light-emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; a pulse width modulator to control the emission duration of the light-emitting element based on a data voltage; and a constant current generator to provide a driving current having a constant level to the light-emitting element based on a constant current generating voltage. The pulse width modulator includes: a first driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; and an N-type transistor connected to the gate electrode, the first electrode, and the second electrode of the first driving transistor. The constant current generator includes: a second driving transistor including a gate electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; and an N-type transistor connected to the gate electrode, the first electrode, and the second electrode of the second driving transistor.

[0008] In an embodiment, a pulse width modulator may include: a first write transistor including a gate electrode receiving a scan signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a second node; a first compensation transistor including a gate electrode receiving a scan signal, a first electrode connected to a third node, and a second electrode connected to the first node; a first emission control transistor including a gate electrode receiving an emission control signal, a first electrode receiving a first high power voltage, and a second electrode connected to the second node; a second emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to a third node, and a second electrode connected to a fourth node; a first initialization transistor including a gate electrode receiving a first initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node; and a first capacitor including a first electrode receiving a scan signal and a second electrode connected to the first node.

[0009] In an implementation, the first driving transistor may be a P-type transistor, and each of the first write transistor and the first compensation transistor may be an N-type transistor.

[0010] In an implementation, the first initialization transistor may be an N-type transistor.

[0011] In an implementation, each of the first emission control transistor and the second emission control transistor may be an N-type transistor.

[0012] In an embodiment, the constant current generator may include: a second write transistor including a gate electrode receiving a constant current generation scan signal, a first electrode connected to a data line transmitting a constant current generation voltage, and a second electrode connected to a fifth node; a second compensation transistor including a gate electrode receiving a constant current generation scan signal, a first electrode connected to a sixth node, and a second electrode connected to a fourth node; a third emission control transistor including a gate electrode receiving an emission control signal, a first electrode receiving a second high power voltage, and a second electrode connected to a fifth node; a fourth emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to the sixth node, and a second electrode connected to a first electrode of a light-emitting element; a second initialization transistor including a gate electrode receiving a second initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to a fourth node; a bypass transistor including a gate electrode receiving a bypass gate signal, a first electrode connected to a second initialization voltage line transmitting a second initialization voltage, and a second electrode connected to the first electrode of the light-emitting element; and a second capacitor including a first electrode receiving a second high power voltage and a second electrode connected to the fourth node.

[0013] In an implementation, the second driving transistor may be a P-type transistor, and each of the second write transistor and the second compensation transistor may be an N-type transistor.

[0014] In an implementation, the second initialization transistor may be an N-type transistor.

[0015] In an implementation, each of the third emission control transistor and the fourth emission control transistor may be an N-type transistor.

[0016] In an implementation, the bypass transistor may be an N-type transistor.

[0017] In an embodiment, the second initialization voltage line may be separated from the low power line.

[0018] In an embodiment, a voltage level of the second initialization voltage may be higher than or equal to a voltage level of the low power voltage.

[0019] In an implementation, a voltage level of the first high power voltage may be higher than a voltage level of the second high power voltage.

[0020] In an embodiment, one frame may include a display scan period in which a data voltage is written and a self scan period in which a data voltage is not written. The second initialization gate signal may have a turn-on voltage level in a first initialization period in the display scan period and a second initialization period in the self scan period.

[0021] In an embodiment, the first initialization gate signal may have a turn-on voltage level during the first initialization period and have a turn-off voltage level during the second initialization period.

[0022] The pixel in the embodiment includes: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; a pulse width modulator controlling the emission duration of the light emitting element based on a data voltage; and a constant current generator providing a driving current having a constant level to the light emitting element based on a constant current generating voltage. The constant current generator includes: a bypass transistor including a gate electrode receiving a bypass gate signal, a first electrode connected to a second initialization voltage line transmitting a second initialization voltage and separated from the low power line, and a second electrode connected to the first electrode of the light emitting element.

[0023] In an embodiment, a voltage level of the second initialization voltage may be higher than or equal to a voltage level of the low power voltage.

[0024] In an embodiment, a pulse width modulator may include: a first driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first write transistor including a gate electrode receiving a scan signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a second node; a first compensation transistor including a gate electrode receiving a scan signal, a first electrode connected to the third node, and a second electrode connected to the first node; a first emission control transistor including a gate electrode receiving an emission control signal, a first electrode receiving a first high power voltage, and a second electrode connected to the second node; a second emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a first initialization transistor including a gate electrode receiving a first initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node; and a first capacitor including a first electrode receiving a sweep signal and a second electrode connected to the first node.

[0025] In an implementation, the first driving transistor may be a P-type transistor, and at least one of the first write transistor, the first compensation transistor, and the first initialization transistor may be an N-type transistor.

[0026] In an embodiment, the constant current generator may further include: a second driving transistor including a gate electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; a second write transistor including a gate electrode receiving a constant current generating scan signal, a first electrode connected to a data line transmitting a constant current generating voltage, and a second electrode connected to a fifth node; a second compensation transistor including a gate electrode receiving a constant current generating scan signal, a first electrode connected to a sixth node, and a second electrode connected to a fourth node; a third emission control transistor including a gate electrode receiving an emission control signal, a first electrode receiving a second high power voltage, and a second electrode connected to the fifth node; a fourth emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to the sixth node, and a second electrode connected to the first electrode of the light-emitting element; a second initialization transistor including a gate electrode receiving a second initialization gate signal, a first electrode receiving the first initialization voltage, and a second electrode connected to the fourth node; and a second capacitor including a first electrode receiving a second high power voltage and a second electrode connected to the fourth node.

[0027] In an embodiment, the second driving transistor may be a P-type transistor, and at least one of the second write transistor, the second compensation transistor, and the second initialization transistor may be an N-type transistor.

[0028] In an implementation, a voltage level of the first high power voltage may be higher than a voltage level of the second high power voltage.

[0029] The display device in the embodiment includes: a display panel including a plurality of pixels; a scan driver providing a scan signal to the plurality of pixels in sequence; and a data driver providing a data voltage and a constant current generating voltage to each of the plurality of pixels. Each of the plurality of pixels includes: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; a pulse width modulator controlling the emission duration of the light emitting element based on the data voltage; and a constant current generator providing a driving current having a constant level to the light emitting element based on the constant current generating voltage. The pulse width modulator includes: a first driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; and an N-type transistor connected to the gate electrode, the first electrode, and the second electrode of the first driving transistor. The constant current generator includes: a second driving transistor including a gate electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; and an N-type transistor connected to the gate electrode, the first electrode, and the second electrode of the second driving transistor.

[0030] In an embodiment, a pulse width modulator may include: a first write transistor including a gate electrode receiving a scan signal among a plurality of scan signals, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a second node; a first compensation transistor including a gate electrode receiving the scan signal, a first electrode connected to a third node, and a second electrode connected to the first node; a first emission control transistor including a gate electrode receiving an emission control signal, a first electrode receiving a first high power voltage, and a second electrode connected to the second node; a second emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to a third node, and a second electrode connected to a fourth node; a first initialization transistor including a gate electrode receiving a first initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node; and a first capacitor including a first electrode receiving a sweep signal and a second electrode connected to the first node.

[0031] In an embodiment, the constant current generator may include: a second write transistor including a gate electrode receiving a constant current generation scan signal, a first electrode connected to a data line transmitting a constant current generation voltage, and a second electrode connected to a fifth node; a second compensation transistor including a gate electrode receiving a constant current generation scan signal, a first electrode connected to a sixth node, and a second electrode connected to a fourth node; a third emission control transistor including a gate electrode receiving an emission control signal, a first electrode receiving a second high power voltage, and a second electrode connected to a fifth node; a fourth emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to the sixth node, and a second electrode connected to a first electrode of a light-emitting element; a second initialization transistor including a gate electrode receiving a second initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to a fourth node; a bypass transistor including a gate electrode receiving a bypass gate signal, a first electrode connected to a second initialization voltage line transmitting a second initialization voltage, and a second electrode connected to the first electrode of the light-emitting element; and a second capacitor including a first electrode receiving a second high power voltage and a second electrode connected to the fourth node.

[0032] In an embodiment, the second initialization voltage line may be separated from the low power line.

[0033] The pixel in the embodiment may include an N-type transistor connected to an electrode of the driving transistor, so that power consumption of the pixel can be reduced.

[0034] In the pixel of the embodiment, the second initialization voltage line connected to the first electrode of the bypass transistor can be separated from the low power line connected to the second electrode of the light emitting element, so that leakage current of the light emitting element can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0036] Figure 1 is a block diagram showing an embodiment of a display device.

[0037] Figure 2 Is used to describe Figure 1 Diagram of a variable frequency drive of a display device.

[0038] Figure 3 It is shown that the Figure 1 A circuit diagram of an embodiment of a pixel in a display device.

[0039] Figure 4 is shown in the display scan period to include Figure 1 FIG. 1 is a diagram of an embodiment of signals and voltages provided to pixels in a display device.

[0040] Figures 5 to 10 Is used to describe Figure 3 A diagram showing the operation of a pixel during a display scan period.

[0041] Fig.11 is shown in the self-scan period to include Figure 1 FIG. 1 is a diagram of an embodiment of signals and voltages provided to pixels in a display device.

[0042] Figures 12 to 16 Is used to describe Figure 3 Graph of the operation of a pixel during the self-scan period.

[0043] Fig.17 It is shown that the Figure 1 A circuit diagram of another embodiment of a pixel in a display device.

[0044] Fig.18 is shown in the display scan period to include Figure 1 FIG. 1 is a diagram of another embodiment of signals and voltages provided to pixels in a display device.

[0045] Fig.19 is shown in the self-scan period to include Figure 1 FIG. 1 is a diagram of another embodiment of signals and voltages provided to pixels in a display device.

[0046] Fig. 20 It is shown that the Figure 1 A circuit diagram of another embodiment of a pixel in a display device.

[0047] Fig.21 is shown in the display scan period to include Figure 1 FIG. 1 is a diagram of another embodiment of signals and voltages provided to pixels in a display device.

[0048] Fig. 22 is shown in the self-scan period to include Figure 1 FIG. 1 is a diagram of another embodiment of signals and voltages provided to pixels in a display device.

[0049] Fig.23 It is shown that the Figure 1 A circuit diagram of another embodiment of a pixel in a display device.

[0050] Fig.24 is a block diagram showing an embodiment of a display device.

[0051] Fig.25 It is shown that the Fig.24 A circuit diagram of an embodiment of a pixel in a display device.

[0052] Fig.26 is shown in a frame including Fig.24 FIG. 1 is a diagram of an embodiment of signals and voltages provided to pixels in a display device.

[0053] Fig. 27 is a block diagram showing an embodiment of a display device.

[0054] Fig.28 It is shown that the Fig. 27 A circuit diagram of an embodiment of a pixel in a display device.

[0055] Fig.29 is shown in the display scan period to include Fig. 27 FIG. 1 is a diagram of an embodiment of signals and voltages provided to pixels in a display device.

[0056] Fig.30 is shown in the self-scan period to include Fig. 27 FIG. 1 is a diagram of an embodiment of signals and voltages provided to pixels in a display device.

[0057] Fig.31 is a block diagram showing an embodiment of a display device.

[0058] Fig.32 It is shown that the Fig.31 A circuit diagram of an embodiment of a pixel in a display device.

[0059] Fig.33 is to show the display scan period Fig.32 FIG. 1 is a diagram of an implementation of signals and voltages provided to a pixel.

[0060] Fig.34 It shows that in the self-scan period Fig.32 FIG. 1 is a diagram of an implementation of signals and voltages provided to a pixel.

[0061] Fig.35 is a block diagram illustrating an embodiment of an electronic device.

[0062] Fig.36 It shows that Fig.35 FIG. 1 is a diagram of an implementation example in which the electronic device is implemented as a smart watch. DETAILED DESCRIPTION

[0063] Hereinafter, a pixel and a display device in an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals will be used for the same elements.

[0064] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0065] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as the second element, second component, second region, second layer or second part.

[0066] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, the singular forms "one", "a kind of" and "the" are intended to include plural forms (including "at least one") unless the context clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "include" and / or "include" or "include" and / or "include" specify the presence of the features, regions, wholes, steps, operations, elements and / or components described, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or groups thereof.

[0067] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, relative terms are intended to also include different orientations of the device. For example, if the device in one of the drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, the exemplary term "lower" may include both "lower" and "upper" orientations, depending on the specific orientation of the drawings. Similarly, if the device in one of the drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the exemplary term "below" or "below" may include both upper and lower orientations.

[0068] In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, a term such as "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0069] Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0070] Figure 1 is a block diagram showing an embodiment of the display device 100 .

[0071] refer to Figure 1 , the display device 100 may include a display panel 110 , a scan driver 120 , a data driver 130 , a power management circuit 140 , and a controller 150 .

[0072] The display panel 110 may include pixels PX. In an embodiment, the pixels PX may include a first pixel emitting light having a first color, a second pixel emitting light having a second color, and a third pixel emitting light having a third color. For example, in an embodiment, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0073] The scan driver 120 may sequentially provide the first scan signal SPWM[1] to the nth scan signal SPWM[n] (where n is a natural number greater than 1) to the pixels PX. The scan driver 120 may sequentially generate the first scan signal SPWM[1] to the nth scan signal SPWM[n] corresponding to the first pixel row to the nth pixel row, respectively, based on the first control signal CNT1. The first control signal CNT1 may include a scan clock signal, a scan start signal, etc.

[0074] The data driver 130 may provide a data signal DS to the pixel PX. The data signal DS may include a data voltage VDAT and a constant current generating voltage VCCG. The data driver 130 may generate data signals DS corresponding to the pixel columns respectively based on the second image data IMD2 and the second control signal CNT2. In an embodiment, the second image data IMD2 may include grayscale values ​​corresponding to the pixels PX respectively. The second control signal CNT2 may include a data clock signal, a horizontal start signal, a load signal, etc.

[0075] The power management circuit 140 may provide the first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, the first initialization voltage VINT, the first initialization gate signal VST1, the second initialization gate signal VST2, the constant current generation scan signal SCCG, the emission control signal EM, the sweep signal SWP, and the bypass gate signal BCB to the pixels PX in common. The power management circuit 140 may generate the first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, the first initialization voltage VINT, the first initialization gate signal VST1, the second initialization gate signal VST2, the constant current generation scan signal SCCG, the emission control signal EM, the sweep signal SWP, and the bypass gate signal BCB based on the third control signal CNT3.

[0076] The controller 150 may control the operation (or driving) of the scan driver 120, the operation (or driving) of the data driver 130, and the operation (or driving) of the power management circuit 140. The controller 150 may generate a first control signal CNT1, a second image data IMD2, a second control signal CNT2, and a third control signal CNT3 based on the first image data IMD1 and the control signal CNT. In an embodiment, the first image data IMD1 may include grayscale values ​​corresponding to the pixels PX, respectively. The controller 150 may convert the first image data IMD1 into the second image data IMD2. The control signal CNT may include a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc.

[0077] Figure 2 Is used to describe Figure 1 FIG. 1 is a diagram of a variable frequency drive of a display device 100 .

[0078] refer to Figure 1 and Figure 2 , the display device 100 may display an image through a variable frequency driving scheme capable of changing a driving frequency. The driving frequency may indicate a frequency at which an image is displayed from the display device 100 within one second (in other words, the number of frames FRM).

[0079] Each of the frames FRM of the display device 100 may include a display scanning period DSP and at least one self scanning period SS. During the display scanning period DSP, the data voltage VDAT may be written to the pixel PX, and the pixel PX may emit light for a duration corresponding to the written data voltage VDAT. During the self scanning period SS, the data voltage VDAT may not be written to the pixel PX, and the pixel PX may emit light for a duration corresponding to the data voltage VDAT written in the display scanning period DSP.

[0080] In an embodiment, the length of the display scanning period DSP and the length of the self-scanning period SS may be substantially equal to each other. However, the number of self-scanning periods SS included in the frame FRM may be determined according to the driving frequency. In an embodiment, when the driving frequency decreases, the number of self-scanning periods SS included in the frame FRM may increase.

[0081] When the display device 100 is driven at a first frequency FRQ1 (e.g., about 120 Hz), the frame FRM may include one display scan period DSP and one self scan period SS. When the display device 100 is driven at a second frequency FRQ2 (e.g., about 60 Hz) less than the first frequency FRQ1, the frame FRM may include one display scan period DSP and three consecutive self scan periods SS. When the display device 100 is driven at a third frequency FRQ3 (e.g., about 30 Hz) less than the second frequency FRQ2, the frame FRM may include one display scan period DSP and seven consecutive self scan periods SS.

[0082] Figure 3 It is shown that the Figure 1 A circuit diagram of an implementation of a pixel PX[k] in a display device 100 of FIG. Figure 3 Pixels PX[k] included in a k-th pixel row may be shown (where k is a natural number greater than or equal to 1 and less than or equal to n).

[0083] refer to Figures 1 to 3 , the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM, and a constant current generator CCG. The light emitting element LED may emit light based on a driving current ILED. The light emitting element LED may include a first electrode and a second electrode connected to a low power line VSSL transmitting a low power voltage VSS.

[0084] In an embodiment, the light emitting element LED may be a micro light emitting diode ("μLED"). The micro light emitting diode may refer to an ultra-small light emitting diode having a size of about 100 micrometers (μm) or less.

[0085] The pulse width modulator PWM can control the emission duration of the light emitting element LED based on the data voltage VDAT. The pulse width modulator PWM may include a first driving transistor T1 (hereinafter also referred to as a "first transistor") and at least one N-type transistor (e.g., an N-channel metal oxide semiconductor ("NMOS") transistor) connected to the electrode of the first transistor T1. Compared with a P-type transistor (e.g., a P-channel metal oxide semiconductor ("PMOS") transistor), an N-type transistor may have a relatively small drain-source voltage and may have a relatively small cut-off current. The pulse width modulator PWM may include at least one N-type transistor connected to the electrode of the first transistor T1, so that the power consumption of the pixel PX[k] can be reduced.

[0086] In an embodiment, the pulse width modulator PWM may include a first transistor T1, a first write transistor T2 (hereinafter also referred to as a "second transistor"), a first compensation transistor T3 (hereinafter also referred to as a "third transistor"), a first emission control transistor T4 (hereinafter also referred to as a "fourth transistor"), a second emission control transistor T5 (hereinafter also referred to as a "fifth transistor"), a first initialization transistor T6 (hereinafter also referred to as a "sixth transistor"), and a first capacitor C1.

[0087] The constant current generator CCG can provide a driving current ILED having a constant level to the light emitting element LED based on the constant current generating voltage VCCG. The constant current generator CCG can include a second driving transistor T7 (hereinafter also referred to as a "seventh transistor") and at least one N-type transistor connected to an electrode of the seventh transistor T7. The constant current generator CCG can include at least one N-type transistor connected to an electrode of the seventh transistor T7, so that the power consumption of the pixel PX[k] can be reduced.

[0088] In an embodiment, the constant current generator CCG may include a seventh transistor T7, a second write transistor T8 (hereinafter also referred to as an "eighth transistor"), a second compensation transistor T9 (hereinafter also referred to as a "ninth transistor"), a third emission control transistor T10 (hereinafter also referred to as a "tenth transistor"), a fourth emission control transistor T11 (hereinafter also referred to as an "eleventh transistor"), a second initialization transistor T12 (hereinafter also referred to as a "twelfth transistor"), a bypass transistor T13 (hereinafter also referred to as a "thirteenth transistor"), and a second capacitor C2.

[0089] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 may be turned on based on a voltage difference between the second node N2 and the first node N1.

[0090] The second transistor T2 may include a gate electrode receiving a scan signal SPWM[k] corresponding to the pixel PX[k], a first electrode connected to a data line DL transmitting a data signal DS, and a second electrode connected to a second node N2. The second transistor T2 may transmit a data voltage VDAT to the second node N2 in response to the scan signal SPWM[k] having a turn-on voltage level.

[0091] The third transistor T3 may include a gate electrode receiving the scan signal SPWM[k], a first electrode connected to the third node N3, and a second electrode connected to the first node N1. The third transistor T3 may connect the third node N3 to the first node N1 in response to the scan signal SPWM[k] having a turn-on voltage level. In other words, the third transistor T3 may diode-connect the first transistor T1 in response to the scan signal SPWM[k] having a turn-on voltage level.

[0092] The fourth transistor T4 may include a gate electrode receiving the emission control signal EM, a first electrode receiving the first high power voltage VDD1, and a second electrode connected to the second node N2. The fourth transistor T4 may transmit the first high power voltage VDD1 to the second node N2 in response to the emission control signal EM having a turn-on voltage level.

[0093] The fifth transistor T5 may include a gate electrode receiving the emission control signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The fifth transistor T5 may connect the third node N3 to the fourth node N4 in response to the emission control signal EM having a turn-on voltage level.

[0094] The sixth transistor T6 may include a gate electrode receiving the first initialization gate signal VST1, a first electrode receiving the first initialization voltage VINT, and a second electrode connected to the first node N1. The sixth transistor T6 may transmit the first initialization voltage VINT to the first node N1 in response to the first initialization gate signal VST1 having a turn-on voltage level.

[0095] The seventh transistor T7 may include a gate electrode connected to the fourth node N4, a first electrode connected to the fifth node N5, and a second electrode connected to the sixth node N6. The seventh transistor T7 may generate a driving current ILED corresponding to a voltage difference between the fifth node N5 and the fourth node N4.

[0096] The eighth transistor T8 may include a gate electrode receiving the constant current generation scan signal SCCG, a first electrode connected to the data line DL, and a second electrode connected to the fifth node N5. The eighth transistor T8 may transmit the constant current generation voltage VCCG to the fifth node N5 in response to the constant current generation scan signal SCCG having a turn-on voltage level.

[0097] The ninth transistor T9 may include a gate electrode receiving the constant current generating scan signal SCCG, a first electrode connected to the sixth node N6, and a second electrode connected to the fourth node N4. The ninth transistor T9 may connect the sixth node N6 to the fourth node N4 in response to the constant current generating scan signal SCCG having a turn-on voltage level. In other words, the ninth transistor T9 may diode-connect the seventh transistor T7 in response to the constant current generating scan signal SCCG having a turn-on voltage level.

[0098] The tenth transistor T10 may include a gate electrode receiving the emission control signal EM, a first electrode receiving the second high power voltage VDD2, and a second electrode connected to the fifth node N5. The tenth transistor T10 may transmit the second high power voltage VDD2 to the fifth node N5 in response to the emission control signal EM having a turn-on voltage level.

[0099] The eleventh transistor T11 may include a gate electrode receiving the emission control signal EM, a first electrode connected to the sixth node N6, and a second electrode connected to the first electrode of the light emitting element LED. The eleventh transistor T11 may connect the sixth node N6 to the first electrode of the light emitting element LED in response to the emission control signal EM having a turn-on voltage level.

[0100] The twelfth transistor T12 may include a gate electrode receiving the second initialization gate signal VST2, a first electrode receiving the first initialization voltage VINT, and a second electrode connected to the fourth node N4. The twelfth transistor T12 may transmit the first initialization voltage VINT to the fourth node N4 in response to the second initialization gate signal VST2 having a turn-on voltage level.

[0101] The thirteenth transistor T13 may include a gate electrode receiving a bypass gate signal BCB, a first electrode connected to a second initialization voltage line VAINTL transmitting a second initialization voltage VAINT, and a second electrode connected to a first electrode of the light emitting element LED. The thirteenth transistor T13 may transmit the second initialization voltage VAINT to the first electrode of the light emitting element LED in response to the bypass gate signal BCB having a turn-on voltage level.

[0102] The second initialization voltage line VAINTL may be separated from the low power line VSSL.

[0103] When the second initialization voltage line VAINTL is connected to the low power line VSSL (in other words, when the first electrode of the thirteenth transistor T13 is connected to the second electrode of the light emitting element LED), since the light emitting element LED and the thirteenth transistor T13 are connected in parallel, the leakage current flowing through the light emitting element LED may increase. The light emitting element LED may unintentionally emit light due to the leakage current flowing through the light emitting element LED, and when the display device 100 displays black, the black display characteristics of the display device 100 may deteriorate.

[0104] In the illustrated embodiment, the second initialization voltage line VAINTL can be separated from the low power line VSSL, so that a current path from the first electrode of the light emitting element LED to the second initialization voltage line VAINTL can be formed through the thirteenth transistor T13, and thus, the leakage current flowing through the light emitting element LED can be reduced. Therefore, the black display characteristics of the display device 100 can be improved.

[0105] In an embodiment, each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, and the thirteenth transistor T13 may be a P-type transistor, and each of the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 may be an N-type transistor. In an embodiment, each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, and the thirteenth transistor T13 may be a polysilicon transistor, and each of the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 may be an oxide semiconductor transistor.

[0106] The first capacitor C1 may include a first electrode receiving the sweep signal SWP and a second electrode connected to the first node N1. The first capacitor C1 may store a voltage of the first node N1.

[0107] The second capacitor C2 may include a first electrode receiving the second high power voltage VDD2 and a second electrode connected to the fourth node N4. The second capacitor C2 may store a voltage of the fourth node N4.

[0108] Figure 4 The DSP is shown in the display scan period. Figure 1 FIG. 1 is a diagram of an embodiment of signals and voltages provided to a pixel PX in a display device 100 .

[0109] refer to Figure 1 , Figure 3 and Figure 4 , the display scanning period DSP may include: a first initialization period P1 (hereinafter also referred to as the "first period"), in which the gate electrode of the first transistor T1 and the gate electrode of the seventh transistor T7 are initialized; a first writing period P2 (hereinafter also referred to as the "second period"), in which the data voltage VDAT compensating the threshold voltage of the first transistor T1 is written to the gate electrode of the first transistor T1; a second writing period P3 (hereinafter also referred to as the "third period"), in which the constant current generating voltage VCCG compensating the threshold voltage of the seventh transistor T7 is written to the gate electrode of the seventh transistor T7; a first emission period P4 (hereinafter also referred to as the "fourth period"), in which the light emitting element LED emits light; and a first bypass period P5 (hereinafter also referred to as the "fifth period"), in which the charge of the light emitting element LED is released. The fourth period P4 may include a fourth-first period P4-1 in which the driving current ILED having a constant level flows through the light emitting element LED and a fourth-second period P4-2 in which the driving current ILED does not flow through the light emitting element LED. The periods P1 to P3 and P5 except the fourth period P4 within the display scanning period DSP may be non-emission periods.

[0110] The first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, the first initialization voltage VINT, the first initialization gate signal VST1, the second initialization gate signal VST2, the constant current generation scan signal SCCG, the emission control signal EM, the sweep signal SWP and the bypass gate signal BCB may be commonly provided to the pixels PX. The scan signals SPWM[1], ..., SPWM[k], ... and SPWM[n] may be sequentially provided to the pixels PX based on the pixel rows.

[0111] Each of the first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, and the first initialization voltage VINT may be a constant voltage whose voltage level is constant. In an embodiment, the voltage level VL1 of the first high power voltage VDD1 is higher than the voltage level VL2 of the second high power voltage VDD2. For example, in an embodiment, the voltage level VL1 of the first high power voltage VDD1 may be about 5.2V, and the voltage level VL2 of the second high power voltage VDD2 may be about 4.6V. In an embodiment, the voltage level VL4 of the second initialization voltage VAINT is higher than or equal to the voltage level VL3 of the low power voltage VSS. For example, in an embodiment, the voltage level VL3 of the low power voltage VSS may be -5V, and the voltage level VL4 of the second initialization voltage VAINT may be about -4V to about -5V.

[0112] The data signal DS may have the data voltage VDAT in the second period P2 , and have the constant current generating voltage VCCG in the third period P3 .

[0113] Each of the first and second initialization gate signals VST1 and VST2 may have a turn-on voltage level (eg, a relatively high logic level) in the first period P1 , and have a turn-off voltage level (eg, a relatively low logic level) in the second to fifth periods P2 to P5 .

[0114] The constant current generating scan signal SCCG may have a turn-on voltage level (eg, a relatively high logic level) in the third period P3 , and have a turn-off voltage level (eg, a relatively low logic level) in the first, second, fourth, and fifth periods P1 , P2 , P4 , and P5 .

[0115] Each of the scan signals SPWM[1], ..., SPWM[k], ..., and SPWM[n] may have an on voltage level (e.g., a relatively high logic level) in the second period P2, and an off voltage level (e.g., a relatively low logic level) in the first period P1 and the third to fifth periods P3 to P5. The scan signals SPWM[1], ..., SPWM[k], ..., and SPWM[n] may be sequentially shifted by a predetermined duration (e.g., one horizontal time).

[0116] The emission control signal EM may have a turn-on voltage level (eg, a relatively low logic level) in the fourth period P4 , and have a turn-off voltage level (eg, a relatively high logic level) in the first to third periods P1 to P3 and the fifth period P5 .

[0117] The sweep signal SWP may have a relatively high voltage level in the first to third periods P1 to P3 and the fifth period P5 , and linearly decrease from the relatively high voltage level to a relatively low voltage level in the fourth period P4 .

[0118] The bypass gate signal BCB may have a turn-on voltage level (eg, a relatively low logic level) in the first to third periods P1 to P3 and the fifth period P5 , and have a turn-off voltage level (eg, a relatively high logic level) in the fourth period P4 .

[0119] Figures 5 to 10 Is used to describe Figure 3 FIG. 4 is a diagram showing the operation of pixel PX[k] within the DSP during the display scan period.

[0120] refer to Figure 4 and Figure 5, in the first period P1, the sixth transistor T6 may be turned on in response to the first initialization gate signal VST1 having a turn-on voltage level, and the twelfth transistor T12 may be turned on in response to the second initialization gate signal VST2 having a turn-on voltage level. Therefore, the first initialization voltage VINT may be applied to the first node N1 through the sixth transistor T6, the first initialization voltage VINT may be applied to the fourth node N4 through the twelfth transistor T12, and the gate electrode of the first transistor T1 and the gate electrode of the seventh transistor T7 may be initialized.

[0121] refer to Figure 4 and Figure 6 In the second period P2, the second transistor T2 and the third transistor T3 may be turned on in response to the scan signal SPWM[k] having the turn-on voltage level. Therefore, the data voltage VDAT compensating for the threshold voltage VTH1 of the first transistor T1 may be applied to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3.

[0122] refer to Figure 4 and Figure 7 , in the third period P3, the eighth transistor T8 and the ninth transistor T9 may be turned on in response to the constant current generation scan signal SCCG having the turn-on voltage level. Therefore, the constant current generation voltage VCCG compensating for the threshold voltage VTH2 of the seventh transistor T7 may be applied to the fourth node N4 through the eighth transistor T8, the seventh transistor T7, and the ninth transistor T9.

[0123] refer to Figure 4 and Figure 8 , in the fourth-first period P4-1, the seventh transistor T7 may generate a driving current ILED having a constant level corresponding to the voltage difference between the first electrode and the gate electrode of the seventh transistor T7 (e.g., the voltage difference between the fifth node N5 and the fourth node N4), and the light emitting element LED may emit light having a brightness corresponding to the driving current ILED. In the fourth period P4, the sweep signal SWP may be linearly reduced from a relatively high voltage level to a relatively low voltage level, and the emission control signal EM may have a turn-on voltage level. Therefore, the voltage of the first node N1 may change in response to the change of the sweep signal SWP caused by the coupling effect of the first capacitor C1, and the first high power voltage VDD1 may be applied to the second node N2. Therefore, in the fourth-first period P4-1, the voltage difference between the first electrode and the gate electrode of the first transistor T1 (e.g., the difference between the first high power voltage VDD1 and the voltage of the first node N1) may be less than the threshold voltage VTH1 of the first transistor T1, so that the first transistor T1 may be turned off.

[0124] refer to Figure 4 and Fig. 9 , in the fourth-second period P4-2, since the sweep signal SWP decreases linearly due to the coupling effect of the first capacitor C1, the voltage of the first node N1 can be continuously reduced. Therefore, the voltage difference between the first electrode and the gate electrode of the first transistor T1 (for example, the difference between the first high power voltage VDD1 and the voltage of the first node N1) can be greater than the threshold voltage VTH1 of the first transistor T1, and the first transistor T1 can be turned on. The first high power voltage VDD1 can be applied to the fourth node N4 through the fourth transistor T4, the first transistor T1 and the fifth transistor T5, and the seventh transistor T7 can be turned off. Therefore, the seventh transistor T7 can stop generating the drive current ILED, and the light-emitting element LED can not emit light. In the fourth period P4, the drive current ILED corresponding to the constant current generation voltage VCCG can flow through the light-emitting element LED for a duration corresponding to the data voltage VDAT, and the light-emitting element LED can emit light with a brightness corresponding to the constant current generation voltage VCCG for a duration corresponding to the data voltage VDAT. Therefore, the brightness of the light emitted from the light-emitting element LED can correspond to the emission duration of the light-emitting element LED.

[0125] refer to Figure 4 and Fig.10 In the fifth period P5, the thirteenth transistor T13 may be turned on in response to the bypass gate signal BCB having the turn-on voltage level. Therefore, the charge stored in the first electrode of the light emitting element LED by the parasitic capacitor of the light emitting element LED may be released to the second initialization voltage line VAINTL through the thirteenth transistor T13, and leakage current may be prevented from flowing through the light emitting element LED.

[0126] Fig.11 It is shown that during the self-scan period SS, Figure 1 FIG. 1 is a diagram of an embodiment of providing signals and voltages to pixels PX in the display device 100 .

[0127] refer to Figure 1 , Figure 3 and Fig.11, the self-scan period SS may include: a second initialization period P6 (hereinafter also referred to as the "sixth period"), in which the gate electrode of the seventh transistor T7 is initialized; a third writing period P7 (hereinafter also referred to as the "seventh period"), in which the constant current generation voltage VCCG compensating for the threshold voltage of the seventh transistor T7 is written to the gate electrode of the seventh transistor T7; a second emission period P8 (hereinafter also referred to as the "eighth period"), in which the light-emitting element LED emits light; and a second bypass period P9 (hereinafter also referred to as the "ninth period"), in which the charge of the light-emitting element LED is released. The eighth period P8 may include an eighth-first period P8-1 in which a driving current ILED having a constant level flows through the light-emitting element LED and an eighth-second period P8-2 in which the driving current ILED does not flow through the light-emitting element LED. The periods P6, P7, and P9 other than the eighth period P8 in the self-scan period SS may be non-emission periods.

[0128] About the reference Fig.11 The signals and voltages described will be omitted with reference to Figure 4 The components of the signals and voltages described are substantially the same or similar to the components described.

[0129] The data signal DS may have the constant current generating voltage VCCG in the seventh period P7.

[0130] The first initialization gate signal VST1 has a turn-off voltage level in the sixth period P6 to the ninth period P9. The second initialization gate signal VST2 has a turn-on voltage level in the sixth period P6 and has a turn-off voltage level in the seventh period P7 to the ninth period P9.

[0131] The scan signals SPWM[1], . . . , SPWM[k], . . . , and SPWM[n] may have a turn-off voltage level in the sixth to ninth periods P6 to P9.

[0132] Figures 12 to 16 Is used to describe Figure 3 FIG. 4 is a diagram of the operation of the pixel PX[k] during the self-scan period SS.

[0133] refer to Fig.11 and Fig.12 In the sixth period P6, the twelfth transistor T12 may be turned on in response to the second initialization gate signal VST2 having a turn-on voltage level. Therefore, the first initialization voltage VINT may be applied to the fourth node N4 through the twelfth transistor T12, and the gate electrode of the seventh transistor T7 may be initialized.

[0134] refer to Fig.11 and Fig.13, in the seventh period P7, the eighth transistor T8 and the ninth transistor T9 may be turned on in response to the constant current generation scan signal SCCG having the turn-on voltage level. Therefore, the constant current generation voltage VCCG compensating for the threshold voltage VTH2 of the seventh transistor T7 may be applied to the fourth node N4 through the eighth transistor T8, the seventh transistor T7, and the ninth transistor T9.

[0135] refer to Fig.11 and Fig.14 , in the eighth-first period P8-1, the seventh transistor T7 may generate a driving current ILED having a constant level corresponding to the voltage difference between the first electrode and the gate electrode of the seventh transistor T7 (e.g., the voltage difference between the fifth node N5 and the fourth node N4), and the light emitting element LED may emit light having a brightness corresponding to the driving current ILED. In the eighth period P8, the sweep signal SWP may be linearly reduced from a relatively high voltage level to a relatively low voltage level, and the emission control signal EM may have a turn-on voltage level. Therefore, the voltage of the first node N1 may change in response to the change of the sweep signal SWP caused by the coupling effect of the first capacitor C1, and the first high power voltage VDD1 may be applied to the second node N2. Therefore, in the eighth-first period P8-1, the voltage difference between the first electrode and the gate electrode of the first transistor T1 (e.g., the difference between the first high power voltage VDD1 and the voltage of the first node N1) may be less than the threshold voltage VTH1 of the first transistor T1, so that the first transistor T1 may be turned off.

[0136] refer to Fig.11 and Fig.15, in the eighth-second period P8-2, since the sweep signal SWP decreases linearly due to the coupling effect of the first capacitor C1, the voltage of the first node N1 can be continuously reduced. Therefore, the voltage difference between the first electrode and the gate electrode of the first transistor T1 (for example, the difference between the first high power voltage VDD1 and the voltage of the first node N1) can be greater than the threshold voltage VTH1 of the first transistor T1, and the first transistor T1 can be turned on. The first high power voltage VDD1 can be applied to the fourth node N4 through the fourth transistor T4, the first transistor T1 and the fifth transistor T5, and the seventh transistor T7 can be turned off. Therefore, the seventh transistor T7 can stop generating the drive current ILED, and the light emitting element LED can not emit light. In the eighth period P8, the drive current ILED corresponding to the constant current generation voltage VCCG can flow through the light emitting element LED for a duration corresponding to the data voltage VDAT written in the second period P2, and the light emitting element LED can emit light with a brightness corresponding to the constant current generation voltage VCCG for a duration corresponding to the data voltage VDAT written in the second period P2. The brightness of the light emitted from the light emitting element LED may therefore correspond to the emission duration of the light emitting element LED.

[0137] refer to Fig.11 and Fig.16 In the ninth period P9, the thirteenth transistor T13 may be turned on in response to the bypass gate signal BCB having the turn-on voltage level. Therefore, the charge stored in the first electrode of the light emitting element LED by the parasitic capacitor of the light emitting element LED may be released to the second initialization voltage line VAINTL through the thirteenth transistor T13, and leakage current may be prevented from flowing through the light emitting element LED.

[0138] Fig.17 It is shown that the Figure 1 FIG. 1 is a diagram of another embodiment of a pixel PX[k] in a display device 100 .

[0139] refer to Figure 1 and Fig.17 , the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM and a constant current generator CCG. Fig.17 The pixel PX[k] described will be omitted with reference to Figure 3 The components of the pixel PX[k] described are substantially the same or similar to the components described.

[0140] In an embodiment, each of the first transistor T1, the seventh transistor T7, and the thirteenth transistor T13 may be a P-type transistor, and each of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be an N-type transistor. In an embodiment, each of the first transistor T1, the seventh transistor T7, and the thirteenth transistor T13 may be a polysilicon transistor, and each of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be an oxide semiconductor transistor.

[0141] Fig.18 It shows that during the display scan period, the DSP includes Figure 1 FIG. 1 is a diagram of another embodiment of signals and voltages provided to a pixel PX of the display device 100 . Fig.19 It is shown that during the self-scan period SS, Figure 1 FIG. 1 is a diagram of another embodiment of signals and voltages provided to a pixel PX of the display device 100 .

[0142] About the reference Fig.18 and Fig.19 The signals and voltages described will be omitted with reference to Figure 4 and Fig.11 The components of the signals and voltages described are substantially the same or similar to the components described.

[0143] refer to Fig.18 and Fig.19 , the emission control signal EM may have a turn-on voltage level (e.g., a relatively high logic level) in the fourth period P4 and the eighth period P8, and have a turn-off voltage level (e.g., a relatively low logic level) in the first period P1 to the third period P3, the fifth period P5 to the seventh period P7, and the ninth period P9.

[0144] Fig. 20 It is shown that the Figure 1 A circuit diagram of another embodiment of a pixel PX[k] in the display device 100 is shown.

[0145] refer to Figure 1 and Fig. 20 , the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM and a constant current generator CCG. Fig. 20 The pixel PX[k] described will be omitted with reference to Figure 3The components of the pixel PX[k] described are substantially the same or similar to the components described.

[0146] In an embodiment, each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 may be a P-type transistor, and each of the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 may be an N-type transistor. In an embodiment, each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 may be a polysilicon transistor, and each of the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 may be an oxide semiconductor transistor.

[0147] Fig.21 The DSP is shown in the display scan period. Figure 1 FIG. 1 is a diagram of another embodiment of signals and voltages provided to a pixel PX in a display device 100 . Fig. 22 It is shown that during the self-scan period SS, Figure 1 FIG. 1 is a diagram of another embodiment of signals and voltages provided to a pixel PX in a display device 100 .

[0148] About the reference Fig.21 and Fig. 22 The signals and voltages described will be omitted with reference to Figure 4 and Fig.11 The components of the signals and voltages described are substantially the same or similar to the components described.

[0149] refer to Fig.21 and Fig. 22 , the bypass gate signal BCB can have a turn-on voltage level (e.g., a relatively high logic level) in the first period P1 to the third period P3, the fifth period P5 to the seventh period P7, and the ninth period P9, and have a turn-off voltage level (e.g., a relatively low logic level) in the fourth period P4 and the eighth period P8.

[0150] Fig.23 It is shown that the Figure 1 1 is a circuit diagram of another embodiment of a pixel PX[k] of the display device 100.

[0151] refer to Figure 1 and Fig.23, the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM and a constant current generator CCG. Fig.23 The pixel PX[k] described will be omitted with reference to Figure 3 The components of the pixel PX[k] described are substantially the same or similar to the components described.

[0152] The first transistor T1 may include a first gate electrode connected to the first node N1, a second gate electrode receiving the first high power voltage VDD1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. Therefore, the first transistor T1 may have a dual gate structure including a first gate electrode and a second gate electrode.

[0153] The second transistor T2 may include a first gate electrode receiving the scan signal SPWM[k], a second gate electrode receiving the scan signal SPWM[k], a first electrode connected to the data line DL transmitting the data signal DS, and a second electrode connected to the second node N2. Therefore, the second transistor T2 may have a dual-gate structure including a first gate electrode and a second gate electrode.

[0154] The third transistor T3 may include a first gate electrode receiving the scan signal SPWM[k], a second gate electrode receiving the scan signal SPWM[k], a first electrode connected to the third node N3, and a second electrode connected to the first node N1. Therefore, the third transistor T3 may have a double gate structure including a first gate electrode and a second gate electrode.

[0155] The sixth transistor T6 may include a first gate electrode receiving the first initialization gate signal VST1, a second gate electrode receiving the first initialization gate signal VST1, a first electrode receiving the first initialization voltage VINT, and a second electrode connected to the first node N1. Therefore, the sixth transistor T6 may have a dual-gate structure including a first gate electrode and a second gate electrode.

[0156] The seventh transistor T7 may include a first gate electrode connected to the fourth node N4, a second gate electrode receiving the second high power voltage VDD2, a first electrode connected to the fifth node N5, and a second electrode connected to the sixth node N6. Therefore, the seventh transistor T7 may have a dual-gate structure including a first gate electrode and a second gate electrode.

[0157] The eighth transistor T8 may include a first gate electrode receiving the constant current generating scan signal SCCG, a second gate electrode receiving the constant current generating scan signal SCCG, a first electrode connected to the data line DL, and a second electrode connected to the fifth node N5. Therefore, the eighth transistor T8 may have a double-gate structure including a first gate electrode and a second gate electrode.

[0158] The ninth transistor T9 may include a first gate electrode receiving the constant current generation scan signal SCCG, a second gate electrode receiving the constant current generation scan signal SCCG, a first electrode connected to the sixth node N6, and a second electrode connected to the fourth node N4. Therefore, the ninth transistor T9 may have a dual-gate structure including a first gate electrode and a second gate electrode.

[0159] The twelfth transistor T12 may include a first gate electrode receiving the second initialization gate signal VST2, a second gate electrode receiving the second initialization gate signal VST2, a first electrode receiving the first initialization voltage VINT, and a second electrode connected to the fourth node N4. Therefore, the twelfth transistor T12 may have a double-gate structure including a first gate electrode and a second gate electrode.

[0160] Fig.24 is a block diagram showing an embodiment of the display device 101 .

[0161] refer to Fig.24 , the display device 101 may include a display panel 110, a scan driver 120, a data driver 130, a power management circuit 141 and a controller 150. Fig.24 The display device 101 will be described with reference to Figure 1 Components of the display device 100 described are substantially the same as or similar to the description of the components.

[0162] The power management circuit 141 may provide the first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, the first initialization voltage VINT, the initialization gate signal VST, the constant current generation scan signal SCCG, the emission control signal EM, the sweep signal SWP, and the bypass gate signal BCB to the pixels PX in common. The power management circuit 141 may generate the first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, the first initialization voltage VINT, the initialization gate signal VST, the constant current generation scan signal SCCG, the emission control signal EM, the sweep signal SWP, and the bypass gate signal BCB based on the third control signal CNT3.

[0163] The display device 101 may display an image by a fixed frequency driving scheme in which the driving frequency cannot be changed. Each frame in the display device 101 may include only Figure 2 Display scanning period DSP.

[0164] Fig.25 It is shown that the Fig.24 A circuit diagram of an implementation of a pixel PX[k] in a display device 101 of FIG.

[0165] refer to Fig.24 and Fig.25 , the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM and a constant current generator CCG. Fig.25 The pixel PX[k] described will be omitted with reference to Figure 3 The components of the pixel PX[k] described are substantially the same or similar to the components described.

[0166] The sixth transistor T6 may include a gate electrode receiving the initialization gate signal VST, a first electrode receiving the first initialization voltage VINT, and a second electrode connected to the first node N1. The sixth transistor T6 may transmit the first initialization voltage VINT to the first node N1 in response to the initialization gate signal VST having a turn-on voltage level.

[0167] The twelfth transistor T12 may include a gate electrode receiving the initialization gate signal VST, a first electrode receiving the first initialization voltage VINT, and a second electrode connected to the fourth node N4. The twelfth transistor T12 may transmit the first initialization voltage VINT to the fourth node N4 in response to the initialization gate signal VST having a turn-on voltage level.

[0168] Fig.26 is shown in a frame FRM including Fig.24 FIG. 1 is a diagram of an embodiment of signals and voltages provided to a pixel PX in a display device 101 .

[0169] About the reference Fig.26 The signals and voltages described will be omitted with reference to Figure 4 The components of the signals and voltages described are substantially the same or similar to the components described.

[0170] refer to Fig.26 , the initialization gate signal VST may have a turn-on voltage level (eg, a relatively high logic level) in the first period P1 , and have a turn-off voltage level (eg, a relatively low logic level) in the second to fifth periods P2 to P5 .

[0171] Fig. 27 is a block diagram illustrating an embodiment of the display device 102 .

[0172] refer to Fig. 27 , the display device 102 may include a display panel 110, a scan driver 122, a data driver 130, a power management circuit 142, and a controller 150. Fig. 27 The display device 102 will be omitted from the description. Figure 1 Components of the display device 100 described are substantially the same as or similar to the description of the components.

[0173] The scan driver 122 may sequentially provide first to nth scan signals SPWM[1] to SPWM[n] and first to mth sweep signals SWP[1] to SWP[m] (where m is a natural number greater than 1) to the pixels PX. The scan driver 122 may sequentially generate first to mth sweep signals SWP[1] to SWP[m] corresponding to the first to mth blocks BLK[1] to BLK[m], respectively, based on the first control signal CNT1. Each of the first to mth blocks BLK[1] to BLK[m] may include a plurality of pixel rows.

[0174] The power management circuit 142 can commonly provide a first high power voltage VDD1, a second high power voltage VDD2, a low power voltage VSS, a second initialization voltage VAINT, a first initialization voltage VINT, a first initialization gate signal VST1, a second initialization gate signal VST2, a constant current generation scan signal SCCG, an emission control signal EM and a bypass gate signal BCB to the pixel PX.

[0175] Fig.28 It is shown that the Fig. 27 A circuit diagram of an implementation of a pixel PX[k] in a display device 102 of FIG.

[0176] refer to Fig. 27 and Fig.28 , the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM and a constant current generator CCG. Fig.28 The pixel PX[k] described will be omitted with reference to Figure 3 The components of the pixel PX[k] described are substantially the same or similar to the components described.

[0177] The first capacitor C1 may include a first electrode receiving a sweep signal SWP[j] corresponding to a j-th block including pixels PX[k] therein and a second electrode connected to the first node N1, where j is a natural number greater than or equal to 1 and less than or equal to m.

[0178] Fig.29 It shows that during the display scan period, the DSP includes Fig. 27 FIG. 1 is a diagram of an embodiment of signals and voltages provided to a pixel PX in a display device 102 . Fig.30 It is shown that during the self-scan period SS, Fig. 27 FIG. 1 is a diagram of an embodiment of signals and voltages provided to a pixel PX in a display device 102 .

[0179] About the reference Fig.29 and Fig.30The signals and voltages described will be omitted with reference to Figure 4 and Fig.11 The components of the signals and voltages described are substantially the same or similar to the components described.

[0180] refer to Fig.29 and Fig.30 , a first high power voltage VDD1, a second high power voltage VDD2, a low power voltage VSS, a second initialization voltage VAINT, a first initialization voltage VINT, a first initialization gate signal VST1, a second initialization gate signal VST2, a constant current generation scan signal SCCG, an emission control signal EM, and a bypass gate signal BCB may be commonly provided to the pixels PX. Scan signals SPWM[1], ..., SPWM[k], ..., and SPWM[n] may be sequentially provided to the pixels PX based on pixel rows. Sweep signals SWP[1], ..., SWP[j], ..., and SWP[m] may be sequentially provided to the pixels PX based on blocks.

[0181] Each of the sweep signals SWP[1], ..., SWP[j], ..., and SWP[m] may have a relatively high voltage level in the first period P1 to the third period P3, the fifth period P5 to the seventh period P7, and the ninth period P9, and may have a relatively high voltage level after linearly decreasing from a relatively high voltage level to a relatively low voltage level in the fourth period P4 and the eighth period P8. Each of the sweep signals ..., SWP[j], ..., and SWP[m] other than the first sweep signal SWP[1] may have a relatively low voltage level before linearly decreasing from a relatively high voltage level to a relatively low voltage level. In the fourth period P4 and the eighth period P8, the duration in which the sweep signals SWP[1], ..., SWP[j], ..., and SWP[m] linearly decrease from a relatively high voltage level to a relatively low voltage level may be sequentially shifted by a predetermined duration.

[0182] In reference Figures 27 to 30 In the described display device 102, sweep signals SWP[1], ..., SWP[j], ... and SWP[m], each having a duration in which the voltage level linearly decreases from a relatively high voltage level to a relatively low voltage level, may be provided to the first block BLK[1] to the mth block BLK[m], respectively, so that the pixels PX may emit light sequentially on a block basis during the fourth time period P4 and the eighth time period P8.

[0183] Fig.31 is a block diagram showing an embodiment of the display device 103 .

[0184] refer to Fig.31, the display device 103 may include a display panel 110, a scan driver 123, a data driver 130, a power management circuit 143 and a controller 150. Fig.31 The display device 103 described herein will be omitted with reference to Figure 1 Components of the display device 100 described are substantially the same as or similar to the description of the components.

[0185] The scan driver 123 may sequentially provide the pixels PX with first scan signals SPWM[1] to nth scan signals SPWM[n], first first initialization gate signals VST1[1] to nth first initialization gate signals VST1[n], first second initialization gate signals VST2[1] to nth second initialization gate signals VST2[n], first constant current generation scan signals SCCG[1] to nth constant current generation scan signals SCCG[n], first emission control signals EM[1] to nth emission control signals EM[n], first frequency sweep signals SWP[1] to nth frequency sweep signals SWP[n], and first bypass gate signals BCB[1] to nth bypass gate signals BCB[n]. The scan driver 123 can sequentially generate the first scan signal SPWM[1] to the nth scan signal SPWM[n], the first first initialization gate signal VST1[1] to the nth first initialization gate signal VST1[n], the first second initialization gate signal VST2[1] to the nth second initialization gate signal VST2[n], the first constant current generation scan signal SCCG[1] to the nth constant current generation scan signal SCCG[n], the first emission control signal EM[1] to the nth emission control signal EM[n], the first sweep signal SWP[1] to the nth sweep signal SWP[n] and the first bypass gate signal BCB[1] to the nth bypass gate signal BCB[n] based on the first control signal CNT1.

[0186] The power management circuit 143 may commonly provide the first high power voltage VDD1 , the second high power voltage VDD2 , the low power voltage VSS, the second initialization voltage VAINT, and the first initialization voltage VINT to the pixels PX.

[0187] Fig.32 It is shown that the Fig.31 A circuit diagram of an implementation of a pixel PX[k] in a display device 103 of FIG.

[0188] refer to Fig.31 and Fig.32 , the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM and a constant current generator CCG. Fig.32 The pixel PX[k] described will be omitted with reference to Figure 3The components of the pixel PX[k] described are substantially the same or similar to the components described.

[0189] The fourth transistor T4 may include a gate electrode receiving the emission control signal EM[k] corresponding to the pixel PX[k], a first electrode receiving the first high power voltage VDD1 , and a second electrode connected to the second node N2 .

[0190] The fifth transistor T5 may include a gate electrode receiving the emission control signal EM[k], a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0191] The sixth transistor T6 may include a gate electrode receiving a first initialization gate signal VST1[k] corresponding to the pixel PX[k], a first electrode receiving a first initialization voltage VINT, and a second electrode connected to the first node N1.

[0192] The eighth transistor T8 may include a gate electrode receiving the constant current generating scan signal SCCG[k] corresponding to the pixel PX[k], a first electrode connected to the data line DL, and a second electrode connected to the fifth node N5.

[0193] The ninth transistor T9 may include a gate electrode receiving the constant current generating scan signal SCCG[k], a first electrode connected to the sixth node N6, and a second electrode connected to the fourth node N4.

[0194] The tenth transistor T10 may include a gate electrode receiving the emission control signal EM[k], a first electrode receiving the second high power voltage VDD2 , and a second electrode connected to the fifth node N5 .

[0195] The eleventh transistor T11 may include a gate electrode receiving the emission control signal EM[k], a first electrode connected to the sixth node N6, and a second electrode connected to the first electrode of the light emitting element LED.

[0196] The twelfth transistor T12 may include a gate electrode receiving a second initialization gate signal VST2[k] corresponding to the pixel PX[k], a first electrode receiving a first initialization voltage VINT, and a second electrode connected to a fourth node N4.

[0197] The thirteenth transistor T13 may include a gate electrode receiving a bypass gate signal BCB[k] corresponding to the pixel PX[k], a first electrode connected to a second initialization voltage line VAINTL transmitting a second initialization voltage VAINT, and a second electrode connected to a first electrode of the light emitting element LED.

[0198] The first capacitor C1 may include a first electrode receiving a sweep signal SWP[k] corresponding to the pixel PX[k] and a second electrode connected to the first node N1.

[0199] Fig.33 is to show the display scan period Fig.32 Schematic diagram of an embodiment of the signals and voltages provided to the pixel PX[k]. Fig.34 It shows that in the self-scan period Fig.32 Schematic diagram of an embodiment of the signals and voltages provided to the pixel PX[k].

[0200] About the reference Fig.31 , Fig.33 and Fig.34 The signals and voltages described will be omitted with reference to Figure 4 and Fig.11 The components of the signals and voltages described are substantially the same or similar to the components described.

[0201] refer to Fig.31 , Fig.33 and Fig.34 , the display scanning period DSP[k] for the k-th pixel row may include a first period P1, a second period P2, a third period P3, a fourth period P4, and a fifth period P5. The self-scanning period SS[k] for the k-th pixel row may include a sixth period P6, a seventh period P7, an eighth period P8, and a ninth period P9. The display scanning period and the self-scanning period for the pixel row may be shifted based on the pixel row by the duration corresponding to the first period P1.

[0202] The first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, and the first initialization voltage VINT may be commonly provided to the pixels PX. The first initialization gate signals VST1[1], ..., VST1[k], ..., and VST1[n], the second initialization gate signals VST2[1], ..., VST2[k], ..., and VST2[n], the constant current generation scan signals SCCG[1], ..., SCCG[k], ..., and SCCG[n], the scan signals SPWM[1], ..., SPWM[k], ..., and SPWM[n], the emission control signals EM[1], ..., EM[k], ..., and EM[n], the sweep signals SWP[1], ..., SWP[k], ..., and SWP[n], and the bypass gate signals BCB[1], ..., BCB[k], ..., and BCB[n] may be sequentially provided to the pixels PX based on the pixel rows.

[0203] The data signal DS may have a data voltage VDAT[k] in the second period P2 and a constant current generation voltage VCCG[k] in the third period P3. The data voltage VDAT[k+1] and the constant current generation voltage VCCG[k+1] for the k+1th pixel row may be shifted from the data voltage VDAT[k] and the constant current generation voltage VCCG[k] for the kth pixel row by a duration corresponding to the first period P1.

[0204] The first initialization gate signal VST1 [k] may have a turn-on voltage level in the first period P1 , and have a turn-off voltage level in the second to ninth periods P2 to P9 .

[0205] The second initialization gate signal VST2 [k] may have a turn-on voltage level in the first period P1 and the sixth period P6 , and have a turn-off voltage level in the second period P2 to the fifth period P5 and the seventh period P7 to the ninth period P9 .

[0206] The constant current generating scan signal SCCG[k] may have an on voltage level in the third and seventh periods P3 and P7 , and have an off voltage level in the first, second, fourth to sixth, eighth, and ninth periods P1 , P2 , P4 to P6 , P8 , and P9 .

[0207] The scan signal SPWM[k] may have an on voltage level in the second period P2 , and have an off voltage level in the first period P1 and the third to ninth periods P3 to P9 .

[0208] The emission control signal EM[k] may have a turn-on voltage level in the fourth period P4 and the eighth period P8 , and have a turn-off voltage level in the first to third periods P1 to P3 , the fifth to seventh periods P5 to P7 , and the ninth period P9 .

[0209] The sweep signal SWP[k] may have a turn-on voltage level in the first to third periods P1 to P3 , the fifth to seventh periods P5 to P7 , and the ninth period P9 , and linearly decrease from a relatively high voltage level to a relatively low voltage level in the fourth and eighth periods P4 and P8 .

[0210] The bypass gate signal BCB[k] may have a turn-on voltage level in the first to third periods P1 to P3 , the fifth to seventh periods P5 to P7 , and the ninth period P9 , and have a turn-off voltage level in the fourth and eighth periods P4 and P8 .

[0211] Fig.35 is a diagram showing an electronic device 1000 . Fig.36 It shows that Fig.35FIG. 1 is a diagram of an embodiment in which the electronic device 1000 is implemented as a smart watch.

[0212] refer to Fig.35 and Fig.36 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output ("I / O") device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 may also include a plurality of ports capable of communicating with a graphics card, a sound card, a memory card, a universal serial bus ("USB") device, etc., or communicating with other systems.

[0213] In an embodiment, if Fig.36 As shown in , the electronic device 1000 can be implemented as a smart watch. However, the present disclosure is not limited thereto, and in another embodiment, the electronic device 1000 can be implemented as a television, a mobile phone, a video phone, a smart tablet, a tablet personal computer ("PC"), a car navigation system, a laptop computer, a head-mounted display, etc.

[0214] The processor 1010 may perform a predetermined calculation or task. In an embodiment, the processor 1010 may be a microprocessor, a central processing unit ("CPU"), etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. In an embodiment, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect ("PCI") bus. In an embodiment, the processor 1010 may provide the first image data ( Figure 1 , Fig.24 , Fig. 27 and Fig.31 IMD1) and control signal ( Figure 1 , Fig.24 , Fig. 27 and Fig.31 of CNT).

[0215] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, in an embodiment, the memory device 1020 may include: a non-volatile memory device such as an erasable programmable read-only memory ("EPROM"), an electrically erasable programmable read-only memory ("EEPROM"), a flash memory, a phase change random access memory ("PRAM"), a resistive random access memory ("RRAM"), a nano floating gate memory ("NFGM"), a polymer random access memory ("PoRAM"), a magnetic random access memory ("MRAM"), or a ferroelectric random access memory ("FRAM"); and / or a volatile memory device such as a dynamic random access memory ("DRAM"), a static random access memory ("SRAM"), or a mobile DRAM.

[0216] The storage device 1030 may include a solid-state drive ("SSD"), a hard disk drive ("HDD"), a compact disk read-only memory ("CD-ROM"), etc. The I / O device 1040 may include an input device such as a keyboard, a keypad, a touch pad, a touch screen, or a mouse; and an output device such as a speaker or a printer. The power supply 1050 may provide the power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components via a bus or other communication links. The display device 1060 may correspond to Figure 1 The display device 100, Fig.24 The display device 101, Fig. 27 The display device 102 and Fig.31 Thus, the display device 1060 may include pixels operated (or driven) by a pulse width modulation scheme, such as Figure 3 , Fig.17 , Fig. 20 , Fig.23 , Fig.25 , Fig.28 and Fig.32 The pixel PX[k] shown in .

[0217] The display device in the embodiment can be applied to display devices included in computers, notebook computers, mobile phones, smart phones, smart tablets, smart watches, portable media players ("PMP"), personal digital assistants ("PDA"), Moving Picture Experts Group standard audio layer III ("MP3") players, etc.

[0218] Although the pixel and the display device in the embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples, and modifications and changes may be made by those skilled in the art without departing from the technical spirit described in the appended claims.

Claims

1. A pixel comprising: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; A pulse width modulator, which controls the emission duration of the light emitting element based on the data voltage, the pulse width modulator comprising: The first driving transistor comprises: a gate electrode connected to the first node; a first electrode connected to the second node; and a second electrode connected to a third node; and An N-type transistor connected to the gate electrode of the first driving transistor, the first electrode, and the second electrode; and a constant current generator for providing a driving current having a constant level to the light emitting element based on a constant current generating voltage, the constant current generator comprising: The second driving transistor comprises: a gate electrode connected to the fourth node; a first electrode connected to the fifth node; and a second electrode connected to the sixth node; and An N-type transistor is connected to the gate electrode of the second driving transistor, the first electrode, and the second electrode.

2. The pixel according to claim 1, wherein: The pulse width modulator comprises: A first write transistor comprising: A gate electrode, receiving a scanning signal; a first electrode connected to a data line transmitting the data voltage; and a second electrode connected to the second node; A first compensation transistor comprising: A gate electrode, receiving the scanning signal; a first electrode connected to the third node; and a second electrode connected to the first node; A first emission control transistor comprising: A gate electrode, receiving an emission control signal; a first electrode receiving a first high power voltage; and a second electrode connected to the second node; The second emission control transistor comprises: a gate electrode, receiving the emission control signal; a first electrode connected to the third node; and a second electrode connected to the fourth node; A first initialization transistor includes: A gate electrode, receiving a first initialization gate signal; A first electrode receiving a first initialization voltage; and a second electrode connected to the first node; and A first capacitor comprising: A first electrode receives a frequency sweep signal; and A second electrode is connected to the first node.

3. The pixel according to claim 2, wherein: The first driving transistor is a P-type transistor, and Each of the first write transistor and the first compensation transistor is an N-type transistor.

4. The pixel according to claim 3, wherein: The first initialization transistor is an N-type transistor.

5. The pixel according to claim 3, wherein: Each of the first emission control transistor and the second emission control transistor is an N-type transistor.

6. The pixel according to claim 2, wherein: The constant current generator comprises: A second write transistor comprising: A gate electrode receives a constant current to generate a scanning signal; a first electrode connected to the data line transmitting the constant current generating voltage; and a second electrode connected to the fifth node; The second compensation transistor comprises: A gate electrode, receiving the constant current to generate a scanning signal; a first electrode connected to the sixth node; and a second electrode connected to the fourth node; A third emission control transistor comprises: a gate electrode, receiving the emission control signal; a first electrode receiving a second high power voltage; and a second electrode connected to the fifth node; A fourth emission control transistor comprising: a gate electrode, receiving the emission control signal; a first electrode connected to the sixth node; and a second electrode connected to the first electrode of the light emitting element; The second initialization transistor comprises: A gate electrode receiving a second initialization gate signal; A first electrode, receiving the first initialization voltage; and a second electrode connected to the fourth node; Bypass transistor, including: A gate electrode, receiving a bypass gate signal; a first electrode connected to a second initialization voltage line transmitting a second initialization voltage; and a second electrode connected to the first electrode of the light emitting element; and a second capacitor comprising: a first electrode receiving the second high power voltage; and The second electrode is connected to the fourth node.

7. The pixel according to claim 6, wherein: The second driving transistor is a P-type transistor, and Each of the second write transistor and the second compensation transistor is an N-type transistor.

8. The pixel according to claim 7, wherein: The second initialization transistor is an N-type transistor.

9. The pixel according to claim 7, wherein: Each of the third emission control transistor and the fourth emission control transistor is an N-type transistor.

10. The pixel according to claim 7, wherein: The bypass transistor is an N-type transistor.

11. The pixel according to claim 6, wherein: The second initialization voltage line is separated from the low power line.

12. The pixel according to claim 11, wherein: A voltage level of the second initialization voltage is higher than or equal to a voltage level of the low power voltage.

13. The pixel according to claim 6, wherein: A voltage level of the first high power voltage is higher than a voltage level of the second high power voltage.

14. The pixel according to claim 6, wherein: One frame includes a display scanning period in which the data voltage is written and a self scanning period in which the data voltage is not written, and The second initialization gate signal has a turn-on voltage level in a first initialization period within the display scanning period and in a second initialization period within the self scanning period.

15. The pixel according to claim 14, wherein: The first initialization gate signal has a turn-on voltage level in the first initialization period, and has a turn-off voltage level in the second initialization period.

16. A pixel comprising: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; a pulse width modulator to control the emission duration of the light emitting element based on the data voltage; as well as a constant current generator for providing a driving current having a constant level to the light emitting element based on a constant current generating voltage, the constant current generator comprising: Bypass transistor, including: A gate electrode, receiving a bypass gate signal; a first electrode connected to a second initialization voltage line transmitting a second initialization voltage and separated from the low power line; and A second electrode is connected to the first electrode of the light emitting element.

17. The pixel according to claim 16, wherein: A voltage level of the second initialization voltage is higher than or equal to a voltage level of the low power voltage.

18. The pixel according to claim 16, wherein: The pulse width modulator comprises: The first driving transistor comprises: a gate electrode connected to the first node; a first electrode connected to the second node; and a second electrode connected to a third node; A first write transistor comprising: A gate electrode, receiving a scanning signal; a first electrode connected to a data line transmitting the data voltage; and a second electrode connected to the second node; A first compensation transistor comprising: A gate electrode, receiving the scanning signal; a first electrode connected to the third node; and a second electrode connected to the first node; A first emission control transistor comprising: A gate electrode, receiving an emission control signal; a first electrode receiving a first high power voltage; and a second electrode connected to the second node; The second emission control transistor comprises: a gate electrode, receiving the emission control signal; a first electrode connected to the third node; and a second electrode connected to a fourth node; A first initialization transistor includes: A gate electrode, receiving a first initialization gate signal; A first electrode receiving a first initialization voltage; and a second electrode connected to the first node; and A first capacitor comprising: A first electrode receives a frequency sweep signal; and A second electrode is connected to the first node.

19. The pixel according to claim 18, wherein: The first driving transistor is a P-type transistor, and At least one of the first write transistor, the first compensation transistor, and the first initialization transistor is an N-type transistor.

20. The pixel according to claim 18, wherein: The constant current generator also includes: The second driving transistor comprises: a gate electrode connected to the fourth node; a first electrode connected to the fifth node; and a second electrode connected to the sixth node; A second write transistor comprising: A gate electrode receives a constant current to generate a scanning signal; a first electrode connected to the data line transmitting the constant current generating voltage; and a second electrode connected to the fifth node; The second compensation transistor comprises: A gate electrode, receiving the constant current to generate a scanning signal; a first electrode connected to the sixth node; and a second electrode connected to the fourth node; A third emission control transistor comprises: a gate electrode, receiving the emission control signal; a first electrode receiving a second high power voltage; and a second electrode connected to the fifth node; A fourth emission control transistor comprising: a gate electrode, receiving the emission control signal; a first electrode connected to the sixth node; and a second electrode connected to the first electrode of the light emitting element; The second initialization transistor comprises: A gate electrode receiving a second initialization gate signal; A first electrode, receiving the first initialization voltage; and a second electrode connected to the fourth node; and A second capacitor comprising: a first electrode receiving the second high power voltage; and The second electrode is connected to the fourth node.

21. The pixel according to claim 20, wherein: The second driving transistor is a P-type transistor, and At least one of the second write transistor, the second compensation transistor, and the second initialization transistor is an N-type transistor.

22. The pixel according to claim 20, wherein: A voltage level of the first high power voltage is higher than a voltage level of the second high power voltage.

23. A display device comprising: Display panel, including: a plurality of pixels, each of the plurality of pixels comprising: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; A pulse width modulator, which controls the emission duration of the light emitting element based on the data voltage, the pulse width modulator comprising: The first driving transistor comprises: a gate electrode connected to the first node; a first electrode connected to the second node; and a second electrode connected to a third node; and An N-type transistor connected to the gate electrode of the first driving transistor, the first electrode, and the second electrode; and a constant current generator for providing a driving current having a constant level to the light emitting element based on a constant current generating voltage, the constant current generator comprising: The second driving transistor comprises: a gate electrode connected to the fourth node; a first electrode connected to the fifth node; and a second electrode connected to the sixth node; and an N-type transistor connected to the gate electrode of the second driving transistor, the first electrode, and the second electrode; A scanning driver for sequentially providing scanning signals to the plurality of pixels; and A data driver supplies the data voltage and the constant current generation voltage to each of the plurality of pixels.

24. The display device according to claim 23, wherein: The pulse width modulator comprises: A first write transistor comprising: A gate electrode, receiving a scanning signal among the plurality of scanning signals; a first electrode connected to a data line transmitting the data voltage; and a second electrode connected to the second node; A first compensation transistor comprising: A gate electrode, receiving the scanning signal; a first electrode connected to the third node; and a second electrode connected to the first node; A first emission control transistor comprising: A gate electrode, receiving an emission control signal; a first electrode receiving a first high power voltage; and a second electrode connected to the second node; The second emission control transistor comprises: a gate electrode, receiving the emission control signal; a first electrode connected to the third node; and a second electrode connected to the fourth node; A first initialization transistor includes: A gate electrode, receiving a first initialization gate signal; A first electrode receiving a first initialization voltage; and a second electrode connected to the first node; and A first capacitor comprising: A first electrode receives a frequency sweep signal; and A second electrode is connected to the first node.

25. The display device according to claim 24, wherein: The constant current generator comprises: A second write transistor comprising: A gate electrode receives a constant current to generate a scanning signal; a first electrode connected to the data line transmitting the constant current generating voltage; and a second electrode connected to the fifth node; The second compensation transistor comprises: A gate electrode, receiving the constant current to generate a scanning signal; a first electrode connected to the sixth node; and a second electrode connected to the fourth node; A third emission control transistor comprises: a gate electrode, receiving the emission control signal; a first electrode receiving a second high power voltage; and a second electrode connected to the fifth node; A fourth emission control transistor comprising: a gate electrode, receiving the emission control signal; a first electrode connected to the sixth node; and a second electrode connected to the first electrode of the light emitting element; The second initialization transistor comprises: A gate electrode receiving a second initialization gate signal; A first electrode, receiving the first initialization voltage; and a second electrode connected to the fourth node; Bypass transistor, including: A gate electrode, receiving a bypass gate signal; a first electrode connected to a second initialization voltage line transmitting a second initialization voltage; and a second electrode connected to the first electrode of the light emitting element; and A second capacitor comprising: a first electrode receiving the second high power voltage; and The second electrode is connected to the fourth node.

26. The display device according to claim 25, wherein: The second initialization voltage line is separated from the low power line.

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