Time sequence compression and decompression method for IO parallel port output control time sequence
By performing segmented compression and decompression output methods on the IO parallel output timing, the problem of excessive memory occupancy in the prior art is solved, and more efficient memory usage and timing output are achieved.
Patent Information
- Application Number
- CN202311349123.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-18
- Publication Date
- 2025-04-18
Smart Images
Figure CN119854418A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of peripheral control, and in particular relates to a timing compression and decompression method for an IO parallel port output control timing. Background Art
[0002] In the prior art, many specific peripherals require specific timing to drive their operation. For example, if the peripheral is a scanning device controller, the working principle of the existing CIS scanner is as follows:
[0003] 1. The photosensitive element on the CIS image sensor device outputs analog power according to the light intensity;
[0004] 2. ADC converts the input analog signal into a digital signal; analog shifting is performed until all the linearly arranged signals on the image sensor are collected, and this direction is opposite to the main scan;
[0005] 3. The scanning control system controls the image sensor device to move to the next scanning line position in the vertical direction (this direction is the sub-scanning direction), and repeats operations 1-2;
[0006] 4. Repeat this process until all the contents on the scanned medium are input;
[0007] 5. The above is completed by the scanning control module, and some data storage, image processing, transmission and other tasks are completed by other modules of the CPU. Figure 1 shown.
[0008] Currently, most common scanner controllers are dedicated printer control chips, such as Qbit's QB63xx. Such dedicated chips have a dedicated timing generation interface to generate timing for the control timing of CIS and AFE. Or the scanning device control is realized in the form of FPGA / MCU+host computer. The control interface connection diagram of CIS and AFE is as follows: Figure 2 As shown, D0-D5 are the serial timing IO ports of ClockGen, and each IO port independently outputs the required timing waveform.
[0009] Methods for outputting the specific timing include: using a dedicated control chip for the specific peripheral environment, or using a general IO port to simulate the required timing through programming.
[0010] Generally, software simulation timing generates the required timing into memory, and IO parallel port output timing reads the preset content from the memory to the IO port address. Data 0 and 1 correspond to the low level and high level of the parallel port output IO port respectively.
[0011] There are many ways to generate in-memory timing, including:
[0012] The most direct way is to write the program directly according to the timing content and generate the required timing through loops. However, this method is not practical for more complex timing transformations, as a slight timing change may cause overall changes in the code.
[0013] For software simulation timing, the timing is usually stored in memory and then output through the IO port. However, there are two problems:
[0014] 1. This will continue to occupy memory space.
[0015] 2. The amount of memory space occupied is proportional to the number of cycles of the overall timing. Figure 3 Describes the combined timing of two IO pins. The overall timing depends on the number of clock cycles to determine the memory usage. Figure 3 As shown in the figure, there are a lot of repeated timings in the entire timing. If this segment of timing is directly saved in the memory and then read from the memory output by the IO pin, it will not only waste memory space but also waste memory bandwidth.
[0016] In addition, commonly used technical terms include:
[0017] Parallel port: A parallel interface that can have N IO ports; n being 8 means there are 8 IO pin ports that can output 8 timing signals in parallel.
[0018] CIS: (Contact image sensor) Contact image sensor. Converts light signals into electrical signals.
[0019] ADC: Analog-to-digital converter, used to convert analog signals into digital signals. Summary of the invention
[0020] In order to solve the above problems, the purpose of this application is to propose a compression method for simulation timing to solve the problems in the prior art. This method is to segment the timing stored in the memory to compress the memory, and then the MCU can output each segment. For scenarios where the MCU has very little available memory, the compression method can effectively solve the problem of too large timing data memory.
[0021] Specifically, the present invention provides a timing compression and decompression method for an IO parallel port output control timing, the method comprising the following steps:
[0022] S1, cycle description:
[0023] A cycle description type cycle_t is: u_intN1[X]; where N represents the number of IO parallel ports, indicating that in a cycle, each number has N valid bits. In general, the minimum number of bits defined for integers in a system is 8 bits, so N1 in u_intN1 is set to a multiple of 8, and the N valid bits are taken;
[0024] S2, segment description:
[0025] The entire timing is described in segments using cycle_t as a unit. Consecutive identical cycles are divided into the same segment, and a cycle_t is used to record its content and the number of consecutive cycles. A segment is used to describe the same cycle, which includes the content of the same cycle, one_cycle, and the number of times the memory is repeated, repeat; and the total segments. The total segments is a fixed array. The value can be defined according to the actual waveform and declared before step S2.1. Assume that the array size is defined as 88, i.e., segments
[88] . The specific process includes:
[0026] S2.1, let init_cycle be the content of the first cycle in memory;
[0027] next_cycle=init_cycle; assign value to next_cycle, next_cycle is the next cycle content in memory;
[0028] S2.2, loop all the data in the memory, expressed as, for i:0 to totalSize, where totalSize is the total number of all the data in the memory. If the loop is performed, proceed to step S2.3; if the loop ends, proceed to step S2.8;
[0029] S2.3, determine whether init_cycle == next_cycle? If yes, proceed to step S2.4; otherwise, proceed to step S2.5;
[0030] S2.4, repeats+=1, next_cycle is the next cycle content in the memory;
[0031] S2.5, create a new segment, in which repeat = repeats, one_cycle = init_cycle; S2.6, add the new segment to the total segments;
[0032] S2.7, repeat is cleared to 0, init_cycle is the new cycle content, and a new segment count is started, repeats = 0, init_cycle = next_cycle; return to step S2.2;
[0033] S2.8, all timing analysis is completed, and segments are passed to MCU, where segments are the total segments; the generated segments are the compression results, which are compressed and output to MCU; S3, start MCU for decompression and output;
[0034] S3.1, determine whether the MCU loops all segments? Expressed as, for i:0 to allSegs, where allSegs is the total number of segments; if not, end; if looping, proceed to step S3.2;
[0035] S3.2, determine whether to repeat in a loop? It is expressed as, for j:0 to repeat[i], where repeat[i] represents the number of times one_cycle is repeated in the i-th segment; if not, return to step S3.1, if yes, proceed to step S3.3;
[0036] S3.3, output one_cycle, and return to step S3.2.
[0037] In step S1, assuming that N=8 and X=5, then N1 is also 8, and a cycle description type cycle_t can be defined as: cycle_t:u_int8[5].
[0038] The step S2 further comprises:
[0039] Describe a structure struct, expressed as: struct segment;
[0040] The contents of the structure include:
[0041] The description information of a cycle is expressed as: cycle_t one_cycle;
[0042] The number of repetitions of the cycle, expressed as: uint16 repeat.
[0043] Steps S2.1 to S2.7 are steps for compressing segments, and step S2.8 is a step for synchronizing results after compression is completed.
[0044] In the method, assume that a cycle consists of a 0 and a 1, that is, X=2, and there are three valid IO pin ports output in parallel, that is, N=3, N1=8; M is the value of repeat in each segment, and the range of repeat can be [1, 0xffffffff];
[0045] The segment1 sequence repeats 3 cycles, then segment1.repeat=3,u_int8 one_cycle[2]:{0b011,0b010};
[0046] The segment2 timing repeats 2 cycles, then segment2.repeat=2,u_int8 one_cycle[2]:{0b111,0b110};
[0047] The segment3 timing repeats 14 cycles, then segment3.repeat = M,u_int8 one_cycle[2]:{0b101,0b100};
[0048] The segment4 timing repeats 1 cycle, then segment4.repeat=2,u_int8 one_cycle[2]:{0b111,0b110};
[0049] The segment5 sequence repeats 2 cycles, then segment5.repeat=3,u_int8 one_cycle[2]:{0b011,0b010};
[0050] For the above five time series, the required space size is fixed, that is, the space occupied by the five segment structures is 5*sizeof(segment), which does not change with the number of repeats M in each segment.
[0051] The step S3 includes S3.1 to S3.3, where the MCU decompresses segments and outputs the decompression result one_cycle in real time.
[0052] The method is to generate the timing by the main CPU, and optimize the memory of the timing by simulating the control of the timing output by the MCU, and the memory size occupied by the optimized timing meets the hardware limitation of the small memory of the MCU.
[0053] Therefore, the advantages of the present application are: the present method uses the functional requirements of the IO parallel port output timing to perform segmented abstract description of the generated timing, effectively compressing the memory space. The present invention can be applied to the application of emulating printer scanning timing and produce good results. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention.
[0055] Figure 1It is a schematic diagram of the composition of an existing CIS scanner.
[0056] Figure 2 It is a schematic diagram of the control interface connection between the existing CIS and AFE.
[0057] Figure 3 It is a schematic diagram describing the combination timing of two IO pin ports in the prior art.
[0058] Figure 4 It is a schematic diagram of a specific embodiment of the present application.
[0059] Figure 5 It is a schematic diagram of a clock cycle described in an embodiment of the present application.
[0060] Figure 6 It is a flow chart of step S2 of the method of the present application.
[0061] Figure 7 It is a schematic diagram of the segmented description of the 5-segment timing in the embodiment of the present application. DETAILED DESCRIPTION
[0062] In order to more clearly understand the technical content and advantages of the present invention, the present invention is now further described in detail in conjunction with the accompanying drawings.
[0063] This application proposes a timing compression and decompression method for IO parallel port output control timing, which is a memory optimization of the analog control timing generated by the main CPU and output by the MCU, and optimizes the memory size occupied by the generated timing to meet the hardware limitation of the small memory of the MCU. The main contents include: a segmented compression method for IO parallel port simulation timing, and the specific method is to describe the timing in segments. Figure 4 Take the parallel port timing description as an example. The method is as follows:
[0064] S1, cycle description:
[0065] A cycle description type cycle_t is: u_intN1[X]; where N represents the number of IO parallel ports, indicating that in a cycle, each number has N valid bits. In general, the minimum number of bits defined for integers in a system is 8 bits, so N1 in u_intN1 is set to a multiple of 8, and the N valid bits are taken;
[0066] A cycle:
[0067] Cycle: A high level and a low level form a clock cycle. Assume that the number of bits in a cycle is X, that is, a cycle is represented by X 0s or 1s. Figure 5 As shown, X=5, there are 5 numbers {1,1,0,0,0} that describe a clock cycle.
[0068] The number of IO parallel ports is N, which means that each number has N valid bits in a cycle.
[0069] Note that in general systems, the minimum number of bits defined for integers is 8 bits, so N1 in u_intN1 is set to a multiple of 8, and the N valid bits are taken.
[0070] cycle_t is defined as: u_intN1[X]
[0071] Assume N = 8, X = 5, then N1 is also 8, and a cycle description type cycle_t can be defined as:
[0072] cycle_t:u_int8[5];
[0073] S2, segment description:
[0074] The entire timing is described in segments using cycle_t as the unit. Continuous identical cycles are divided into the same segment, and a cycle_t is used to record its content and the number of consecutive cycles. A segment is used to describe it, which includes the content of the same cycle, one_cycle, the number of times the memory is repeated, and the total segments. The total segments is a fixed array. This value can be defined according to the actual waveform and declared before step S2.1. Assume that the array size is defined as 88, that is, segments
[88] ; the specific process is as shown in the figure below:
[0075] Suppose the structure is: struct segment
[0076] Description information of a cycle: cycle_t one_cycle;
[0077] The number of repetitions of the cycle: uint16 repeat;
[0078] like Figure 6 As shown:
[0079] S2.0, Start,
[0080] S2.1, let init_cycle be the content of the first cycle in memory;
[0081] next_cycle=init_cycle; assign value to next_cycle, next_cycle is the next cycle content in memory;
[0082] S2.2, loop all the data in the memory, expressed as for i:0 to totalSize, where totalSize is the total number of all the data in the memory; if the loop is performed, proceed to step S2.3; if the loop ends, proceed to step S2.8;
[0083] S2.3, determine whether init_cycle == next_cycle? If yes, proceed to step S2.4; otherwise, proceed to step S2.5;
[0084] S2.4, repeats+=1, next_cycle is the next cycle content in the memory;
[0085] S2.5, create a new segment, in which repeat = repeats, one_cycle = init_cycle; S2.6, add the new segment to the total segments;
[0086] S2.7, repeat is cleared to 0, init_cycle is the new cycle content, and a new segment count is started, repeats = 0, init_cycle = next_cycle; return to step S2.2;
[0087] S2.8, after all timing analysis is completed, segments are passed to xburst0; segments here are total segments; the generated segments are compression results, which are compressed and output to MCU; steps S2.1 to S2.7 are steps for compressing segments, and step S2.8 is a step for synchronizing the results after compression is completed;
[0088] S3, start xburst0; MCU, i.e. xburst0, decompresses segments and outputs the decompression result one_cycle in real time;
[0089] S3.1, determine whether xburst0 loops through all segments? Expressed as for i:0to allSegs, where allSegs is the total number of segments; if not, end; if looping, proceed to step S3.2; S3.2, determine whether to loop repeat? Expressed as for j:0to repeat[i], where repeat[i] indicates the number of times one_cycle is repeated in the i-th segment; if not, return to step S3.1, if yes, proceed to step S3.3;
[0090] S3.3, output one_cycle, and return to step S3.2.
[0091] In addition, Figure 7 For example:
[0092] In the figure, a cycle is composed of a 0 and a 1, that is, X=2, and there are 3 valid IO pin ports output in parallel, that is, N=3, N1=8; M is the value of repeat in each segment; the repeat range can be [1,0xffffffff];
[0093] The segment1 sequence repeats 3 cycles, then segment1.repeat=3,u_int8 one_cycle[2]:{0b011,0b010};
[0094] The segment2 timing repeats 2 cycles, then segment2.repeat=2,u_int8 one_cycle[2]:{0b111,0b110};
[0095] The segment3 timing repeats 14 cycles, then segment3.repeat = M,u_int8 one_cycle[2]:{0b101,0b100};
[0096] The segment4 timing repeats 1 cycle, then segment4.repeat=2,u_int8 one_cycle[2]:{0b111,0b110};
[0097] The segment5 sequence repeats 2 cycles, then segment5.repeat=3,u_int8 one_cycle[2]:{0b011,0b010};
[0098] The above time series is divided into 5 segments and described separately. The more repeated time series are, the higher the compression ratio is. If the method of directly storing the time series in memory is adopted, (10+M)*16 bits of space are required, and the space occupied is proportional to M.
[0099] However, when using the timing compression method proposed in this application, for the above 5-segment timing, a fixed space size is required, that is, the space occupied by the 5 segment structures is 5*sizeof(segment), which does not change with the number of repeats M in each segment.
[0100] For situations with many repeated sequences, this description method can save space very effectively.
[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A timing compression and decompression method for IO parallel port output control timing, characterized in that: The method The following steps are involved: S1, cycle description: A cycle description type cycle_t is: u_intN1[X]; where N represents the number of IO parallel ports, indicating that in a cycle, each number has N valid bits. In general, the minimum number of bits defined for integers in a system is 8 bits, so N1 in u_intN1 is set to a multiple of 8, and the N valid bits are taken; S2, segment description: The entire timing is described in segments using cycle_t as a unit. Consecutive identical cycles are divided into the same segment, and a cycle_t is used to record its content and the number of consecutive cycles. A segment is used to describe the same cycle, which includes the content of the same cycle, one_cycle, and the number of times the memory is repeated, repeat; and the total segments. The total segments is a fixed array. The value can be defined according to the actual waveform and declared before step S2.
1. Assume that the array size is defined as 88, i.e., segments[88]. The specific process includes: S2.1, let init_cycle be the content of the first cycle in memory; next_cycle=init_cycle; assign value to next_cycle, next_cycle is the next cycle content in memory; S2.2, loop all the data in the memory, expressed as, for i:0 to totalSize, where totalSize is the total number of all the data in the memory. If the loop is performed, proceed to step S2.3; if the loop ends, proceed to step S2.8; S2.3, determine whether init_cycle == next_cycle? If yes, proceed to step S2.4; otherwise, proceed to step S2.5; S2.4, repeats+=1, next_cycle is the next cycle content in the memory; S2.5, create a new segment, in which repeat = repeats, one_cycle = init_cycle; S2.6, the new segment is added to the total segments; S2.7, repeat is cleared to 0, init_cycle is the new cycle content, and a new segment count is started, repeats = 0, init_cycle = next_cycle; return to step S2.2; S2.8, all timing analysis is completed, and segments are passed to MCU, where segments are the total segments; the generated segments are the compression results, which are compressed and output to MCU; S3, start MCU for decompression and output; S3.1, determine whether the MCU loops all segments? Expressed as, for i:0 to allSegs, where allSegs is the total number of segments; if not, end; if looping, proceed to step S3.2; S3.2, determine whether to repeat in a loop? It is expressed as, for j:0 to repeat[i], where repeat[i] represents the number of times one_cycle is repeated in the i-th segment; if not, return to step S3.1, if yes, proceed to step S3.3; S3.3, output one_cycle, and return to step S3.
2.
2. The timing compression and decompression method of an IO parallel port output control timing according to claim 1, characterized in that: In step S1, assuming that N=8 and X=5, then N1 is also 8, and a cycle description type cycle_t can be defined as: cycle_t:u_int8[5].
3. The timing compression and decompression method of an IO parallel port output control timing according to claim 1, characterized in that: The step S2 further comprises: Describe a structure struct, expressed as: struct segment; The contents of the structure include: The description information of a cycle is expressed as: cycle_t one_cycle; The number of repetitions of the cycle, expressed as: uint16 repeat.
4. The timing compression and decompression method of an IO parallel port output control timing according to claim 1, characterized in that: Steps S2.1 to S2.7 are steps for compressing segments, and step S2.8 is a step for synchronizing results after compression is completed.
5. The timing compression and decompression method of an IO parallel port output control timing according to claim 1, characterized in that: In the method, assume that a cycle consists of a 0 and a 1, that is, X=2, and there are three valid IO pin ports output in parallel, that is, N=3, N1=8; M is the value of repeat in each segment, and the range of repeat can be [1, 0xffffffff]; The segment1 sequence repeats 3 cycles, then segment1.repeat=3,u_int8 one_cycle[2]:{0b011,0b010}; The segment2 timing repeats 2 cycles, then segment2.repeat=2,u_int8 one_cycle[2]:{0b111,0b110}; The segment3 timing repeats 14 cycles, then segment3.repeat = M,u_int8 one_cycle[2]:{0b101,0b100}; The segment4 timing repeats 1 cycle, then segment4.repeat=2,u_int8 one_cycle[2]:{0b111,0b110}; The segment5 sequence repeats 2 cycles, then segment5.repeat=3,u_int8 one_cycle[2]:{0b011,0b010}; For the above five time series, the required space size is fixed, that is, the space occupied by the five segment structures is 5*sizeof(segment), which does not change with the number of repeats M in each segment.
6. The timing compression and decompression method of an IO parallel port output control timing according to claim 1, characterized in that: The step S3 includes S3.1 to S3.3, where the MCU decompresses segments and outputs the decompression result one_cycle in real time.
7. The timing compression and decompression method of an IO parallel port output control timing according to claim 1, characterized in that: The method is that the main CPU generates the timing, and the MCU outputs the timing to simulate the control timing memory optimization, and the memory size occupied by the optimized timing meets the hardware limitation of the small memory of the MCU.