Operational methods to mitigate hysteresis problems in high-K metal-insulator-metal capacitors

Abstract

This document discloses an operational method for mitigating hysteresis problems in high-k metal-insulator-metal (MIM) capacitors. In one embodiment, a method for reducing image hysteresis associated with a pixel comprised of a plurality of pixels is described. The pixel includes a photodiode, a first floating diffuser coupled to the photodiode via a transfer transistor, a second floating diffuser coupled to the first floating diffuser via dual floating diffuser transistors, and a lateral overflow integrating capacitor coupled between the second floating diffuser and a bias voltage source. The lateral overflow integrating capacitor is further coupled to a pixel reference voltage source via a reset transistor. Operation of the pixel includes an idle period and an integration period following the idle period. The method further includes configuring the lateral overflow integrating capacitor to be zero-biased or positively biased during the idle period.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and specifically, but not exclusively, to pixel units having reduced time lag after the pixel unit is exposed to light. Background Technology

[0002] CMOS image sensors (CIS) have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, and in medical, automotive, and other applications. An image sensor operates in response to image light from an external scene that is incident on the sensor. An image sensor comprises an array of pixels with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate a corresponding charge in response. The charge of an individual pixel can be measured as the output voltage of each photosensitive element. Generally, the output voltage varies as a function of the intensity and duration of the incident light. The output voltage of the individual photosensitive elements is used to generate a digital image (i.e., image data) representing the external scene.

[0003] Image sensor technology continues to evolve rapidly. The demand for higher resolution and lower power consumption has spurred further miniaturization and integration of these devices with high dynamic range and low light sensitivity. For example, some automotive image sensors use high-k (high dielectric constant) metal-to-metal (MIM) capacitor technology to improve the capacitance of high lateral overflow integral capacitors (LOFICs). This improves the dynamic range of the image sensor. However, the use of high-k capacitors can lead to image hysteresis (for example, after a bright image has been captured by the image sensor), which negatively impacts the image sensor's performance. Therefore, there is a need for systems and methods to reduce image hysteresis in image sensors employing high-k capacitors as LOFICs to achieve high dynamic performance. Summary of the Invention

[0004] One aspect of this disclosure relates to a method for reducing image hysteresis associated with a pixel included in a plurality of pixels, the pixel including a photodiode, a first floating diffuser coupled to the photodiode via a transfer transistor, a second floating diffuser coupled to the first floating diffuser via a dual floating diffuser transistor, and a lateral overflow integrating capacitor coupled between the second floating diffuser and a bias voltage source, the lateral overflow integrating capacitor being further coupled to a pixel reference voltage source via a reset transistor, wherein operation of the pixel includes an idle period and an integration period following the idle period, the method comprising: configuring the lateral overflow integrating capacitor to be zero-biased or forward-biased during the idle period; and configuring the lateral overflow integrating capacitor to be reverse-biased at least at the beginning of the integration period when the photodiode is exposed to light.

[0005] Another aspect of this disclosure relates to an image sensor comprising: a plurality of pixels arranged in a plurality of rows and columns of a pixel array, each pixel comprising: a photodiode; a first floating diffuser connected to the photodiode; a transfer transistor connecting the photodiode to the first floating diffuser; a second floating diffuser; a dual floating diffuser coupled between the first floating diffuser and the second floating diffuser; and a lateral overflow integrating capacitor coupled between the second floating diffuser and a bias voltage source, wherein the photodiode is configured to generate charge during an integration period, and wherein an idle period precedes the integration period, wherein operation of the pixel comprises: configuring the lateral overflow integrating capacitor to be zero-biased or forward-biased during the idle period; and configuring the lateral overflow integrating capacitor to be reverse-biased at least at the beginning of the integration period when the photodiode is exposed to light. Attached Figure Description

[0006] Non-limiting and non-exhaustive embodiments of this disclosure are described with reference to the following figures, wherein similar reference numerals refer to similar parts unless otherwise specified.

[0007] Figure 1 The illustration depicts an imaging system according to an embodiment of the present disclosure.

[0008] Figure 2 This is a diagram of dielectric relaxation according to an embodiment of the present disclosure.

[0009] Figure 3 This is an electrical schematic diagram of pixels according to an embodiment of the present disclosure.

[0010] Figure 4 This is a timing diagram illustrating the various stages of image sensor operation according to embodiments of the present disclosure.

[0011] Figure 5A and 5B This is a timing diagram of the voltage bias of a high lateral overflow integral capacitor (LOFIC) according to an embodiment of the present disclosure.

[0012] Figure 6A This is an electrical schematic diagram of pixels according to an embodiment of the present disclosure.

[0013] Figure 6B This is a timing diagram illustrating the various stages of image sensor operation according to embodiments of the present disclosure.

[0014] Figures 7A to 7C The illustration shows the sample voltage of a high-k (high dielectric constant) metal-to-metal (MIM) capacitor according to an embodiment of the present disclosure.

[0015] Figure 8A and 8B This is a timing diagram of LOFIC voltage bias according to an embodiment of the present disclosure.

[0016] Figure 9 This is a timing diagram illustrating the various stages of image sensor operation according to embodiments of the present disclosure.

[0017] Figure 10A and 10B This is a timing diagram of LOFIC voltage bias according to an embodiment of the present disclosure.

[0018] Several views throughout the figures correspond to reference characters indicating the respective components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to aid in understanding the various embodiments of the invention, the dimensions of some elements in the figures may be enlarged relative to other elements. Furthermore, common and well-known elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate a less obstructed view of these various embodiments of the invention. Detailed Implementation

[0019] Apparatus and methods for addressing the hysteresis effect of image sensors are disclosed. Numerous specific details are set forth in the following description to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the stated specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring particular aspects.

[0020] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one embodiment of the invention. Therefore, the appearance of the phrase "in an example" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same example. Furthermore, the particular feature, structure, or characteristic may be combined in any suitable manner in one or more examples.

[0021] Spatially relative terms (e.g., “below,” “under,” “lower,” “below,” “above,” “upper,” etc.) may be used herein for ease of description to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as “below,” “below,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptive terms used herein will be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers.

[0022] Several technical terms are used throughout this specification. These terms will be given their general meaning in the field of their respective domains, unless otherwise specifically defined herein or the context in which they are used will clearly imply otherwise. It should be noted that component names and symbols are used interchangeably in this document (e.g., Si and silicon); however, they have the same meaning.

[0023] In short, image sensors can use high-k metal-insulator-metal (MIM) capacitor technology to form lateral overflow integrating capacitors (LOFICs) with higher capacitance, thereby increasing the dynamic range of the image sensor. For example, such image sensors are used in the automotive industry, where high dynamic range is required to span usage scenarios ranging from driving at night with very little external light to driving during very bright daytime. However, high-k MIM capacitors can suffer from high image hysteresis, meaning that after a pixel is exposed to light, the high-k MIM capacitor requires a relatively long time to discharge to its initial value and thus prepare for the next exposure to light. For example, under bright lighting conditions during the pixel integration cycle, image hysteresis caused by high-k MIM capacitors may result from the trapping of charge within a high-dielectric-constant material (or high-k material) contained in the insulating material of the high-k MIM capacitor, which then spends a relatively long time (e.g., a long idle time) discharging during material relaxation before starting the acquisition of the next frame during the next integration cycle. In some embodiments, the discharge time of a high-k MIM can be approximately 400 ms, which is significantly longer than the typical frame time of 33 ms for the image sensor itself, thus causing image lag artifacts. Furthermore, in many practical applications, the lag time should be further reduced, for example, to below 20 ms. Therefore, as the capacitance of the LOFIC in the pixel circuitry increases, image lag increases, which can lead to slower frame rates.

[0024] Generally, the hysteresis time of high-k MIM LOFIC capacitors results in a long idle time required for discharge. In some embodiments of the invention, during the idle period, the high-k MIM LOFIC capacitor is biased to a voltage bias with the opposite sign to the voltage bias at the end of the integration time. This reversal of the voltage bias reduces the accumulated charge, which accelerates the discharge process of the high-k MIM LOFIC capacitor, thus achieving a shorter idle time and, conversely, a higher frame rate for the image sensor. However, this method can lead to (for example) deteriorating dark image non-uniformity (DINU), which interferes with machine vision applications.

[0025] In some embodiments of the invention, the high-k MIM LOFIC capacitor mitigates image lag by progressing through negative and positive biases during the integration period. Furthermore, since the voltage bias of the high-k MIM LOFIC capacitor can begin with a negative bias and then transition to a positive bias as more charge is generated by the photodiode and overflows into the high-k MIM LOFIC capacitor during the integration period, the reduced final voltage bias of the high-k MIM LOFIC reduces image lag. Therefore, the image sensor can operate at a higher frame rate because only a shorter idle time is needed to discharge the high-k MIM LOFIC capacitor.

[0026] Figure 1 The illustration depicts an exemplary imaging system 100 according to an embodiment of the present disclosure. The imaging system 100 includes a pixel array 102, a control circuitry system 104, a readout circuitry system 106, and functional logic 110. In one example, the pixel array 102 is a two-dimensional (2D) array of photodiode or image sensor pixels 112 (e.g., pixels P1, P2…, Pn). As illustrated, the photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx). In operation, the photodiodes or image sensor pixels 112 acquire image data of an external scene in response to detected incident light, which can then be used to reproduce 2D images of people, places, objects, etc. However, in other embodiments, the photodiodes or image sensor pixels 112 may be arranged in a configuration other than rows and columns.

[0027] As will be discussed, in various embodiments, one or more photodiodes or image sensor pixels 112 may also be configured to provide HDR image signals. In this case, image charge generated by one or more photodiodes or image sensor pixels 112 under bright illumination conditions may also be transferred to a coupled LOFIC and / or additional floating diffuser in each pixel circuit associated with one or more photodiodes or image sensor pixels 112 to store image charge. For example, each of the pixel circuits associated with one or more photodiodes or image sensor pixels 112 may include a LOFIC (e.g., a high-k MIM capacitor) configured to store overflow image charge received from one or more photodiodes. In various embodiments, the readout circuitry 106 may be configured to read out image signals with different conversion gains via column bit lines 118.

[0028] In one embodiment, after each photodiode or image sensor pixel 112 in the pixel array 102 acquires its image charge, image data is read out by the readout circuitry system 106 via bit line 118 and then transmitted to functional logic 110. In various embodiments, the readout circuitry system 106 may include a signal amplifier, an analog-to-digital (ADC) conversion circuitry system, and a data transmission circuitry system. Functional logic 110 may store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others). In some embodiments, control circuitry system 104 and functional logic 110 may be combined into a single functional block to control image capture by the photodiode or image sensor pixel 112 and the readout of image data from the readout circuitry system 106. For example, functional logic 110 may be a digital processor. In one embodiment, the readout circuitry 106 can read one line of image data at a time along the readout column line (bit line 118) or can use various other techniques to read the image data, such as serial readout or simultaneous full parallel readout of all pixels (not illustrated).

[0029] In one example, control circuitry 104 is coupled to pixel array 102 to control the operation of the plurality of photodiode or image sensor pixels 112 in pixel array 102. For example, control circuitry 104 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for simultaneously activating all photodiode or image sensor pixels 112 within pixel array 102 to simultaneously capture their respective image data during a single data acquisition window. In another embodiment, the shutter signal is a rolling shutter signal, such that pixels in each row, column, or group are sequentially activated during consecutive acquisition windows. In another example, image acquisition is synchronized with an illumination effect such as a flash. In one or more embodiments, control circuitry 104 may include circuitry for modulating or adjusting the voltage level of the bias voltage provided to the LOFIC associated with the plurality of photodiode or image sensor pixels 112.

[0030] In one embodiment, the readout circuitry 106 includes an analog-to-digital converter (ADC) that converts analog image data received from the pixel array 102 into a digital representation. The digital representation of the image data can be provided to functional logic 110. In some embodiments, the data transmission circuitry 108 can receive the digital representation of the image data from the ADC in parallel and can provide the image data to functional logic 110 serially.

[0031] In one example, the imaging system 100 is implemented on a single semiconductor wafer. In another example, the imaging system 100 is located on stacked semiconductor wafers. For example, the pixel array 102 may be implemented on a pixel wafer, while the readout circuitry 106, control circuitry 104, and functional logic 110 may be implemented on an application-specific integrated circuit (ASIC) wafer, wherein the pixel wafer and the ASIC wafer are interconnected by bonding (hybrid bonding, oxide bonding, etc.) or one or more through-substrate vias (TSVs). In another example, the pixel array 102 and control circuitry 104 are implemented on a pixel wafer, while the readout circuitry 106 and functional logic 110 are implemented on an ASIC wafer, wherein the pixel wafer and the ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, etc.) or one or more TSVs.

[0032] In various embodiments, the imaging system 100 may be included in the imaging apparatus of a digital camera, mobile phone, laptop computer, endoscope, security camera, head-mounted display device, or imaging apparatus for automobiles, etc. Additionally, the imaging system 100 may be coupled to other hardware components, such as processors (general purpose or other), memory elements, outputs (USB ports, wireless transmitters, HDMI ports, etc.), illumination / flash, electrical inputs (keyboards, touch displays, tracking pads, mice, microphones, etc.), and / or displays. These other hardware components may deliver instructions to the imaging system 100, retrieve image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0033] Figure 2 This is a diagram of dielectric relaxation according to embodiments of the present disclosure. The horizontal axis indicates the relaxation time in milliseconds (ms) for a high-k MIM LOFIC capacitor, and the vertical axis indicates the relaxation current in amperes. Generally, for the same charge accumulated or stored in a high-k MIM LOFIC, a higher relaxation current requires a shorter relaxation time. For example, when the relaxation current decreases from about 7E-11A to about 3E-12A, the relaxation time of the illustrated high-k MIM LOFIC capacitor increases significantly above 33 ms, making the idle period required by the image sensor to avoid image hysteresis impractically long, i.e., reducing the frame rate of the image sensor to an unacceptably low value. As discussed above, for many applications, the target relaxation time can be below 33 ms or even below 20 ms. Some embodiments of the inventive techniques for reducing hysteresis are discussed below.

[0034] Figure 3This is an electrical schematic diagram of pixel 210 according to an embodiment of the present disclosure. Pixel 210 may be coupled to bit line 218, for example, to provide a readout column of image data to a readout circuitry system (e.g., readout circuitry system 106). In operation, pixel 210 may receive control signals from a control circuitry system such as control circuitry system 104 to control the operation of a plurality of transistors contained in pixel 210. The control circuitry system may control the operation of the plurality of transistors in a desired sequence using a relative timing that ensures the orderly readout of image data. Voltages supplied to different elements of pixel 210 are shown on the left-hand side of the circuit; however, in different embodiments, voltages marked differently may have the same or different values.

[0035] The illustrated embodiment of pixel 210 includes a photodiode (PD) 211, a first floating diffuser (FD1) 213, a transfer transistor 212, a dual floating diffuser 216, a second floating diffuser (FD2) 217 ​​connected to a lateral overflow integrating capacitor (LOFIC) 215, a lateral overflow gate transistor 234, a reset (RST) transistor 214, a row select transistor 221, and a source follower (SF) transistor 220. The transfer transistor 212 (which may also be referred to as transfer gate 212) is coupled between the photodiode 211 and the first floating diffuser FD1 213, thereby controlling the charge transfer operation between the photodiode 211 and the first floating diffuser FD1 213. The transfer transistor 212 operates based on a transfer control signal TX applied to its gate terminal. The transfer transistor 212 is configured to be switched in response to the received transfer control signal TX. In the illustrated embodiment, the first floating diffuser FD1 213... Figure 3 In the schematic diagram, a capacitor is depicted coupled to a transfer transistor 212, and a dual floating diffusion transistor 216 selectively couples a first floating diffusion section FD1 213 to a capacitor 219. In some embodiments, the capacitor 219 is coupled to receive an optional floating diffusion section capacitance control signal FDC and is coupled to the first floating diffusion section FD1 213 via the dual floating diffusion transistor 216. In one example, the floating diffusion section capacitance control signal FDC can be used to provide a boost control signal to the capacitor 219 coupled to the first floating diffusion section FD1 213. In embodiments, the combination of the first floating diffusion section FD1 213 and the second floating diffusion section FD2 (or floating node FD2) can also be collectively referred to as the floating diffusion section associated with pixel 210. It should be understood that the capacitor 219 may be formed of a junction capacitor, a metal-oxide-metal capacitor, or a metal-insulator-metal capacitor.

[0036] While the dual floating diffusion transistor 216 is enabled (e.g., turned on), the coupling between the second floating diffusion section FD2 217 and the first floating diffusion section FD1 213 provides additional capacitance to store the charge generated by the photodiode 211 and modulate the conversion gain of the pixel 210. For example, when the transfer transistor 212 is enabled to transfer the image charge accumulated by the photodiode 211 to the first floating diffusion section FD1 213, the dual floating diffusion transistor 216 can be enabled to couple LOFIC 215 to the first floating diffusion section FD1 213, thereby providing additional capacitance to increase the overall charge capacity of the first floating diffusion section FD1 213. In some embodiments, the bias voltage VCAP can be provided by a bias voltage source and configured to provide different voltage levels depending on the operation of the pixel 210 (e.g., whether the pixel 210 has been selected to be active during an integration period or a readout period).

[0037] RST transistor 214 may be coupled to receive a pixel reference voltage (e.g., voltage AVDD) and may be coupled to receive a reset control signal RSTG at its gate terminal. The reset transistor RST 214 is configured to be switched in response to the reset control signal RSTG and is configured to reset pixel 210 during, for example, an idle period, a precharge period, and a readout period between image signal readout and reset signal readout.

[0038] LOFIC 215 may be coupled between a bias voltage VCAP and a second floating diffusion portion FD2 217. In the context of this application, the bias voltage VCAP may be implemented by a variable voltage source, a combination of multiple voltage sources (where individual voltage sources may be immutable), or other methods known to those skilled in the art. In embodiments, a pixel reference voltage (e.g., voltage AVDD) is supplied by a pixel reference voltage source, which may be configured to provide a fixed voltage. In some embodiments, LOFIC 215 may be fabricated as a metal-to-metal (MIM) capacitor having an insulating material with a high dielectric constant (e.g., a high-k dielectric) sandwiched between a first metal electrode or plate and a second metal electrode or plate. In some embodiments, LOFIC 215 may be fabricated as a trench capacitor or a stacked MIM capacitor within a metal layer disposed on a substrate or wafer. For ease of reference, the first metal electrode or plate of LOFIC 215 may be designated as the A-side or CTM (top metal of capacitor) side, and the second metal electrode or plate of LOFIC 215 may be designated as the B-side or CBM (bottom metal of capacitor) side. The A-side or CTM side of LOFIC 215 is coupled to receive the bias voltage VCAP. The A-side or CTM side of LOFIC 215 is also coupled to receive the pixel reference voltage (e.g., voltage AVDD) through the second reset transistor 232. The second reset transistor 232 is configured to selectively couple LOFIC 215 to the reference or pixel reference voltage (e.g., voltage AVDD) in response to the second reset control signal RST2. The B-side or CBM of LOFIC 215 is coupled to the first floating diffuser FD1 213 (first floating diffuser). The B-side or CBM of LOFIC 215 is coupled to the source of the reset transistor 214 and the drain of the lateral overflow gate transistor 234. In exemplary operation, during a reset or precharge cycle, a reset control signal RSTG is configured to turn on reset transistor 214 and a second reset control signal RST2 is configured to turn on second reset transistor 232, such that both the A-side or CTM-side and the B-side or CBM-side of LOFIC 215 are coupled to receive (for example) a pixel reference voltage (e.g., voltage AVDD) from a pixel reference voltage source to ensure zero bias across LOFIC 215, thereby initiating the discharge process of LOFIC 215. In various embodiments, the insulating material disposed between the first metal electrode or plate and the second metal electrode or plate of LOFIC 215 may be a single layer of high-k material or a multilayer stack, depending on the required LOFIC capacitance. In various examples, the high-k material may comprise one of alumina (Al2O3), zirconium dioxide (ZrO2), hafnium oxide (HfO), or combinations thereof. In various embodiments, LOFIC 215 may be biased by a bias voltage VCAP 236.In addition, the A side of LOFIC 215 can be reset to the pixel reference voltage, such as voltage AVDD (or other voltage provided to the source side of the second reset transistor 232).

[0039] Please refer to later. Figures 4 to 9 As explained, the bias voltage VCAP coupled to LOFIC 215 can be modulated during the idle period (before the integration period). In some embodiments, the bias voltage VCAP can be modulated between a high bias voltage VCAPHi (e.g., 2.8 V) and a low bias voltage VCAPLo (e.g., approximately 0 V). In embodiments, other voltage levels may be implemented depending on the design and operational requirements of the image sensor (for example). By controlling the voltage level of the bias voltage VCAP, the voltage across LOFIC 215 can be adjusted. In various embodiments, the bias voltage VCAP may be supplied by a bias voltage source included in control circuitry (e.g., control circuitry system 104) coupled to pixel 210. It should also be understood that, in various instances, the VCAPLo and VCAPHI bias voltage levels may be determined taking into account the stability range of high-k materials.

[0040] Continuing the discussion of the circuitry of pixel 210, a dual floating diffusion transistor 216 is coupled between the first floating diffusion section FD1 213 and the second floating diffusion section FD2 217, and is further coupled to receive a dual floating diffusion section control signal DFD at its gate terminal. That is, the dual floating diffusion transistor 216 is configured to be turned on in response to the dual floating diffusion section control signal DFD and is configured to transfer image charge from the first floating diffusion section FD1 213 to the second floating diffusion section FD2 217, thereby allowing (for example) when photodiode 211 is saturated or when the generated charge exceeds the full well capacity (FWC) of photodiode 211, image charge to overflow from photodiode 211 to the second floating diffusion section FD2 217 through the first floating diffusion section FD1 213. A lateral overflow gate transistor 234 is coupled between FD2 217 and LOFIC 215, and is further coupled to receive a lateral overflow gate control signal LFG at its gate terminal. Lateral overflow gate transistor 234 is configured to be switched in response to a lateral overflow gate control signal LFG. Additionally, the gate terminal of source follower transistor SF 220 is coupled to floating diffusion node FD1 213. The source / drain terminals of source follower transistor SF 220 are coupled between a reference or pixel voltage (e.g., voltage AVDD) and a row select transistor. Row select transistor 221 may be coupled between bit line 218 and source follower transistor SF 220. Row select transistor 221 is configured to be switched in response to a row select control signal RS and is configured to selectively transmit signals from source follower transistor SF 220 to bit line 218. It should be understood that, depending on the specific requirements of the imaging system, pixel 210 may contain fewer, additional, and / or alternative components (e.g., transistors, capacitors, buffers, switches).

[0041] In operation, transfer transistor 212 receives transfer control signal TX to realize (for example) charge transfer from photodiode 211 to first floating diffuser FD1 213 during a charge transfer cycle following an integration cycle. Generally, the amount of charge transferred depends on the exposure of photodiode 211 and the operation of pixel 210. In some embodiments, capacitor 219 may be formed by metallization present in the physical layout of the device. Transfer transistor 212, dual floating diffuser 216, and lateral overflow gate transistor 234 are configured to allow excess photogenerated charge (e.g., generated under strong light conditions) to overflow from photodiode 211 to LOFIC 215. In some embodiments, LOFIC 215 may increase the charge storage capacity of second floating diffuser FD2217, such as a capacitor. For example, in response to high-intensity illumination, photodiode 211 may generate more charge than the first floating diffuser FD1 213 can store. The additional or excess charge may be stored by LOFIC 215. In some embodiments, the bias voltage VCAP modulates how much charge LOFIC 215 can store. Generally, the first floating diffuser FD1 213 is read out using the high conversion gain (HCG) portion of the data readout, while the second floating diffuser FD2 217 and floating diffuser 213 are read out using the low conversion gain (LCG) portion of the readout. Overall, the HCG and LCG readouts constitute dual conversion gain (DCG) data readout.

[0042] In some embodiments, the operation of RST transistor 214 and dual floating diffusion transistor 216 can reset floating diffusion section FD1 213 to a high voltage representing a dark state because the voltage is proportionally reduced to the intensity of charge on photodiode PD 211 when photogenerated electrons are transferred to the first floating diffusion section FD1 213. To reset the first floating diffusion section FD1 213, RST transistor 214, lateral overflow gate transistor 234, and dual floating diffusion transistor 216 are enabled (turned on) by their respective control signals. In some embodiments, RST transistor 214 may be in the on state while dual floating diffusion transistor 216 remains in the off state, thus resetting the second floating diffusion section FD2 217 but not the first floating diffusion section FD1 213. In an embodiment, the second reset transistor 232 is configured to provide local reset to the coupled LOFIC 215, reduce load effects, and improve the settling time of LOFIC 215.

[0043] Example 1

[0044] Figure 4 This is a diagram illustrating embodiments according to this disclosure (e.g., Figure 3An exemplary timing diagram of the operation of an image sensor. It illustrates different cycles across the pixel operation loop associated with each pixel—readout, idle, precharge, integration, next readout in the next frame, etc.—in LOFIC (e.g., Figure 3 The diagram shows the voltages at the top metal electrode or plate of the capacitor (referred to as the CTM side or A side) and the bottom metal electrode or plate of the capacitor (referred to as the CBM side or B side) of the LOFIC 215. These different time periods are not plotted to scale. For example, in many embodiments, the integration period can be significantly longer than other illustrated periods of the pixel operating cycle. The illustrated bias voltage range across the LOFIC 215 can be from 0 V to 2.8 V; however, in different embodiments, different operating voltage ranges can be applied to the CTM and CBM sides of the LOFIC 215 by the configuration of the bias voltage VCAP applied to the CTM side or by charge accumulation on the CBM side (e.g., charge overflowing from photodiode 211). A row of capacitor images at the bottom of the figure represents the voltage bias states across the LOFIC 215 at different periods of the pixel operating cycle. As explained above, LOFIC 215 can be a high-k MIM capacitor, which is a high-k dielectric sandwiched between the top metal electrode or plate (first metal electrode or plate) and the bottom metal electrode or plate (second metal electrode or plate) of the capacitor.

[0045] It should be understood that the bias voltage VCAP applied to the top metal electrode (or first metal electrode) of the capacitor can be configured to forward bias, zero bias, or reverse bias the LOBIC 215 by adjusting the voltage value at the top metal electrode (or first metal electrode) of the capacitor to be higher than, equal to, or lower than the voltage value applied to the bottom metal electrode (or second metal electrode) of the capacitor at the floating node between the reset transistor 214 and the lateral overflow gate transistor 234. The voltage applied to the top metal electrode (or first metal electrode) of the capacitor may be referred to as the first bias voltage value, and the voltage applied to the bottom metal electrode (or second metal electrode) of the capacitor may be referred to as the second bias voltage value. The first bias voltage value at the top metal electrode of the capacitor can be configured to be higher than, equal to, or lower than the second bias voltage value at the bottom metal electrode of the capacitor.

[0046] For example, when the first bias voltage at the CTM side exceeds the second bias voltage at the CBM side, the LOFIC 215 is configured to be forward biased. Conversely, when the first bias voltage at the CTM side is less than the second bias voltage at the CBM side, the LOFIC 215 is configured to be reverse biased. When the first bias voltage at the CTM side is equal to the second bias voltage at the CBM side, the LOFIC 215 is configured to be zero biased.

[0047] In some embodiments, the control circuit (e.g., Figure 1 The control circuit 104 illustrated herein may include a circuitry that modulates the voltage level supplied by the bias voltage VCAP. In some embodiments, the bias voltage VCAP may be contained on an ASIC chip, while the control circuitry is contained on a pixel chip. In other embodiments, the bias voltage VCAP may be contained on an ASIC chip that also includes the control circuitry.

[0048] In some embodiments, during an idle period, for example, by configuring the switch 236 on the CTM side (A side) of the LOFIC 215 to receive the bias voltage VCAP and applying a first bias voltage value to the CTM side (e.g., by adjusting the bias voltage and closing the switch 236 on the CTM side (A side) of the LOFIC 215), a first bias voltage value is applied. Figure 3 As shown in the diagram, the CTM side (A side) of LOFIC 215 is set to a first bias voltage value (e.g., 1.4 V), while the CBM side (B side) is set to a second bias voltage value (e.g., 2.8 V), which can be supplied by a pixel reference voltage (e.g., voltage AVDD) through reset transistor 214. The voltage bias across LOFIC 215, as previously described, is defined as the difference between the voltage at the CTM side (e.g., from the bias voltage VCAP) and the voltage at the CBM plate (e.g., the voltage at the node between reset transistor 214 and lateral overflow gate transistor 234). Therefore, during idle periods, LOFIC 215 can be reverse biased to compensate for residual charge accumulated from previous frames. For example, LOFIC 215 can be biased with a voltage of -1.4 V.

[0049] During the pre-charge cycle following the idle cycle, the LOFIC 215 can be configured to begin the discharge process with zero bias.

[0050] At the start of the integration cycle, after the pre-charge (reset) cycle is completed, both the CTM side (A side) and CBM side (B side) of the LOFIC can be set to a common bias voltage, for example, 1.4 V. The bias voltage at the CTM side (A side) can be set by the operation of switch 236, wherein the bias voltage VCAP is configured accordingly, and a second bias voltage value at the CBM side (B side) can be set by the pixel reference voltage (e.g., by the voltage AVDD of reset transistor 214). Therefore, at the start of the integration cycle, there is a 0 V voltage bias across the board of LOFIC 215 (i.e., LOFIC 215 is zero biased at the start of the integration cycle). As charge accumulates during the integration period (e.g., as excess photogenerated charge overflows from photodiode PD 211 into LOBIC 215), the second bias voltage at the CBM side of LOBIC 215 decreases to a lower value, such as 0 V (for strong light), at the end of the integration period due to the accumulation of negative charge generated by photodiode PD 211 at LOBIC 215. Therefore, in this example representing relatively bright external conditions, LOBIC 215 can be forward biased to 1.4 V at the end of the integration period.

[0051] The voltage figures described above are given as non-limiting examples. For instance, the integration period may not end precisely at 1.4 V on the CBM side of the LOFIC215, resulting in a 0 V bias. The voltage values ​​illustrated may vary in different embodiments, while still reflecting the principles characterizing the operation of these different embodiments.

[0052] An integration cycle is followed by a readout cycle, which in turn is followed by another idle cycle of the next frame, and so on. Depending on the second bias voltage value at the CBM side of the LOFIC 215 at the end of the integration cycle corresponding to the amount of charge accumulated in the LOFIC 215, the next idle cycle may require a longer or shorter time for the LOFIC (e.g., a high-k MIM capacitor) to discharge properly, potentially resulting in high hysteresis between pixel exposures. See below for reference. Figure 5A and 5B Describe some scenarios with time lag. For ease of reference and without loss of generality, spanning... Figure 5A , 5B The bias voltages of the LOFIC 215 illustrated in the figures of 8A and 8B are shown as normalized from 1 V to -1 V.

[0053] Figure 5A and 5B This is a timing diagram of the LOFIC voltage bias according to an embodiment of the present disclosure. Specifically, Figure 5A The diagram illustrates crossing LOFIC (e.g., under relatively bright (bright) conditions during the integration period. Figure 3 An exemplary representation of the voltage change of the LOFIC 215, while Figure 5B The diagram illustrates the process of crossing LOFIC (e.g., under relatively dark (low light) conditions during the integration process. Figure 3 An exemplary representation of the voltage change of the LOFIC (215). In both cases, the horizontal axis represents time: the left side of the origin is the idle period and the right side of the origin is the integration period. The vertical axis represents the time span across the LOFIC (e.g., ...). Figure 3 The voltage bias of the top and bottom metal electrodes or plates of the LOFIC 215, with a negative bias corresponding to the LOFIC (e.g., Figure 3 The CTM side of the LOFIC (215) has a lower voltage value than the CBM side of the LOFIC (e.g., the LOFIC is reverse biased), and a positive bias corresponds to the CTM side of the LOFIC having a higher voltage value than the CBM side of the LOFIC (e.g., the LOFIC is forward biased). These voltage biases are expressed in the range of about -1 V (bias low or BL) to about +1 V (bias high or BH); however, these values ​​should be understood as representative voltage values ​​only, and other values ​​are possible in different embodiments, depending on the design of the image sensor and the voltages supplied to different nodes of the image sensor circuitry system. Furthermore, in the context of this disclosure, the terms "about," "approximately," and similar terms mean + / - 5% of the stated values.

[0054] Figure 5A The diagram illustrates LOFIC (e.g., under relatively bright (bright) conditions during the integration process. Figure 3 The voltage of the LOFIC215 changes. At the start of the integration cycle, the voltage bias BL across the top and bottom metal plates of the LOFIC is approximately 0V. When the LOFIC (e.g., Figure 3 The LOFIC 215 responds to the amount of incident light accumulating the charge generated by the photodiode PD 211 during the integration period. Figure 3 The LOFIC 215 is positively biased or forward biased, for example, at the end of the integration cycle, the final voltage bias BH is positive 1 V. The integration cycle is followed by the readout cycle, and then by the next idle cycle of the next frame. Because the LOFIC (e.g., Figure 3 The LOFIC 215 is negatively biased to -1 V at the start of the idle cycle, so this negative bias effectively accelerates the operation of a positively biased LOFIC (e.g., ) by enabling charge compensation. Figure 3 The discharge of LOFIC 215 is reduced, thus reducing the discharge with LOFIC (e.g., high k MIM LOFIC capacitors, e.g.) Figure 3The LOFIC 215) is associated with image lag and improves the frame rate of the image sensor.

[0055] Figure 5B The diagram illustrates crossing LOFIC (e.g., under relatively dark (low light) conditions during the integration period. Figure 3 The voltage change of the top and bottom metal electrodes or plates of the LOFIC 215. As... Figure 5A In the scenario shown, the integration period spans LOBIC (e.g., Figure 3 The 0 V voltage bias (BL) begins on the top and bottom metal electrodes or plates of the LOFIC 215. This is because during the idle period prior to the integration cycle, the LOFIC (e.g., Figure 3 The LOFIC 215 has been negatively biased (reverse biased), so during the said idle period the LOFIC (e.g., Figure 3 The charge accumulated in the photodiode PD 211 (LOFIC 215) may not be completely discharged. Therefore, even if the photodiode PD 211 remains exposed to a dark field during the integration period, and the voltage of the photodiode remains 0 V or close to 0 V at the end of the integration period, in the absence of light (e.g., as...), the charge may not be completely discharged. Figure 5A The diagram illustrates the positive bias or forward bias operation during the integration period, and the negative voltage bias (reverse bias) operation during the idle period in the LOFIC (e.g., Figure 3 The photogenerated charge accumulated in the LOFIC 215 may not be offset by the charge accumulated during the positive voltage bias operation in the integration cycle. Therefore, due to the LOFIC (e.g., a high k MIM LOFIC capacitor, such as...) Figure 3 The image lag problem associated with the LOFIC (215) due to the residual charge remaining in the LOFIC may still exist, as explained above. This may affect the overall image quality or operation of the image sensor due to the need for a long idle period and the inability to have a frame rate.

[0056] Example 2

[0057] Figure 6A This is an electrical schematic diagram of a pixel according to an embodiment of the present disclosure. The schematic diagram illustrates a pixel circuit system with a LOFIC. The voltage bias operation applied to the LOFIC can be relatively easily incorporated into existing image sensor products because... Figure 3 Compared to the pixel diagram shown in the previous example (which, for example, requires the addition of an extra transistor for local reset), here only the bias operation of the bias voltage VCAP needs to be configured. In some embodiments, this update can be achieved by tuning the pixel control circuitry system (e.g., Figure 1The control circuit system 104 is implemented using the existing application-specific integrated circuit (ASIC) design.

[0058] Figure 6B This is a timing diagram illustrating the various stages of image sensor operation according to embodiments of the present disclosure. Figure 6B Can be displayed and Figure 6A The illustration shows a timing diagram associated with the exemplary pixel 210B. The bottom row of capacitor symbols illustrates the voltage at the top metal electrode (CTM side or A side) and bottom metal electrode (CBM side or B side) of the capacitor during different periods of the pixel operation cycle—readout, idle, pre-charge, integration, and transition to the next readout. As previously stated, the illustrated voltage range is from 0 V to 2.8 V; however, different voltage ranges may be applied in different embodiments.

[0059] In an embodiment, during an idle period, both the CTM side (A side) and CBM side (B side) of the LOFIC 215 in pixel 210B are configured to receive a common bias voltage value, which causes the LOFIC 215 to be zero-biased, thereby allowing the LOFIC to discharge. For example, as Figure 6B As illustrated in the diagram, by closing switch 236, which couples the bias voltage VCAP to the CTM side (A side) of LOBIC 215, a first bias voltage of 2.3 V is provided to the CTM side (A side) of LOBIC 215, thus setting the CTM side (A side) of LOBIC 215 to 2.3 V. Simultaneously, by enabling reset transistor 214, a second bias voltage of 2.3 V is also set to the CBM side (B side). In this embodiment, during the idle period, LOBIC 215 is zero-biased, causing LOBIC 215 to begin the discharge process.

[0060] During the pre-charge or reset cycle, the CTM side (A side) of LOFIC 215 is set to a first bias voltage value lower than the second bias voltage value applied to the CBM side (B side) of LOFIC 215, causing LOFIC 215 to be reverse biased. For example, the CTM side (A side) of LOFIC 215 is set to a first bias voltage value of 2.3 V by configuring the bias voltage VCAP, and the CBM side (B side) of LOFIC is set to a second bias voltage value of 2.8 V by configuring the voltage level of the pixel reference voltage (e.g., voltage AVDD). At the start of the integration cycle, the CTM side (A side) of LOFIC 215 is set to a first bias voltage value lower than the second bias voltage value applied to the CBM side (B side) of LOFIC 215, causing LOFIC 215 to continue to be reverse biased. For example, at the start of the integration cycle, after pre-charging (reset) is complete, the CTM side (A side) of LOFIC 215 is set to a first bias voltage value of 0.9 V by configuring the bias voltage VCAP, and the CBM side (B side) of LOFIC is set to a second bias voltage value of 1.4 V by configuring the pixel reference voltage (e.g., voltage AVDD). Subsequently, at the start of the integration cycle, a voltage bias of -0.5 V exists across LOFIC 215; that is, LOFIC 215 is configured to be reverse biased at the start of the integration cycle. In the illustrated embodiment, the bias voltage VCAP can be configured such that the first bias voltage value applied to the CTM side (A side) of LOFIC 215 during the integration cycle is lower than the first bias voltage value applied to the CTM side (A side) of LOFIC 215 during the pre-charging cycle, to ensure the voltage swing range required across the target bias voltage of LOFIC 215 and the LOFIC readout voltage.

[0061] When the photodiode PD generates photocharge in response to incoming light (e.g., under bright light conditions), charge can begin to accumulate in LOFIC 215 during the integration period. The voltage value at the CBM side of LOFIC 215 (e.g., the second bias voltage value) can begin to decrease to a lower value (e.g., 0.4 V), so that LOFIC 215 can be forward biased at the end of the integration period due to the accumulation of negative charge at LOFIC 215. Therefore, LOFIC 215 changes its voltage bias from -0.5 V (BL) at the beginning of the integration period to 0.5 V (BH) at the end of the integration period. That is, LOFIC 215 can be reverse biased at the beginning of the integration period and become forward biased as LOFIC 215 accumulates the charge overflowing from photodiode PD 211. This compensates for or cancels residual charge accumulated in the LOFIC 215 (e.g., charge accumulated and trapped by the insulating material of the LOFIC 215 during the current or previous frame), thus reducing the discharge time of the LOFIC 215 and thereby reducing image hysteresis associated with the LOFIC 215. For example, the image charge discharged from the LOFIC 215 during idle periods has opposite polarity to the image charge discharged from the LOFIC 215 during forward bias operation and can compensate for each other during subsequent readout operations. In this way, the trapped charge released from the insulating material of the LOFIC can be reduced or eliminated in such a way that those trapped charges will not affect the readout voltage (signal) of the LOFIC 215 being read during readout operations.

[0062] On the other hand, under dark conditions, the photodiode PD generates very little or no charge, and the LOFIC215 maintains its initial voltage bias of -0.5 V. It should be understood that the amount of charge that can be stored in the LOFIC 215 is related to the bias voltage applied across the LOFIC 215; therefore, by reducing the bias voltage across the LOFIC 215, the charge can be stored in the LOFIC 215. Figure 5B Compared to the illustration in the diagram, the amount of charge accumulated and stored in the LOFIC 215 under low-light conditions can be reduced accordingly. This shortens the discharge time of the LOFIC 215 and reduces image hysteresis associated with the LOFIC 215 during subsequent readout operations.

[0063] Figures 7A to 7C The figure illustrates the relationship between the sample signal voltage of a high-k (high dielectric constant) metal-to-metal (MIM) LOFIC and the amount of charge accumulated in the LOFIC during the integration period, according to an embodiment of the present disclosure. Figures 7A to 7C Diagrammatic explanation in Figure 6AThe sample signal voltage of LOFIC used in pixel 210B. As explained above, the voltage values ​​are given as non-limiting examples, and the voltage values ​​illustrated may vary in different embodiments, while still reflecting the principles characterizing the operation of these different embodiments.

[0064] Figure 7A The diagram illustrates the LOFIC (e.g., at the end of the integration period in the case of low signal (relatively low light conditions) Figure 6A The voltages on the CTM side (A side) and CBM side (B side) of the LOFIC (e.g., LOFIC 215). In this scenario, throughout the entire integration cycle, the CTM side of the LOFIC (e.g., LOFIC 215) remains at its initial value of 0.9 V (first bias voltage value). Because a relatively small amount of charge is generated by the photodiode PD during the integration cycle, the voltage on the CBM side of the LOFIC (e.g., LOFIC 215) (second bias voltage value) also remains constant at or near 1.4 V. Therefore, the LOFIC (e.g., LOFIC 215) continues to be reverse biased.

[0065] Figure 7B The diagram illustrates the voltages on the CTM side (A side) and CBM side (B side) of a LOFIC (e.g., LOFIC 215) at the end of the integration cycle under a medium-level signal (medium brightness field) scenario. Here, a considerable amount of charge is generated by the photodiode PD (e.g., photodiode PD 211) during the integration cycle, thus causing the second bias voltage value at the CBM side of the LOFIC (e.g., LOFIC 215) to change from 1.4 V to 0.9 V, which is equivalent to changing the bias voltage of the LOFIC (e.g., LOFIC 215) from -0.5 V to 0 V. That is, the LOFIC (e.g., LOFIC 215) is configured to operatively switch from reverse bias operation to zero bias operation.

[0066] Figure 7CThe diagram illustrates the voltage values ​​on the CTM side (A side) and CBM side (B side) of the LOFIC (e.g., LOFIC 215) at the end of the integration cycle under a high-level signal (bright field) scenario. Here, a relatively high amount of charge generated by the photodiode PD (e.g., photodiode PD 211) overflows into the coupled LOFIC (e.g., LOFIC 215) during the integration cycle, causing the second bias voltage value at the CBM side of the LOFIC (e.g., LOFIC 215) to change from 1.4 V to 0.4 V, which is equivalent to changing the voltage bias of the LOFIC (e.g., LOFIC 215) from -0.5 V to 0.5 V. That is, the LOFIC (e.g., LOFIC 215) is configured to operatively switch from reverse bias operation to forward bias operation. See below for reference. Figure 8A and 8B Discuss the relevance of these termination bias operations in LOFIC.

[0067] Figure 8A and 8B This is a timing diagram associated with an exemplary pixel (e.g., pixel 210B) according to embodiments of this disclosure. Specifically, Figure 8A The illustration is in the above text. Figure 7C The change in LOFIC voltage bias during the integration process under relatively bright (bright) conditions, while Figure 8B The illustration is in the above text. Figure 7A The voltage change of the LOFIC during the integration process under relatively dark (low light) conditions is shown. In both graphs, the horizontal axis represents time: idle time is to the left of the origin and integration time is to the right of the origin. The vertical axis represents the voltage bias across the LOFIC, with a negative bias corresponding to a lower bias voltage on the CTM side of the LOFIC than on the CBM side, and a positive bias corresponding to a higher bias voltage on the CTM side than on the CBM side. These voltage biases are represented as ranging from approximately -0.5 V (BL) to approximately 0.5 V (BH); however, these values ​​should be understood as representative voltage values ​​only, and other values ​​are possible in different embodiments, depending on the image sensor design and the voltages supplied to different nodes of the image sensor circuitry.

[0068] Figure 8A The illustration is in the above text. Figure 7C The voltage bias of the LOFIC changes during the integration process under relatively bright (bright) conditions. At the start of the integration process, the voltage bias across the LOFIC (e.g., Figure 6A The voltage bias of the electrode or plate of the LOFIC 215 (of pixel 210B) is approximately -0.5 V. With LOFIC (e.g., Figure 6AIn pixel 210B, the LOFIC 215 accumulates the charge generated by the photodiode PD, and at the end of the integration cycle, the final voltage bias is approximately 0.5 V. By allowing the LOFIC (e.g., Figure 6A The LOFIC 215 of pixel 210B is switched from reverse bias to forward bias, which can compensate for or cancel the residual charge in the LOFIC, thereby reducing image hysteresis associated with the LOFIC.

[0069] Figure 8B The illustration is in the above text. Figure 7A Under relatively dark (low light) conditions during the integration process across LOFIC (e.g., Figure 6A The voltage of the electrode or plate of pixel 210B (LOFIC 215) changes. As... Figure 8A In the scenario illustrated, the integration process begins with a -0.5 V bias across the electrodes or plates of the LOFIC. However, because the photodiode is still exposed to the dark field during the integration process, it generates very little or no charge, so the voltage bias of the LOFIC remains constant at -0.5 V at the end of the integration cycle.

[0070] Since LOFIC returns to its 0V bias at the start of the next idle cycle, Figure 8A In either the scenario in 8B (bright light) or the scenario in 8B (dark field), the voltage bias across the LOFIC plate is maintained within a maximum range of -0.5 V to 0.5 V. In many embodiments, limiting the voltage bias across the CTM and CBM electrodes or plates of the LOFIC results in a smaller amount of charge accumulating on said electrodes or plates because the charge (Q) of a capacitor is the product of the capacitor's capacitance (C) and the bias voltage (V), i.e., Q = Cv. When the voltage bias across the CTM and CBM electrodes or plates of the LOFIC is limited to approximately + / - 0.5 V, the capacitor charge Q is also reduced, thereby reducing the capacitor's hysteresis time. Therefore, at the start of the next idle process, the amount of hysteresis accumulated by the LOFIC (e.g., a high-k MIM capacitor) is smaller, resulting in shorter idle times and improved frame rates. Furthermore, since the LOFIC voltage bias is approximately 0 V during the idle period, there is no need for complex bias voltage VCAP control, which sets the voltage bias to a specific predetermined value for a specific amount of time during the idle period.

[0071] Example 3

[0072] Figure 9 This is a timing diagram illustrating the various stages of image sensor operation according to embodiments of the present disclosure. Figure 9 Showcase targeting Figure 6A An exemplary timing diagram of the schematic circuitry is shown. The bottom row of capacitor diagrams illustrates the LOCICs (e.g., capacitors) included in the pixel circuitry during different periods of the pixel operation cycle—readout, idle, precharge, integration, transition to the next readout, etc. Figure 6A The voltage at the top metal electrode or plate (CTM side or A side) and bottom metal electrode or plate (CBM side or B side) of the capacitor of pixel 210B (LOFIC 215). The illustrated voltage range during the integration period is from 2.8 V to 0 V; however, different voltages may be used in different embodiments.

[0073] In some embodiments, during an idle period, the LOFIC (e.g., Figure 6A The CTM side of the LOFIC 215 is coupled to a switch (e.g., switch 236 in Figure 6) that provides a bias voltage VCAP (from a bias voltage source) while the LOFIC (e.g., Figure 6A The CTM side (A side) of the LOFIC 215 (of pixel 210B) is set to a first bias voltage value of 1.4 V, while the CBM side (B side) of the LOFIC is set to a second bias voltage value of approximately 0 V by enabling the reset transistor to allow the CBM side (B side) of the LOFIC to couple to a pixel reference voltage source (e.g., a voltage source providing a pixel reference voltage (e.g., voltage AVDD)). Therefore, during the idle period, the LOFIC (e.g., Figure 6A The LOFIC 215 is biased to approximately 1.4 V. That is, LOFIC (e.g., Figure 6A The LOFIC 215 is positively biased during the idle cycle. During the pre-charge cycle, the LOFIC (e.g., Figure 6A The CTM side (A side) of the LOFIC 215 can continue to be set to 1.4 V, while the CBM side (B side) is set to approximately 2.8 V, thereby causing the LOFIC (e.g., Figure 6A The LOFIC 215 is reverse biased to compensate for or cancel out the LOFIC (e.g., Figure 6A A portion of the residual charge accumulated in LOFIC 215.

[0074] At the start of the integration cycle, after pre-charge (reset) is complete, the CTM side (A side) of the LOFIC is set to 0 V (e.g., by configuring the bias voltage VCAP) and the LOFIC (e.g., Figure 6A The CBM side (B side) of the LOFIC 215 is set to 1.4 V. That is, at the start of the integration cycle, the voltage across the LOFIC (e.g., Figure 6AThe LOFIC 215 board has a -1.4V bias, causing the LOFIC to be reverse biased. When the photodiode PD is exposed to bright light, as charge accumulates during the integration period, the LOFIC (e.g., Figure 6A The voltage value (e.g., the second bias voltage value) at the CBM side of the LOFIC 215 is due to the negative charge generated by PD 211 in the LOFIC (e.g., Figure 6A The accumulation at LOFIC 215) decreases to a lower value, such as about 0 V, at the end of the integration period. Therefore, LOFIC (e.g., Figure 6A The voltage bias of the LOFIC 215 changes from approximately -1.4 V (reverse bias) at the start of the integration cycle to approximately 0 V (zero bias) at the end of the integration cycle. However, in dark field scenarios, the photodiode PD generates very little or no charge, and the LOFIC (e.g., Figure 6A The LOFIC215 maintains its initial bias of -1.4 V. See below for reference. Figure 10A and 10B Explain these two scenarios (bright field and dark field).

[0075] Figure 10A and 10B This is a timing diagram of LOFIC voltage bias according to an embodiment of the present disclosure. Figure 10A The illustration is in the above text. Figure 9 Under relatively bright (bright) conditions during the integration process, LOFIC (e.g., Figure 6A The voltage of the LOFIC 215 changes, and Figure 10B The illustration is in the above text. Figure 9 The voltage change of the LOFIC during the integration process under relatively dark (low light) conditions. In both graphs, the horizontal axis represents time: the idle period is to the left of the origin and the integration period is to the right of the origin. The vertical axis represents the span across the LOFIC (e.g., Figure 6A The voltage bias of the CTM and CBM electrodes or plates of the LOFIC 215. These voltage biases across the LOFIC are expressed as ranging from -1 V to 1 V; however, these values ​​should be understood as representative voltage values ​​only and other values ​​are possible in different embodiments.

[0076] Figure 10A The diagram illustrates LOFIC (e.g., under relatively bright (bright) conditions during the integration period. Figure 6A The voltage of the LOFIC 215 changes. During the idle period before the integration period, the LOFIC (e.g., Figure 6AThe LOFIC215 is configured such that the board across the LOFIC has a positive 1 V, thus causing the LOFIC to be forward biased. At the start of the integration cycle, the voltage across the board of the LOFIC is biased to approximately -1 V (BL). As the LOFIC (e.g., Figure 6A The LOFIC 215 accumulates the charge generated by the photodiode PD, and at the end of the integration cycle, the final bias across the LOFIC can be reduced to approximately 0 V (BH). That is, the LOFIC is configured so that the plate across the LOFIC is biased in opposite directions during the idle cycle and subsequent integration cycles, such that the LOFIC (e.g., ...) Figure 6A The residual charge in the LOFIC 215 can be stably compensated, thereby maintaining the LOFIC readout voltage at the CBM side (B side) of the LOFIC (or the junction node between the reset transistor (e.g., reset transistor 214) and the lateral overflow gate transistor (e.g., lateral overflow gate transistor 234)) during the readout cycle.

[0077] Figure 10B The diagram illustrates crossing LOFIC (e.g., under relatively dark (low light) conditions during the integration period. Figure 6A The voltage of the LOFIC 215 board changes. During the idle cycle, the LOFIC (e.g., Figure 6A LOFIC 215) is configured to span LOFIC (e.g., Figure 6A The board of LOFIC 215 has a positive 1V, which causes LOFIC (e.g., Figure 6A The LOFIC 215 is positively biased. As... Figure 10A In the scenario shown (integration period), LOFIC (for example, Figure 6A LOFIC 215) is configured to span LOFIC (e.g., Figure 6A The electrodes or plates of the LOFIC 215 are reverse biased with a -1 V bias. However, since the photodiode remains exposed to a dark field during integration, it generates very little or no charge. Therefore, at the end of the integration cycle, the LOFIC (e.g., Figure 6A The voltage bias of the LOFIC 215 remains constant at approximately -1V. Thus, the charge accumulated during the idle period and the charge accumulated during the integration period have opposite polarities and can compensate for each other, for example, canceling out the charge from the LOFIC (e.g., ...). Figure 6A The LOFIC 215) insulation material releases trapped charges, thereby reducing image lag during subsequent readout cycles in relatively dark landscape conditions.

[0078] Due to LOFIC (for example, Figure 6AThe voltage bias of the LOFIC 215 returns to -1 V at the start of the idle cycle. Figure 10B In the dark condition, the voltage bias of the LOFIC reverses from -1 V at the end of the integration cycle to 1 V at the beginning of the idle cycle, accelerating the discharge process of the LOFIC and thus reducing its hysteresis time. However, in Figure 10A Under relatively bright conditions, this reversal of the voltage bias of LOFIC does not exist. As a result, under bright field conditions, as described above... Figure 10B Compared to the scenario described in [the text], the minimum idle period can still remain relatively long.

[0079] The above description of the illustrated examples of the invention, including the content described in the abstract, is not intended to be exhaustive or limited to the precise forms disclosed. Although specific embodiments and examples of the invention have been described herein for illustrative purposes, various equivalent modifications may be made without departing from the broader spirit and scope of the invention. In fact, it should be understood that specific exemplary voltage, current, frequency, power range values, time, etc., are provided for illustrative purposes and other values ​​may be used in other embodiments and examples according to the teachings of the invention. In the context of this disclosure, the terms "about," "approximately," and similar terms mean + / - 5% of the stated values.

[0080] Based on the above detailed description, these modifications can be made to the embodiments of the invention. The terminology used in the appended claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope will be determined entirely by the appended claims, which will be understood according to the established principles of interpretation of the claims. Therefore, this specification and the figures should be considered illustrative rather than limiting.

Claims

1. A method for reducing image lag associated with a pixel included in a plurality of pixels, the pixel including a photodiode, a first floating diffusion coupled to the photodiode by a transfer transistor, a second floating diffusion coupled to the first floating diffusion by a double floating diffusion transistor, and a lateral overflow integration capacitor coupled between the second floating diffusion and a bias voltage source, and the lateral overflow integration capacitor is further coupled to a pixel reference voltage source by a reset transistor, wherein operation of the pixel includes an idle period and an integration period after the idle period, the method comprising: configuring the lateral overflow integration capacitor to be zero-biased or forward-biased during the idle period; and configuring the lateral overflow integration capacitor to be reverse-biased at the beginning of the integration period when the photodiode is exposed to light. wherein configuring the lateral overflow integration capacitor to be zero-biased during the idle period comprises:

2. The method of claim 1, wherein the lateral overflow integration capacitor includes an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled through a switch to the bias voltage source to receive a first bias voltage, wherein the second metal electrode is coupled through the reset transistor to the pixel reference voltage source to receive a second bias voltage; coupling the bias voltage source to the first metal electrode of the lateral overflow integration capacitor, thereby providing the first bias voltage to the first metal electrode of the lateral overflow integration capacitor; and causing the reset transistor to turn on to couple the second metal electrode of the lateral overflow integration capacitor to the pixel reference voltage source, thereby providing the second bias voltage to the second metal electrode of the lateral overflow integration capacitor; wherein the first bias voltage and the second bias voltage are configured to be the same.

3. The method of claim 2, wherein configuring the lateral overflow integration capacitor to be reverse-biased at the beginning of the integration period comprises: configuring the first bias voltage to be lower than the second bias voltage at the beginning of the integration period.

4. The method of claim 3, comprising: configuring the transfer transistor and the double floating diffusion transistor such that image charge photogenerated by the photodiode overflows to the lateral overflow integration capacitor during the integration period, thereby causing the second bias voltage at the second metal electrode to decrease; and configuring the first bias voltage of the bias voltage source such that the lateral overflow integration capacitor is reverse-biased at the beginning of the integration period and becomes forward-biased at a later time during the integration period as the second bias voltage at the second metal electrode of the lateral overflow integration capacitor decreases to be less than the first bias voltage provided to the first metal electrode, wherein the forward-bias voltage between the first metal electrode and the second metal electrode is set based on an amount of overflow image charge received from the photodiode.

5. The method of claim 4, wherein the forward-bias voltage is configured to equal a reverse-bias voltage at the beginning of the integration period.

6. The method of claim 5, wherein the forward-bias voltage is 0.5 V. wherein configuring the lateral overflow integration capacitor to be forward-biased during the idle period comprises:

7. The method of claim 1, wherein the lateral overflow integration capacitor includes an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to the bias voltage source through a switch, wherein the second metal electrode is coupled to the pixel reference voltage source through the reset transistor; coupling the bias voltage source to the first metal electrode of the lateral overflow integration capacitor, thereby providing the first bias voltage to the first metal electrode of the lateral overflow integration capacitor; and causing the reset transistor to turn on to couple the second metal electrode of the lateral overflow integration capacitor to the pixel reference voltage source, thereby providing the second bias voltage to the second metal electrode of the lateral overflow integration capacitor; wherein the first bias voltage and the second bias voltage are configured to be the same. coupling the bias voltage source to the first metal electrode of the lateral overflow integration capacitor to provide a first bias voltage to the first metal electrode of the lateral overflow integration capacitor; and causing the reset transistor to turn on to couple the second metal electrode of the lateral overflow integration capacitor to the pixel reference voltage source to provide a second bias voltage to the second metal electrode of the lateral overflow integration capacitor, wherein the first bias voltage is greater than the second bias voltage.

8. The method of claim 7, wherein when the lateral overflow integration capacitor is configured to be forward biased during the idle period, the lateral overflow integration capacitor is configured to be reverse biased during the integration period such that charges accumulated in the lateral overflow integration capacitor during the idle period and during the integration period cancel each other out to maintain a readout voltage at the second metal electrode during a readout period that occurs after the integration period.

9. The method of claim 1, wherein the operations of the pixel further comprise a pre-charge period between the idle period and the integration period, including during the pre-charge period, configuring a first bias voltage of the bias voltage source to be less than a second bias voltage of the pixel reference voltage source such that the lateral overflow integration capacitor is reverse biased.

10. The method of claim 9, further comprising: configuring the first bias voltage in the integration period to be less than the first bias voltage in the pre-charge period.

11. An image sensor, comprising: a plurality of pixels arranged in a number of rows and a number of columns of a pixel array, each pixel comprising: a photodiode; a first floating diffusion connected to the photodiode; a transfer transistor connecting the photodiode to the first floating diffusion; a second floating diffusion; a double floating diffusion transistor coupled between the first floating diffusion and the second floating diffusion; and a lateral overflow integration capacitor coupled between the second floating diffusion and a bias voltage source, wherein the photodiode is configured to generate charges during an integration period, and wherein the integration period is preceded by an idle period, wherein operations of the pixel comprise: configuring the lateral overflow integration capacitor to be zero biased or forward biased during the idle period; and configuring the lateral overflow integration capacitor to be reverse biased at the beginning of the integration period when the photodiode is exposed to light.

12. The image sensor of claim 11, wherein the lateral overflow integration capacitor includes an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled through a switch to the bias voltage source to receive a first bias voltage, wherein the second metal electrode is coupled through a reset transistor to a pixel reference voltage source to receive a second bias voltage; wherein configuring the lateral overflow integration capacitor to be zero biased during the idle period comprises: coupling the first metal electrode of the lateral overflow integration capacitor to the bias voltage source to receive the first bias voltage; and turning on the reset transistor to couple the second metal electrode of the lateral overflow integration capacitor to the pixel reference voltage source to enable the second metal electrode of the lateral overflow integration capacitor to receive the second bias voltage; wherein the first bias voltage and the second bias voltage are configured to have the same voltage.

13. The image sensor of claim 12, wherein configuring the lateral overflow integration capacitor to be reverse-biased at the beginning of the integration period comprises: configuring the first bias voltage to be lower than the second bias voltage at the beginning of the integration period.

14. The image sensor of claim 11, wherein the lateral overflow integration capacitor is a high-k dielectric constant metal-against-metal (MIM) capacitor.

15. The image sensor of claim 11, wherein the lateral overflow integration capacitor includes an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled through a switch to the bias voltage source to receive a first bias voltage during the idle period, wherein the second metal electrode is coupled through a reset transistor to a pixel reference voltage source to receive a second bias voltage during the idle period, wherein the operation of the pixel comprises: configuring the transfer transistor and the double-floated diffusion transistor to allow image charge photogenerated by the photodiode to overflow to the lateral overflow integration capacitor during the integration period, causing the second bias voltage at the second metal electrode to decrease; and configuring the first bias voltage of the bias voltage source such that the lateral overflow integration capacitor is reverse-biased at the beginning of the integration period and becomes forward-biased at a later time during the integration period when the second bias voltage at the second metal electrode of the lateral overflow integration capacitor decreases to be less than the first bias voltage at the first metal electrode, wherein a forward-bias voltage between the first metal electrode and the second metal electrode of the lateral overflow integration capacitor is set based on an amount of overflow image charge received from the photodiode.

16. The image sensor of claim 15, wherein the forward-bias voltage is configured to equal a reverse-bias voltage at the beginning of the integration period.

17. The image sensor of claim 11, wherein the lateral overflow integration capacitor includes an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to the bias voltage source through a switch, wherein the second metal electrode is coupled to a pixel reference voltage source through a reset transistor, wherein the image sensor further includes the reset transistor coupled between the lateral overflow integration capacitor and the pixel reference voltage source; wherein configuring the lateral overflow integration capacitor to be forward-biased during the idle period comprises: coupling the bias voltage source to the first metal electrode of the lateral overflow integration capacitor, providing a first bias voltage to the first metal electrode of the lateral overflow integration capacitor; and causing the reset transistor to turn on to couple the second metal electrode of the lateral overflow integration capacitor to the pixel reference voltage source, providing a second bias voltage to the second metal electrode of the lateral overflow integration capacitor, wherein the first bias voltage is greater than the second bias voltage.

18. The image sensor of claim 17, wherein when the lateral overflow integration capacitor is configured to be forward biased during the idle period, the lateral overflow integration capacitor is configured to be reverse biased during the integration period, such that image charges accumulated in the lateral overflow integration capacitor during the idle period and during the integration period cancel each other out, thereby maintaining a readout voltage at the second metal electrode of the lateral overflow integration capacitor during a readout period.

19. The image sensor of claim 18, wherein the operations of the pixel further comprise a pre-charge period between the idle period and the integration period, including during the pre-charge period, configuring the first bias voltage of the bias voltage source applied to the first metal electrode of the lateral overflow integration capacitor to be less than the second bias voltage of the pixel reference voltage source, such that the lateral overflow integration capacitor is reverse biased.

20. The image sensor of claim 19, further comprising: configuring the bias voltage source such that the first bias voltage provided by the bias voltage source in the integration period is less than the first bias voltage provided by the bias voltage source in the pre-charge period.

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