Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a plurality of scanning lines, a plurality of data line sets and a plurality of pixel electrode sets, each pixel electrode set comprises a first type of pixel electrodes and a second type of pixel electrodes, and the first type of pixel electrodes and the second type of pixel electrodes are alternately arranged in the first direction; the data line group comprises a first type of data lines and a second type of data lines, and the first type of data lines and the second type of data lines are alternately arranged in a first direction; the first type of data lines are connected with the second type of pixel electrodes of the first type of pixel rows and the first type of pixel electrodes of the second type of pixel rows, and the second type of data lines are connected with the first type of pixel electrodes of the first type of pixel rows and the second type of pixel electrodes of the second type of pixel rows. The data lines are arranged in a staggered manner, so that the aperture opening ratio of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the related art, the first metal layer at the bottom is generally used as a gate line and a common electrode line to transmit gate signals and common signals. In order to prevent signal short circuit, a safe distance needs to be reserved between the gate line and the common electrode line, which leads to a decrease in pixel aperture ratio and penetration ratio. Summary of the invention

[0003] Embodiments of the present application provide an array substrate and a display panel to solve the problem of decreased pixel aperture ratio and transmittance in the array substrate in the related art.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, the present application provides an array substrate, comprising:

[0006] A plurality of scan lines and a plurality of data line groups, wherein the plurality of data line groups are arranged along a first direction, the scan lines extend along the first direction, and the plurality of scan lines are arranged along a second direction intersecting the first direction; the plurality of scan lines and the plurality of data line groups are intersected to form a plurality of pixel regions; and

[0007] A plurality of pixel electrode groups, one of the pixel electrode groups is correspondingly arranged in one of the pixel regions, the plurality of pixel electrode groups are arranged along the first direction to form pixel rows, the pixel rows include first-type pixel rows and second-type pixel rows, the first-type pixel rows and the second-type pixel rows are alternately arranged along the second direction; in the second direction, the pixel electrode groups of the first-type pixel rows are correspondingly arranged between two adjacent pixel electrode groups of the second-type pixel rows;

[0008] The pixel electrode group includes a first type of pixel electrodes and a second type of pixel electrodes, and the first type of pixel electrodes and the second type of pixel electrodes are alternately arranged in the first direction.

[0009] In one embodiment, the data line group includes a first type of data lines and a second type of data lines, and the first type of data lines and the second type of data lines are alternately arranged in a first direction; the first type of data lines connect the second type of pixel electrodes of the first type of pixel rows and the first type of pixel electrodes of the second type of pixel rows, and the second type of data lines connect the first type of pixel electrodes of the first type of pixel rows and the second type of pixel electrodes of the second type of pixel rows.

[0010] In one embodiment, the first type of data line includes a first routing portion, a second routing portion, a third routing portion, a fourth routing portion, a fifth routing portion, and a sixth routing portion, the first routing portion and the second routing portion are arranged in the first type of pixel row, the fourth routing portion and the fifth routing portion are arranged in the second type of pixel row, the third routing portion and the sixth routing portion are arranged between the first type of pixel row and the second type of pixel row, the third routing portion is connected to the fourth routing portion from one end of the second routing portion in the reverse direction of the first direction, and the sixth routing portion is connected to the first routing portion from one end of the fifth routing portion in the first direction;

[0011] The second-category data line includes a seventh routing portion, an eighth routing portion, a ninth routing portion, a tenth routing portion, an eleventh routing portion and a twelfth routing portion, the seventh routing portion and the eighth routing portion are arranged in the first-category pixel row, the tenth routing portion and the eleventh routing portion are arranged in the second-category pixel row, the ninth routing portion and the twelfth routing portion are arranged between the first-category pixel row and the second-category pixel row, the ninth routing portion connects the eighth routing portion and the tenth routing portion, and the twelfth routing portion connects the eleventh routing portion and the seventh routing portion;

[0012] The first routing portion and the second routing portion are connected to the second type of pixel electrodes of the first type of pixel rows, the fourth routing portion and the fifth routing portion are connected to the first type of pixel electrodes of the second type of pixel rows, the seventh routing portion and the eighth routing portion are connected to the first type of pixel electrodes of the first type of pixel rows, and the ninth routing portion and the tenth routing portion are connected to the second type of pixel electrodes of the second type of pixel rows.

[0013] In one embodiment, the first routing portion and the seventh routing portion are parallel to each other, the second routing portion and the eighth routing portion are parallel to each other, the fourth routing portion and the tenth routing portion are parallel to each other, and the fifth routing portion and the eleventh routing portion are parallel to each other;

[0014] A first angle is formed between the first routing portion and the second routing portion, and a second angle is formed between the fourth routing portion and the fifth routing portion.

[0015] In one embodiment, the array substrate further comprises a plurality of thin film transistor groups, the thin film transistor groups are arranged between two adjacent pixel electrode groups and located in the corner area of ​​the pixel electrode groups, each of the thin film transistor groups comprises a first thin film transistor and a second thin film transistor, a control end of the first thin film transistor and a control end of the second thin film transistor are connected to the scan line, an input end of the first thin film transistor is connected to the first type of data line, an input end of the second thin film transistor is connected to the second type of data line, in the first pixel row, an output end of the first thin film transistor is connected to the second type of pixel electrode, and an output end of the second thin film transistor is connected to the first type of pixel electrode; in the second pixel row, an output end of the first thin film transistor is connected to the first type of pixel electrode, and an output end of the second thin film transistor is connected to the second type of pixel electrode;

[0016] Among them, the first thin film transistors and the second thin film transistors are alternately arranged in rows along the first direction; in each of the thin film transistor groups, the first thin film transistors are arranged on a side of the first type of data line away from the second type of data line, and the second thin film transistors are arranged on a side of the second type of data line away from the first type of data line.

[0017] In one embodiment, each of the pixel regions is a dual-pixel domain region, and the first-type pixel electrode and the second-type pixel electrode correspond to one pixel domain region respectively.

[0018] In one embodiment, the array substrate further includes a common wiring, and the common wiring is extended along the first direction. In the array substrate viewed from a top view, in the second direction, the common wiring is arranged between two adjacent pixel domains.

[0019] In one embodiment, the plurality of pixel electrode groups are arranged in the same layer to form a pixel electrode layer, the array substrate further comprises a first common electrode layer connected to the common wiring, the pixel electrode layer and the first common electrode layer are arranged in different layers, the first common electrode layer comprises a plurality of first common electrodes, and one of the first common electrodes is arranged in a corresponding pixel region;

[0020] In the array substrate in a top view, a first common electrode overlaps with a first type of pixel electrode and a second type of pixel electrode of the same pixel electrode group;

[0021] The first common electrode layer is provided with slits.

[0022] In one embodiment, the plurality of pixel electrode groups are arranged in the same layer to form a pixel electrode layer, the array substrate further comprises a first common electrode layer and a second common electrode layer connected to the common wiring, the pixel electrode layer and the first common electrode layer are arranged in different layers, and the pixel electrode layer and the second common electrode layer are arranged in the same layer;

[0023] The first common electrode layer includes a plurality of first common electrodes, one of the first common electrodes is disposed in a corresponding pixel region, and in the array substrate in a top view, one of the first common electrodes overlaps with the first type of pixel electrode and the second type of pixel electrode of the same pixel electrode group at the same time;

[0024] The second common electrode layer includes a plurality of second common electrodes, and in the array substrate in a top view, one of the second common electrodes partially overlaps with the data line group;

[0025] At least one through hole is provided on the second common electrode;

[0026] The pixel electrode layer is provided with slits.

[0027] In one embodiment, in the second direction, the first type of pixel electrodes and the second type of pixel electrodes are alternately arranged into pixel columns, and a plurality of the pixel columns are arranged along the first direction, wherein, in the same picture frame, the voltage polarity connected to the first type of data line is opposite to the voltage polarity connected to the second type of data line.

[0028] In a second aspect, the present application provides a display panel, comprising the above-mentioned array substrate and an opposing substrate arranged opposite to the array substrate.

[0029] In one embodiment, the display panel further comprises a plurality of spacers, wherein the spacers are arranged between the first type pixel row and the second type pixel row;

[0030] In the display panel viewed from a top view, at least one of the scan line and the data line group is partially overlapped with the spacer, and the spacer is disposed at the intersection of the first light shielding strip and the second light shielding strip.

[0031] In one embodiment, a third light-shielding portion is connected to both sides of the intersection of the first light-shielding strip and the second light-shielding strip; in the display panel viewed from a top-down perspective, the third light-shielding portion and portions of the first light-shielding strip and the second light-shielding strip respectively connected to the third light-shielding portion cover the spacer as a whole.

[0032] The array substrate of the present application includes a plurality of scan lines and a plurality of data line groups, wherein the plurality of data line groups are arranged along a first direction, the scan lines extend along the first direction (x), and the plurality of scan lines are arranged along a second direction (y) intersecting the first direction; the plurality of scan lines and the plurality of data line groups are cross-arranged to form a plurality of pixel areas; and a plurality of pixel electrode groups, wherein one pixel electrode group is correspondingly arranged in one pixel area, and the plurality of pixel electrode groups are arranged along the first direction to form pixel rows, wherein the pixel rows include a first type of pixel rows and a second type of pixel rows, and the first type of pixel rows and the second type of pixel rows are alternately arranged along the second direction; in the second direction, the The pixel electrode group of the first type of pixel row is correspondingly arranged between two adjacent pixel electrode groups of the second type of pixel row; wherein the pixel electrode group includes a first type of pixel electrode and a second type of pixel electrode, and the first type of pixel electrode and the second type of pixel electrode are alternately arranged in the first direction; the data line group includes a first type of data line and a second type of data line, and the first type of data line and the second type of data line are alternately arranged in the first direction; the first type of data line connects the second type of pixel electrode of the first type of pixel row and the first type of pixel electrode of the second type of pixel row, and the second type of data line connects the first type of pixel electrode of the first type of pixel row and the second type of pixel electrode of the second type of pixel row. Through the above scheme, there is no data line between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group, which greatly reduces the distance between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group, and although a data line is added between the pixel electrode groups, the small distance between the first data line and the second data line reduces the wiring area in the first direction to improve the aperture ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0034] Attached Figure 1 This is a schematic diagram of the structure of an optional array substrate in an embodiment of the present application;

[0035] Attached Figure 2 is a schematic cross-sectional structure diagram of an optional array substrate in an embodiment of the present application;

[0036] Attached Figure 3 is a schematic structural diagram of another optional array substrate in an embodiment of the present application;

[0037] Attached Figure 4 is a schematic cross-sectional structure diagram of another optional array substrate in an embodiment of the present application;

[0038] Attached Figure 5 This is a schematic diagram of the structure of an optional display panel in an embodiment of the present application;

[0039] Attached Figure 6 This is a schematic diagram of the structure of an optional light-shielding layer in an embodiment of the present application;

[0040] Attached Figure 7 Schematic diagram of the structure of two optional through holes in the second common electrode in the embodiments of the present application.

[0041] Description of reference numerals in the figures:

[0042] 1. display panel; 10. array substrate; 10a. pixel area; 20. black matrix layer; 21. first light shielding strip; 22. second light shielding strip; 22a. first light shielding portion; 22b. second light shielding portion; 22c. third light shielding portion; 30. spacer;

[0043] 100, scan line;

[0044] 200, data line group; 210, first type data line; 211, first routing section; 212, second routing section; 213, third routing section; 214, fourth routing section; 215, fifth routing section; 216, sixth routing section; 220, second type data line; 221, seventh routing section; 222, eighth routing section; 223, ninth routing section; 224, tenth routing section; 225, eleventh routing section; 226, twelfth routing section;

[0045] 300, pixel electrode group; 300a, first type pixel row; 300b, second type pixel row; 311, first type pixel electrode; 312, second type pixel electrode;

[0046] 400, thin film transistor group; 410, first thin film transistor; 420, second thin film transistor;

[0047] 500, public routing;

[0048] 600, first common electrode layer; 610, first common electrode;

[0049] 700, second common electrode layer; 700a, through hole; 710, second common electrode. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0051] It should be noted that the first direction x may be a direction parallel to one side of the array substrate 10 in a plan view, and may be, for example, a lateral direction of the array substrate 10. The second direction y may be a direction parallel to the other side of the array substrate 10 in a plan view, and may be a longitudinal direction of the array substrate 10. Optionally, in some embodiments, the first direction x and the second direction y may also be non-perpendicular to each other.

[0052] Optionally, the array substrate 10 may be based on a Fringe Field Switching (FFS) technology driving architecture or a High Transmission Fringe Field Switching (HFS) technology driving architecture, or may be based on an In-Plane Switching (IPS) technology driving architecture, or may be based on a Vertical Alignment (VA) technology or a Twisted Nematic (TN) driving architecture, etc. The following application embodiment will be described based on the array substrate 10 being a High Transmission Fringe Field Switching technology driving architecture.

[0053] Reference Figures 1 to 4 As shown, according to the first aspect of the present application, an array substrate 10 is provided, comprising:

[0054] A plurality of scan lines 100 and a plurality of data line groups 200, the plurality of data line groups 200 are arranged along a first direction, the scan lines 100 extend along the first direction (the positive direction of the x-axis in the figure), and the plurality of scan lines 100 are arranged along a second direction (the positive direction of the y-axis in the figure) intersecting the first direction; the plurality of scan lines 100 and the plurality of data line groups 200 are cross-arranged to form a plurality of pixel regions 10a; in some embodiments of the present application, each pixel region 10a is a dual-pixel domain region, and the first type of pixel electrode 311 and the second type of pixel electrode 312 respectively correspond to a pixel domain region.

[0055] A plurality of pixel electrode groups 300, one pixel electrode group 300 is correspondingly arranged in one pixel area 10a, the plurality of pixel electrode groups 300 are arranged along a first direction to form pixel rows, the pixel rows include first-type pixel rows 300a and second-type pixel rows 300b, the first-type pixel rows 300a and the second-type pixel rows 300b are alternately arranged along a second direction; in the second direction, the pixel electrode group 300 of the first-type pixel row 300a is correspondingly arranged between two adjacent pixel electrode groups 300 of the second-type pixel row 300b;

[0056] The pixel electrode group 300 includes a first type of pixel electrodes 311 and a second type of pixel electrodes 312, and the first type of pixel electrodes 311 and the second type of pixel electrodes 312 are alternately arranged in a first direction;

[0057] The data line group 200 includes a first type of data line 210 and a second type of data line 220, and the first type of data line 210 and the second type of data line 220 are arranged alternately in a first direction; the first type of data line 210 connects the second type of pixel electrode 312 of the first type of pixel row 300a and the first type of pixel electrode 311 of the second type of pixel row 300b, and the second type of data line 220 connects the first type of pixel electrode 311 of the first type of pixel row 300a and the second type of pixel electrode 312 of the second type of pixel row.

[0058] The array substrate 10 of the embodiment of the present application adopts a data line group 200 layout, so that there is no data line between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group 300, which greatly reduces the distance between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group 300. Although a data line is added between the pixel electrode groups 300, in the first direction, the distance between two data lines in the same data line group 200 is smaller than the distance from the data line to the nearest pixel electrode, that is, the distance between the first data line and the second data line is smaller, thereby reducing the wiring area in the first direction to improve the aperture ratio.

[0059] In some embodiments, the first data line and the second data line may also be arranged in different layers. In the first direction, the first data line and the second data line may be smaller, and even the first data line and the second data line may at least partially overlap, so as to further reduce the distance between the first data line and the second data line in the first direction F1 and improve the aperture ratio.

[0060] Reference Figure 1 and Figure 3In some more specific embodiments, the first type of data line 210 includes a first routing portion 211, a second routing portion 212, a third routing portion 213 and a fourth routing portion 214, a fifth routing portion 215 and a sixth routing portion 216, the first routing portion 211 and the second routing portion 212 are arranged in the first type of pixel row 300a, the fourth routing portion 214 and the fifth routing portion 215 are arranged in the second type of pixel row 300b, the third routing portion 213 and the sixth routing portion 216 are arranged between the first type of pixel row 300a and the second type of pixel row 300b, the third routing portion 213 is connected to the fourth routing portion 214 from one end of the second routing portion 212 in the reverse direction of the first direction, and the sixth routing portion 216 is connected to the first routing portion 211 from one end of the fifth routing portion 215 in the first direction; by setting the third routing portion 213 and the sixth routing portion 216, the layout area of ​​the two in the second direction can be reduced, and the aperture ratio can be improved.

[0061] The second type of data line 220 includes a seventh routing portion 221, an eighth routing portion 222, a ninth routing portion 223, a tenth routing portion 224, an eleventh routing portion 225 and a twelfth routing portion 226. The seventh routing portion 221 and the eighth routing portion 222 are arranged in the first type of pixel row 300a, the tenth routing portion 224 and the eleventh routing portion 225 are arranged in the second type of pixel row 300b, the ninth routing portion 223 and the twelfth routing portion 226 are arranged between the first type of pixel row 300a and the second type of pixel row 300b, the ninth routing portion 223 connects the eighth routing portion 222 and the tenth routing portion 224, and the twelfth routing portion 226 connects the eleventh routing portion 225 and the seventh routing portion 221. The sixth routing portion 216 and the twelfth routing portion 226 are arranged in the same manner, which will not be repeated here.

[0062] The first routing portion 211 and the second routing portion 212 are connected to the second type of pixel electrode 312 of the first type of pixel row 300a, the fourth routing portion 214 and the fifth routing portion 215 are connected to the first type of pixel electrode 311 of the second type of pixel row 300b, the seventh routing portion 221 and the eighth routing portion 222 are connected to the first type of pixel electrode 311 of the first type of pixel row 300a, and the ninth routing portion 223 and the tenth routing portion 224 are connected to the second type of pixel electrode 312 of the second type of pixel row 300b.

[0063] Among them, the first routing portion 211 and the seventh routing portion 221 are parallel to each other, the second routing portion 212 and the eighth routing portion 222 are parallel to each other, the fourth routing portion 214 and the tenth routing portion 224 are parallel to each other, and the fifth routing portion 215 and the eleventh routing portion 225 are parallel to each other; there is a first angle between the first routing portion 211 and the second routing portion 212, and there is a second angle between the fourth routing portion 214 and the fifth routing portion 215. It should be noted that due to the parallel relationship between some routing portions, there is also an angle between the corresponding routing portions, which will not be repeated here.

[0064] In some embodiments of the present application, the array substrate 10 also includes a plurality of thin film transistor groups 400, which are arranged between two adjacent pixel electrode groups 300 and located in the corner area of ​​the pixel electrode group 300, each thin film transistor group 400 includes a first thin film transistor 410 and a second thin film transistor 420, the control end of the first thin film transistor 410 and the control end of the second thin film transistor 420 are connected to the scan line 100, the input end of the first thin film transistor 410 is connected to the first type of data line 210, and the input end of the second thin film transistor 420 is connected to the second type of data line 220, in the first pixel row, the output end of the first thin film transistor 410 is connected to the second type of pixel electrode 312, and the output end of the second thin film transistor 420 is connected to the first type of pixel electrode 311; in the second pixel row, the output end of the first thin film transistor 410 is connected to the first type of pixel electrode 311, and the output end of the second thin film transistor 420 is connected to the second type of pixel electrode 312.

[0065] It can be understood that in the same thin film transistor group 400, a first thin film transistor 410 and a second thin film transistor 420 share a gate, that is, a first thin film transistor 410 and a second thin film transistor 420 are gathered side by side by sharing a gate to form the thin film transistor group 400, which reduces the total layout area of ​​the entire thin film transistor and thereby improves the aperture ratio.

[0066] Secondly, in the first direction, the first thin film transistor 410 and the second thin film transistor 420 are arranged side by side, which further reduces the layout area in the second direction and improves the aperture ratio.

[0067] Optionally, in some embodiments of the present application, the first thin film transistors 410 and the second thin film transistors 420 are alternately arranged in rows along the first direction; in each thin film transistor group 400, the first thin film transistor 410 is arranged on a side of the first type of data line 210 away from the second type of data line 220, and the second thin film transistor 420 is arranged on a side of the second type of data line 220 away from the first type of data line 210. It can be understood that by arranging the data line group 200 between two thin film transistors in the thin film transistor group 400, the distance between the first data line and the second data line in the data line group 200 is shortened, thereby improving the aperture ratio.

[0068] In some embodiments of the present application, the array substrate 10 further includes a common wiring 500 extending along a first direction. In the display panel 1 viewed from a top perspective, in a second direction, the common wiring 500 is arranged between two adjacent pixel domains.

[0069] Reference Figure 1 and Figure 2As shown, in some specific embodiments of the present application, multiple pixel electrode groups 300 are arranged in the same layer to form a pixel electrode layer, the array substrate 10 also includes a first common electrode layer 600 connected to the common wiring 500, the pixel electrode layer and the first common electrode layer 600 are arranged in different layers, the first common electrode layer 600 includes multiple first common electrodes 610, and a first common electrode 610 is correspondingly arranged in a pixel area 10a; in the array substrate 10 under a top view, a first common electrode 610 overlaps with a first type of pixel electrode 311 and a second type of pixel electrode 312 of the same pixel electrode group 300 at the same time; the first common electrode layer 600 is provided with a slit.

[0070] Reference Figure 3 and Figure 4 As shown, in some other specific embodiments of the present application, a plurality of pixel electrode groups 300 are arranged in the same layer to form a pixel electrode layer, and the array substrate 10 further includes a first common electrode layer 600 and a second common electrode layer 700 connected to the common wiring 500, the pixel electrode layer and the first common electrode layer 600 are arranged in different layers, and the pixel electrode layer and the second common electrode layer 700 are arranged in the same layer; the first common electrode layer 600 includes a plurality of first common electrodes 610, and a first common electrode 610 is correspondingly arranged in a pixel area 10a, and in the array substrate 10 under a top view angle, a first common electrode 610 overlaps with a first type of pixel electrode 311 and a second type of pixel electrode 312 of the same pixel electrode group 300 at the same time. The second common electrode layer 700 includes a plurality of second common electrodes 710, and in the array substrate 10 under a top view angle, a second common electrode 710 partially overlaps with a data line group 200; the second common electrode 710 is provided with at least one through hole 700a, and the through hole 700a is as shown in FIG. Figure 7 (a) and Figure 7 (b) shows that it can have a variety of shapes, which are not limited in this application; the pixel electrode layer is provided with a slit. In this embodiment, by setting the top pixel electrode and the double-layer common electrode structure, it is beneficial to reduce the capacitance between the pixel and the data line. It should be noted that this capacitance will cause the pixel signal to be coupled by the fluctuation of the data signal, resulting in vertical crosstalk.

[0071] In some embodiments of the present application, in the second direction, the first type of pixel electrodes 311 and the second type of pixel electrodes 312 are alternately arranged into pixel columns, and a plurality of pixel columns are arranged along the first direction, wherein, in the same picture frame, the voltage polarity connected to the first type of data line 210 is opposite to the voltage polarity connected to the second type of data line 220. For example, the first data line is connected to a positive polarity voltage, and the second data line is connected to a negative polarity voltage; or, the first data line is connected to a negative polarity voltage, and the second data line is connected to a positive polarity voltage.

[0072] It should be noted that since the first data line connects the second type of pixel electrode in the first pixel row and the first type of pixel electrode in the second pixel row, and the second data line connects the first type of pixel electrode in the first pixel row and the second type of pixel electrode in the second pixel row, the voltage polarities of the first type of pixel electrode and the second type of pixel electrode in the same pixel column are the same, and the voltage polarities of the first type of pixel electrode and the second type of pixel electrode in the same pixel row are opposite, thereby achieving a column flipping effect, reducing horizontal crosstalk and improving the display effect.

[0073] Reference Figure 5 As shown, according to the second aspect of the present application, a display panel 1 is provided, comprising an array substrate 10 and an opposing substrate arranged opposite to each other. The array substrate 10 is set to be the array substrate 10 of any of the above embodiments, that is, the display panel 1 also has all the technical features of all the embodiments of the above array substrate 10, and also has all the beneficial effects brought by all the technical features, which will not be described one by one here.

[0074] Reference Figure 6 As shown, in some embodiments of the present application, the opposing substrate includes a black matrix layer 20, and the black matrix layer 20 includes a first shading strip 21 and a second shading strip 22. The first shading strip 21 extends along the first direction, and the second shading strip 22 extends along the second direction. A plurality of first shading strips 21 and a plurality of second shading strips 22 are cross-connected to form a plurality of openings, some of the openings are facing the first type of pixel electrode, and another portion of the openings are facing the second type of pixel electrode; the second shading strip 22 includes a first shading portion 22a and a second shading portion 22b. In the first direction, the width of the first shading portion 22a is greater than the width of the second shading portion 22b. In the first direction, the first shading portion 22a and the second shading portion 22b are alternately arranged, and in the second direction, the first shading portion 22a and the second shading portion 22b are alternately connected and arranged; the wider first shading portion 22a and the narrower second shading portion 22b are alternately connected and arranged in the second direction, so that the edge of the second shading strip 22 in the second direction is non-linear, thereby reducing the risk of vertical stripes on the display panel 1. Optionally, both side edges of the second shading strip 22 in the second direction are non-linear to further reduce the risk of vertical stripes on the display panel 1. In addition, the wider first shading portion 22a and the narrower second shading portion 22b are alternately arranged in the first direction and the second direction, thereby improving the uniformity of the display.

[0075] In the display panel 1 in a top view, the first light shielding strip 21 covers the scan line 100, the second wiring portion 212 and the fifth wiring portion 215, the first light shielding portion 22a covers the portion of the data line group 200 between two adjacent groups of pixel electrode groups 300 in the first direction, and the second light shielding portion 22b covers the area between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group 300. Since the data line group 200 is arranged between two adjacent pixel electrode groups 300 in the first direction, the distance between the adjacent pixel electrode groups 300 is large, while the distance between the two pixel electrodes in the same pixel electrode group 300 is small, therefore, based on the consideration of the maximum aperture ratio, the width of the first light shielding portion 22a is greater than the width of the second light shielding portion 22b. Furthermore, since the width of the first light shielding portion 22a is greater than the width of the second light shielding portion 22b, the edge of the second light shielding strip 22 in the second direction is non-linear, thereby reducing the risk of vertical stripes on the display panel 1 and improving the uniformity of display.

[0076] Correspondingly, the display panel 1 further includes a plurality of spacers 30, and the spacers 30 are disposed between the first type pixel row 300a and the second type pixel row 300b; Figure 1 and Figure 3 As shown, in the display panel 1 in a top-down perspective, at least one of the scan line 100 and the data line group 200 is arranged to overlap with a portion of the spacer 30, and the spacer 30 is arranged at the intersection of the first light shielding strip 21 and the second light shielding strip 22. In some embodiments, the third light shielding portion 22c is connected to both sides of the intersection of the first light shielding strip 21 and the second light shielding strip 22; in the display panel 1 in a top-down perspective, the third light shielding portion 22c and the first light shielding strip 21 and the second light shielding strip 22 connected to the third light shielding portion 22c respectively cover a spacer 30 as a whole. It can be understood that the first light shielding portion 22a covers the middle area of ​​the spacer 30, and the third light shielding portion 22c covers the two side areas of the spacer 30, so that the first light shielding portion 22a and the third light shielding portion 22c cover the entire spacer 30. Secondly, since the third light shielding portion 22 c is connected to both sides of the first light shielding portion 22 a , the edge of the second light shielding strip 22 in the second direction is more uneven, thereby reducing the risk of vertical lines on the display panel 1 .

[0077] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. An array substrate, characterized in that: include: A plurality of scan lines and a plurality of data line groups, wherein the plurality of data line groups are arranged along a first direction, the scan lines extend along the first direction, and the plurality of scan lines are arranged along a second direction intersecting the first direction; the plurality of scan lines and the plurality of data line groups are intersected to form a plurality of pixel regions; as well as A plurality of pixel electrode groups, one of the pixel electrode groups is correspondingly arranged in one of the pixel regions, the plurality of pixel electrode groups are arranged along the first direction to form pixel rows, the pixel rows include first-type pixel rows and second-type pixel rows, the first-type pixel rows and the second-type pixel rows are alternately arranged along the second direction; in the second direction, the pixel electrode groups of the first-type pixel rows are correspondingly arranged between two adjacent pixel electrode groups of the second-type pixel rows; The pixel electrode group includes a first type of pixel electrodes and a second type of pixel electrodes, and the first type of pixel electrodes and the second type of pixel electrodes are alternately arranged in the first direction.

2. The array substrate according to claim 1, characterized in that: The data line group includes a first type of data lines and a second type of data lines, and the first type of data lines and the second type of data lines are alternately arranged in a first direction; the first type of data lines connect the second type of pixel electrodes of the first type of pixel rows and the first type of pixel electrodes of the second type of pixel rows, and the second type of data lines connect the first type of pixel electrodes of the first type of pixel rows and the second type of pixel electrodes of the second type of pixel rows.

3. The array substrate according to claim 2, characterized in that: The first type of data line comprises a first routing portion, a second routing portion, a third routing portion, a fourth routing portion, a fifth routing portion and a sixth routing portion, the first routing portion and the second routing portion are arranged in the first type of pixel row, the fourth routing portion and the fifth routing portion are arranged in the second type of pixel row, the third routing portion and the sixth routing portion are arranged between the first type of pixel row and the second type of pixel row, the third routing portion is connected to the fourth routing portion from one end of the second routing portion in the reverse direction of the first direction, and the sixth routing portion is connected to the first routing portion from one end of the fifth routing portion in the first direction; The second-category data line includes a seventh routing portion, an eighth routing portion, a ninth routing portion, a tenth routing portion, an eleventh routing portion and a twelfth routing portion, the seventh routing portion and the eighth routing portion are arranged in the first-category pixel row, the tenth routing portion and the eleventh routing portion are arranged in the second-category pixel row, the ninth routing portion and the twelfth routing portion are arranged between the first-category pixel row and the second-category pixel row, the ninth routing portion connects the eighth routing portion and the tenth routing portion, and the twelfth routing portion connects the eleventh routing portion and the seventh routing portion; The first routing portion and the second routing portion are connected to the second type of pixel electrodes of the first type of pixel rows, the fourth routing portion and the fifth routing portion are connected to the first type of pixel electrodes of the second type of pixel rows, the seventh routing portion and the eighth routing portion are connected to the first type of pixel electrodes of the first type of pixel rows, and the ninth routing portion and the tenth routing portion are connected to the second type of pixel electrodes of the second type of pixel rows.

4. The array substrate according to claim 3, characterized in that: The first routing portion and the seventh routing portion are parallel to each other, the second routing portion and the eighth routing portion are parallel to each other, the fourth routing portion and the tenth routing portion are parallel to each other, and the fifth routing portion and the eleventh routing portion are parallel to each other; A first angle is formed between the first routing portion and the second routing portion, and a second angle is formed between the fourth routing portion and the fifth routing portion.

5. The array substrate according to claim 4, characterized in that: The array substrate further comprises a plurality of thin film transistor groups, wherein the thin film transistor groups are arranged between two adjacent pixel electrode groups and located in a corner area of ​​the pixel electrode groups, each of the thin film transistor groups comprises a first thin film transistor and a second thin film transistor, a control end of the first thin film transistor and a control end of the second thin film transistor are connected to the scan line, an input end of the first thin film transistor is connected to the first type of data line, an input end of the second thin film transistor is connected to the second type of data line, and in the first pixel row, an output end of the first thin film transistor is connected to the second type of pixel electrode, and an output end of the second thin film transistor is connected to the first type of pixel electrode; In the second pixel row, the output end of the first thin film transistor is connected to the first type of pixel electrode, and the output end of the second thin film transistor is connected to the second type of pixel electrode; Among them, the first thin film transistors and the second thin film transistors are alternately arranged in rows along the first direction; in each of the thin film transistor groups, the first thin film transistors are arranged on a side of the first type of data line away from the second type of data line, and the second thin film transistors are arranged on a side of the second type of data line away from the first type of data line.

6. The array substrate according to claim 5, characterized in that: Each of the pixel areas is a dual-pixel domain area, and the first-type pixel electrode and the second-type pixel electrode correspond to one pixel domain area respectively.

7. The array substrate according to claim 6, characterized in that: The array substrate further includes a common wiring, which is extended along the first direction. In the array substrate viewed from a top view, the common wiring is arranged between two adjacent pixel domains in the second direction.

8. The array substrate according to claim 7, characterized in that: The plurality of pixel electrode groups are arranged in the same layer to form a pixel electrode layer, the array substrate further comprises a first common electrode layer connected to the common wiring, the pixel electrode layer and the first common electrode layer are arranged in different layers, the first common electrode layer comprises a plurality of first common electrodes, and one of the first common electrodes is arranged in a corresponding pixel region; In the array substrate in a top view, a first common electrode overlaps with a first type of pixel electrode and a second type of pixel electrode of the same pixel electrode group; The first common electrode layer is provided with slits.

9. The array substrate according to claim 7, characterized in that: The plurality of pixel electrode groups are arranged in the same layer to form a pixel electrode layer, the array substrate further comprises a first common electrode layer and a second common electrode layer connected to the common wiring, the pixel electrode layer and the first common electrode layer are arranged in different layers, and the pixel electrode layer and the second common electrode layer are arranged in the same layer; The first common electrode layer includes a plurality of first common electrodes, one of the first common electrodes is disposed in a corresponding pixel region, and in the array substrate in a top view, one of the first common electrodes overlaps with the first type of pixel electrode and the second type of pixel electrode of the same pixel electrode group at the same time; The second common electrode layer includes a plurality of second common electrodes, and in the array substrate in a top view, one of the second common electrodes partially overlaps with the data line group; At least one through hole is provided on the second common electrode; The pixel electrode layer is provided with slits.

10. The array substrate according to claim 8 or 9, characterized in that: In the second direction, the first type of pixel electrodes and the second type of pixel electrodes are alternately arranged into pixel columns, and a plurality of the pixel columns are arranged along the first direction, wherein, in the same picture frame, the voltage polarity connected to the first type of data line is opposite to the voltage polarity connected to the second type of data line.

11. A display panel, characterized in that: It comprises the array substrate according to any one of claims 1 to 10 and an opposing substrate arranged opposite to the array substrate.

12. The display panel according to claim 11, characterized in that: The counter substrate comprises a black matrix layer, the black matrix layer comprises a first light shielding strip and a second light shielding strip, the first light shielding strip extends along the first direction, the second light shielding strip extends along the second direction, a plurality of the first light shielding strips and a plurality of the second light shielding strips are cross-connected to form a plurality of openings, some of the openings are facing the first type of pixel electrode, and another part of the openings are facing the second type of pixel electrode; The second light shielding strip includes a first light shielding portion and a second light shielding portion. In the first direction, the width of the first light shielding portion is greater than the width of the second light shielding portion. In the first direction, the first light shielding portion and the second light shielding portion are alternately arranged. In the second direction, the first light shielding portion and the second light shielding portion are alternately connected. In the display panel viewed from a top-down perspective, the first shading strip covers the scan line, the second routing portion and the fifth routing portion, the first shading portion covers the portion of the data line group between two adjacent groups of pixel electrode groups in the first direction, and the second shading portion covers the area between the first type of pixel electrodes and the second type of pixel electrodes in the pixel electrode group.

13. The display panel according to claim 12, characterized in that: The display panel further comprises a plurality of spacers, wherein the spacers are arranged between the first type pixel row and the second type pixel row; In the display panel viewed from a top view, at least one of the scan line and the data line group is partially overlapped with the spacer, and the spacer is disposed at the intersection of the first light shielding strip and the second light shielding strip.

14. The display panel according to claim 13, characterized in that: A third shading portion is connected to both sides of the intersection of the first shading strip and the second shading strip; in the display panel viewed from a top view, the third shading portion and the portions of the first shading strip and the second shading strip respectively connected to the third shading portion cover the spacer as a whole.

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