Digital silicon photomultiplier

Abstract

The invention discloses a digital silicon photomultiplier and application thereof, and relates to the field of data processing. The digital silicon photomultiplier comprises a pixel array, the pixel array comprises a plurality of pixel groups, each pixel group comprises two or more pixels, each pixel group outputs data through an independent bus, and the pixels are configured to detect visible light photons; and the data reading circuit is connected with all the pixel groups, and the data reading circuit is configured to obtain digital counting pulses according to output data of the pixel groups and count counting data. According to the photon counting data reading method and device, the pixel arrays are grouped for data reading, and different from an existing mode of reading through one bus and a micro-cell / TDC array, the photon counting data reading method and device can balance high-speed reading processing of photon counting data and system power consumption.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a digital silicon photomultiplier. Background Art

[0002] Analog silicon photomultipliers (SiPMs) convert light signals into scintillation pulses by summing the avalanche current output by each microcell (MC) at a node, and can directly use a single time-to-digital converter (TDC) to sample the scintillation pulses to extract the timestamp of the pulse event. In contrast, in digital SiPMs, each MC outputs a digital signal, and the digital outputs of all MCs are sent to the TDC for sampling through OR logic to obtain the timestamp. Under this architecture, the first digital SiPM chip was proposed by Thomas Frach et al. in 2009. The chip integrates MC, TDC and photon counters, each MC is connected to a separate transistor for active quenching, and is connected to the TDC through a configurable trigger network to obtain the time information of the event, and all MCs are connected to the counter through a separate synchronous bus to collect the number of MCs triggered during the event as the energy information of the event.

[0003] After that, Philips used this architecture to design a commercial digital SiPM named Digital Photon Counter (DPC). Seifert et al. used Philips' DPC to demonstrate the performance potential of digital SiPM in TOF-PET (Time Of Flight- Positron Emission Computed Tomography) detectors. A single DPC consists of a 2×2 pixel block array, TDC and trigger control module, and a single pixel block integrates 4 sub-pixel block arrays. For the trigger logic, DPC provides 4 different trigger count thresholds from high to low selected according to the number of sub-pixel blocks triggered. When the chip reaches the trigger count threshold and is triggered, it enters the verification logic. The MC array of each sub-pixel block is divided into multiple verification areas. Under this logic, the trigger event is verified to be a dark pulse or a real pulse event by logically connecting different verification areas. When the verification condition is not met, it is directly reset to wait for the next event to arrive. If the verification condition is met, it directly enters the chip acquisition state. After the acquisition is completed, the collected time and energy information are output. The single readout time of the chip is 680ns, and the event data is transmitted at a rate of 200Mbit / s through two synchronous serial links. Since the overall architecture is relatively simple and the composition of the output data is relatively simple, the data that needs to be output is relatively small, and the pressure on data transmission is not great. However, the processing method of first identifying and then acquiring is adopted, and the verification logic is relatively complex, which leads to many events being screened out before data acquisition, limiting the counting rate of SiPM. At the same time, under this architecture, it is still affected by saturation, crosstalk, and dark counts, and the response to energy information is similar to that of analog SiPM; for time information, each flashing event only records a timestamp based on the trigger count threshold, which is more similar to a semi-digital SiPM.

[0004] Different from the architecture proposed by Frach, in 2011, the digital SiPM proposed by Veerappan is more similar to an image sensor. It borrows the concept of CMOS image sensor. Each individual MC is integrated with a corresponding processing module. The digital SiPM contains a 160×128 MC array, and each individual MC is integrated with an independent 10-bit wide TDC. There is a serial output interface at the top and bottom of each column. The 10-bit information of each pixel is output in parallel by column through a total of 320 independent serial interfaces. The maximum parallel working rate of all interfaces is 160Mbit / s. Due to the large number of TDCs occupying most of the available area on the chip, the achievable fill factor is only less than 20%, the chip data readout time is greater than 4 microseconds, and the overall system power consumption is as high as 550 milliwatts.

[0005] It can be found that both the existing analog SiPM and digital SiPM have some drawbacks. On the one hand, due to the large parasitics of on-chip interconnects, bonding wires and external loads, the good inherent performance of the SPAD is not fully utilized, and the generated signal will deteriorate; on the other hand, it is highly sensitive to electronic noise and temperature changes. The existing digital SiPM architecture, which connects the pixel array to the counter and TDC photon counting digitization architecture by bus, is difficult to process photon counting data at a high speed; and the digital SiPM using micro-unit / TDC array improves the time performance, but the detection efficiency is low and the system power consumption is high.

[0006] The content of the background technology description is only for facilitating understanding of the relevant technology in this field and is not regarded as an admission of the prior art. Summary of the invention

[0007] Therefore, the present application intends to provide a digital silicon photomultiplier that can achieve high-speed and accurate readout of pulse event information with ideal circuit power consumption.

[0008] The present application provides a digital silicon photomultiplier, the digital silicon photomultiplier comprising: A pixel array, the pixel array comprising a plurality of pixel groups, each of the pixel groups comprising two or more pixels, each of the pixel groups outputting data via an independent bus, the pixels being used to detect visible light photons; A data readout circuit is connected to all the pixel groups through a plurality of the buses, and is used to obtain digital counting pulses and count counting data according to output data of the pixel groups.

[0009] In the embodiment of the present application, the number of pixels in all the pixel groups is the same.

[0010] In an embodiment of the present application, the pixel array includes a first pixel array and a second pixel array, the first pixel array and the second pixel array each include a plurality of pixel groups, and the first pixel array and the second pixel array are respectively connected to one of the data readout circuits.

[0011] In the embodiment of the present application, the first pixel array and the second pixel array include the same number of pixel groups, and the same number of pixels in each of the pixel groups.

[0012] In an embodiment of the present application, the data readout circuit reads out the data of the pixel group in a hierarchical manner in a cascade manner. The data readout circuit includes at least two stages of circuits, and the amount of input data of each stage of the circuit is greater than the amount of output data.

[0013] In the embodiment of the present application, the size of input data of each stage of circuit is larger than the size of output data.

[0014] In an embodiment of the present application, the readout circuit includes a first-level circuit, a second-level circuit and a third-level circuit connected in sequence.

[0015] In an embodiment of the present application, the first-level circuit is connected to all the pixel groups, the first-level circuit is configured to sum the data of each pixel group and output multiple first-level outputs including weights, the second-level circuit is configured to sum the first-level outputs with the same weights and output multiple second-level outputs including weights, and the third-level circuit is configured to sum the second-level outputs with the same weights and obtain the number of the triggered pixel groups to obtain counting data.

[0016] In an embodiment of the present application, the digital silicon photomultiplier also includes: a comparator, which is connected to the data readout circuit and configured to compare the counting data of the data readout circuit with a preset counting threshold, and the comparator flips when the counting data crosses the corresponding counting threshold.

[0017] In an embodiment of the present application, the digital silicon photomultiplier further includes: a time-to-digital converter, which is connected to the comparator and configured to measure the time difference between the flip time of the comparator and a clock signal.

[0018] In an embodiment of the present application, the time-to-digital converter includes a resolution control module and a measurement module, the resolution control module is configured to output a control voltage to the measurement module, the measurement module is configured to maintain the same state as the resolution control module according to the control voltage, and to process the output of the comparator and generate the time difference.

[0019] In an embodiment of the present application, the resolution control module includes a first-stage delay phase-locked loop and a second-stage delay phase-locked loop. An anti-error locking structure is arranged in the first-stage delay phase-locked loop. The second-stage delay phase-locked loop completes locking and fine time precision control based on the reference signal generated by the anti-error locking structure.

[0020] In an embodiment of the present application, the measurement module includes a vernier delay chain and a decision circuit, the vernier delay chain is configured to maintain the same state as the resolution control module according to the control voltage and receive the flip time of the comparator and the clock signal, and the decision circuit is configured to process the flip time of the comparator and the clock signal to obtain the time difference.

[0021] In an embodiment of the present application, the digital silicon photomultiplier also includes a power management module, which is configured to use different low-voltage difference linear regulators to adjust the power supply according to the current, power consumption changes and multi-power requirements of different functional modules in the digital silicon photomultiplier to achieve different power supply to different functional modules.

[0022] In an embodiment of the present application, the low-dropout linear regulator includes a main-pole-compensated low-dropout linear regulator and a capacitor-free regulator. The main-pole-compensated low-dropout linear regulator is configured to adjust the power supply for the readout circuit, and the capacitor-free regulator is configured to adjust the power supply for the time-to-digital converter.

[0023] In an embodiment of the present application, the time-to-digital converter further includes a control voltage selector, which is configured to select from an external control voltage and a control voltage output by the resolution control module, and output the result to the measurement module.

[0024] In the embodiment of the present application, when the resolution control module is in a normal state, the control voltage selector uses the control voltage output by the resolution control module as the output; otherwise, the control voltage selector uses the external control voltage as the output.

[0025] In the embodiment of the present application, the measurement module includes a plurality of measurement channels, and the data processed by each measurement channel corresponds to a different counting threshold.

[0026] In an embodiment of the present application, the time-to-digital converter further includes a signal selector, and the signal selector is configured to transmit the signal to be measured to a corresponding measurement channel.

[0027] In an embodiment of the present application, the digital silicon photomultiplier further includes: a data packaging module, which is connected to the time-to-digital converter and is configured to decode, identify, package, combine coarse counting codes, compress and output the output of the time-to-digital converter to the outside.

[0028] In an embodiment of the present application, the data packaging module includes: a data processing module and a counter, the data processing module is configured to decode, identify, package, combine coarse counting codes, compress and output to the outside the output of the time-to-digital converter, and the counter is configured to provide the coarse counting code.

[0029] In an embodiment of the present application, the data processing module includes a first frame and a second frame, the first frame is configured to decode the output of the time-to-digital converter, and the second frame is configured to identify the decoded data, and pack the data, combine the coarse counting code, compress and output it to the outside.

[0030] In the embodiment of the present application, the second frame opens a time window of a first predetermined size when detecting that the digital count pulse crosses the lowest count threshold, and detects whether the highest count threshold of the rising edge of the digital count pulse is reached within the time window; If not, the event corresponding to the digital count pulse is deemed to be an invalid event; If so, the falling edge acquisition phase is entered, the data of the rising edge of the digital count pulse is latched, a second predetermined time window is opened, and it is detected whether the minimum counting threshold of the falling edge of the digital count pulse is reached. If it is reached, the event corresponding to the digital count pulse is determined to be a valid event.

[0031] The digital silicon photomultiplier provided in the present application can strike a balance between high-speed readout processing of photon counting data and system power consumption, can read out the photon counting data of the entire array in real time, avoids the introduction of a large number of TDCs, can obtain a higher count rate and time resolution, has high data processing efficiency, and simultaneously realizes decoding, error detection, and TDC state detection functions, realizes the function of completing the screening of effective pulse events and extracting effective information on the photomultiplier chip, solves the problem of effective event loss when setting a lower counting threshold, and is of great significance for optimizing the time resolution of the digital SiPM.

[0032] Part of the optional features and other effects of the embodiments of the present application are described below, and part of them can be understood by reading this document. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present application will be further described in the form of exemplary embodiments, which will be described in detail by the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same reference numerals represent the same structure, wherein: Figure 1 The structure diagram of the digital silicon photomultiplier according to the embodiment of the present application is shown; Figure 2The structure diagram of the digital silicon photomultiplier according to the specific embodiment of the present application is shown; Figure 3 A schematic diagram of an interface circuit according to an embodiment of the present application is shown; Figure 4 shows an architecture diagram of a data readout circuit according to a specific embodiment of the present application; Figure 5 A schematic diagram of a time-to-digital converter according to an embodiment of the present application is shown; Figure 6 A schematic diagram of a power management module according to an embodiment of the present application is shown; Figure 7 A schematic diagram of a power management module according to a specific embodiment of the present application is shown; Figure 8 A schematic diagram of a power management module according to another specific embodiment of the present application is shown; Fig. 9 A schematic diagram of a data packaging module according to an embodiment of the present application is shown; Fig.10 A first frame timing diagram of a data packaging module according to an embodiment of the present application is shown; Fig.11 A schematic diagram showing a second frame of a data packaging module according to a specific embodiment of the present application is shown; Fig.12 is a second frame timing diagram of a data packaging module according to an embodiment of the present application; Fig.13 A schematic diagram of a second frame state machine of a data packaging module according to an embodiment of the present application is shown; Fig.14 A schematic diagram of a second frame state machine of a data packaging module according to a specific embodiment of the present application is shown; Fig.15 A schematic diagram showing a second frame of a data packaging module according to a specific embodiment of the present application is shown; Fig.16 A timing diagram of a data conversion module of a second frame of a data packaging module according to a specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0035] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on another element or there may also be a centered element. When an element is considered to be "connected" to another element, it may be directly connected to another element or there may be a centered element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for illustrative purposes. The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical solution of the present application can be practiced without one or more of these specific details, or other modes, components, materials, devices or operations, etc. may be adopted. In these cases, known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0036] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0037] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The term "and / or" or "and / or" includes any and all combinations of one or more related listed items.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] As mentioned above, among the technologies known to the inventors, digital SiPM shows great development potential in pulse event detection, and has higher detection performance and efficiency than analog SiPM. However, existing digital SiPM has problems such as difficulty in high-speed processing of photon counting data, low detection efficiency, and high system power consumption.

[0040] In this regard, the present application provides a digital SiPM. The digital SiPM can be applied in multiple fields, for example, scientific instruments, medical equipment, high-energy physics, deep space and deep sea exploration, extremely weak light imaging, radiation monitoring, automatic driving, security inspection equipment, consumer electronics or smart home appliances, etc. Taking medical equipment as an example, it can be applied in PET equipment. In this scenario, the digital SiPM, scintillation crystals and some electronic devices together constitute a detector. The front end of the digital SiPM is coupled with a scintillation crystal. After the scintillation crystal receives the 511keV Gamma ray, it converts it into visible light photons and outputs it to the digital SiPM, which performs a series of processing on the visible light photons and then outputs them. The digital SiPM can be integrated with an MC array, a data readout circuit, a comparator, a TDC, etc. When a pulse event occurs, the visible light photons are detected by the MC array and converted into digital counting pulses via a digital interface circuit. The data readout circuit counts the counting data of the digital counting pulses of all MC arrays and compares them with the preset counting threshold in the comparator. TDC records the time point when all counting data crosses the counting threshold, and decodes it through the data packaging module to obtain all the "counting threshold-time" information pairs of the event.

[0041] Figure 1 FIG. 1 shows an architecture diagram of a digital SiPM according to an embodiment of the present application. In order to more clearly demonstrate the digital SiPM provided by the present application, Figure 1 For explanation. A digital SiPM generally includes: a pixel array 100 and a data readout circuit 200. The pixel array 100 includes a plurality of pixel groups 110, each of the pixel groups 110 includes two or more pixels 111, each of the pixel groups 110 outputs data via an independent bus, and the pixels 111 are configured to detect visible light photons, and can convert visible light photons into digital counting pulses. Originally, the information output by each pixel 111 needs to be read out, and the present application simplifies this method to read out all pixels 111 in a pixel group only once, which can reduce the amount of data in the readout circuit and increase the readout rate.

[0042] The pixel array 100 may include a×b pixels 111, wherein a and b are both integers greater than 2, and in one example, a and b are both 80. The pixel group 110 includes c×d pixels 111, wherein c and d are both integers greater than 1, and at least one of c and d is greater than or equal to 2. It can be understood that, in some examples, all the pixel groups 110 constitute the pixel array 100, and in other examples, one or some pixels 111 output data individually, not in the form of a pixel group 110, while other pixels 111 are grouped in a specific manner to form the pixel group 110, and all pixels 111 that output data individually and all pixel groups 110 together constitute the pixel array 100, and the number of pixels 111 included in each pixel group 110 may be the same or different. Generally speaking, pixels 111 where visible light photons are relatively concentrated can be set to output data individually, and pixels 111 where visible light photons are relatively sparse can be set to output data together in pixel groups 110, thereby improving data processing efficiency and reducing data loss. Alternatively, pixels 111 where visible light photons are relatively concentrated can be set to output data in pixel groups 110 composed of relatively fewer pixels (each pixel group 110 includes relatively fewer pixels 111), and pixels 111 where visible light photons are relatively sparse can be set to output data together in pixel groups 110 composed of relatively more pixels (each pixel group 110 includes relatively more pixels 111).

[0043] The data readout circuit 200 is connected to all the pixel groups 110, and is configured to obtain digital count pulses and count the count data according to the output data of the pixel groups 110. It can be understood that when there are pixels 111 that output data individually, the data readout circuit 200 is also connected to all pixels 111 that output data individually, and obtains digital count pulses and counts the count data according to the output data of all pixels 111 that output data individually and all pixel groups 110.

[0044] In one example, in order to reduce the complexity of the system, the number of pixels 111 in all the pixel groups 110 is set to be the same. Figure 2 FIG. 2 shows an architecture diagram of a digital silicon photomultiplier according to a specific embodiment of the present application. Figure 2 As shown, exemplarily, when the pixel array 100 includes 80×80 pixels 111, all pixels 111 are evenly divided into 40×40 pixel groups 110, one pixel group 110 may also be called a block, one pixel 111 may also be called an MC, and 2×2 MCs are allocated to each block.

[0045] In one example, in order to increase the data processing speed, two data readout circuits 200 are provided, the pixel array 100 includes a first pixel array 100 and a second pixel array 100, the first pixel array 100 and the second pixel array 100 each include a plurality of pixel groups 110, and the first pixel array 100 and the second pixel array 100 are respectively connected to one data readout circuit 200. Of course, it can be understood that when two data readout circuits 200 still cannot meet the requirements of the data processing speed, the number of data readout circuits 200 can be increased, but since the more the number of data readout circuits 200, the higher the complexity of the system structure, a balance should be struck between the two.

[0046] Exemplarily, the pixel array 100 is evenly divided into two parts, the upper and lower parts, both parts of the pixel array 100 include 40×80 pixels 111, the first pixel array 100 (the upper pixel array 100) corresponds to one data readout circuit 200, and the second pixel array 100 (the lower pixel array 100) corresponds to another data readout circuit 200.

[0047] Furthermore, in one example, the first pixel array 100 and the second pixel array 100 include the same number of pixel groups 110, and the same number of pixels 111 in each pixel group 110. For subsequent data processing logic, such a setting makes the data processing logic simpler.

[0048] Preferably, in an example of the present application, the digital silicon photomultiplier further includes an interface circuit 700 , and the interface circuit 700 is connected between the pixel 111 and the data readout circuit 200 .

[0049] Figure 3 FIG. 1 shows a schematic diagram of an interface circuit according to an embodiment of the present application. Figure 3 As shown, the interface circuit 700 includes a photoelectric device SPAD 710, a quenching unit 720, a comparison unit circuit 730, etc. The main body of the photoelectric device SPAD 710 includes a shallow P+ / N junction for blue light detection and a guard ring around the PN junction, and a custom layer is added to improve dark noise. The function of the photoelectric device SPAD 710 is to realize weak light detection and convert the optical signal into an electrical signal. The quenching unit 720 mainly adopts an NMOS tube, and its function is to complete the quenching / resetting of the photoelectric device SPAD 710, maintain the normal detection work of the photoelectric device SPAD 710, and receive the avalanche current of the photoelectric device SPAD 710, and convert it into an analog voltage signal output. In practical applications, the dead time, response speed, pulse width and other parameters of the output analog pulse can be flexibly adjusted by adjusting the width-to-length ratio and gate voltage of the quenching unit 720.

[0050] Preferably, in an example of the present application, the data readout circuit 200 uses a cascaded manner to hierarchically read out the data of the pixel group 110. The cascaded manner can reduce the amount of data step by step, and the amount of input data of each level of circuit is greater than the amount of output data, and the size of input data of each level of circuit is greater than the size of output data, so that the real-time readout of the photon counting data of the entire array can be achieved, avoiding the introduction of a large number of TDCs.

[0051] Figure 4 FIG. 4 shows an architecture diagram of a data readout circuit according to a specific embodiment of the present application. Figure 4 As shown, the readout circuit includes a first-stage circuit 210, a second-stage circuit 220 and a third-stage circuit 230 connected in sequence. The amount of input data of each stage circuit is greater than the amount of output data, and the size of input data of each stage circuit is greater than the size of output data. The three-stage circuit enables real-time readout of the photon counting data of the entire array, avoiding the introduction of a large number of TDCs.

[0052] Further, the first-stage circuit 210 is connected to all the pixel groups 110, and the first-stage circuit 210 is configured to sum the data of each pixel group 110 and output a plurality of first-stage outputs including weights, the second-stage circuit 220 is configured to sum the first-stage outputs with the same weights and output a plurality of second-stage outputs including weights, and the third-stage circuit 230 is configured to sum the second-stage outputs with the same weights and obtain the number of the triggered pixel groups 110. As an example, continue to refer to Figure 3The first stage circuit 210 is composed of 20 40-4 compressors (where 40-4 means that 40 pixel inputs are compressed into a 4-bit binary number), which convert the number of high levels in the output signal of the pixel group 110 into a 4-bit binary number, and output four signals B, C, D, and E. Each signal represents a different weight, for example, the weight of B is 2, the weight of C is 4, the weight of D is 8, and the weight of E is 16. The output of the first stage circuit 210 is equal to the number of high levels in the input. For example, if there are 10 high levels in the 40 inputs, 1010 is output, and if there are 6 high levels, 0110 is output. The second stage circuit 220 is composed of 4 20-4 compressors (where 20-4 means that 20 first-stage inputs are compressed into a 4-bit binary number), each of which converts the signal of the same weight bit in the first stage into a new 4-bit binary number, and counts the number of the weights. The third stage circuit 230Adder_8bits adds the four 4-bit binary outputs of the second stage into an 8-bit binary number according to the corresponding weights, and completes the addition of the count data between different columns. This result represents the number of all triggered pixel groups 110 in the pixel array 100 in a pulse width event. In the multi-count threshold sampling method, the 8-bit count data of the data readout circuit 200 can be compared with the preset count threshold in the comparator to obtain the count-time sampling point of this pulse event.

[0053] Further, in one example of the present application, see Figure 1 and Figure 2 The digital silicon photomultiplier further includes: a comparator 300, which is connected to the data readout circuit 200 and configured to compare the counting data of the data readout circuit 200 with a preset counting threshold, and flips when the counting data crosses the preset counting threshold.

[0054] Further, in one example of the present application, see Figure 1 and Figure 2 The digital silicon photomultiplier also includes: a time-to-digital converter 400, which is connected to the comparator 300 and configured to record the time corresponding to the flip, measure the time difference between the flip time of the comparator 300 and the clock signal, so as to obtain the count-time sampling point of the pulse event.

[0055] Figure 5 FIG. 2 shows a schematic diagram of a time-to-digital converter according to an embodiment of the present application. Figure 5As shown, in one example of the present application, the time-to-digital converter 400 includes a resolution control module 410 and a measurement module 420, the resolution control module 410 is configured to output a control voltage to the measurement module 420, the measurement module 420 is configured to maintain the same state as the resolution control module 410 according to the control voltage, and is also configured to process the output of the comparator 300 and generate the time difference.

[0056] Further, see Figure 5 The resolution control module 410 includes a first-stage delay phase-locked loop 411 and a second-stage delay phase-locked loop 412. The first-stage delay phase-locked loop 411 is provided with an anti-error locking structure. The second-stage delay phase-locked loop 412 completes locking and fine time precision control according to the reference signal generated by the anti-error locking structure. The second-stage delay phase-locked loop 412 includes a plurality of vernier delay chains, and the vernier delay chains include an intermediate tap. The first-stage delay phase-locked loop 411 can also be called a coarse precision module, and the second-stage delay phase-locked loop 412 can also be called a fine precision module. The fine precision module is arranged at the rear end of the coarse precision module, and both receive clock signals. As an example but not limitation, the first-stage delay phase-locked loop 411 can be driven by a 100MHz clock, with a built-in error-proof lock structure, which can make the delay of 16 delay units a clock cycle (the size of a clock cycle is, for example, 10ns), and the delay of each delay unit is 10ns / 16=625ps. At the same time, 16 reference signals with a phase difference of 625ps are generated in the link, and control voltages VC_dll and VF_dll are output. The reference signal and the control voltage are both output to the second-stage delay phase-locked loop 412. As an example but not limitation, the second-stage delay phase-locked loop 412 is driven by the reference signal to complete locking. The second-stage delay phase-locked loop 412 includes 16 vernier delay chains, each of which can obtain a delay of 625ps / 16=39ps. Since the vernier delay chain includes an intermediate tap, a signal with an accuracy of about 20ps can be obtained at most, and control voltages VC_vdl, VF_vdl, and VD_vdl are output.

[0057] Further, the measurement module 420 includes a vernier delay chain and a decision circuit, the vernier delay chain is configured to maintain the same state as the resolution control module 410 according to the control voltage and receive the flip time of the comparator 300 and the clock signal, and the decision circuit is configured to process the flip time of the comparator 300 and the clock signal to obtain the time difference. The vernier delay chain maintains the same state as the resolution control module 410 according to the control voltage, and can have a time resolution capability of up to 20ps. As an example and not a limitation, the vernier delay chain includes an upper chain and a lower chain, the clock and the signal to be measured are distributed into the upper chain and the lower chain, and then processed by the decision circuit, and finally outputs a thermometer code containing the time difference information of the upper and lower chains and a measurement completion signal.

[0058] Further, see Figure 5 , the time-to-digital converter 400 also includes a signal selector 430 and a control voltage selector 440, both of which are connected to the measurement module 420, and the signal selector 430 is configured to selectively input the measured signal into the corresponding measurement channel 421. It should be particularly noted that the measurement module 420 has multiple measurement channels 421, each measurement channel 421 is related to the size of the counting threshold, and in one example, the number of measurement channels 421 is eight. The control voltage selector 440 is configured to receive the control voltage input by the second-stage delay-locked loop 412 and the control voltage input from the outside, and select among these control voltages and then input them into the measurement channel 421. For example Figure 5 As shown in , the control voltage selector 440 selects VC, VF, VD from the control voltages VC_vdl, VF_vdl, VD_vdl input by the second-stage delay phase-locked loop 412 and the control voltages VC_in, VF_in, VD_in input externally. Regarding the selection of the control voltage, in one example, when the working states of the first-stage delay phase-locked loop 411 and the second-stage delay phase-locked loop 412 are both normal, the control voltage selector 440 selects the control voltages VC_vdl, VF_vdl, VD_vdl input by the second-stage delay phase-locked loop 412 as outputs, otherwise, the control voltages VC_in, VF_in, VD_in input externally are selected as outputs. The measurement channel 421 performs data processing according to VC, VF, VD, the signal to be measured, and the reference signal input by the first-stage delay phase-locked loop 411.

[0059] In another example of the present application, in order to enable each circuit to work effectively, the digital silicon photomultiplier also includes a power management module 500, and the power management module 500 is configured to use different low voltage difference linear regulators to adjust the power supply according to the current, power consumption changes and power supply requirements of different functional modules in the digital silicon photomultiplier to achieve different power supply to different functional modules.

[0060] Figure 6 FIG. 1 shows a schematic diagram of a power management module according to an embodiment of the present application. Figure 6 As shown, see also Figure 1 The power management module 500 includes a bandgap reference circuit 510 , a voltage buffer 520 , a reference current generating circuit 530 and a low voltage dropout linear regulator 540 .

[0061] Specifically, different power management strategies are adopted for the data readout circuit 200 and the time-to-digital converter 400 .

[0062] For the data readout circuit 200, it uses a multi-level combinational logic circuit to complete the processing of the large array SPAD digital counting pulse count data, and has a large circuit scale. When an annihilation event occurs, many photons will arrive at the same time and trigger the reversal of the data readout circuit 200 in large quantities. The peak current of the data readout circuit 200 can reach tens of milliamperes within a few nanoseconds. Under such a fast load current transient change, the low-dropout linear regulator selects a main pole compensation type structure. The architecture of the main pole compensation type low-dropout linear regulator is as follows Figure 7 As shown, the entire power management module 500 includes a bandgap reference circuit 510, an operational amplifier 550, a super source follower 560, a power PMOS 590, a feedback resistor network 570, and an external capacitor 580. The transient response stability of the output voltage of the low-dropout linear regulator is ensured by relying on a large external capacitor. Since the readout circuit is a digital circuit, it has a good tolerance to power supply noise, so the chip external noise introduced by the dominant pole compensation type low-dropout linear regulator has little effect on the performance of the circuit.

[0063] As a module for collecting the time information of SiPM pulse waveform, the time digital converter 400 has a high requirement for measurement resolution. However, the time measurement module 420 such as the vernier delay line and the delay phase-locked loop in the time digital converter 400 is very sensitive to the noise of the internal power supply voltage of the chip and requires a low ripple noise power supply. Therefore, a capacitor-free low voltage drop linear regulator that can avoid the introduction of external noise is selected. Its architecture is shown in the figure below. Figure 8 As shown, the entire power management module 500 includes a bandgap reference circuit 510, an operational amplifier 550, a feedforward ripple cancellation circuit 560', a power PMOS 590, and a feedback resistor network 570, etc.

[0064] In another example of this application, see Figure 1 The digital silicon photomultiplier further includes: a data packing module 600, which is connected to the time-to-digital converter 400 and is configured to decode, identify, pack, combine coarse counting codes, compress and output the output of the time-to-digital converter 400 to the outside.

[0065] Fig. 9 FIG. 2 shows a schematic diagram of a data packaging module according to an embodiment of the present application. Fig. 9As shown, the data packing module 600 includes: a data processing module 610 and a counter 620. The data processing module 610 is configured to decode, identify, pack, combine coarse counting codes, compress and output to the outside the output of the time digital converter 400, and the counter 620 is configured to provide the coarse counting code. Each of the data processing modules 610 includes a plurality of first frames 611 and at least one second frame 612. The plurality of first frames 611 are located between the time digital converter 400 and the second frame 612, and each of the first frames 611 corresponds to a rising edge channel or a falling edge channel. The data processed by the measurement channel 421 is output to the first frame 611 of the data packing module 600. The number of the first frames 611 is related to the counting threshold set for the screening event. In an application scenario, four counting thresholds are set, and the rising edge and falling edge of the digital count pulse correspond to four channels. Then, eight first frames 611 are set accordingly, and each first frame 611 corresponds to one rising edge channel or one falling edge channel. The number of the first frames 611 connected to the rising edge channel is the same as the number of the first frames 611 connected to the falling edge channel. Multiple first frames 611 are configured to decode the output data of the rising edge channel or the falling edge channel to obtain decoded data. Multiple first frames 611 are arranged in parallel, so as to process the output data of N rising edge channels and the output data of N falling edge channels in parallel. Among them, the rising edge channel indicates that the corresponding TDC detects the rising edge of the digital count pulse, and correspondingly, the falling edge channel indicates that the corresponding TDC detects the falling edge of the digital count pulse. The second frame 612 is configured to judge the validity of the corresponding pulse event according to the decoded data. In an example, the number of the second frame 612 is one, which is connected to all the first frames 611, receives the data decoded by all the first frames 611, extracts valid events, and finally outputs the data according to the occurrence order of valid events. When the number of the first frames 611 is small, such as only eight in the above example, the number of the second frames 612 is generally set to one to meet the data processing requirements. However, when the number of the first frames 611 is large, the data processing volume is large, and one second frame 612 cannot meet the data processing requirements, multiple second frames 612 can be set. It should be noted that when multiple second frames 612 are set, the data processed by the multiple second frames 612 need to be fused to finally obtain valid event data.

[0066] Continue to see Fig. 9Each of the first frames 611 is configured to receive the system working clock signal CLK, the fine counting measurement data TDC_DATA_I[A-1:0] and the data conversion flag TDC_VALID. The CLK is provided by the system clock, and the TDC_DATA_I[A-1:0] and the TDC_VALID are output by the TDC. The first frame 611 performs corresponding actions or processes related data according to the above data, and then outputs the decoded data and channel data valid flag information.

[0067] Specifically, the first frame 611 detects TDC_VALID of the corresponding channel, and when the first falling edge of the system working clock after the TDC_VALID is detected to be high level, the fine count measurement data output by the time-to-digital converter 400 is latched for subsequent processing. After the latching is completed, the first frame 611 decodes the fine count measurement data through binary conversion to obtain the decoded data. If there is a bit error in the fine count measurement data after being decoded through binary conversion, the first frame 611 generates a bit error signal to realize the function of bit error identification.

[0068] Fig.10 The first frame timing diagram of the data packaging module according to the embodiment of the present application is shown. In one example, the fine count measurement data includes VDL_I[31:0] and DLL_I[15:0]. The specific decoding process is, for example, firstly decoding the latched 32-bit thermometer code VDL_I[31:0] into a 6-bit binary code through data decoding, and then decoding the 16-bit binary code DLL_I[15:0] into a 4-bit binary code, and judging whether there is a code error in the 6-bit binary code and the 4-bit binary code, and if there is a code error, generating a dec_err decoding error signal.

[0069] In addition, in addition to decoding and error detection of data, the data processing module 610 can also assist in the state detection of TDC. Specifically, in one example, each of the first frames 611 is also configured to receive the data output mode control signal DATA_SEL output by the TDC, and select the working mode according to DATA_SEL. When DATA_SEL is at a low level, the first frame 611 selects the normal mode, decodes the fine count measurement data, and outputs the decoded data; when DATA_SEL is at a high level, the first frame 611 selects the test mode, outputs the original data of the corresponding channel, and the original data is stored as a detection signal by the second frame 612. For example, in the normal mode, the CH_FRAME_OUT output of the first frame 611 is a combination of TDC decoded data, and the valid data is 10 bits in total; in the test mode, the CH_FRAME_OUT output is the original data that has not been decoded, and the original data is 48 bits of data formed by combining VDL_I[31:0] and DLL_I[15:0].

[0070] Furthermore, the second frame 612 can also select the working mode according to the data output mode control signal output by the time-to-digital converter 400. Here, in one example, after the first frame 611 receives the data output mode control signal DATA_SEL, when outputting data, it outputs DATA_SEL to the second frame 612; in another example, in addition to being connected to the first frame 611 and performing data transmission, the TDC is also connected to the second frame 612 and performing data transmission. The second frame 612 directly receives the DATA_SEL of the TDC without being forwarded by the first frame 611. In comparison, this method has higher processing efficiency.

[0071] Specifically, the details of the second frame 612 selecting the working mode according to DATA_SEL include: when the data output mode control signal is at a low level, the second frame 612 selects the normal mode and extracts valid events according to the decoded data; when the data output mode control signal is at a high level, the second frame 612 selects the test mode and stores the original data of the corresponding channel as a detection signal. Exemplarily, in the normal mode, the second frame 612 packages the relevant data into 152-bit valid data and outputs it to the outside of the system; in the test mode, the second frame 612 outputs the 48-bit TDC original code for the external device to test the state of the TDC.

[0072] For the output of the first framework 611, see Fig. 9In addition to the above-mentioned CH_FRAME_OUT, there is also a valid flag signal LOAD_CH. Each of the first frames 611 outputs LOAD_CH containing a specific counting threshold to the second frame 612, and each of the first frames 611 corresponds to a different counting threshold. Specifically, in terms of structural setting, the multiple first frames 611 corresponding to the rising edge channel and the falling edge channel are arranged in order according to the size of the counting threshold. For example, the multiple first frames 611 corresponding to the rising edge channel are arranged in order from low to high counting thresholds; the multiple first frames 611 corresponding to the falling edge channel are arranged in order from high to low counting thresholds.

[0073] Further, see Fig.10 The output LOAD_CH of the first frame 611 is set to 1 at the second clock falling edge after the corresponding data conversion flag TDC_VALID=1, indicating that there is data in the corresponding channel and it lasts for one clock cycle, so that the signal can be collected at the rising edge of the digital count pulse in the next clock cycle.

[0074] Fig.11 FIG. 2 shows a schematic diagram of a second frame of a data packaging module according to a specific embodiment of the present application. Fig.11 As shown, the second frame 612 includes a valid event extraction module 6121, and the valid event extraction module 6121 is connected to all the first frames 611. According to different outputs of the first frames 611, the valid event extraction module 6121 has at least one of an idle state, a rising edge acquisition state, a falling edge acquisition state, a delay state, an end state, and a waiting state.

[0075] Specifically, the initial state of the second frame 612 is an idle state, in which the second frame 612 waits for a signal from the first frame 611 . Fig.12This is a second framework timing diagram of the data packaging module according to the embodiment of the present application, wherein CLK100 represents the clock signal, LOAD_CH[0] represents the lowest count threshold mark signal of the rising edge of the digital count pulse, and the channel is 0, LOAD_CH[N-1] represents the highest count threshold mark signal of the rising edge of the digital count pulse, and the channel is N-1, LOAD_CH[2N-1] represents the highest count threshold mark signal of the falling edge of the digital count pulse, and the channel is 2N-1, CH0_FRAME_OUT[K-1:0] represents the decoded data of channel 0, CH(N-1)_FRAME_OUT[K-1:0] represents the decoded data of channel N-1, CH(2N-1)_FRAME_OUT[K-1:0] represents the decoded data of channel 2N-1, LOAD represents the valid mark of data packaging completion, and FRAME_OUT[K-1:0] represents the output data. Fig.12 As shown, in the idle state, the second frame 612 performs different operations according to the difference in the valid flag signals of the lowest counting threshold and the highest counting threshold of the rising edge of the digital counting pulse monitored at the rising edge of the clock.

[0076] In the first case, when the valid flag signal of the lowest counting threshold is detected to be high level at the rising edge of the clock, a state transition occurs to enter the rising edge acquisition state. At the same time, the counter 620 is turned on to start counting, and the count value is latched during the counting process. In the subsequent process, according to the difference of the valid flag signal of the highest counting threshold of the rising edge of the digital counting pulse at the rising edge of the clock, the second frame 612 also performs different operations: including A~D.

[0077] A. Within the first preset number of clocks thereafter, the second frame 612 detects the valid flag signal LOAD_CH[N-1] with the highest threshold at each clock rising edge, and latches the decoded data CH0_FRAME_OUT[K-1:0]~CH(N-1)_FRAME_OUT[K-1:0]. If the valid flag signal LOAD_CH[N-1] with the highest counting threshold is at a low level, the corresponding photon event is determined to be an invalid event. At this time, the end point of this photon event collection is reached, and then it is immediately converted to the idle state, and the valid flag signal LOAD_CH[0] with the lowest counting threshold is restarted at the clock rising edge.

[0078] B. Within the first preset number of clocks thereafter, if the valid flag signal LOAD_CH[N-1] of the highest count threshold is at a high level at the rising edge of the clock, the second frame 612 enters the falling edge acquisition state and latches all the data collected in the rising edge acquisition state. In the falling edge acquisition state, the second frame 612 also performs different operations according to the difference in the valid flag signal LOAD_CH[2N-1] of the lowest count threshold corresponding to the falling edge of the digital count pulse.

[0079] C. If the valid flag signal LOAD_CH[2N-1] of the lowest count threshold corresponding to the falling edge of the digital count pulse is high within the second preset number of clocks, the corresponding pulse event is a valid event, and the decoded data CH corresponding to the falling edge of the digital count pulse in each clock rising edge is N_FRAME_OUT[K-1:0]~CH(2N-1)_FRAME_OUT[K-1:0] are all latched, and the end point of this pulse event collection is reached at this time. Then, the delay state is entered, the third preset number of clocks are maintained, and the decoded data of each clock rising edge is latched to ensure that when new data arrives at the lowest count threshold channel of the falling edge of the digital count pulse, it can be replaced with the new data. After maintaining the third preset number of clocks in the delay state, the end state is entered, and the data packaging completion valid flag LOAD is set to 1, and the fourth preset number of clocks are maintained in the end state. After maintaining the fourth preset number of clocks in the end state, the waiting state is entered, and the idle state is entered after the waiting state continues for the fifth preset number of clocks, waiting for a new pulse event to arrive. Since the valid flag signal corresponding to the lowest count threshold is usually recognized as valid data, the purpose of continuing the fifth preset number of clocks in the waiting state is to eliminate the influence of digital noise, and wait for the fifth preset number of clocks to detect whether the lowest count threshold channel of the falling edge of the digital count pulse is re-triggered. If so, the existing data is replaced.

[0080] D. If within the second preset number of clocks, there is no valid flag signal LOAD_CH[2N-1] of the lowest count threshold of the falling edge of the digital count pulse and it is at a high level, then the corresponding photon event is determined to be an invalid event. At this time, the end point of this photon event collection is reached, and then it is immediately switched to the idle state, and the valid flag signal LOAD_CH[0] of the lowest count threshold is monitored again at the rising edge of the clock.

[0081] In the second case, when the valid flag signal LOAD_CH[N-1] of the highest counting threshold is high when the rising edge of the clock is detected, the second frame 612 enters the falling edge acquisition state, and then executes the steps of the above case C.

[0082] To calibrate the time, according to an example of this application, see Fig. 9The data packaging module 600 further includes a counter 620. Exemplarily, the counter 620 is a coarse counting module, which can be 100 MHz and configured to calibrate the coarse time of the measurement and convert it into a Gray code output. The value of the counter 620 is latched before the above-mentioned rising edge acquisition state and the direct jump from the idle state to the falling edge acquisition state. The counter 620 is connected to the second frames 612 of the plurality of data processing modules 610 and performs unidirectional data transmission.

[0083] It should be particularly noted that the values ​​of the first preset number to the fifth preset number can be set according to the pulse events actually collected.

[0084] In order to store data, according to an example of this application, see Fig. 9 The data packaging module 600 also includes a readable and writable register 630 and a standard SPI interface.

[0085] In one example of the present application, the valid event extraction module 6121 includes a state machine. Fig.13 FIG. 2 shows a schematic diagram of a second frame state machine of a data packaging module according to an embodiment of the present application. Fig.13 As shown, six states of the state machine are shown: IDLE, RINING, FALLING, DELAY, END and WAIT.

[0086] Fig.14A schematic diagram of the second frame state machine of the data packaging module according to a specific embodiment of the present application is shown. In order to more clearly represent the workflow of the state machine, the present application is described in more detail by taking the counting threshold of four as an example. The initial state of the state machine is the IDLE state. When the valid flag bit of the lowest count threshold of the rising edge of the digital count pulse is detected as LOAD_CH[0]=1 on the rising edge of the clock, it starts to enter the RISING state of the rising edge collection of the digital count pulse, and at this time, a 5-bit counter 620 is turned on, and the value [36:0] of the Gray code counter is latched. In the next three clocks (10ns per clock), the valid flag bit LOAD_CH[3] of the highest count threshold of the rising edge of the digital count pulse is detected at the rising edge of each clock to see if the level is high. At the same time, the input of CH0_FRAME_OUT[9:0]-CH3_FRAME_OUT[9:0] of the rising edge of the digital count pulse is latched. When LOAD_CH[3] is not detected as high within the 30ns time window, it means that the pulse event is an invalid event, and it returns to the IDLE state and starts detecting LOAD_CH[0] again. If within the time window, the valid flag bit of the highest count threshold of the rising edge of the digital count pulse is judged to be high at the rising edge of the clock, the state machine jumps to the falling edge acquisition FALLING state, and the data collected on the rising edge of the digital count pulse are latched and no longer changed. If in the IDLE state, the level of the valid flag bit of the highest count threshold LOAD_CH[3] of the rising edge of the digital count pulse is detected to be high at the rising edge of the clock, then the inputs of CH0_FRAME_OUT[9:0]-CH3_FRAME_OUT[9:0] of the rising edge of the digital count pulse are directly latched, and the value of the Gray code counter 620 is latched, and it jumps directly to the falling edge acquisition FALLING state. After entering the falling edge acquisition FALLING state, a 170ns time window is opened, and the inputs of CH4_FRAME_OUT[9:0]-CH7_FRAME_OUT[9:0] of the falling edge of the digital count pulse are latched at each rising edge of the clock. If within this time window, the valid flag LOAD_CH[7] of the lowest count threshold of the falling edge of the digital count pulse detected on the rising edge of the clock is high, it means that the digital count pulse is a valid pulse, and all the data of CH4_FRAME_OUT[9:0]-CH6_FRAME_OUT[9:0] of the falling edge of the collected digital count pulse are latched and no longer changed. At this time, the state machine state jumps to the delay DELAY state, which lasts for 30ns. In this state, CH7_FRAME_OUT is latched in at each rising edge of the clock to ensure that when new data arrives at the lowest count threshold channel, it is replaced with new data.After the DELAY state, it enters the END state for one cycle. After entering this state, the clock falls and the LOAD signal is set to 1 for one cycle. After that, it enters the WAIT state at the rising edge of the clock. After waiting for three cycles in this state, it returns to the IDLE state and waits for new events to arrive.

[0087] In addition, in order to reduce the amount of data processing, the second frame 612 uses the count value corresponding to the valid flag information of the first channel in the rising edge channel as the initial time of the corresponding pulse event. That is, the second frame 612 only records the Gray code count value GrayCNT[36:0] when LOAD_CH[0]=1 as the initial time of the corresponding pulse event. For the remaining channels, in the rising edge acquisition state, when the valid flag information of the corresponding channel is detected to be high at the rising edge of the clock, the corresponding count value is latched and used as the delay difference between the channel and the first channel. Among them, the first channel has the smallest count threshold in the rising edge channel. Exemplarily, for LOAD_CH[1]~LOAD_CH[3], when the LOAD_CH of the corresponding channel is detected to be high at the rising edge of the clock, the corresponding 5-bit count value NUM_CYC is latched as the delay difference between the channel and channel 0. After entering the falling edge acquisition stage, except for the last channel, the second frame 612 latches the count value corresponding to the falling edge of all digital count pulses when the valid flag signal is high. For example, for LOAD_CH[4]~LOAD_CH[6], when LOAD_CH is detected as a high level at the rising edge of the clock, the corresponding count value NUM_CYC is latched. In the falling edge acquisition stage and the waiting detection stage, if the second frame 612 detects that the valid flag signal of the lowest count threshold of the falling edge of the digital count pulse is a high level at the rising edge of the clock, the count value at this time is latched. For example, if LOAD_CH[7] is detected at the rising edge of the clock, the count value at this time is latched. The second frame 612 uses the data latched by all channels, the count value and the delay difference as the output data of the data packaging module 600. For example, the second frame 612 finally combines the latched data of 8 channels, the data latched by the Gray code counter and the 7 delayed data into a 152-bit data output.

[0088] Further, in one example of the present application, see Fig. 9 The second framework 612 also includes a first-in-first-out module 6122 and a data conversion module 6123.

[0089] Fig.15 FIG. 4 is a schematic diagram showing a second frame of a data packaging module according to a specific embodiment of the present application. Fig.15When LOAD=1 is detected at the rising edge of the clock, the data latched by all channels, the count value and the delay difference are written into the first-in-first-out module 6122FIFO, and the first-in-first-out method is adopted to output the first-entered data first.

[0090] Fig.16 The timing diagram of the data conversion module of the second frame of the data packaging module according to the specific embodiment of the present application is shown. The data conversion module 6123, exemplarily, in the DATA_TO_7bit module, detects whether there is data in the FIFO of the first-in-first-out module at each rising edge of the clock. When FIFO_EMPTY=0, it means that there is data in the FIFO of the first-in-first-out module at this time, then the data in the FIFO of the first-in-first-out module is read out, and the output data is converted into a 7-bit serial output starting from the low bit to the high bit. Through the high-speed data transmission interface (DATA_TO_7bit), efficient data transmission can be achieved.

[0091] For example, in the present application, the first frame 611 may be a CH_FRAME module, and the second frame 612 may be a DATA_FRAME module. It is understandable that the first frame 611 and the second frame 612 are not limited to the above examples, and any frame that can realize the functions of the present application may be used as the first frame 611 and the second frame 612.

[0092] The digital silicon photomultiplier provided in the present application can strike a balance between high-speed readout processing of photon counting data and system power consumption, can read out the photon counting data of the entire array in real time, avoids the introduction of a large number of TDCs, can obtain a higher count rate and time resolution, has high data processing efficiency, and simultaneously realizes decoding, error detection, and TDC state detection functions, realizes the function of completing the screening of effective pulse events and extracting effective information on the photomultiplier chip, solves the problem of effective event loss when setting a lower counting threshold, and is of great significance for optimizing the time resolution of the digital SiPM.

[0093] In addition to the above-mentioned silicon photomultipliers, the present application also provides an application of any of the above-mentioned examples of silicon photomultipliers in scientific instruments, medical equipment, high-energy physics, deep space and deep sea exploration, extremely weak light imaging, radiation monitoring, autonomous driving, security equipment, consumer electronics or smart home appliances. Those skilled in the art should know that all applications of the silicon photomultipliers provided by the present application in scientific instruments, medical equipment, high-energy physics, deep space and deep sea exploration, extremely weak light imaging, radiation monitoring, autonomous driving, security equipment, consumer electronics or smart home appliances fall within the scope of protection of the present application.

[0094] Those skilled in the art will appreciate that the above modules can be distributed in the device according to the description of the embodiment, or can be changed accordingly and only used in one or more devices different from the embodiment. The multiple modules of the above embodiments can be combined into one module, or one module can be further divided into multiple sub-modules.

[0095] Although the present application provides the method operation steps as described in the above embodiments or flow charts, more or fewer operation steps may be included in the method based on routine or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided in the embodiments of the present application.

[0096] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0097] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present application. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present application, the specific implementation methods and the scope of application of the present application, all belong to the scope of protection of the present application. In summary, the content of this specification should not be construed as a limitation on the present application.

Claims

1. A digital silicon photomultiplier, characterized in that: The digital silicon photomultiplier comprises: A pixel array, the pixel array comprising a plurality of pixel groups, each of the pixel groups comprising two or more pixels, each of the pixel groups outputting data via an independent bus, the pixels being configured to detect visible light photons; A data readout circuit is connected to all the pixel groups through a plurality of the buses, and the data readout circuit is configured to obtain digital counting pulses and count counting data according to output data of the pixel groups.

2. The digital silicon photomultiplier according to claim 1, characterized in that: The number of pixels in all the pixel groups is the same.

3. The digital silicon photomultiplier according to claim 1, characterized in that: The pixel array includes a first pixel array and a second pixel array, each of the first pixel array and the second pixel array includes a plurality of pixel groups, and the first pixel array and the second pixel array are respectively connected to one of the data readout circuits.

4. The digital silicon photomultiplier according to claim 3, characterized in that: The first pixel array and the second pixel array include the same number of pixel groups, and each of the pixel groups includes the same number of pixels.

5. The digital silicon photomultiplier according to claim 1, characterized in that: The data readout circuit reads out the data of the pixel group in a cascade manner, the amount of input data of each stage of the circuit is greater than the amount of output data, and the size of input data of each stage of the circuit is greater than the size of output data.

6. The digital silicon photomultiplier according to claim 5, characterized in that: The data readout circuit includes a first-level circuit, a second-level circuit and a third-level circuit connected in sequence, the first-level circuit is connected to all the pixel groups, the first-level circuit is configured to sum the data of each pixel group respectively and output multiple first-level outputs containing weights, the second-level circuit is configured to sum the first-level outputs with the same weights respectively and output multiple second-level outputs containing weights, and the third-level circuit is configured to sum the second-level outputs with the same weights respectively and obtain the number of the triggered pixel groups to obtain counting data.

7. The digital silicon photomultiplier according to claim 1, characterized in that: The digital silicon photomultiplier further includes a comparator connected to the data readout circuit and configured to compare the count data of the data readout circuit with a preset count threshold, wherein the comparator flips when the count data exceeds the corresponding count threshold.

8. The digital silicon photomultiplier according to claim 1, characterized in that: The digital silicon photomultiplier further includes a time-to-digital converter, which is connected to the comparator and configured to measure the time difference between the flip time of the comparator and a clock signal.

9. The digital silicon photomultiplier according to claim 8, characterized in that: The time-to-digital converter includes a resolution control module and a measurement module, wherein the resolution control module is configured to output a control voltage to the measurement module, and the measurement module is configured to maintain the same state as the resolution control module according to the control voltage, and process the output of the comparator and generate the time difference.

10. The digital silicon photomultiplier according to claim 9, characterized in that: The resolution control module includes a first-stage delay phase-locked loop and a second-stage delay phase-locked loop. The first-stage delay phase-locked loop is provided with an anti-error locking structure. The second-stage delay phase-locked loop completes locking and fine time precision control according to the reference signal generated by the anti-error locking structure.

11. The digital silicon photomultiplier according to claim 9, characterized in that: The measurement module includes a vernier delay chain and a decision circuit. The vernier delay chain is configured to maintain the same state as the resolution control module according to the control voltage and receive the flip time of the comparator and the clock signal. The decision circuit is configured to process the flip time of the comparator and the clock signal to obtain the time difference.

12. The digital silicon photomultiplier according to claim 9, characterized in that: The time-to-digital converter further includes a control voltage selector configured to select from an external control voltage and a control voltage output by the resolution control module, and output the result to the measurement module.

13. The digital silicon photomultiplier according to claim 12, characterized in that: When the resolution control module is in a normal state, the control voltage selector uses the control voltage output by the resolution control module as output; otherwise, the control voltage selector uses the external control voltage as output.

14. The digital silicon photomultiplier according to claim 9, characterized in that: The measurement module includes a plurality of measurement channels, and the data processed by each measurement channel corresponds to a different counting threshold.

15. The digital silicon photomultiplier according to claim 9, characterized in that: The time-to-digital converter further includes a signal selector configured to transmit the signal to be measured to a corresponding measurement channel.

16. The digital silicon photomultiplier according to claim 1, characterized in that: The digital silicon photomultiplier also includes a power management module, which is configured to use different low-voltage difference linear regulators to adjust the power supply according to the current, power consumption changes and power supply requirements of different functional modules in the digital silicon photomultiplier to achieve different power supply to different functional modules.

17. The digital silicon photomultiplier according to claim 16, characterized in that: The low-dropout linear regulator includes a main-pole-compensated low-dropout linear regulator and a capacitor-free regulator. The main-pole-compensated low-dropout linear regulator is configured to regulate the power supply for the data readout circuit, and the capacitor-free regulator is configured to regulate the power supply for the time-to-digital converter.

18. The digital silicon photomultiplier according to claim 1, characterized in that: The digital silicon photomultiplier further includes a data packaging module, including a data processing module and a counter, wherein the data processing module is configured to decode, identify, package, combine coarse counting codes, compress and output to the outside the output of the time-to-digital converter, and the counter is configured to provide the coarse counting code.

19. The digital silicon photomultiplier according to claim 18, characterized in that: The data processing module includes a first frame and a second frame, wherein the first frame is configured to decode the output of the time-to-digital converter, and the second frame is configured to identify the decoded data, and pack the data, combine the coarse counting code, compress and output it to the outside.

20. The digital silicon photomultiplier according to claim 19, characterized in that: The second frame is configured to open a time window of a first predetermined size when a digital count pulse is detected to have crossed a minimum count threshold, and detect within the time window whether a maximum count threshold of a rising edge of the digital count pulse has been reached; If not, the event corresponding to the digital count pulse is deemed to be an invalid event; If so, the falling edge acquisition phase is entered, the data of the rising edge of the digital count pulse is latched, a second predetermined time window is opened, and it is detected whether the minimum counting threshold of the falling edge of the digital count pulse is reached. If it is reached, the event corresponding to the digital count pulse is determined to be a valid event.

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