Chip aging system and method, chip and terminal equipment

Abstract

The invention provides a chip aging system and method, a chip and terminal equipment, and the system comprises a central controller which is used for determining the information of a power supply signal according to the type of an input to-be-tested chip, and outputting a control instruction which comprises the information of the power supply signal; and the aging plugboard is used for generating and outputting a power supply signal according to the control instruction. The technical scheme of the invention provides the chip aging system capable of supporting aging tests on various chips, and the convenience of the chip aging tests is improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip aging system and method, a chip, and a terminal device. Background Art

[0002] Chip aging testing is a key step in evaluating chip reliability and performance stability, and is usually performed by simulating the long-term operating conditions of the chip in actual use.

[0003] Aging boards (also called aging boards or aging test boards) play a vital role in chip aging tests. Specifically, an aging board is a printed circuit board (PCB) designed with multiple slots or pads for mounting and fixing the chip to be tested. Through these slots or pads, the chip can be electrically connected to the aging test system. The aging board connects the chip to be tested to the aging test equipment through the circuit traces and connectors on it. These connections include power supply, signal input / output, clock signal, etc., to ensure that the chip can work normally during the test process. The aging board can also provide an interface with external test equipment, so that the test equipment can measure and monitor various electrical parameters of the chip.

[0004] However, the current aging plug-in board only supports testing one type of chip, resulting in a wide variety of aging plug-ins, which brings inconvenience to chip aging testing. Summary of the invention

[0005] The technical solution of the present application provides a chip aging system that can support aging tests on multiple chips, thereby improving the convenience of chip aging tests.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] In a first aspect, a chip aging system is provided for supplying power to at least one chip to be tested, the chip aging system comprising: a central control controller for determining information of a power supply signal according to the type of the input chip to be tested, and outputting a control instruction, wherein the control instruction comprises information of the power supply signal; and an aging plug-in board for generating and outputting the power supply signal according to the control instruction.

[0008] Optionally, the aging plug-in board includes: a communication interface for receiving the control instruction; multiple test interfaces, each test interface is used to access a type of chip to be tested, and each test interface is used to output the power supply signal, and the power supply signal is generated based on the control instruction.

[0009] Optionally, the aging plug-in board includes: a power supply module, configured to receive the control instruction and generate the power supply signal according to the control instruction.

[0010] Optionally, the central control stores a plurality of chip types and their corresponding voltage values ​​of power supply signals; the central control searches for the corresponding voltage value according to the input type of the chip to be tested as the information of the power supply signal.

[0011] Optionally, the control instruction includes information of the power supply signal, including: the control instruction includes a voltage value of the power supply signal; or the control instruction includes index information, and the index information is used to uniquely identify the power supply signal.

[0012] Optionally, the power supply signal includes at least one of the following: an internal digital power supply voltage, an analog ground voltage, and an analog power supply voltage.

[0013] Optionally, the central control unit and the aging board are integrated in the same chip.

[0014] Optionally, the chip aging system further includes: an aging device, used to provide an aging environment for the at least one chip to be tested, wherein the aging environment is defined by aging parameters, and the aging parameters include temperature and / or humidity.

[0015] In a second aspect, the present application also discloses a method for powering an aging chip, which comprises: a central control controller determines information of a power supply signal according to the type of chip to be tested input, and outputs a control instruction, wherein the control instruction includes information of the power supply signal; and an aging plug-in board generates and outputs the power supply signal according to the control instruction.

[0016] In a third aspect, the present application further discloses a terminal device, which includes the chip aging system.

[0017] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0018] In the technical solution of the present application, since different types of chips to be tested have different requirements for power supply signals, the central control controller of the chip aging system of the technical solution of the present application can identify the type of chip to be tested and determine the power supply signal suitable for the chip to be tested, and send the corresponding power supply signal information to the aging board through control instructions; the aging board can provide the corresponding power supply signal for the chip to be tested, and assist in completing the aging test of the chip to be tested. The above-mentioned chip aging system can support aging tests for multiple chips and avoid designing a wide variety of aging boards. On the one hand, it can reduce hardware costs, and on the other hand, it improves the convenience of chip aging tests.

[0019] Furthermore, in the technical solution of the present application, the control instruction includes the voltage value of the power supply signal; or, the control instruction includes index information, and the index information is used to uniquely identify the power supply signal. In the technical solution of the present application, by carrying the voltage value or index information of the corresponding power supply signal in the control instruction, it is possible to directly or indirectly instruct the aging plug-in board to provide the corresponding power supply information, thereby completing the aging test of the chip.

[0020] Furthermore, the technical solution of the present application sets a communication interface in the aging plug-in board to receive control instructions from the central control controller; by setting multiple test interfaces in the aging plug-in board, it can be used to access various types of chips to be tested, thereby supporting aging tests on various types of chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of the structure of a chip aging system provided in an embodiment of the present application;

[0022] Figure 2 is a structural schematic diagram of another chip aging system provided in an embodiment of the present application;

[0023] Figure 3 is a structural schematic diagram of another chip aging system provided in an embodiment of the present application;

[0024] Figure 4 is a structural schematic diagram of another chip aging system provided in an embodiment of the present application;

[0025] Figure 5 It is a flow chart of a chip aging method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to facilitate understanding of the technical solution of the present application, a brief introduction to the relevant technologies involved in the present application is first given.

[0027] Chip aging test is an accelerated life test method. It tests the chip for a long time under extreme conditions (such as high temperature, high voltage, high load, etc.) to accelerate the manifestation of potential defects inside the chip, thereby screening out chips that fail early.

[0028] Chip aging test can screen out early failed chips. Among them, chips may fail due to manufacturing defects, material problems and other reasons in the early use stage. Aging test can accelerate the appearance of these defects. Chip aging test can also improve product reliability. By screening out early failed chips, the reliability and service life of the final product can be improved. Chip aging test can also control chip quality to ensure that the chips shipped meet quality standards and reduce the risk of product failure during customer use.

[0029] As described in the background art, current aging boards only support testing of one type of chip, resulting in a wide variety of aging boards, which brings inconvenience to chip aging testing.

[0030] In the technical solution of the present application, since different types of chips to be tested have different requirements for power supply signals, the central control controller of the chip aging system of the technical solution of the present application can identify the type of chip to be tested and determine the power supply signal suitable for the chip to be tested, and send the corresponding power supply signal information to the aging board through control instructions; the aging board can provide the corresponding power supply signal for the chip to be tested, and assist in completing the aging test of the chip to be tested. The above-mentioned chip aging system can support aging tests for multiple chips and avoid designing a wide variety of aging boards. On the one hand, it can reduce hardware costs, and on the other hand, it improves the convenience of chip aging tests.

[0031] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0032] The present application embodiment provides a communication method, referring to Figure 1 , detailed description is given below.

[0033] In this embodiment, the chip aging system 10 is used to supply power to at least one chip to be tested 20. The chip aging system 10 includes a central control 101 and an aging board 102.

[0034] In a specific implementation, the chip under test 20 may be connected to the burn-in board 102, and the burn-in board 102 outputs a power supply signal to the chip under test 20. For example, the burn-in board 102 outputs the power supply voltage required by the chip under test 20 to the chip under test 20.

[0035] In a specific implementation, the central controller 101 can determine the information of the power supply signal according to the input type of the chip to be tested 20 and output a control instruction. For example, the type of the chip to be tested 20 can be input by a user.

[0036] In a variation, the central control 101 may also automatically identify the type of the chip to be tested 20. Exemplarily, the central control 101 may automatically take a picture of the chip to be tested 20 or obtain it from the outside, and the central control 101 performs picture recognition on the picture to obtain the type of the chip to be tested 20. The picture of the chip to be tested 20 includes content related to the type of the chip to be tested 20, such as an identifier of the type of the chip to be tested 20.

[0037] In a non-limiting embodiment, multiple chip types and their corresponding voltage values ​​of power supply signals are stored in the central controller 101. The central controller 101 searches for the corresponding voltage value according to the input type of the chip to be tested as the information of the power supply signal.

[0038] In this embodiment, different types of chips correspond to different voltage values ​​of power supply signals. The central controller 101 may store the chip types and the voltage values ​​of power supply signals corresponding thereto.

[0039] For example, please refer to Table 1, which shows different types of chips and the voltage values ​​of their corresponding power supply signals. Among them, the chip aging system 10 supports the aging of 6 types of chips to be tested, specifically: 4010O1B05, 4021BDB01, 4010Q3A1G, 4021Q3B1X, 4021Q1A1G and 2510. Taking chip 4010O1B05 as an example, the voltage value of its corresponding power supply signal AVDD (analog power supply voltage) is 1.32 volts (V), the corresponding power supply signal VDDI (internal digital power supply voltage) value is 2.5V, and the corresponding power supply signal AVEE (analog ground voltage) value is -2V. Correspondingly, for chip 4021BDB01, the voltage values ​​of its corresponding power supply signals AVDD, VDDI and AVEE are 1.2V, 1.8V and -2V respectively.

[0040] Table 1

[0041]

[0042] Furthermore, the central control unit 101 is connected to the aging board 102 , and transmits the control instruction to the aging board 102 , so as to indicate the information of the power supply signal of the test chip to the aging board 102 .

[0043] In a specific embodiment, the power supply signal may be a voltage signal. Specifically, the power supply signal may include at least one of the following: an internal digital power supply voltage VDDI, an analog ground voltage AVEE (also referred to as an analog negative power supply voltage), and an analog power supply voltage AVDD. The internal digital power supply voltage VDDI may power the digital circuit inside the chip to be tested, and is usually a positive voltage. The analog ground voltage AVEE may provide a negative power supply voltage for the analog circuit inside the chip to be tested. The analog positive power supply voltage AVDD may provide a positive power supply voltage for the analog circuit inside the chip to be tested.

[0044] In a variation, the power supply signal may also be a current signal or a power signal. That is, the chip aging system may provide current or power to the chip to be tested to support the normal operation of the chip to be tested.

[0045] It should be noted that the aging plug-in board can also provide any other feasible signal type according to the actual application scenario, and this application does not limit this.

[0046] In a specific embodiment, the control instruction includes a voltage value of the power supply signal.

[0047] For example, the type of the chip to be tested 20 is 4010Q3A1G, and the central control controller 101 determines that its corresponding AVDD is 1.32V, VDDI is 2.5V, and AVEE is -2V, so the central control controller 101 carries the voltage values ​​of the above power supply signals in the control instruction, so that the aging board generates AVDD of 1.32V, VDDI of 2.5V, and AVEE of -2V, which are provided to the chip to be tested 4010Q3A1G.

[0048] In another specific embodiment, the control instruction includes index information, and the index information is used to uniquely identify the voltage value of the power supply signal.

[0049] In this embodiment, the central control 101 and the aging board 102 may store the corresponding relationship between the index information and the power supply signal, so that the control instruction may only include the index information, thereby reducing the signaling overhead.

[0050] For example, the type of the chip to be tested 20 is 4010Q3A1G, and the central control controller 101 determines that its corresponding AVDD is 1.32V, VDDI is 2.5V, AVEE is -2V, and its corresponding index number is 3. Therefore, the central control controller 101 carries the index number 3 in the control instruction, and the aging board can determine that AVDD is 1.32V, VDDI is 2.5V, and AVEE is -2V according to the index number 3 and the corresponding relationship between the stored index information and the power supply signal. The aging board generates the above voltages and provides them to the chip to be tested 4010Q3A1G.

[0051] In a non-limiting example, see Figure 2 In order to support the communication between the aging board 102 and the central controller 101, a communication interface can be set on the aging board 102. The aging board 102 is coupled to the central controller 101 through the communication interface, and the communication interface can receive control instructions.

[0052] Accordingly, in order to support the aging board 102 to power various types of chips under test 200 , multiple test interfaces can be set in the aging board, each test interface is used to connect a type of chip under test, and each test interface is used to output a corresponding power supply signal to the chip under test 20 .

[0053] For example, taking the example that the burn-in board supports the six types of chips shown in Table 1, six test interfaces can be set in the burn-in board, which are respectively used to access the six types of chips.

[0054] Furthermore, the aging board 102 may also include a driving interface, through which the aging board 102 provides driving signals to the chip to be tested, such as clock signals, data signals, control signals, etc. Through the driving signals, the chip can be placed in an operating state similar to that in actual use during the test, so as to evaluate its performance and reliability in real scenarios.

[0055] In a specific implementation, the test interface and / or the driver interface may have different interface specifications to suit different types of chips to be tested. For example, the interface types may be the following: built-in self-test (BIST), mobile industry processor interface (MIPI), quad serial peripheral interface (QSPI), etc.

[0056] In a non-limiting example, see Figure 3 The aging board 102 may include a power module 1021. The power module 1021 is used to receive a control instruction and generate a power supply signal according to the control instruction.

[0057] In this embodiment, the aging plug board itself has a voltage generation function and an instruction parsing function, and can parse the information of the power supply signal carried in the control instruction.

[0058] Exemplarily, the burn-in board includes a processor, in which a power module 1021 is provided. The power module 1021 receives a control instruction including a voltage value of a power supply signal, and generates a voltage with a corresponding voltage value and provides it to the chip 20 to be tested.

[0059] In another non-limiting embodiment, see Figure 4 The chip aging system further includes a power board 103. The power board 103 is coupled to the central control controller 101, can receive control instructions from the central control controller 101, and generate and output power signals to the aging board 102 according to the control instructions. The aging board 102 is coupled to the chip to be tested 20, and forwards the power signals to the chip to be tested 20.

[0060] Different from the above-mentioned embodiment, in this embodiment, the aging board itself does not have a voltage generation function, and is only used to forward the power supply signal of the power board 103 to the chip under test 20.

[0061] In a non-limiting embodiment, the chip aging system further includes an aging device (not shown), which is used to provide an aging environment for at least one chip 20 to be tested. The aging environment is defined by aging parameters, which include temperature and / or humidity.

[0062] Exemplarily, the aging equipment may be a test chamber, and temperature and / or humidity settings may be performed to simulate the actual operating environment of the chip.

[0063] The embodiment of the present application can be used as a sample loading platform during reliability testing, which can solve the problem of numerous aging boards in the laboratory, improve operation accuracy and stability, and provide better management and control.

[0064] In a non-limiting embodiment, the present application also discloses a method for powering an aged chip, the method comprising the following steps:

[0065] In step 501, the central control unit determines the information of the power supply signal according to the type of the input chip to be tested, and outputs a control instruction, wherein the control instruction includes the information of the power supply signal.

[0066] In step 502, the aging board generates and outputs a power supply signal according to a control instruction.

[0067] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0068] It is understandable that, in a specific implementation, the power supply method for the aged chip can be implemented in the form of a software program, and the software program runs in a processing module integrated inside the chip or chip module. The method can also be implemented in the form of software combined with hardware, which is not limited in this application.

[0069] Exemplarily, the software program may include two parts, the first part runs in the central control controller, and step 501 is executed by the central control controller; the second part runs in the aging board, such as the power module of the aging board, to execute step 502.

[0070] Regarding the various modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run in the processing module integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units can be implemented in the form of software programs. It is implemented in the form of a software program, which runs on the processing module integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal equipment, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal equipment, or, at least some modules / units can be implemented in the form of a software program, which runs on the processing module integrated inside the terminal equipment, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0071] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0072] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0073] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0074] The "connection" that appears in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.

[0075] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination. The mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, which may be electrical, mechanical or other forms.

[0076] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0077] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0078] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A chip aging system, characterized in that: Used to supply power to at least one chip to be tested, the chip aging system comprises: A central control controller, used to determine the information of the power supply signal according to the type of the chip to be tested input, and output a control instruction, wherein the control instruction includes the information of the power supply signal; The aging plug board is used to generate and output the power supply signal according to the control instruction.

2. The chip aging system according to claim 1, characterized in that: The aging plug-in board comprises: A communication interface, used for receiving the control instruction; A plurality of test interfaces, each test interface is used to access a type of chip to be tested, and each test interface is used to output the power supply signal, and the power supply signal is generated based on the control instruction.

3. The chip aging system according to claim 1, characterized in that: The aging plug-in board comprises: The power supply module is used to receive the control instruction and generate the power supply signal according to the control instruction.

4. The chip aging system according to claim 1, characterized in that: The central control stores various chip types and their corresponding power supply signal voltage values; The central controller searches for a corresponding voltage value according to the type of the chip to be tested input, to serve as information of the power supply signal.

5. The chip aging system according to claim 1, characterized in that: The control instruction includes information of the power supply signal, including: The control instruction includes the voltage value of the power supply signal; or, The control instruction includes index information, and the index information is used to uniquely identify the power supply signal.

6. The chip aging system according to claim 1, characterized in that: The power supply signal includes at least one of the following: Internal digital power supply voltage, analog ground voltage, analog power supply voltage.

7. The chip aging system according to any one of claims 1 to 6, characterized in that: The central control unit and the aging plug-in board are integrated in the same chip.

8. The chip aging system according to any one of claims 1 to 6, characterized in that: Also includes: The aging equipment is used to provide an aging environment for the at least one chip to be tested, wherein the aging environment is defined by aging parameters, and the aging parameters include temperature and / or humidity.

9. A power supply method for an aging chip, characterized in that: include: The central control controller determines the information of the power supply signal according to the type of the chip to be tested input, and outputs a control instruction, wherein the control instruction includes the information of the power supply signal; The aging plug-in board generates and outputs the power supply signal according to the control instruction.

10. A terminal device, characterized in that: include: The chip aging system according to any one of claims 1 to 7.

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