Heterogeneous virtualization platform virtual machine migration method and system

Abstract

The invention provides a heterogeneous virtualization platform virtual machine migration method and system.The method comprises the steps that a segment is intercepted from binary codes in an executable file of a source architecture, and part of the binary codes are obtained; obtaining first running data of partial binary codes running on the source architecture machine; for N heterogeneous chip systems of the heterogeneous virtualization platform, translating and running part of the binary codes to obtain N pieces of second running data of the part of the binary codes running on the N heterogeneous chip systems; determining a target architecture system and a target translation process according to the architecture of the N heterogeneous chip systems based on the first operation data and the N second operation data; based on the target architecture system and the target translation process, translating the source architecture executable file through one or more of a static translator, a dynamic translation actuator and an interpreter to obtain an executable file used for running on a target architecture machine; therefore, the virtual machine migration effect of the heterogeneous virtualization platform is improved.

Description

Technical Field

[0001] The present application relates to the technical field of heterogeneous chip virtual machine migration, and in particular to a method and system for heterogeneous virtualization platform virtual machine migration. Background Art

[0002] China Coal Technology and Engineering Mining Research Institute has built a large number of digital systems during its digital transformation. In order to manage these systems as a whole, it has built corresponding computer rooms and hardware equipment. On this basis, it has adopted virtualization hyper-convergence technology to allocate corresponding virtual machine resources to these systems.

[0003] Previously, heterogeneous virtualization platforms were mainly based on X86 architecture instruction sets and ARM architecture instruction sets. In order to respond to the national information and innovation industry policy, domestic CPU chips such as Hygon, Kunpeng, Zhaoxin, Loongson, and Shenwei were selected, including instruction set architectures such as X86, ARM, LoognArch, MIPS, SW64, and RISC-V. It is particularly important to migrate virtual machines between different chip architectures on heterogeneous virtualization platforms to achieve better operating results for the migrated virtual machines. For example, the technology of automated migration from X86 to other domestic instruction set architectures is particularly important. Summary of the invention

[0004] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the first objective of the present application is to propose a method for migrating virtual machines on a heterogeneous virtualization platform, thereby improving the effect of virtual machine migration on a heterogeneous virtualization platform.

[0006] The second objective of the present application is to provide a virtual machine migration system for a heterogeneous virtualization platform.

[0007] The third objective of the present application is to provide an electronic device.

[0008] A fourth objective of the present application is to provide a computer-readable storage medium.

[0009] A fifth object of the present application is to provide a computer program product.

[0010] To achieve the above-mentioned purpose, the first embodiment of the present application proposes a method for migrating virtual machines on a heterogeneous virtualization platform, comprising:

[0011] intercepting a section of the binary code in the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine;

[0012] For N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the part of the binary code to obtain N second running data of the part of the binary code running on the N heterogeneous chip systems;

[0013] Based on the first operation data and the N second operation data, determine the target architecture base according to the architectures of the N heterogeneous chip systems and select a target translation process from a plurality of translation processes; wherein the plurality of translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by a static translator and a dynamic translation executor;

[0014] Based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

[0015] To achieve the above-mentioned purpose, the second embodiment of the present application proposes a heterogeneous virtualization platform virtual machine migration system, including:

[0016] The system includes an instruction selector, a static translator, a dynamic translation executor and an interpreter, wherein the instruction selector is used to:

[0017] intercepting a section of the binary code in the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine;

[0018] For N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the part of the binary code to obtain N second running data of the part of the binary code running on the N heterogeneous chip systems;

[0019] Based on the first operation data and the N second operation data, determine the target architecture base according to the architectures of the N heterogeneous chip systems and select a target translation process from a plurality of translation processes; wherein the plurality of translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by a static translator and a dynamic translation executor;

[0020] Based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

[0021] To achieve the above-mentioned purpose, the third aspect embodiment of the present application proposes an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method described in the first aspect.

[0022] To achieve the above-mentioned purpose, the fourth aspect of the present application proposes a computer-readable storage medium, in which computer-readable storage medium is stored computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the method described in the first aspect.

[0023] To achieve the above-mentioned purpose, the fifth aspect of the present application proposes a computer program product, including a computer program, which implements the method described in the first aspect when executed by a processor.

[0024] The present application provides a method and system for migrating virtual machines on a heterogeneous virtualization platform. According to the running data of a portion of binary code of an intercepted source architecture executable file in each heterogeneous chip system, a target architecture base and a target translation process are selected; based on the target architecture base and the target translation process, the source architecture executable file is translated; and then, according to the translation efficiency, it is determined whether the current target architecture base and the target translation process can obtain an ideal translation result. If the translation result is not ideal, the target architecture base and the target translation process are adjusted to re-translate and obtain the executable file of the target architecture system; thereby improving the effect of virtual machine migration on the heterogeneous virtualization platform.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 A schematic diagram of a flow chart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of a flow chart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in another embodiment of the present application;

[0029] Figure 3 A schematic diagram of a flow chart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in another embodiment of the present application;

[0030] Figure 4A schematic diagram of a flow chart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in another embodiment of the present application;

[0031] Figure 5 A block diagram of a virtual machine migration system for a heterogeneous virtualization platform provided in an embodiment of the present application;

[0032] Figure 6 A block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0034] The following describes the heterogeneous virtualization platform virtual machine migration method, device and equipment of the embodiments of the present application with reference to the accompanying drawings.

[0035] Figure 1 A flowchart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in an embodiment of the present application.

[0036] It should be noted that the executor of the heterogeneous virtualization platform virtual machine migration method in the embodiment of the present application is the heterogeneous virtualization platform virtual machine migration device in the embodiment of the present application, and the heterogeneous virtualization platform virtual machine migration device can be configured in an electronic device so that the electronic device can execute the heterogeneous virtualization platform virtual machine migration function.

[0037] like Figure 1 As shown, the heterogeneous virtualization platform virtual machine migration method includes the following steps:

[0038] Step 101, intercepting a section from the binary code in the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine;

[0039] In some embodiments, the first running data includes a first execution time when the portion of the binary code is run on the source architecture machine.

[0040] Exemplarily, the source architecture executable file is an X86 executable file, a section of binary code is intercepted from the X86 binary code of the X86 executable file, and the section of binary code is run on an X86 machine to obtain first running data.

[0041] Step 102: for N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run part of the binary code to obtain N second running data of the part of the binary code running on the N heterogeneous chip systems.

[0042] As an implementation method, for the N heterogeneous chip systems of the heterogeneous virtualization platform, part of the binary code is translated by a static translator to obtain N executable codes corresponding to the N heterogeneous chip systems respectively; the N executable codes are run on the N heterogeneous chip systems respectively to obtain N second running data of part of the binary code running on the N heterogeneous chip systems.

[0043] In some embodiments, the second operating data includes a second execution time, CPU resource occupancy, memory resource occupancy, and storage resource occupancy value of a portion of the binary code running on the nth heterogeneous chip system; wherein 1≤n≤N.

[0044] Exemplarily, the mining research institute includes N heterogeneous chip systems, such as LoognArch, MIPS, SW64, RISC-V, etc.

[0045] Step 103, based on the first operating data and the N second operating data, determine the target architecture base according to the architecture of the N heterogeneous chip systems and select a target translation process from multiple translation processes; wherein the multiple translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by a static translator and a dynamic translation executor.

[0046] As a way to achieve this, Figure 2 As shown, a method for determining a target architecture base and a target translation process includes:

[0047] Step 201 , obtaining the execution efficiency of the partial binary code running on the nth heterogeneous chip system based on the first execution time and the second execution time of the partial binary code running on the nth heterogeneous chip system.

[0048] Step 202 , based on the execution efficiency, CPU resource occupancy, memory resource occupancy and storage resource occupancy of the partial binary code running on the nth heterogeneous chip system, obtain the resource values ​​of N heterogeneous chip systems.

[0049] Step 203 , based on the resource values ​​of the N heterogeneous chip systems and according to the architectures of the N heterogeneous chip systems, a target architecture system is determined and a target translation process is selected from a plurality of translation processes.

[0050] As an implementation method, the execution efficiency is obtained by the following formula:

[0051] 1-(t2-t1) / t1

[0052] Wherein, t1 is the first execution time, and t2 is the second execution time.

[0053] In some embodiments, the resource values ​​of N heterogeneous chip systems are calculated by the following formula (1):

[0054]

[0055] Among them, Vn is the resource value of the nth heterogeneous chip system, λ1, λ2, and λ3 are all adjustment parameters, which are adjusted according to the actual situation and importance of the CPU, memory, and storage of the virtualization platform; En is the execution efficiency running on the nth heterogeneous chip system, Cn is the CPU resource occupancy running on the nth heterogeneous chip system, Mn is the memory resource occupancy running on the nth heterogeneous chip system, and Sn is the storage resource occupancy value running on the nth heterogeneous chip system.

[0056] In some embodiments, Figure 3 As shown, based on the resource value of the nth heterogeneous chip system, a method for determining a target architecture base according to the architectures of N heterogeneous chip systems and selecting a target translation process from multiple translation processes includes:

[0057] Step 301: Determine a target heterogeneous chip system with a maximum resource value based on the resource values ​​of N heterogeneous chip systems.

[0058] Step 302, determining a target architecture system according to the architecture of the target heterogeneous chip system.

[0059] Step 303: When the resource value of the target heterogeneous chip system is greater than the upper threshold of the resource value, a static translation process is selected as the target translation process.

[0060] Step 304: When the resource value of the target heterogeneous chip system is less than or equal to the upper threshold of the resource value and greater than or equal to the lower threshold of the resource value, a dynamic translation process is selected as the target translation process.

[0061] It should be noted that the translation process also includes the interpreter translation process, and the interpreter translation process includes the interpreter direct running process.

[0062] Exemplarily, from V1...Vn, the heterogeneous chip system with Max(Vn) is selected for priority allocation. For example, the V value of the Loongson architecture system is the highest, so the X86 executable code is preferentially translated into the Loongson binary code, that is, the Loongson binary is used as the target architecture binary. The upper threshold of the resource value is 1, and the lower threshold of the resource value is 0. When 0<V of the target heterogeneous chip system<=1, the dynamic translation process is selected; when V of the target heterogeneous chip system>1, the static translation process is selected.

[0063] It should be noted here that when Vn is a negative number, it means that the heterogeneous chip system resources are exhausted and cannot be allocated.

[0064] Step 104, based on the target architecture binary and the target translation process, the source architecture executable file is translated through one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

[0065] As a way to achieve this, Figure 4 As shown, based on the target architecture binary and the target translation process, a method for obtaining an executable file for running on a target architecture machine by translating a source architecture executable file through one or more of a static translator, a dynamic translation executor and an interpreter includes:

[0066] Step 401, when the target translation process is a static translation process, a source architecture executable file is translated by a static translator to obtain a translated target executable file.

[0067] Step 402, when the target translation process is a dynamic translation process, the source architecture executable file is translated by a static translator and a dynamic translation executor in a static and dynamic combination manner to obtain a translated target executable file;

[0068] Step 403, obtaining the translation efficiency of the static translator.

[0069] Step 404, based on the translation efficiency and a preset threshold, determine a new target architecture base, a new target translation process, and whether to use the translated target executable file as one or more of the executable files for running on the target architecture machine.

[0070] As an implementation manner, a method for obtaining the translation efficiency of a static translator includes: obtaining the translation amount of the static translator as T, the total code amount as C, calculating T / C, and obtaining the translation efficiency.

[0071] In some embodiments, a method is provided for translating a source architecture executable file in a static and dynamic combination manner by a static translator and a dynamic translation executor to obtain a translated target executable file; the method includes: performing offline translation and deep optimization on the binary code in the source architecture executable file by a static translator to obtain a static translation result; and transferring the static translation result to a dynamic translation executor; loading the binary code and the static translation result in the source architecture executable file by the dynamic translation executor; performing online translation and optimization on the untranslated part of the binary code in the source architecture executable file, and merging the online translation and optimization results into the static translation results to obtain a translated target executable file.

[0072] In some embodiments, the preset thresholds include a first efficiency threshold a1 and a second efficiency threshold a2, and based on the translation efficiency and the preset thresholds, a method for determining a new target architecture binary, a new target translation process, and whether to use the translated target executable file as one or more of the executable files for running on the target architecture machine includes:

[0073] When the translation efficiency is less than or equal to the first efficiency threshold, directly running the source architecture executable file through the interpreter to obtain an executable file for running on the target architecture machine;

[0074] When the translation efficiency is greater than the first efficiency threshold and less than the second efficiency threshold, and the target translation process is a dynamic translation process, the source architecture executable file is retranslated by the static translator to obtain the translated target executable file and return to reacquire the translation efficiency of the static translator;

[0075] When the translation efficiency is greater than the first efficiency threshold and less than the second efficiency threshold, and the target translation process is a static translation process, returning to re-determine a new target architecture base and a target translation process from the N heterogeneous chip systems based on the first operation data and the second operation data;

[0076] When the translation efficiency is greater than the second efficiency threshold, the translated target executable file is used as an executable file for running on the target architecture machine.

[0077] It can be understood that when T / C < a1, it indicates that the currently selected target translation process has a very poor translation effect on the binary code of the source architecture. Most of the code translations fail, and the interpreter needs to be directly run to execute the binary code of the source architecture. When a1 < T / C <= a2, if the target translation process is a dynamic translation process, the binary code of the source architecture is re-translated directly through the static translator; if the target translation process is a static translation process, a higher system with a V value lower than the current target architecture system V value is returned to re-perform the target translation process. When T / C > a2, it indicates that the code obtained by the current target translation process is relatively ideal and can be migrated and used on the target machine.

[0078] The virtual machine migration method for a heterogeneous virtualization platform according to an embodiment of the present application selects a target architecture base and a target translation process based on the running data of a partial binary code of an executable file of a source architecture intercepted on various heterogeneous chip systems; translates the executable file of the source architecture based on the target architecture base and the target translation process; and then determines whether the current target architecture base and the target translation process can obtain an ideal translation result according to the translation efficiency. In the case where the translation result is not ideal, the target architecture base and the target translation process are adjusted to re-perform the translation to obtain an executable file of the target architecture system; thereby improving the virtual machine migration effect of the heterogeneous virtualization platform.

[0079] To clearly illustrate the above embodiments, specific examples are now used for illustration. Figure 5 It is a block diagram of a virtual machine migration system for a heterogeneous virtualization platform provided by an embodiment of the present application. As Figure 5 shown, the virtual machine migration method of the heterogeneous virtualization platform of the present application is applied to a virtual machine migration system for a heterogeneous virtualization platform. The virtual machine migration system for a heterogeneous virtualization platform includes an instruction selector 501, a static translator 502, a dynamic translation executor 503, and an interpreter 504. The instruction selector 501 is used for:

[0080] Intercept a section from the binary encoding in the executable file of the source architecture to obtain a partial binary code; and obtain first running data of the partial binary code running on the source architecture machine;

[0081] For N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the partial binary code to obtain N second running data of the partial binary code running on the N heterogeneous chip systems;

[0082] Based on the first operation data and the N second operation data, determine the target architecture base according to the architectures of the N heterogeneous chip systems and select a target translation process from a plurality of translation processes; wherein the plurality of translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator 502, and the dynamic translation process includes a static and dynamic combined translation process implemented by the static translator 502 and a dynamic translation executor 503;

[0083] Based on the target architecture binary and the target translation process, the source architecture executable file is translated through one or more of the static translator 502, the dynamic translation executor 503 and the interpreter 504 to obtain an executable file for running on the target architecture machine.

[0084] The following is an explanation using X86 source binary code as an example.

[0085] In order to combine the advantages of static translator 502 and dynamic translation executor 503 and avoid their shortcomings, a binary translation system combining static and dynamic is constructed. This binary translation system includes a static translator 502 and a dynamic translation executor 503. When working, the format of the target code to be translated is first selected by the instruction selector 501, and the dynamic translation executor 503 or the static translator 502 is directly translated according to the performance. Among them, the static translator 502 performs offline translation and deep optimization on the X86 executable file, and then hands the translated static translation result to the dynamic translation executor 503. The dynamic translation executor 503 loads the source file of X86 and the static translation result together. If it is found that there is still an X86 code that has not been translated during the execution process, the dynamic translator is called to perform online translation and optimization, and the results of online translation and optimization are merged into the static translation result for use together.

[0086] Among them, the role of the static translator 502 is to translate and optimize the X86 source binary code, generate executable code on the target virtual machine, and store it in the form of a file. And the static translator 502 can choose to translate and optimize the X86 source binary code with the help of the dynamic translation information of the dynamic translation executor 503. The role of the static translator 502 is to translate the X86 binary before the program is executed to generate a static translation result. The static translation result includes the translated target binary code and some auxiliary information. The static translator 502 performs offline translation, and the time of offline translation does not occupy the running time. The static translation result obtained by translation can be used by the dynamic translation executor 503 for many times; therefore, the static translator 502 can achieve some more powerful optimizations and generate more efficient target architecture codes. However, the static translator 502 also has some limitations, such as the inability to identify the targets of indirect jumps and indirect calls, and the inability to process code self-modification programs, etc., which must be solved by the dynamic translation executor 503.

[0087] The main optimizations implemented by the static translator 502 include local register allocation (LRA), global register allocation (GRA) and extended basic block optimization (EBO), among which local register allocation refers to the register allocation algorithm within a basic block; global register allocation refers to the register allocation algorithm across basic blocks; extended basic block optimization refers to many compilation routine optimizations across basic blocks, such as constant propagation, dead code removal, etc.

[0088] In order to solve the limitation of static translator 502 that it cannot handle indirect jump targets, semantic enhancement can be used to successfully identify a class of indirect jump targets, which largely overcomes this limitation of static translator 502 and improves the performance of system migration.

[0089] In some embodiments, the structure of static translator 502 is as follows Figure 3 As shown, it includes a file loading unit, a translation unit, an optimization unit and a translation result output unit, wherein the file loading unit is used to load the X86 source binary code and the translation information generated by the dynamic translation executor 503 into the memory, and then the translation unit translates it, and the translated intermediate result is handed over to the optimization unit for optimization (the translation unit will also perform certain optimizations during the translation process), and finally the translation result output unit outputs the output results of the translation unit and the optimization unit in a certain format to obtain a static translation result, which is passed to the dynamic translation executor 503 for use.

[0090] Among them, the function of the dynamic translation executor 503 is to use the static translation results of the static translator 502 to execute the target binary program through translation, local code execution and interpretation. The execution unit of the program is a Block, that is, a group of linear X86 instruction codes, until a jump instruction is encountered. Dynamic translation is performed during the execution process, and the dynamic translation information results are recorded for use by the static translator 502. The input of the dynamic part of the heterogeneous virtualization platform virtual machine migration system is the file generated by the static part and the binary source code of X86. The dynamic part interprets or translates and executes the generated local code in units of source code Block.

[0091] The function of the dynamic translation executor 503 is to make full use of the translation results of the static translator 502 for the X86 source binary file, and assist in the interpretation and dynamic translation method to achieve the effect of correctly executing the X86 executable file on the target machine. The system structure of the dynamic translation executor 503 is shown in the figure

[0092] In some embodiments, the dynamic translation executor 503 includes a dynamic master control module, a file loading module, a command line parameter analysis module, a disassembly module, a native code execution environment module, an interpretation module, a translation module and an optimization module, wherein the dynamic master control module is responsible for coordinating the work of each module, the file loading module is responsible for loading the X86 executable file and the translation result of the static translator 502, the command line parameter analysis module is responsible for analyzing the command line parameters when the program is started, and obtaining the translated program information, the disassembly module is responsible for disassembling the X86 executable code and forming a basic unit of dynamic translation or interpretation, and the native code execution environment module is responsible for constructing the context environment for the operation of the native code, including register mapping, native code loading and execution, context switching, memory management, etc. The interpretation module is responsible for interpreting and executing the disassembled X86 executable code, the translation module is responsible for translating the disassembled X86 executable code, and the optimization module includes optimization measures taken to improve the performance of the binary translation system. The algorithms and implementations of the main modules are described in detail below.

[0093] The dynamic master control module is the master control module for dynamic execution, which controls the interpretation, translation and execution of the X86 Block and the local code. Starting from the X86 entry address, the module simulates the execution semantics of the X86 program. For basic blocks with local code, the local code is directly executed. For basic blocks without local code, the local code is translated first and then executed. This module ends until the simulated X86 program ends. The execution flow of the dynamic execution master control module in the dynamic translation part of the binary translation system divides the master control module into four main sub-modules, namely the basic block division module, the interpreter 504 module, the dynamic translation module, and the local code execution module. The dynamic master control module includes the following implementation flow:

[0094] 1) Assign the entry address to pc (pc is the program counter of the X86 code, that is, the virtual address of the X86 code, the X86 address that this module will translate and execute). Build information based on the content of pc. (The content in information will be used when translating or interpreting).

[0095] 2) Determine whether the X86 address corresponding to the PC already has local code. If local code exists, go to 7) to execute the local code.

[0096] 3) Build X86 Block (Block division).

[0097] 4) Determine whether the Block with pc as the entry needs to be interpreted or translated. If the Block is interpreted, go to 5), otherwise go to 6) the local code translation submodule.

[0098] 5) The interpreter 504 simulates X86 instructions, updates pc, and goes to 8).

[0099] 6) Translate the pc entry block and establish a link with the existing local code.

[0100] 7) The local code is executed and some information about the build information is returned after execution, including updating the PC.

[0101] 8) Determine whether the X86 program has ended. If so, this module ends. Otherwise, record the indirect target address; go to 2).

[0102] The disassembly module is responsible for dividing the blocks and disassembling the blocks, recording the information into IR1. The instructions at the end of the block are: branch, jmp^indirect jump, indirect call, ret and halt. The disassembly module implements the following process:

[0103] 1) Assign block->entry_vaddr to pc.

[0104] 2) Disassemble the instruction pointed to by pc.

[0105] 3) Fetch the next instruction.

[0106] 4) Determine whether the instruction type is a Block end instruction; otherwise, go to 2).

[0107] 5) Store the disassembled IR1 of the block into the irl cache of the block.

[0108] 6) Set the irl num of the block to the IR1 number, irl addr to the irl cache address, and mark the flag of the block as disassembled.

[0109] The disassembly module is mainly used to disassemble a given dynamic translation unit. It takes the entry pc of the translation unit as a parameter, disassembles the translation unit, stores the disassembly result in IR1, and records the block information.

[0110] The instructions of the X86 file executed by the dynamic translation executor 503 are divided into basic blocks. The disassembly module needs to disassemble each instruction in the basic block one by one, and record the disassembly result in the intermediate representation of the X86 instruction until the last control transfer instruction of the basic block is identified, and the execution process of the dynamic disassembly is completed.

[0111] The interpretation module consists of two parts. One part is the running part, which is executed after the disassembly module completes the operation and represents the X86 binary code as the IR1 intermediate representation. This module simulates the execution of the X86 instructions one by one; the other part is the initialization part, which initializes the virtual execution environment before executing the interpretation of the instructions. Among them, the running part consists of a general control function and a series of instruction interpretation functions. The general control function is a general scheduler, which interprets each instruction cyclically. The interpretation of specific instructions calls each specific instruction interpretation function (almost all X86 instructions correspond to an instruction interpretation function). The interpretation of each instruction usually pre-analyzes the meaning of the instruction, and then interprets it with instructions of the same semantics and executes it at the same time. The initialization part only completes the initialization of the virtual operating environment.

[0112] The translation module has two submodules, namely the flag analysis module and the instruction translation module. The flag analysis module works before the instruction translation, which can greatly improve the efficiency of the translated IR2 instruction sequence; its function is to translate the X86 source program generated by the disassembly module and generate an IR2 instruction sequence with the same semantics. At the same time, the modules closely related to the translation, such as dynamic register allocation and flag calculation, are organized to work simultaneously. The most basic unit of this module is a series of instruction translation functions, each of which corresponds to an X86 instruction with the same operation semantics. The module starts with the general entry function Translate(), and after conditional judgment of translation tags, selection of loading related functions according to compilation options, etc., it indirectly calls this series of X86 instruction translation functions to implement the semantics of the source program. In the dynamic translation process, important related modules such as flagpattern, flag calculation, and register dynamic allocation work simultaneously, among which the flag pattern module and the flag calculation module can effectively improve the efficiency of the translated IR2 instructions.

[0113] The local code execution environment module is responsible for constructing the context environment for local code execution. When the BT controller finds that a block has been translated, this module is called to start the execution of the block. The context switch is required when switching from the BT controller to the local code execution and from the local code execution to the controller. Since the local code linking technology is used in the translation, multiple blocks may be executed at one time for the local code execution.

[0114] In order to implement the above embodiment, the present application also proposes an electronic device. Figure 6 , Figure 6 is a block diagram of an electronic device provided in an embodiment of the present application. Figure 6 As shown, the electronic device 600 includes: a processor 601, and a memory 602 communicatively connected to the processor 601; the memory 602 stores computer-executable instructions; the processor 601 executes the computer-executable instructions stored in the memory to implement the method provided in the aforementioned embodiment.

[0115] In order to implement the above embodiments, the present application also proposes a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the methods provided by the above embodiments.

[0116] In order to implement the above embodiments, the present application also proposes a computer program product, including a computer program, which implements the methods provided by the above embodiments when executed by a processor.

[0117] The collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in this application are in compliance with relevant laws and regulations and do not violate public order and good morals.

[0118] It should be noted that personal information from users should be collected for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign the agreement / authorization including authorization of relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others who have access to personal information data comply with its privacy policy and procedures.

[0119] The present application is expected to provide an implementation scheme for users to selectively block the use or access of personal information data. That is, the present disclosure is expected to provide hardware and / or software to prevent or block access to such personal information data. Once the personal information data is no longer needed, the risk can be minimized by limiting data collection and deleting the data. In addition, when applicable, such personal information is de-identified to protect the privacy of the user.

[0120] In the description of the aforementioned embodiments, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0121] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0122] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0123] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0124] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0125] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0126] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0127] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for migrating virtual machines on a heterogeneous virtualization platform, characterized in that: The method comprises the following steps: intercepting a section of the binary code in the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine; For N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the part of the binary code to obtain N second running data of the part of the binary code running on the N heterogeneous chip systems; Based on the first operation data and the N second operation data, determine the target architecture base according to the architectures of the N heterogeneous chip systems and select a target translation process from a plurality of translation processes; wherein the plurality of translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by a static translator and a dynamic translation executor; Based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

2. The method according to claim 1, characterized in that: The first operation data includes a first execution time of the part of the binary code running on the source architecture machine, and the second operation data includes a second execution time, a CPU resource occupancy rate, a memory resource occupancy rate, and a storage resource occupancy value of the part of the binary code running on the nth heterogeneous chip system; wherein 1≤n≤N; The method of determining a target architecture base and selecting a target translation process from a plurality of translation processes based on the first operation data and the N second operation data according to the architectures of the N heterogeneous chip systems comprises: Obtaining, based on the first execution time and a second execution time of the part of the binary code running on the nth heterogeneous chip system, an execution efficiency of the part of the binary code running on the nth heterogeneous chip system; Obtain resource values ​​of N heterogeneous chip systems based on the execution efficiency, CPU resource occupancy rate, memory resource occupancy rate, and storage resource occupancy value of the partial binary code running on the nth heterogeneous chip system; Based on the resource values ​​of the N heterogeneous chip systems, a target architecture system is determined according to the architectures of the N heterogeneous chip systems, and a target translation process is selected from a plurality of translation processes.

3. The method according to claim 2, characterized in that The method of determining a target architecture system based on the resource value of the nth heterogeneous chip system and selecting a target translation process from a plurality of translation processes according to the architectures of the N heterogeneous chip systems comprises: Based on the resource values ​​of the N heterogeneous chip systems, determine a target heterogeneous chip system with a maximum resource value; Determining a target architecture system according to the architecture of the target heterogeneous chip system; When the resource value of the target heterogeneous chip system is greater than the resource value upper limit threshold, selecting a static translation process as a target translation process; When the resource value of the target heterogeneous chip system is less than or equal to the upper threshold of the resource value and greater than or equal to the lower threshold of the resource value, the dynamic translation process is selected as the target translation process.

4. The method according to claim 2, characterized in that: The method of obtaining resource values ​​of N heterogeneous chip systems based on the execution efficiency, CPU resource occupancy rate, memory resource occupancy rate and storage resource occupancy value of the partial binary code running on the nth heterogeneous chip system comprises: obtaining resource values ​​of N heterogeneous chip systems based on the execution efficiency, the CPU resource occupancy rate, the memory resource occupancy rate and the storage resource occupancy value through a first formula, wherein the first formula is expressed as follows: Among them, Vn is the resource value of the nth heterogeneous chip system, λ1, λ2, and λ3 are all adjustment parameters, which are adjusted according to the actual situation and importance of the CPU, memory, and storage of the virtualization platform; En is the execution efficiency running on the nth heterogeneous chip system, Cn is the CPU resource occupancy running on the nth heterogeneous chip system, Mn is the memory resource occupancy running on the nth heterogeneous chip system, and Sn is the storage resource occupancy value running on the nth heterogeneous chip system.

5. The method according to claim 1, characterized in that The translation process also includes an interpreter translation process, and the interpreter translation process includes an interpreter direct running process; based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine; including: When the target translation process is a static translation process, translating the source architecture executable file by the static translator to obtain a translated target executable file; When the target translation process is a dynamic translation process, the source architecture executable file is translated by the static translator and the dynamic translation executor in a dynamic and static combination manner to obtain a translated target executable file; Obtaining translation efficiency of the static translator; Based on the translation efficiency and a preset threshold, determine the new target architecture base, the new target translation process, and whether to use the translated target executable file as one or more of the executable files for running on the target architecture machine.

6. The method according to claim 5, characterized in that The preset threshold includes a first efficiency threshold and a second efficiency threshold, and the determining, based on the translation efficiency and the preset threshold, of a new target architecture binary, a new target translation process, and whether to use the translated target executable file as one or more of the executable files for running on the target architecture machine includes: When the translation efficiency is less than or equal to a first efficiency threshold, directly running the source architecture executable file through the interpreter to obtain an executable file for running on a target architecture machine; When the translation efficiency is greater than the first efficiency threshold and less than the second efficiency threshold, and the target translation process is a dynamic translation process, the source architecture executable file is retranslated by the static translator to obtain a translated target executable file and return to reacquire the translation efficiency of the static translator; When the translation efficiency is greater than the first efficiency threshold and less than the second efficiency threshold, and the target translation process is a static translation process, returning to re-determine a new target architecture system and a target translation process from the N heterogeneous chip systems based on the first operation data and the second operation data; When the translation efficiency is greater than the second efficiency threshold, the translated target executable file is used as the executable file for running on the target architecture machine.

7. The method according to claim 1, characterized in that The N heterogeneous chip systems for the heterogeneous virtualization platform, translating and running the part of the binary code to obtain N second running data of the part of the binary code running on the N heterogeneous chip systems; comprising: For the N heterogeneous chip systems of the heterogeneous virtualization platform, the static translator translates the part of the binary code to obtain N executable codes corresponding to the N heterogeneous chip systems respectively; The N executable codes are respectively run on the N heterogeneous chip systems to obtain N second running data of the partial binary code running on the N heterogeneous chip systems.

8. The method according to claim 5, characterized in that The method of translating the source architecture executable file by the static translator and the dynamic translation executor in a static and dynamic combination manner to obtain a translated target executable file comprises: The static translator performs offline translation and deep optimization on the binary code in the source architecture executable file to obtain a static translation result; and transmits the static translation result to the dynamic translation executor; The binary code in the source architecture executable file and the static translation result are loaded through the dynamic translation executor; the untranslated part of the binary code in the source architecture executable file is translated and optimized online, and the results of the online translation and optimization are merged into the static translation result to obtain the translated target executable file.

9. A virtual machine migration system for a heterogeneous virtualization platform, characterized in that: The system includes an instruction selector, a static translator, a dynamic translation executor and an interpreter, wherein the instruction selector is used to: intercepting a section of the binary code in the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine; For N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the part of the binary code to obtain N second running data of the part of the binary code running on the N heterogeneous chip systems; Based on the first operation data and the N second operation data, determine the target architecture base according to the architectures of the N heterogeneous chip systems and select a target translation process from a plurality of translation processes; wherein the plurality of translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by a static translator and a dynamic translation executor; Based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 8 when being executed by a processor.

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