Memory device, data verification method, device and system thereof and storage medium

Abstract

The invention discloses a memory device, a data verification method, device and system thereof and a storage medium, and relates to the technical field of storage, and the method comprises the following steps: receiving a storage access request sent by a network interconnection module through each user access interface; wherein the storage access request comprises an extended signal value; determining and analyzing a current processing request in the storage access request to obtain an expansion signal value in the current processing request; according to the extended signal value in the current processing request, calling a target data verification process, and carrying out storage data processing on the current processing request; according to the method, the storage controller can conveniently adopt the corresponding protection strategy to carry out data verification by utilizing the setting of the expansion signal value in the storage access request, so that the configuration flexibility is improved, finer data protection can be realized when all user branches access the memory equipment, and the user experience is improved. Therefore, the memory device can adapt to different customer requirements.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory device and a data verification method, device, system and storage medium thereof. Background Art

[0002] With the advent of the information age, the demand for high-speed data transmission and caching has also increased. Memory devices such as DDR (Double Data Rate), LPDDR (Low Power Double Data Rate, a type of DDR) and GDDR (Graphics Double Data Rate, graphics double data rate synchronous dynamic random access memory) are widely used in servers, civil and embedded systems, and have become indispensable components in modern circuit design.

[0003] AXI (Advanced eXtensible Interface, a bus protocol), as part of the AMBA (Advanced Microcontroller Bus Architecture, advanced microcontroller bus architecture) standard, is an advanced bus protocol developed for high-performance, high-bandwidth and low-latency system design. In order to better expand applications, the AXI protocol also specially designed QoS (Quality of Service, an additional signal for expanding AXI interface applications) signals for user customization.

[0004] At present, in the design of system-level architecture, the storage controller (such as DDR controller) in the memory device usually has multiple user access interfaces, but at the same specific time, only one user is allowed to access the memory device. After arbitration inside the storage controller, each user access interface can access the memory device in sequence. The memory device can be divided into multiple areas according to the address range, which are used to cache the data of different users, and choose whether to turn on data verification through register configuration. However, this method is limited to the divided address range and is bound to a specific user, which is very rigid; the user access interface of the storage controller is limited, and there are many independent user branches in the system, which are aggregated into one or more DDR user interfaces through similar network interconnection modules such as AXI Interconnector (AXI interconnector) and NIC400 (a network interconnector). When the data of a specific DDR user interface comes from different user branches, there are usually different data verification requirements, and it is impossible to achieve different verification requirements of each independent user branch of the same DDR user interface. Therefore, how to flexibly and conveniently configure the data verification method of different storage access requests and improve the degree of refinement of data protection is an urgent problem to be solved today. Summary of the invention

[0005] The purpose of the present invention is to provide a data verification method, device, system, memory device and computer-readable storage medium for a memory device, so as to flexibly and conveniently configure data verification methods for different storage access requests and improve the degree of refinement of data protection.

[0006] In order to solve the above technical problems, the present invention provides a data verification method for a memory device, which is applied to a storage controller in the memory device, comprising:

[0007] Receiving a storage access request sent by the network interconnection module through each user access interface; wherein the storage access request includes an extended signal value;

[0008] Determine and parse the current processing request in the storage access request to obtain the extended signal value in the current processing request; wherein the current processing request is any of the storage access requests;

[0009] According to the extended signal value in the current processing request, a target data verification process is called to perform storage data processing on the current processing request; wherein the target data verification process is a preset verification process corresponding to the extended signal value in the current processing request.

[0010] On the other hand, different extended signal values ​​correspond to different preset verification processes, and the preset verification process includes a data-free verification process and a data verification process, and the data verification process includes a cyclic redundancy check process and / or an error detection and correction process.

[0011] On the other hand, calling the target data verification process according to the extended signal value in the current processing request to perform storage data processing on the current processing request includes:

[0012] According to the correspondence between the preset extension signal value and the verification mode, the target data verification process is configured and called through the register configuration interface to perform storage data processing on the current processing request.

[0013] On the other hand, the memory device is a double rate synchronous dynamic random access memory, and the target data verification process is configured and called through a register configuration interface according to the correspondence between the preset extension signal value and the verification mode, and the storage data processing is performed on the current processing request, including:

[0014] Determining the preset verification mode corresponding to the extended signal value in the current processing request according to the correspondence between the preset extended signal value and the verification mode;

[0015] If the preset check mode is a cyclic redundancy check, the cyclic redundancy check function is configured to be turned on, the error detection and correction function is turned off, and the double rate synchronous dynamic random access memory particle mode register is configured to turn on the cyclic redundancy check function through the register configuration interface;

[0016] When the current processing request is a write operation, a check code of a cyclic redundancy check corresponding to the data to be written is calculated, and the data to be written and the check code are written into a double rate synchronous dynamic random access memory particle, so that the double rate synchronous dynamic random access memory particle uses the check code to perform a cyclic redundancy check on the data to be written and return a check result; when the current processing request is a read operation, the data to be read is read from the double rate synchronous dynamic random access memory particle, and the data to be read is sent to the network interconnection module;

[0017] If the preset check mode is error detection and correction, then through the register configuration interface, configure to turn off the cyclic redundancy check function, turn on the error detection and correction function, and configure the double rate synchronous dynamic random access memory particle mode register to turn off the cyclic redundancy check function;

[0018] When the current processing request is a write operation, an error detection and correction check code corresponding to the data to be written is calculated, and the data to be written and the error detection and correction check code are written into the double data rate synchronous dynamic random access memory particle; when the current processing request is a read operation, the data to be read and the corresponding error detection and correction check code are read from the double data rate synchronous dynamic random access memory particle, and the data to be read is verified using the read error detection and correction check code; if the verification is correct, the data to be read is sent to the network interconnection module.

[0019] On the other hand, the extension signal value in each of the storage access requests corresponds to a user branch of the network interconnect module.

[0020] The present invention also provides a data verification device for a memory device, which is applied to a storage controller in the memory device, and includes:

[0021] A request receiving unit, configured to receive a storage access request sent by the network interconnection module through each user access interface; wherein the storage access request includes an extended signal value;

[0022] an arbitration parsing unit, configured to determine and parse a current processing request in the storage access request to obtain an extended signal value in the current processing request; wherein the current processing request is any of the storage access requests;

[0023] A verification control unit is used to call a target data verification process according to the extended signal value in the current processing request to perform storage data processing on the current processing request; wherein the target data verification process is a preset verification process corresponding to the extended signal value in the current processing request.

[0024] The present invention also provides a memory device, comprising:

[0025] Memory for storing computer programs;

[0026] A storage controller is used to implement the steps of the data verification method for the memory device as described above when executing the computer program.

[0027] The present invention also provides a data verification system for a memory device, comprising: a network interconnection module and a memory device as described above; wherein the network interconnection module is used to configure an extended signal value for a storage access request sent by each user branch, and send the configured storage access request to the memory device through a user access interface.

[0028] On the other hand, configuring the extended signal value for the storage access request sent by each user branch includes:

[0029] According to the preset extension signal value corresponding to each of the user branches, an extension signal value is configured for the storage access request sent by each of the user branches.

[0030] In addition, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the data verification method for a memory device as described above are implemented.

[0031] A data verification method for a memory device provided by the present invention is applied to a memory controller in a memory device, comprising: receiving a storage access request sent by a network interconnection module through each user access interface; wherein the storage access request includes an extended signal value; determining and parsing a current processing request in the storage access request, and obtaining the extended signal value in the current processing request; wherein the current processing request is any storage access request; according to the extended signal value in the current processing request, calling a target data verification process, and performing storage data processing on the current processing request; wherein the target data verification process is a preset verification process corresponding to the extended signal value in the current processing request;

[0032] It can be seen that the present invention, by calling the target data verification process according to the extended signal value in the current processing request, performs storage data processing on the current processing request, and can utilize the setting of the extended signal value in the storage access request to enable the storage controller to conveniently adopt the corresponding protection strategy for data verification, thereby improving the configuration flexibility, so that all user branches can achieve more refined data protection when accessing the memory device, so that the memory device can adapt to different customer needs and maximize value. In addition, the present invention also provides a data verification device, system, memory device and computer-readable storage medium for a memory device, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0034] Figure 1 A flow chart of a data verification method for a memory device provided by an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of the structure of a data verification system for a memory device provided by an embodiment of the present invention;

[0036] Figure 3 A schematic diagram of an ECC process of another data verification method for a memory device provided by an embodiment of the present invention;

[0037] Figure 4 A schematic diagram of a CRC process of another data verification method for a memory device provided by an embodiment of the present invention;

[0038] Figure 5 A structural block diagram of a data verification device for a memory device provided by an embodiment of the present invention;

[0039] Figure 6 A schematic diagram of the structure of a memory device provided by an embodiment of the present invention;

[0040] Figure 7 A structural block diagram of a data verification system for a memory device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Please refer to Figure 1 , Figure 1 A flow chart of a data verification method for a memory device provided by an embodiment of the present invention. The method is applied to a storage controller in a memory device and may include:

[0043] Step 101: receiving a storage access request sent by a network interconnection module through each user access interface; wherein the storage access request includes an extended signal value.

[0044] It is understandable that the memory device in this embodiment can be a DDR, LPDDR, GDDR, etc. as a memory storage component. The storage controller can be a control device set in the memory device, such as a DDR controller in DDR. The network interconnection module in this embodiment can connect each user branch (such as Figure 2 The storage access request sent by the operating system kernel, network port, USB, video and audio branches in the system is sent through the corresponding user access interface (such as Figure 2 DDR user interface 0-2 in the memory device) to the memory controller (such as Figure 2 DDR controller in the .

[0045] Correspondingly, the storage access request received by the storage controller in this embodiment may include an extended signal value configured by the network interconnection module, so as to configure the data verification method of the storage access request by configuring the extended signal value in the storage access request. In other words, the network interconnection module can be used to configure the extended signal value for the storage access request sent by each user branch, and send the configured storage access request to the memory device through the user access interface. For example, the extended signal value to be configured for the storage access request sent by each user branch can be the preset extended signal value corresponding to each user branch, that is, the network interconnection module can configure the extended signal value for the storage access request sent by each user branch according to the preset extended signal value corresponding to each user branch, such as Figure 2 The preset extension signal values ​​corresponding to the three user branches, namely, the operating system kernel, the network port and the USB, corresponding to the DDR user interface 0 may be different; the extension signal value to be configured for the storage access request sent by each user branch may be the preset extension signal value of the user access interface corresponding to each user branch, such as Figure 2The preset extension signal values ​​corresponding to the three user branches of the operating system kernel, network port and USB corresponding to the DDR user interface 0 need to be the same.

[0046] Among them, the specific signal type of the extended signal value in the storage access request in this embodiment can be set by the designer according to the practical scenario and user needs. For example, the storage access request is transmitted through the AXI bus, that is, the user access interface can be the AXI interface, and the network interconnection module can be connected to the storage controller through the AXI bus to send a storage access request to the storage controller. The extended signal value can be the value of the additional signal (QoS) applied by the AXI interface, so that the data verification method of the memory device can be configured through the QoS value that the user can customize. The extended signal value can also be the value of the extended signal of other communication buses, and this embodiment does not impose any restrictions on this.

[0047] For example, if Figure 2 As shown, the network interconnection module can combine the three user branches of the operating system kernel, the network port and the USB and assign them to the DDR user access interface 0 (i.e., the user access interface), assign the video user branch to the DDR user access interface 1, and assign the audio user branch to the DDR user access interface 2; in the network interconnection module, through the register configuration interface, configure the QoS value (i.e., the preset extended signal value) corresponding to each user branch, such as the QoS value corresponding to the operating system kernel user branch is 2 (indicating that ECC check protection is required), the QoS value corresponding to the network port user branch and the USB user branch is 0 (indicating that no data check function is required), and the QoS value corresponding to the video user branch and the audio user branch is 2 (indicating that ECC check protection is required), and then perform S003-S009 in sequence; if the system needs to turn on CRC check protection, the QoS value corresponding to each or corresponding user branch can be configured to 1 (indicating that CRC check protection is required). Correspondingly, the network interconnection module can configure the corresponding QoS value for the storage access request sent by each user branch according to the QoS value corresponding to each user branch, and send the configured storage access request to the DDR controller (i.e., the storage controller) through the corresponding user access interface to configure the corresponding data check method.

[0048] Step 102: Determine and parse a current processing request in a storage access request to obtain an extended signal value in the current processing request; wherein the current processing request is any storage access request.

[0049] It is understandable that the current processing request in this embodiment may be a storage access request that the storage controller is currently processing. That is, in this step, the storage controller may first arbitrate and determine the current processing request from all received unprocessed storage access requests, and then parse the current processing request to obtain the extended signal value in the current processing request.

[0050] Correspondingly, the specific method for the storage controller to determine the current processing request in the storage access request in this step can be set by the designer, for example, it can be set in the same or similar manner as the storage access request arbitration method of the storage controller (such as DDR controller) in the related art, such as Figure 2 As shown, the DDR controller can use the arbitration and QoS analysis modules to arbitrate all received storage access requests, determine the storage access request currently being processed (ie, the current processing request), and implement sequential access of each user access interface to the memory device.

[0051] Accordingly, this embodiment also does not limit the specific manner in which the storage controller parses the current processing request, such as Figure 2 As shown, the DDR controller can use the arbitration and QoS parsing modules to parse the current processing request received through the AXI bus to obtain the QoS value (ie, the extended signal value) in the current processing request.

[0052] Step 103: According to the extended signal value in the current processing request, the target data verification process is called to perform storage data processing on the current processing request; wherein the target data verification process is a preset verification process corresponding to the extended signal value in the current processing request.

[0053] It should be noted that the target data verification process in this embodiment can be a preset verification process corresponding to the extended signal value in the current processing request, so as to realize flexible configuration and calling of different data verification methods by setting the preset verification process corresponding to each extended signal value (i.e., the preset extended signal value).

[0054] Correspondingly, the specific number and type of preset verification processes in this embodiment can be set by the designer according to practical scenarios and user needs. For example, all preset verification processes can include a data-free verification process that does not require data verification protection and a data verification process that requires data verification protection; the data verification process can include a CRC (Cyclic Redundancy Check) process and / or an ECC (Error Checking and Correction) process, and can also include other data verification processes. In this implementation, the preset verification processes corresponding to different extended signal values ​​(i.e., preset extended signal values) can be different, and the same preset verification process corresponding to some extended signal values ​​can also be set. This embodiment does not impose any restrictions on this.

[0055] Correspondingly, in this embodiment, the storage controller calls the target data verification process according to the extended signal value in the current processing request, and the specific manner in which the storage controller performs storage data processing on the current processing request can be set by the designer according to practical scenarios and user needs. For example, the storage controller can configure the call of the required preset verification process (i.e., the target data verification process) through the register configuration interface; that is, the storage controller can configure the call of the target data verification process through the register configuration interface according to the correspondence between the preset extended signal value and the verification method, and perform storage data processing on the current processing request; wherein the correspondence between the preset extended signal value and the verification method can be a correspondence between the register configuration of each preset extended signal value and the corresponding preset verification process, so as to use the correspondence to call the corresponding preset verification process through the register configuration.

[0056] For example, when the memory device is DDR (double data rate synchronous dynamic random access memory), and the preset verification process includes a CRC process and an ECC process, in this step, the DDR controller can determine the preset verification mode (i.e., the verification mode of the target data verification process) corresponding to the extended signal value in the current processing request according to the correspondence between the preset extended signal value and the verification mode; if the preset verification mode is CRC, the CRC function is enabled and the ECC function is disabled through the register configuration interface, and the DDR particle mode register is configured to enable the CRC function, so as to call the CRC process;

[0057] When the current processing request is a write operation, the CRC check code corresponding to the data to be written is calculated, and the data to be written and the check code are written to the DDR particles, so that the DDR particles use the check code to perform CRC on the data to be written and return the check result; when the current processing request is a read operation, the data to be read is read from the DDR particles, and the data to be read is sent to the network interconnection module;

[0058] If the preset check mode is ECC, the CRC function is disabled and the ECC function is enabled through the register configuration interface, and the DDR particle mode register is configured to disable the CRC function;

[0059] When the current processing request is a write operation, the ECC check code corresponding to the data to be written is calculated, and the data to be written and the ECC check code are written to the DDR particle; when the current processing request is a read operation, the data to be read and the corresponding ECC check code are read from the DDR particle, and the read ECC check code is used to verify the data to be read; if the verification is correct, the data to be read is sent to the network interconnection module.

[0060] Correspondingly, when the preset verification process also includes a no-data verification process, after determining the preset verification method corresponding to the extended signal value in the current processing request, if the preset verification method is a no-data verification, then when the current processing request is a write operation, the data to be written can be written to the DDR particle; when the current processing request is a read operation, the data to be read is read from the DDR particle, and the data to be read is sent to the network interconnection module.

[0061] like Figure 2 As shown, when the network interconnection module receives the access DDR request sent by each user branch, it generates an AXI bus command (i.e., storage access request) for accessing the DDR user interface and adds the corresponding QoS value. After the DDR controller receives the AXI bus command for accessing the DDR, it arbitrates and parses the QoS value of the AXI bus command currently being processed; if the currently parsed QoS value is 0 (such as the access request of the network port or USB user branch), no data verification protection is required. When the command is a write operation, the data to be written is directly sent to the DDR particle (DDR SDRAM) through the DDR physical layer (DDR PHY); when the command is a read operation, the corresponding data to be read is directly read from the DDR particle, and the read data is returned to the network interconnection module, and then returned to the user side through the network interconnection module.

[0062] Correspondingly, if the currently parsed QoS value is 2 (such as the access request of the operating system kernel video or audio user branch), ECC check protection is required. The DDR controller can be configured to enable the ECC function and disable the CRC function through the register configuration interface, and configure the DDR particles to disable the CRC function through the DDR particle mode register to call the start ECC process; Figure 3 As shown, after the ECC process is started, if the command is a write operation, the ECC check code of the user's written data (i.e., the data to be written) is calculated through the ECC module, and the data and the ECC check code are sent to the DRAM (DDR particles) through the DDR PHY for storage; if the command is a read operation, the user's required data (i.e., the data to be read) and the ECC check code are read from the DRAM, and the data and the ECC check code are checked by the ECC module. If correct, the data to be read is returned to the corresponding user through the network interconnection module; if an error occurs, the ECC module is used to attempt to correct the error, and then the data to be read is returned to the corresponding user through the network interconnection module, and an ECC error interrupt signal is generated, and the error information is recorded in the ECC status register.

[0063] If the currently parsed QoS value is 1, CRC check protection is required. The DDR controller can be configured to disable the ECC function and enable the CRC function through the register configuration interface. The DDR particle mode register is used to configure the DDR particle to enable the CRC function to call and start the CRC process. Figure 4 As shown, after the CRC process is started, if the command is a write operation, the CRC module calculates the CRC check code for the user-written data (i.e., the data to be written), and sends the data and the CRC check code to the DRAM (DDR particles) through the DDR PHY, so that the DRAM automatically performs a CRC check after receiving the written data and the CRC check code, and returns the check result to the DDR PHY through the corresponding pin. If the first check fails, the DDR controller initiates a retransmission. If the second check fails, a CRC error interrupt signal is generated and recorded in the CRC error status register; if the command is a read operation, the user-required data (i.e., the data to be read) is read from the DRAM and returned to the corresponding user through the network interconnection module.

[0064] Furthermore, the method provided in this embodiment may also include a process of adjusting the correspondence between the preset extension signal value and the verification mode, such as the storage controller may receive a correspondence adjustment command sent by the network interconnection module; and adjust the correspondence between the preset extension signal value and the verification mode according to the correspondence adjustment command. The network interconnection module may use a low-speed bus (such as Figure 2 The peripheral bus APB in the memory sends a corresponding relationship adjustment command to the memory controller to adjust the corresponding relationship between the preset extension signal value and the verification mode.

[0065] Correspondingly, the network interconnection module can also adjust the extended signal value corresponding to the target user branch according to the obtained extended signal value configuration instruction to achieve configuration adjustment of the extended signal value corresponding to each user branch; wherein the target user branch can be the user branch corresponding to the extended signal value configuration instruction.

[0066] In this embodiment, the embodiment of the present invention calls the target data verification process according to the extended signal value in the current processing request to perform storage data processing on the current processing request. It can utilize the setting of the extended signal value in the storage access request to enable the storage controller to conveniently adopt the corresponding protection strategy to perform data verification, thereby improving the configuration flexibility and enabling all user branches to achieve more refined data protection when accessing the storage memory device, thereby enabling the memory device to adapt to different customer needs and maximize value.

[0067] Corresponding to the above method embodiment, an embodiment of the present invention further provides a data verification device for a memory device. The data verification device for a memory device described below and the data verification method for a memory device described above can refer to each other.

[0068] Please refer to Figure 5 , Figure 5 This is a structural block diagram of a data verification device for a memory device provided by an embodiment of the present invention. The device is applied to a storage controller in a memory device and may include:

[0069] The request receiving unit 10 is used to receive the storage access request sent by the network interconnection module through each user access interface; wherein the storage access request includes an extended signal value;

[0070] The arbitration parsing unit 20 is used to determine and parse the current processing request in the storage access request to obtain the extended signal value in the current processing request; wherein the current processing request is any storage access request;

[0071] The verification control unit 30 is used to call the target data verification process according to the extended signal value in the current processing request to perform storage data processing on the current processing request; wherein the target data verification process is a preset verification process corresponding to the extended signal value in the current processing request.

[0072] In some embodiments, different extended signal values ​​correspond to different preset verification processes, and the preset verification process includes a data-free verification process and a data verification process, and the data verification process includes a cyclic redundancy check process and / or an error detection and correction process.

[0073] In some embodiments, the verification control unit 30 may be specifically configured to call the target data verification process through a register configuration interface according to the correspondence between the preset extension signal value and the verification method, and perform storage data processing on the current processing request.

[0074] In some embodiments, the memory device is a double rate synchronous dynamic random access memory, and the check control unit 30 may include:

[0075] A verification determination subunit, used to determine a preset verification mode corresponding to the extended signal value in the current processing request according to a correspondence between the preset extended signal value and the verification mode;

[0076] The first configuration subunit is used for, if the preset check mode is a cyclic redundancy check, configuring the cyclic redundancy check function to be turned on, turning off the error detection and correction function, and configuring the double rate synchronous dynamic random access memory particle mode register to turn on the cyclic redundancy check function through the register configuration interface;

[0077] The first check subunit is used to calculate the check code of the cyclic redundancy check corresponding to the data to be written when the current processing request is a write operation, and write the data to be written and the check code into the double rate synchronous dynamic random access memory particle, so as to use the double rate synchronous dynamic random access memory particle to perform a cyclic redundancy check on the data to be written using the check code and return the check result; when the current processing request is a read operation, read the data to be read from the double rate synchronous dynamic random access memory particle, and send the data to be read to the network interconnection module;

[0078] The second configuration subunit is used for, if the preset check mode is error detection and correction, configuring the cyclic redundancy check function to be turned off, the error detection and correction function to be turned on, and configuring the double rate synchronous dynamic random access memory particle mode register to turn off the cyclic redundancy check function through the register configuration interface;

[0079] The second check subunit is used to calculate the error detection and correction check code corresponding to the data to be written when the current processing request is a write operation, and write the data to be written and the error detection and correction check code into the double-speed synchronous dynamic random access memory particle; when the current processing request is a read operation, read the data to be read and the corresponding error detection and correction check code from the double-speed synchronous dynamic random access memory particle, and use the read error detection and correction check code to check the data to be read; if the check is correct, send the data to be read to the network interconnection module.

[0080] In some embodiments, the extension signal value in each storage access request corresponds to a user branch of the corresponding network interconnect module.

[0081] In this embodiment, the embodiment of the present invention verifies the control unit 30 and calls the target data verification process according to the extended signal value in the current processing request to perform storage data processing on the current processing request. The setting of the extended signal value in the storage access request can be utilized to enable the storage controller to conveniently adopt the corresponding protection strategy for data verification, thereby improving the configuration flexibility and enabling all user branches to achieve more refined data protection when accessing the storage memory device, thereby enabling the memory device to adapt to different customer needs and maximize value.

[0082] Corresponding to the above method embodiment, an embodiment of the present invention further provides a memory device. The memory device described below and the data verification method of the memory device described above can refer to each other.

[0083] Please refer to Figure 6 , Figure 6 A schematic diagram of the structure of a memory device provided by an embodiment of the present invention. The memory device may include:

[0084] A memory D1, for storing computer programs;

[0085] The storage controller D2 is used to implement the steps of the data verification method of the memory device provided in the above embodiment when executing the computer program.

[0086] Corresponding to the above method embodiment, an embodiment of the present invention further provides a data verification system for a memory device. The data verification system for a memory device described below and the data verification method for a memory device described above can refer to each other.

[0087] Please refer to Figure 7 , Figure 7 A schematic diagram of a data verification system for a memory device provided in an embodiment of the present invention. The system may include: a network interconnection module 100 and a memory device 200 provided in the previous embodiment;

[0088] The network interconnection module 100 is used to configure an extended signal value for a storage access request sent by each user branch, and send the configured storage access request to the memory device through a user access interface.

[0089] In some embodiments, configuring an extended signal value for a storage access request sent by each user branch includes:

[0090] According to the preset extension signal value corresponding to each user branch, the extension signal value is configured for the storage access request sent by each user branch.

[0091] In some embodiments, the preset extension signal values ​​of all user branches corresponding to a certain user access interface may be the same; the preset extension signal values ​​of all user branches corresponding to a certain user access interface may also be completely or partially different.

[0092] In some embodiments, the network interconnection module 100 can also be used to send a corresponding relationship adjustment command to the network interconnection module to control the storage controller to adjust the corresponding relationship between the preset extension signal value and the verification mode. For example, the network interconnection module 100 can send the corresponding relationship adjustment command to the storage controller via the APB bus.

[0093] In some embodiments, the network interconnection module 100 may also be used to adjust the extended signal value corresponding to the target user branch according to the acquired extended signal value configuration instruction; wherein the target user branch may be a user branch corresponding to the extended signal value configuration instruction.

[0094] Corresponding to the above method embodiment, an embodiment of the present invention further provides a computer program product. The computer program product described below and the data verification method of a memory device described above can refer to each other.

[0095] A computer program product includes a computer program / instruction, which, when executed by a processor, implements the steps of the data verification method for a memory device as provided in the above embodiment.

[0096] Corresponding to the above method embodiment, an embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium described below and the data verification method of a memory device described above can refer to each other.

[0097] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data verification method for a memory device provided in the above embodiment are implemented.

[0098] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, systems, memory devices, computer program products, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0099] The above is a detailed introduction to a data verification method, apparatus, system, memory device and computer-readable storage medium for a memory device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A data verification method for a memory device, characterized in that: Storage controllers used in memory devices include: Receiving a storage access request sent by the network interconnection module through each user access interface; wherein the storage access request includes an extended signal value; Determine and parse the current processing request in the storage access request to obtain the extended signal value in the current processing request; wherein the current processing request is any of the storage access requests; According to the extended signal value in the current processing request, a target data verification process is called to perform storage data processing on the current processing request; wherein the target data verification process is a preset verification process corresponding to the extended signal value in the current processing request.

2. The data verification method of the memory device according to claim 1, characterized in that: Different extended signal values ​​correspond to different preset verification processes, and the preset verification process includes a data-free verification process and a data verification process, and the data verification process includes a cyclic redundancy check process and / or an error detection and correction process.

3. The data verification method of the memory device according to claim 1, characterized in that: The step of calling a target data verification process according to the extended signal value in the current processing request and performing storage data processing on the current processing request includes: According to the correspondence between the preset extension signal value and the verification mode, the target data verification process is configured and called through the register configuration interface to perform storage data processing on the current processing request.

4. The data verification method of the memory device according to claim 3, characterized in that: The memory device is a double rate synchronous dynamic random access memory, and according to the correspondence between the preset extended signal value and the verification mode, the target data verification process is configured and called through the register configuration interface to perform storage data processing on the current processing request, including: Determining the preset verification mode corresponding to the extended signal value in the current processing request according to the correspondence between the preset extended signal value and the verification mode; If the preset check mode is a cyclic redundancy check, the cyclic redundancy check function is configured to be turned on, the error detection and correction function is turned off, and the double rate synchronous dynamic random access memory particle mode register is configured to turn on the cyclic redundancy check function through the register configuration interface; When the current processing request is a write operation, a check code of a cyclic redundancy check corresponding to the data to be written is calculated, and the data to be written and the check code are written into a double rate synchronous dynamic random access memory particle, so that the double rate synchronous dynamic random access memory particle uses the check code to perform a cyclic redundancy check on the data to be written and return a check result; when the current processing request is a read operation, the data to be read is read from the double rate synchronous dynamic random access memory particle, and the data to be read is sent to the network interconnection module; If the preset check mode is error detection and correction, then through the register configuration interface, configure to turn off the cyclic redundancy check function, turn on the error detection and correction function, and configure the double rate synchronous dynamic random access memory particle mode register to turn off the cyclic redundancy check function; When the current processing request is a write operation, an error detection and correction check code corresponding to the data to be written is calculated, and the data to be written and the error detection and correction check code are written into the double data rate synchronous dynamic random access memory particle; when the current processing request is a read operation, the data to be read and the corresponding error detection and correction check code are read from the double data rate synchronous dynamic random access memory particle, and the data to be read is verified using the read error detection and correction check code; if the verification is correct, the data to be read is sent to the network interconnection module.

5. The data verification method of a memory device according to claim 1, characterized in that: The extended signal value in each of the storage access requests corresponds to a user branch of the network interconnection module.

6. A data verification device for a memory device, characterized in that: Storage controllers used in memory devices include: A request receiving unit, configured to receive a storage access request sent by the network interconnection module through each user access interface; wherein the storage access request includes an extended signal value; an arbitration parsing unit, configured to determine and parse a current processing request in the storage access request to obtain an extended signal value in the current processing request; wherein the current processing request is any of the storage access requests; A verification control unit is used to call a target data verification process according to the extended signal value in the current processing request to perform storage data processing on the current processing request; wherein the target data verification process is a preset verification process corresponding to the extended signal value in the current processing request.

7. A memory device, characterized in that: include: Memory for storing computer programs; A storage controller, configured to implement the steps of the data verification method for a memory device as claimed in any one of claims 1 to 5 when executing the computer program.

8. A data verification system for a memory device, characterized in that: include: A network interconnection module and a memory device as described in claim 7; wherein the network interconnection module is used to configure an extended signal value for a storage access request sent by each user branch, and send the configured storage access request to the memory device through a user access interface.

9. The data verification system for a memory device according to claim 8, characterized in that: The configuration of the extended signal value for the storage access request sent by each user branch includes: According to the preset extension signal value corresponding to each of the user branches, an extension signal value is configured for the storage access request sent by each of the user branches.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data verification method for a memory device according to any one of claims 1 to 5 are implemented.

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