Wafer detection method and device compatible with film expansion, equipment and storage medium

Abstract

The invention relates to the technical field of semiconductor detection, and discloses a wafer detection method, device and equipment compatible with film expansion, and a storage medium, and the method comprises the steps: carrying out the image splicing according to a target actual field of view and a crystal grain position relation when a plurality of detectors receive the target actual field of view and the crystal grain position relation of a to-be-detected wafer, and carrying out the image splicing according to the target actual field of view and the crystal grain position relation; the method comprises the steps that a wafer to be detected is detected, a spliced image is obtained, a segmented crystal grain image is generated in the spliced image according to morphological characteristics of a standard crystal grain image, defect detection is conducted on the segmented crystal grain image through an AI deep learning algorithm, and a detection result of the wafer to be detected is obtained. According to the method, accurate splicing of the view images is achieved based on the crystal grain position relation, the crystal grain image of accurate image segmentation is obtained through the morphological characteristics of the standard crystal grain image, the method is also suitable for the wafer after film expansion, and therefore the wafer after film expansion is accurately detected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor detection technology, and in particular to a wafer detection method, device, equipment and storage medium compatible with film expansion. Background Art

[0002] In the wafer preparation process, in order to protect the surface of the chip and improve the chip quality and performance after the wafer is cut, the chip needs to be expanded. The conventional detection method cannot accurately locate the position of each die, cannot achieve precise segmentation, and it is difficult to achieve accurate surface measurement.

[0003] Conventional wafer inspection uses traditional algorithms to inspect wafers before cutting. After positioning the reference (Mark) point, the position relationship of all other dies is converted according to the position of the Mark point for scanning inspection. This solution is still applicable to wafers before cutting or wafers with minor position deviation after cutting, but it is not applicable to wafers after film expansion, because the position relationship between dies on the wafer after film expansion is completely random. The position relationship of each die can no longer be calculated based on Mark positioning or other existing conventional positioning methods, and the position of each die cannot be accurately positioned, which will cause subsequent inspections to fail to flow normally, and accurate segmentation cannot be achieved. It is also difficult to accurately measure and inspect the wafer surface.

[0004] Therefore, how to accurately detect wafers after film expansion is a technical problem that needs to be solved urgently.

[0005] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0006] The main purpose of the present invention is to provide a wafer detection method, device, equipment and storage medium that are compatible with film expansion, aiming to solve the technical problem in the prior art that wafers after film expansion cannot be accurately detected.

[0007] To achieve the above object, the present invention provides a wafer detection method compatible with film expansion, and the wafer detection method compatible with film expansion comprises the following steps:

[0008] When multiple inspection machines receive the target actual field of view image and the position relationship of the grains of the wafer to be inspected, they perform image stitching according to the target actual field of view image and the position relationship of the grains to obtain a stitching image;

[0009] In the spliced ​​image, a segmented grain image is generated according to the morphological features of the standard grain image;

[0010] An AI deep learning algorithm is used to perform defect detection on the segmented grain map to obtain the detection result of the wafer to be tested.

[0011] Preferably, the morphological features include grayscale features, contour features and / or structural features;

[0012] In the spliced ​​image, a segmented grain image is generated according to the morphological features of the standard grain image, including:

[0013] In the spliced ​​image, determining whether the grain morphology features in the target grain region are complex;

[0014] If the grains are complex in shape, multiple morphological features of the standard grain map are matched to generate a segmented grain map;

[0015] If it is not a grain with complex morphology, it is searched according to the grayscale connected domain analysis algorithm, and a segmented grain map is generated according to the corresponding grains found.

[0016] Preferably, when multiple inspection machines receive the target actual field of view image and the grain position relationship of the wafer to be tested, image stitching is performed according to the target actual field of view image and the grain position relationship, and before obtaining the stitched image, the method further includes:

[0017] Get the Wafer image corresponding to the wafer to be tested;

[0018] Generating a grain position relationship on the Wafer image according to the morphological features of the standard grain image;

[0019] Calculating a scanning path according to the position relationship of the grains, scanning the wafer to be tested according to the scanning path, and generating a target actual field of view map;

[0020] The actual visual field map of the target is distributed to multiple detection machines in real time.

[0021] Preferably, after obtaining the Wafer image corresponding to the wafer to be tested, the method further includes:

[0022] Scaling the wafer image by preset pixel precision;

[0023] Selecting a first grain region on the scaled Wafer image, and scanning to generate a first actual field of view image corresponding to the first grain region;

[0024] A standard grain map is generated according to the first actual field of view map in accordance with a positioning algorithm.

[0025] Preferably, obtaining a Wafer image corresponding to the wafer to be tested includes:

[0026] When the wafer to be tested is placed on the testing table, focusing and leveling the wafer to be tested;

[0027] Determining whether to pre-scan the wafer to be tested;

[0028] If yes, the wafer to be tested is pre-scanned to generate a wafer image corresponding to the wafer to be tested.

[0029] Preferably, calculating the scanning path according to the position relationship of the grains includes:

[0030] According to the position relationship of the crystal grains, the module coordinate position of each row of crystal grains is calculated according to the bow-shaped trajectory or the Z-shaped trajectory, the position of each part of the crystal grain in the actual field of view is obtained, and the scanning path is obtained.

[0031] Preferably, searching is performed according to a grayscale connected domain analysis algorithm, and a segmented grain map is generated according to the corresponding grains found, including:

[0032] According to the characteristic parameters of the grain image morphology, the characteristic factors in the image are extracted for searching, and the segmented grain map is generated according to the corresponding grains found.

[0033] In addition, to achieve the above-mentioned purpose, the present invention further proposes a wafer detection device compatible with film expansion, characterized in that the wafer detection device compatible with film expansion comprises:

[0034] A splicing module, which is used for performing image splicing according to the target actual field of view image and the grain position relationship of the wafer to be tested when multiple inspection machines receive the target actual field of view image and the grain position relationship to obtain a spliced ​​image;

[0035] A generating module, used for generating a segmented grain map in the spliced ​​map according to the morphological features of the standard grain map;

[0036] The detection module is used to use an AI deep learning algorithm to perform defect detection on the segmented grain map to obtain the detection result of the wafer to be tested.

[0037] In addition, to achieve the above-mentioned purpose, the present invention also proposes a film expansion compatible wafer detection device, the film expansion compatible wafer detection device includes a memory, a processor, and a film expansion compatible wafer detection program stored on the memory and executable on the processor, the film expansion compatible wafer detection program is configured to implement the steps of the film expansion compatible wafer detection method as described above.

[0038] In addition, to achieve the above-mentioned purpose, the present invention also proposes a storage medium, on which a wafer detection program compatible with film expansion is stored. When the wafer detection program compatible with film expansion is executed by a processor, the steps of the wafer detection method compatible with film expansion are implemented as described above.

[0039] In the present invention, when the target actual field of view and the grain position relationship of the wafer to be tested are received by multiple detection machines, image stitching is performed according to the target actual field of view and the grain position relationship to obtain a stitching image, in which a segmented grain image is generated according to the morphological features of the standard grain image, and an AI deep learning algorithm is used to perform defect detection on the segmented grain image to obtain the test result of the wafer to be tested. Accurate stitching of the field of view is achieved based on the grain position relationship, and then the grain image of accurate image segmentation is obtained through the morphological features of the standard grain image, which is also applicable to wafers after film expansion, thereby accurately detecting the wafers after film expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a structural schematic diagram of a wafer inspection device compatible with film expansion in a hardware operating environment involved in an embodiment of the present invention;

[0041] Figure 2 It is a schematic flow chart of a first embodiment of a wafer inspection method compatible with film expansion according to the present invention;

[0042] Figure 3 It is a structural block diagram of a first embodiment of a wafer inspection device compatible with film expansion according to the present invention;

[0043] Figure 4 It is a structural block diagram of the first embodiment of the wafer inspection system compatible with film expansion of the present invention.

[0044] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0045] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0046] Reference Figure 1 , Figure 1 The present invention is a schematic diagram of the structure of a wafer inspection device compatible with expansion film in the hardware operating environment involved in the embodiment of the present invention.

[0047] like Figure 1As shown, the wafer inspection device compatible with film expansion may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The wired interface of the user interface 1003 may be a USB interface in the present invention. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (WIreless-FIdelity, WI-FI) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM) memory, or a stable memory (Non-volatile Memory, NVM), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0048] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the wafer inspection equipment compatible with expansion film, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0049] like Figure 1 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a wafer detection program compatible with film expansion.

[0050] exist Figure 1 In the film expansion compatible wafer inspection device shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the user device; the film expansion compatible wafer inspection device calls the film expansion compatible wafer inspection program stored in the memory 1005 through the processor 1001, and executes the film expansion compatible wafer inspection method provided by the embodiment of the present invention.

[0051] Based on the above hardware structure, an embodiment of a wafer detection method compatible with film expansion of the present invention is proposed.

[0052] Reference Figure 2 , a first embodiment of a wafer detection method compatible with film expansion of the present invention is proposed.

[0053] In a first embodiment, the wafer inspection method compatible with film expansion includes the following steps:

[0054] Step S10: When multiple inspection machines receive the target actual field of view image and the grain position relationship of the wafer to be inspected, they perform image stitching according to the target actual field of view image and the grain position relationship to obtain a stitching image.

[0055] It should be noted that the executor of this embodiment is the wafer inspection device compatible with film expansion, wherein the wafer inspection device compatible with film expansion can be an electronic device such as a personal computer or a server, and this embodiment does not limit this. After receiving the image, the inspection machine performs image stitching according to the field of view corresponding to each Die, and uses the standard grain map to make the actual die in the stitched image according to the relationship of morphological features. The target actual field of view map is sent to the inspection machine in real time, and the grain position relationship includes the position relationship between each grain. A certain grain may exist in multiple actual field of view maps. The inspection machine stitches multiple actual field of view maps to stitch out a complete grain, that is, to obtain a stitched map.

[0056] Furthermore, in this embodiment, before step S10, the following steps are further included:

[0057] Get the Wafer image corresponding to the wafer to be tested;

[0058] Generating a grain position relationship on the Wafer image according to the morphological features of the standard grain image;

[0059] Calculating a scanning path according to the position relationship of the grains, scanning the wafer to be tested according to the scanning path, and generating a target actual field of view map;

[0060] The actual visual field map of the target is distributed to multiple detection machines in real time.

[0061] Further, in this embodiment, the step of obtaining a Wafer image corresponding to the wafer to be tested includes:

[0062] When the wafer to be tested is placed on the testing table, focusing and leveling the wafer to be tested;

[0063] Determining whether to pre-scan the wafer to be tested;

[0064] If yes, the wafer to be tested is pre-scanned to generate a wafer image corresponding to the wafer to be tested.

[0065] In the specific implementation, after EFEM automatically loads the material, it focuses and levels the wafer, and sets the zoom accuracy according to the selected detection lens magnification 2X / 5X / 10X / 20X. The higher the magnification, the greater the thumbnail pixel accuracy. The minimum zoom pixel accuracy is 12um. The zoom accuracy of different lenses is calculated according to the magnification ratio to avoid the image being too large to be processed.

[0066] Furthermore, in this embodiment, after obtaining the Wafer image corresponding to the wafer to be tested, it also includes: scaling the Wafer image with a preset pixel accuracy; selecting a first grain area on the scaled Wafer image, and scanning to generate a first actual field of view image corresponding to the first grain area; and generating a standard grain image according to the positioning algorithm based on the first actual field of view image.

[0067] It should be noted that the first grain area is an arbitrarily selected grain area, and the preset pixel accuracy is set according to the detection lens magnification. The higher the magnification, the greater the thumbnail pixel accuracy. The Wafer image is scaled by the preset pixel accuracy, and the scaling accuracy of different lenses is calculated according to the magnification ratio, which can avoid the Wafer image being too large to be processed.

[0068] Further, in this embodiment, calculating the scanning path according to the position relationship of the grains includes:

[0069] According to the position relationship of the crystal grains, the module coordinate position of each row of crystal grains is calculated according to the bow-shaped trajectory or the Z-shaped trajectory, the position of each part of the crystal grain in the actual field of view is obtained, and the scanning path is obtained.

[0070] It can be understood that during automatic detection, based on the characteristic coordinates of the Die on the Wafer image, the area array camera is used to calculate the module coordinate position of each row of Dies according to the bow-shaped trajectory or the Z-shaped trajectory, and the module coordinates of the Die are converted into actual pixel coordinates and combined with the pixel coordinates of the field of view map to obtain the position of each part of the Die in the field of view map, forming a scanning path for scanning the field of view map. After executing the scanning instruction, the field of view map is obtained from the camera and sent to each detection machine in turn according to the number of detection machines.

[0071] Furthermore, in this embodiment, in order to improve the inspection speed of the wafer, a wafer import process will be set before the inspection process. After the EFEM automatically loads the material, the wafer is focused and leveled. If there is a Wafer image of the wafer to be inspected, no pre-scan is performed, and the historical Wafer image is directly queried; if there is no Wafer image of the wafer to be inspected, a pre-scan is performed to generate a Wafer image corresponding to the wafer to be inspected. The wafer image is a map of the entire wafer. Select a Die area on the Wafer image. You can manually draw a circle to circle a Die area, or you can automatically select a Die area at will. The image pixel coordinates are converted into module coordinates to scan and generate an actual field of view map. In the field of view map, a standard die image is cut out according to the die morphology characteristics or manually selected areas, and the Die is saved. Create a Die morphology feature relationship (thumbnail template) on the wafer image to find all dies. Different methods need to be used according to different wafer characteristics. Grayscale features can be used for those with fewer grayscale levels, and shape features can be used for those with large grayscale differences. Get all the dies, get the pixel coordinates of all the dies, convert them into module coordinates, and save the thumbnail template.

[0072] Step S20: in the spliced ​​image, generating a segmented grain image according to the morphological features of the standard grain image.

[0073] It is understandable that there may be some edge information in the spliced ​​image. In order to improve the detection speed, the spliced ​​image is segmented and the surrounding useless edge parts are removed. In order to achieve accurate segmentation, a standard grain map is obtained, and the complete grains are calculated according to the morphological characteristics of the standard grain map. Image segmentation is performed to obtain the segmented Die map, and then the segmented grain map is detected by traditional algorithms or AI deep learning detection algorithms to achieve grain defect detection.

[0074] Step S30: Use an AI deep learning algorithm to perform defect detection on the segmented grain map to obtain the detection result of the wafer to be tested.

[0075] It should be understood that the die image is inspected for defects using traditional algorithms or AI deep learning algorithms, the inspection results are obtained, the results are processed, and after the results are processed, they are sent back to the main control machine for display and result storage, and the entire wafer inspection process is completed.

[0076] In this embodiment, when the target actual field of view and the grain position relationship of the wafer to be tested are received by multiple detection machines, image stitching is performed according to the target actual field of view and the grain position relationship to obtain a stitched image. In the stitched image, a segmented grain image is generated according to the morphological features of the standard grain image, and an AI deep learning algorithm is used to perform defect detection on the segmented grain image to obtain the inspection result of the wafer to be tested. Accurate stitching of the field of view is achieved based on the grain position relationship, and then the grain image of accurate image segmentation is obtained through the morphological features of the standard grain image, which is also applicable to the wafer after film expansion, thereby accurately detecting the wafer after film expansion. The wafer after film expansion can be detected through a simple process and efficient detection method without adjusting the equipment structure.

[0077] Continue to refer to Figure 2 Based on the first embodiment of the method described above, a second embodiment of a wafer detection method compatible with film expansion is proposed.

[0078] In this embodiment, the morphological features include grayscale features, contour features and / or structural features; the step S20 includes:

[0079] In the spliced ​​image, determining whether the grain morphology features in the target grain region are complex;

[0080] If the grains are complex in shape, multiple morphological features of the standard grain map are matched to generate a segmented grain map;

[0081] If it is not a grain with complex morphology, it will be searched according to the grayscale connected domain analysis algorithm, and a segmented grain map will be generated according to the corresponding grains found.

[0082] It should be noted that the morphological features include but are not limited to grayscale features, contour features, and structural features. Selecting a certain Die area on the Wafer diagram can be done by manually drawing a circle around a certain Die area, or by automatically selecting a certain Die area at will. The actual field of view is generated by converting the image pixel coordinates into module coordinates and scanning. The calculation method is selected according to the complexity of the grain morphology. For more complex morphologies, the entire die morphology relationship matching method can be used, or matching can be performed based on multiple morphological features. For relatively simple morphologies, the grayscale connected domain analysis algorithm can be used. When making a Die morphology relationship, the Die contour area can be marked by automatic generation or manual drawing. The automatic generation method will automatically calculate the morphology features of the die according to the grayscale or spatial features in the die. Manual drawing can arbitrarily select an area to generate the Die morphology, and generate the morphology relationship through the algorithm; the grayscale connected domain analysis algorithm sets the parameters such as the Die grayscale and energy value, extracts the characteristic factors in the image, such as the local binary pattern (Local Binary Patterns, LBP), the directional gradient histogram (Histogram of Oriented Gradients, HOG), etc., and uses the corresponding matching algorithm for comparison. These characteristic factors can capture the local texture and shape information of the image for matching and recognition. The Die morphology relationship is obtained by using the grayscale connected domain analysis algorithm, which can improve the search speed and accuracy of the wafer. In this embodiment, searching is performed according to the grayscale connected domain analysis algorithm, and a segmented grain map is generated according to the corresponding grains found, including: extracting the characteristic factors in the image for searching according to the grain image morphology characteristic parameters, and generating a segmented grain map according to the corresponding grains found.

[0083] It should be understood that the corresponding parameters are set according to the grayscale information of the grain image, and the Die morphology relationship (thumbnail template) is created on the Wafer image to search for the die, or the grayscale connected domain analysis algorithm is used to obtain all the dies, and the pixel coordinates of all the dies are obtained and converted into module coordinates to obtain the actual coordinates of each die in the module.

[0084] In this embodiment, by judging whether the grain morphology features in the target grain area are complex in the stitching image, if it is a morphologically complex grain, matching is performed according to multiple morphological features of the standard grain image to generate a segmented grain image; if it is not a morphologically complex grain, a search is performed according to the grayscale connected domain analysis algorithm, and a segmented grain image is generated based on the corresponding grains found. Different algorithms are used for image segmentation based on grains of different morphologies, thereby improving the image processing speed and thereby improving the efficiency of the entire wafer inspection.

[0085] In addition, an embodiment of the present invention further proposes a storage medium, on which a wafer detection program compatible with film expansion is stored. When the wafer detection program compatible with film expansion is executed by a processor, the steps of the wafer detection method compatible with film expansion as described above are implemented.

[0086] In addition, refer to Figure 3 The embodiment of the present invention further provides a wafer detection device compatible with film expansion, and the wafer detection device compatible with film expansion includes:

[0087] A stitching module 10 is used for performing image stitching according to the target actual visual field image and the grain position relationship of the wafer to be tested when multiple inspection machines receive the target actual visual field image and the grain position relationship to obtain a stitching image;

[0088] A generating module 20, for generating a segmented grain map in the spliced ​​map according to the morphological features of the standard grain map;

[0089] The detection module 30 is used to use an AI deep learning algorithm to perform defect detection on the segmented grain map to obtain the detection result of the wafer to be tested.

[0090] Other embodiments or specific implementations of the wafer inspection device compatible with film expansion of the present invention can refer to the above-mentioned method embodiments, which will not be repeated here.

[0091] In addition, based on the first embodiment of the above method, the embodiment of the present invention also proposes a wafer detection system compatible with film expansion, referring to Figure 4 The wafer inspection system compatible with film expansion includes: Figure 1 The wafer detection device 100 compatible with film expansion, the microscopic imaging module 200, and the high-precision motion platform 300 shown in the figure; the wafer detection device 100 compatible with film expansion is connected to the microscopic imaging module 200 and the high-precision motion platform 300 respectively, the microscopic imaging module 200 is arranged on the high-precision motion platform 300, and the wafer detection device 100 compatible with film expansion controls the microscopic imaging module 200 to collect the field of view of the wafer to be detected. Usually, the wafer is placed on a chunk disk, the entire wafer is quickly scanned and the scanned actual field of view of the target is saved, the chunk disk is placed on the high-precision motion platform 300, and the wafer detection device 100 compatible with film expansion controls the movement of the high-precision motion platform 300 to achieve scanning of the entire wafer disk.

[0092] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0093] The serial numbers of the embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. In a unit claim that lists several means, several of these means may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order and these words may be interpreted as identifiers.

[0094] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as a read-only memory image (ROM) / random access memory (RAM), a disk, or an optical disk), including a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0095] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A wafer detection method compatible with film expansion, characterized in that: The wafer detection method compatible with film expansion comprises the following steps: When multiple inspection machines receive the target actual field of view image and the position relationship of the grains of the wafer to be inspected, they perform image stitching according to the target actual field of view image and the position relationship of the grains to obtain a stitching image; In the spliced ​​image, a segmented grain image is generated according to the morphological features of the standard grain image; An AI deep learning algorithm is used to perform defect detection on the segmented grain map to obtain the detection result of the wafer to be tested.

2. The wafer detection method compatible with film expansion according to claim 1, characterized in that: The morphological features include grayscale features, contour features and / or structural features; In the spliced ​​image, a segmented grain image is generated according to the morphological features of the standard grain image, including: In the spliced ​​image, determining whether the grain morphology features in the target grain region are complex; If the grains are complex in shape, multiple morphological features of the standard grain map are matched to generate a segmented grain map; If it is not a grain with complex morphology, it is searched according to the grayscale connected domain analysis algorithm, and a segmented grain map is generated according to the corresponding grains found.

3. The wafer detection method compatible with film expansion according to claim 1, characterized in that: When multiple inspection machines receive the target actual field of view image and the position relationship of the grains of the wafer to be tested, image stitching is performed according to the target actual field of view image and the position relationship of the grains, and before obtaining the stitched image, the method further includes: Get the Wafer image corresponding to the wafer to be tested; Generating a grain position relationship on the Wafer image according to the morphological features of the standard grain image; Calculating a scanning path according to the position relationship of the grains, scanning the wafer to be tested according to the scanning path, and generating a target actual field of view map; The actual visual field map of the target is distributed to multiple detection machines in real time.

4. The wafer detection method compatible with film expansion as claimed in claim 3, characterized in that: After obtaining the Wafer image corresponding to the wafer to be tested, it also includes: Scaling the wafer image by preset pixel precision; Selecting a first grain region on the scaled Wafer image, and scanning to generate a first actual field of view image corresponding to the first grain region; A standard grain map is generated according to the first actual field of view map in accordance with a positioning algorithm.

5. The wafer detection method compatible with film expansion as claimed in claim 3, characterized in that: Get the Wafer image corresponding to the wafer to be tested, including: When the wafer to be tested is placed on the testing table, focusing and leveling the wafer to be tested; Determining whether to pre-scan the wafer to be tested; If yes, the wafer to be tested is pre-scanned to generate a wafer image corresponding to the wafer to be tested.

6. The wafer detection method compatible with film expansion as claimed in claim 3, characterized in that: Calculating a scanning path according to the position relationship of the grains includes: According to the position relationship of the crystal grains, the module coordinate position of each row of crystal grains is calculated according to the bow-shaped trajectory or the Z-shaped trajectory, the position of each part of the crystal grain in the actual field of view is obtained, and the scanning path is obtained.

7. The wafer inspection method compatible with film expansion according to any one of claims 2 to 6, characterized in that: The search is performed according to the grayscale connected domain analysis algorithm, and a segmented grain map is generated according to the corresponding grains found, including: According to the characteristic parameters of the grain image morphology, the characteristic factors in the image are extracted for searching, and the segmented grain map is generated according to the corresponding grains found.

8. A wafer inspection device compatible with film expansion, characterized in that: The wafer detection device compatible with film expansion includes: A splicing module, which is used for performing image splicing according to the target actual field of view and the grain position relationship of the wafer to be tested when multiple inspection machines receive the target actual field of view and the grain position relationship to obtain a spliced ​​image; A generating module, used for generating a segmented grain map in the spliced ​​map according to the morphological features of the standard grain map; The detection module is used to use an AI deep learning algorithm to perform defect detection on the segmented grain map to obtain the detection result of the wafer to be tested.

9. A wafer inspection device compatible with film expansion, characterized in that: The film expansion compatible wafer detection device comprises: a memory, a processor, and a film expansion compatible wafer detection program stored in the memory and executable on the processor. When the film expansion compatible wafer detection program is executed by the processor, the steps of the film expansion compatible wafer detection method as described in any one of claims 1 to 7 are implemented.

10. A storage medium, characterized in that: The storage medium stores a wafer detection program compatible with film expansion, and when the wafer detection program compatible with film expansion is executed by the processor, the steps of the wafer detection method compatible with film expansion as described in any one of claims 1 to 7 are implemented.

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