Row driving output stage circuit, display driving chip, and LED display device

Abstract

The present application provides a row driving output stage circuit, a display driving chip, and an LED display device. The row driving output stage circuit is located at the output end of the row driving circuit and is connected to a row of LED lamp beads. The row driving output stage circuit includes: a primary transistor, whose control end receives an input signal, and whose output end is connected to the output end of the row driving circuit, and conducts according to the valid transition edge of the input signal; a first delay unit, which delays the valid transition edge of the input signal for a first time to obtain a first delayed signal; a final stage transistor, whose control end receives the first delayed signal, and whose output end is connected to the output end of the row driving circuit, and conducts after the primary transistor conducts. The primary transistor and the final stage transistor are of the same type of transistor, and the valid transition edge represents that the level state of the input signal changes from invalid to valid. The primary transistor is first turned on to discharge the charge of the parasitic capacitance of the output node, so as to avoid current overshoot at the moment of turning on. At the same time, after the final stage transistor conducts, it provides sufficient current capacity for the LED lamp beads.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and particularly relates to a row driving output stage circuit, a display driving chip, and an LED display device. Background Art

[0002] An LED display device generally includes an LED light source array and a display driving chip. The LED light source array includes a plurality of LED beads arranged in a row-column interleaved manner. The display driving chip is divided into a row driving chip and a column driving chip. For the row driving chip, it is connected to the same end of the LED beads in the same row to achieve common anode driving or common cathode driving. The row driving chip is responsible for providing driving current for all the LED beads on the row when the row is turned on. Therefore, it is required that the size of the MOS transistor in the output stage of the row driving chip is large to ensure sufficient driving current for the LED beads.

[0003] Figure 1 The partial structural schematic diagram of the row driving circuit in the prior art is shown, as Figure 1 shown, the output stage MOS transistor of the row driving circuit is a large-sized NMOS transistor, which is connected to the cathodes of the LED beads (D1, D2... Dm) in the same row. When the MOS transistor is turned on, a conduction path is formed, and current flows through the LED beads. The input signal IN of the row driving circuit needs to pass through a driver chain composed of a series of inverters to gradually increase the driving ability of the inverters to achieve the driving of the output stage MOS transistor. At the moment when the output stage MOS transistor is turned on, the parasitic capacitance Cs at the OUT end of the circuit output node will discharge through the MOS transistor, and due to the very small impedance of the MOS transistor, a large transient current will be generated on the power supply / ground at the moment of turning on, causing voltage fluctuations on the power supply / ground, thereby affecting the working state of the circuit. Therefore, currently, it is difficult to control the turn-on speed of the power transistor when the row driving circuit is turned on, and a large output overshoot will be generated, affecting the circuit operation. Summary of the Invention

[0004] In order to solve the above technical problems, the present application provides a row driving output stage circuit, a display driving chip, and an LED display device.

[0005] According to one aspect of the present invention, there is provided a row driving output stage circuit located at the output end of a row driving circuit. The output end of the row driving circuit is connected to the same end of a row of LED lamp beads. Wherein, the row driving output stage circuit includes: a primary transistor, whose control end receives an input signal, and whose output end is connected to the output end of the row driving circuit, and conducts according to the valid transition edge of the input signal; a first delay unit, which delays the valid transition edge of the input signal by a first time to obtain a first delay signal and then outputs it; a final stage transistor, whose control end receives the first delay signal, and whose output end is connected to the output end of the row driving circuit, and conducts after the primary transistor conducts. Wherein, the primary transistor and the final stage transistor are of the same type of transistor, and the valid transition edge represents that the level state of the input signal changes from invalid to valid.

[0006] Optionally, the row driving output stage circuit further includes: at least one intermediate stage transistor, whose control end is controlled by the input signal, and whose output end is connected to the output end of the row driving circuit, and conducts before the final stage transistor conducts. The at least one intermediate stage transistor and the primary transistor are of the same type of transistor.

[0007] Optionally, the row driving output stage circuit further includes: at least one second delay unit, which is correspondingly connected to the at least one intermediate stage transistor. Each second delay unit delays the valid transition edge of the input signal by a second time to obtain a second delay signal and then outputs it to the control end of the corresponding intermediate stage transistor.

[0008] Optionally, the size of the primary transistor is smaller than the size of the final stage transistor, and the size of the at least one intermediate stage transistor is smaller than the size of the final stage transistor.

[0009] Optionally, the row driving output stage circuit further includes: a plurality of enabling units, which are respectively correspondingly connected to a plurality of delay units. The plurality of delay units include the first delay unit and at least one second delay unit. Each enabling unit is connected between the corresponding delay unit and the control end of the corresponding transistor, and receives the input signal, an enabling signal, and a delay signal to provide a control signal to the corresponding transistor. The delay signal includes the first delay signal or the second delay signal.

[0010] Optionally, when the enabling signal is valid, the enabling unit uses the delay signal as the control signal; when the enabling signal is invalid, the enabling unit uses the input signal as the control signal.

[0011] Optionally, the enabling unit is a logic circuit composed of a plurality of logic gates. The logic gates include NAND gates, NOR gates, NOT gates, AND gates, OR gates, or XOR gates.

[0012] Optionally, the control terminal of each transistor is connected to a plurality of serially-connected inverters to perform signal enhancement processing on the received signal and then provide it to the control terminal of the transistor.

[0013] Optionally, the first delay unit and each of the second delay units each include: a switching transistor and a current source connected to each other, the control terminal of the switching transistor receiving the input signal; a capacitor connected between the intermediate node of the switching transistor and the current source and the ground terminal; and an inverter chain, the input terminal of the inverter chain being connected to the intermediate node of the switching transistor and the current source, and the output terminal of the inverter chain providing a delay signal, the delay signal including the first delay signal or the second delay signal.

[0014] Optionally, the types of the switching transistors included in the first delay unit and the second delay units are the same, and the area of the capacitor included in the first delay unit is larger than the area of the capacitor included in the second delay unit.

[0015] Optionally, when the same type of transistor is an NMOS transistor, the effective transition edge is the rising edge; when the same type of transistor is a PMOS transistor, the effective transition edge is the falling edge.

[0016] According to another aspect of the present invention, there is provided a display driving chip, including: a power supply; and a plurality of row driving circuits, each row driving circuit being connected to the same end of the same row of LED beads, wherein each of the row driving circuits includes the above-mentioned row driving output stage circuit.

[0017] According to another aspect of the present invention, there is provided an LED display device, including: an LED array, the LED array including a plurality of LED beads arranged in an array; and a plurality of row driving circuits, each row driving circuit correspondingly controlling one row of LED beads, and each of the row driving circuits includes the above-mentioned row driving output stage circuit, and the row driving output stage circuit enables a stable driving current to flow through the one row of LED beads after being fully turned on.

[0018] According to another aspect of the present invention, there is provided a terminal electronic device including the above-mentioned row driving output stage circuit.

[0019] The beneficial effects of the present application at least include:

[0020] Embodiments of the present application provide a row driving output stage circuit, a display driving chip, and an LED display device. The output stage of the row driving circuit is divided into multiple levels, and each level includes a transistor. Thus, the row driving output stage circuit includes at least a primary transistor and a final-stage transistor, and a first delay unit is connected to the control terminal of the final-stage transistor. The primary transistor is controlled to conduct first according to the input signal, forming a charge release path for the parasitic capacitance to slowly pull down the voltage of the output node and avoid current overshoot. Then, the first delay unit delays the effective transition edge of the input signal, so that the final-stage transistor conducts after the primary transistor has conducted for a first period of time, and thus the output stage circuit is fully conducted, capable of carrying a large current and providing a current path and sufficient current driving ability for the LED lamp beads at the output end during normal operation. By the cooperation of the primary transistor and the final-stage transistor, output overshoot at the moment of turning on is avoided, and the output stage can be made to conduct slowly to control the turning-on speed.

[0021] Further, the row driving output stage circuit further includes at least one intermediate-stage transistor that conducts before the final-stage transistor. The intermediate-stage transistor and the primary transistor cooperate with each other to precisely adjust the voltage drop speed of the output node, and thus adjust the turning-on speed of the output stage.

[0022] Further, an enabling unit is provided before the delay unit. The enabling unit can control the effective state of the delay signal. When the enabling signal is effective, the delay signal is provided to the control terminal of the corresponding transistor to make the transistor turn on with a delay; when the enabling signal is invalid, the input signal is provided to the corresponding transistor's control terminal to make the controlled transistor conduct and turn off simultaneously with the primary transistor, so that a current path can be quickly formed for the LED lamp beads in a row driving circuit that requires fast turning on.

[0023] It should be noted that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Description of the Drawings

[0024] Figure 1 Shows a partial structural schematic diagram of a row driving circuit in the prior art;

[0025] Figure 2 Shows a schematic circuit diagram of a row driving output stage circuit according to the first embodiment of the present invention;

[0026] Figure 3 Shows Figure 2 waveform schematic diagrams of various signals in the row driving output stage circuit of

[0027] Figure 4 Shows a schematic circuit diagram of a row driving output stage circuit according to the second embodiment of the present invention;

[0028] Figure 5 Shows a schematic circuit diagram of a row driving output stage circuit according to a third embodiment of the present invention;

[0029] Figure 6 Shows a schematic circuit diagram of a row driving output stage circuit according to a fourth embodiment of the present invention;

[0030] Figure 7 Shows a schematic circuit diagram of a row driving output stage circuit according to a fifth embodiment of the present invention;

[0031] Figure 8 Shows a schematic circuit diagram of a row driving output stage circuit according to a sixth embodiment of the present invention;

[0032] Figure 9 Shows a partial structural schematic diagram of an LED display device according to an embodiment of the present invention. Detailed implementation manners

[0033] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein.

[0034] The reference to "one embodiment" or "some embodiments" etc. in this specification means that specific features, structures or characteristics described in combination with the embodiment are included in one or more embodiments of the present application. Thus, the statements such as "in one embodiment", "in some embodiments", "in other some embodiments" etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "include", "comprise", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways. "Multiple" means two or more than two.

[0035] In addition, the same reference numerals in the drawings represent the same or similar structures, so the repeated description thereof will be omitted, that is, the various parts in this specification are described in a combined manner of parallelism and progression, and the key points of each part are the differences from other parts. For the same or similar parts between the parts, reference can be made to each other.

[0036] Figure 2 Shows a schematic circuit diagram of a row driving output stage circuit according to a first embodiment of the present invention, Figure 3 Shows Figure 2 A waveform schematic diagram of each signal in the row driving output stage circuit of.

[0037] And Figure 1Similarly, the row driving circuit of this embodiment is connected to the same end of a row of LED beads. When the output stage power transistor of the row driving circuit is an NMOS, the cathodes of a row of LED beads are connected together and connected to the output end of the row driving circuit. As Figure 2 shown, the row driving output stage circuit 100 of this embodiment is located at the output end of the row driving circuit (other circuit structures of the row driving circuit and the LED beads are not shown). Multiple transistors are selected to jointly serve as the output stage of the row driving circuit, and the output signal OUT is jointly provided from the drains of the multiple transistors. After the row driving output stage circuit 100 is fully turned on, a stable driving current flows through a row of LED beads.

[0038] As Figure 2 , the row driving output stage circuit 100 of this embodiment includes at least two levels of transistors, namely the primary transistor M0 and the final stage transistor M1. The control end of the primary transistor M0 receives the input signal IN, and the output end is connected to the output end of the row driving circuit, that is, the generation end of the output voltage OUT. In this embodiment, the primary transistor M0 is an NMOS transistor, its drain is connected to the output end, its source is grounded, and its gate is controlled by the input signal IN. The primary transistor M0 conducts and turns off according to the valid transition edge and the invalid transition edge of the input signal IN. The valid transition edge represents that the level state of the input signal IN changes from invalid to valid, and the invalid transition edge represents that the level state of the input signal IN changes from valid to invalid. That is, the primary transistor M0 conducts when the input signal IN is valid and turns off when the input signal IN is invalid. Here, the valid can be a high level and the invalid can be a low level. When the transistor is a PMOS transistor, the level state is opposite. A first driving chain 101 is also connected to the control end of the primary transistor M0. The first driving chain 101 includes multiple cascaded inverters to perform signal enhancement processing on the received input signal IN and then provide it to the control end of the primary transistor M0. The first driving chain 101 can include an even number of inverters, such as 4, to amplify the signal according to a certain ratio.

[0039] The final stage transistor M1 is the same type of transistor as the primary transistor M0, and is also an NMOS transistor. The drain of the final stage transistor M1 is connected to the output end, its source is grounded, and its control end is connected to the second driving chain 111. The second driving chain 111 also includes multiple cascaded inverters. A first delay unit 121 is also connected before the second driving chain 111. The first delay unit 121 is used to delay the valid transition edge of the input signal IN by a first time to obtain a first delay signal INDLY1 and then output it. The first delay unit 121 only delays the valid transition edge of the input signal IN by the first time while the invalid transition edge remains unchanged, that is, only delays the rising edge of the input signal IN by the first time to obtain the first delay signal INDLY1. Therefore, the control end of the final stage transistor M1 approximately receives the first delay signal INDLY1, and it conducts after the primary transistor M0 conducts.

[0040] In one embodiment, the first delay unit 121 includes a switching transistor P1, a current source A1, a first capacitor C1, and an inverter chain. The output stages of the row driving output stage circuit are all NMOS transistors, so the switching transistor P1 can be a PMOS transistor. Its control terminal receives the input signal IN, its source terminal receives the supply voltage V1, and its drain terminal is connected to the inverter chain. The switching transistor P1 and the current source A1 are connected in series, and the drain of the switching transistor P1 is grounded through the current source A1, that is, the current source A1 is connected between the drain of the switching transistor P1 and the ground terminal. The first capacitor C1 is connected between the intermediate node of the switching transistor P1 and the current source A1 and the ground terminal, that is, the first capacitor C1 is also connected between the drain of the switching transistor P1 and the ground terminal. The input terminal of the inverter chain is connected to the drain of the switching transistor P1, and the output terminal of the inverter chain provides the first delay signal INDLY1. Here, the inverter chain includes an odd number of inverters, for example, 3 inverters. Then, when the input signal IN is at a low level, the switching transistor P1 is turned on. The size of the switching transistor P1 is large, and it can quickly charge the first capacitor C1, making the input terminal of the inverter chain at a high level and the output terminal at a low level. The level state of the first delay signal INDLY1 is at a low level. When the input signal IN is at a high level, the switching transistor P1 is turned off, and the first capacitor C1 discharges through the current source A1. The current carried by the current source A1 is very small, so that the first capacitor C1 discharges with a very small current, restricting its discharge speed. The charge on the first capacitor C1 is released after a period of time, and only then does the output terminal of the inverter chain become high level, and the level state of the first delay signal INDLY1 is at a high level. Therefore, the first delay signal INDLY1 can only delay the rising edge of the input signal IN, while the falling edge remains unchanged, and the effective transition edge is the rising edge.

[0041] Of course, in other embodiments, the switching transistor in the first delay unit 121 can also be an NMOS transistor. At this time, the input terminal of the current source A1 is connected to the power supply terminal, the output terminal is connected to the drain of the NMOS transistor, the source of the NMOS transistor is grounded, and the connection manner of the first capacitor C1 and the inverter chain is the same as above. At this time, the input terminal of the NMOS transistor receives the inverted signal of the input signal IN, and the output terminal of the inverter chain outputs the inverted signal of the first delay signal. Therefore, an inverter also needs to be provided at the output terminal of the inverter chain to obtain the required first delay signal INDLY1.

[0042] Taking Figure 2 the shown circuit structure as an example, the corresponding signal waveform diagram is as Figure 3 shown, Figure 3Among them, before time t1, the input signal IN is at a low level, the level state of the first delay signal INDLY1 is also at a low level, the output stage transistors are not turned on, and the output voltage OUT at the output terminal is at a high level. At time t1, the input signal IN jumps from a low level to a high level, generating a valid transition edge of the input signal IN. The first delay signal INDLY1 still maintains a low level. At this time, the primary transistor M0 is turned on, and the output voltage OUT begins to slowly decrease, and the final stage transistor M1 is turned off. Since the size of the primary transistor M0 is small, the discharge is slow, and the output voltage will not have a large downward overshoot at time t1. At time t2, the first capacitor C1 is discharged completely, the level state of the first delay signal INDLY1 is at a high level, and the final stage transistor M1 begins to be turned on. The size of the final stage transistor M1 is larger than that of the primary transistor M0, and the on-resistance is very small, so that the output stage is completely turned on, the output voltage OUT is zero, and a current path is formed on the LED lamp bead. Then, the time period from t1 to t2 is the first time, and a constant current flows through the LED lamp bead during the time period from t2 to t3. At time t3, the input signal IN changes from a high level to a low level, generating an invalid transition edge of the input signal IN. The first delay signal INDLY1 also becomes a low level. The primary transistor M0 and the final stage transistor M1 are both turned off, the output stage circuit is turned off, and the output voltage OUT returns to a high level. Then, a new working cycle is started at time t4, repeating the previous actions, and the time period from t1 to t4 is one working cycle.

[0043] Figure 4 The schematic circuit diagram of the row driving output stage circuit according to the second embodiment of the present invention is shown. In some embodiments, the row driving output stage circuit may further include an intermediate stage transistor, such as Figure 4 As shown, the row driving output stage circuit 100 of this embodiment further includes at least one intermediate stage transistor on the basis of Figure 2 The control end of the intermediate stage transistor is controlled by the input signal IN, the output end is connected to the output end of the row driving circuit, the intermediate stage transistor is turned on before the final stage transistor is turned on, and is the same type of transistor as the primary transistor.

[0044] Figure 4Taking an intermediate-stage transistor M2 as an example, of course, it may also include multiple identical intermediate-stage transistors. The drain of the intermediate-stage transistor M2 is connected to the output terminal, the source is grounded, and the control terminal receives the input signal IN through a third driving chain 112 composed of multiple inverters. Therefore, the intermediate-stage transistor M2 in this embodiment can be turned on and off simultaneously with the primary transistor M0. The sizes of both the primary transistor M0 and the intermediate-stage transistor M2 are smaller than the size of the final-stage transistor M1. After the primary transistor M0 and the intermediate-stage transistor M2 are turned on, the output voltage OUT slowly decreases. And the decreasing speed of the output voltage OUT can be adjusted by adjusting the sizes of the primary transistor M0 and the intermediate-stage transistor M2, thereby adjusting the turning-on speed of the output-stage circuit.

[0045] Figure 5 FIG. shows a schematic circuit diagram of a row driving output-stage circuit according to the third embodiment of the present invention. As Figure 5 shown, in this embodiment, Figure 4 on the basis of the

[0046] embodiment, a second delay unit 122 is further added. Each second delay unit is respectively connected to an intermediate-stage transistor correspondingly. For example, the second delay unit 122 is connected to the control terminal of the intermediate-stage transistor M2 through the third driving chain 112. The circuit structure and working principle of the second delay unit 122 are the same as those of the first delay unit 121. The second delay unit 122 delays the valid transition edge of the input signal IN by a second time to obtain a second delay signal INDLY2 and then outputs it to the control terminal of the corresponding intermediate-stage transistor M2.

[0047] Figure 6 FIG. shows a schematic circuit diagram of a row driving output-stage circuit according to the fourth embodiment of the present invention. As Figure 6 shown, the row driving output-stage circuit 100 of this embodiment is Figure 2On the basis of the embodiment, an enabling unit 131 is added. The enabling unit 131 is connected to the first delay unit 121 and can control the effective state of the first delay signal INDLY1, that is, determine whether the first delay signal INDLY1 is effective. When the line driving output stage circuit 100 includes multiple stages of transistors, for example, includes a primary transistor, a final stage transistor, and at least one intermediate stage transistor, and the control terminals of the final stage transistor and each intermediate stage transistor are connected to the delay unit, an enabling unit can be provided for each delay unit of the transistor. That is, the enabling unit 131 can be matched with the delay unit.

[0048] In this embodiment, the enabling unit 131 is connected between the first delay unit 121 and the control terminal of the final stage transistor M1. The enabling unit 131 receives the input signal IN, the enabling signal EN, and the first delay signal INDLY1 to provide the control signal CTRL1 to the final stage transistor M1. The enabling unit 131 can be connected to the output end of the second driving chain 111 or the input end of the second driving chain 111, and the specific position is determined according to actual requirements. When the enabling signal EN is effective, the enabling unit 131 uses the first delay signal INDLY1 as the control signal CTRL1; when the enabling signal EN is invalid, the control signal CTRL1 is controlled by the input signal IN. For example, the enabling unit 131 uses the input signal IN as the control signal CTRL1.

[0049] The enabling unit 131 is a logic circuit composed of multiple logic gates. The logic gates include NAND gates, NOR gates, NOT gates, AND gates, OR gates, or XOR gates. Specifically, taking the final stage transistor M1 as an NMOS transistor and the first delay unit 121 as Figure 2 the circuit structure shown in, and taking the enabling unit 131 including a NOT gate O3, an OR gate, and an AND gate as an example for illustration. The input end of the NOT gate O3 receives the enabling signal EN, and the output end is connected to one input end of the OR gate. The other input end of the OR gate receives the first delay signal INDLY1, and the output end is connected to one input end of the AND gate. The other input end of the AND gate receives the input signal IN, and the output end provides the control signal CTRL1. In some embodiments, the OR gate can be replaced by a combination of a NOR gate and a NOT gate, and the AND gate can be replaced by a combination of a NAND gate and a NOT gate. For example Figure 6In it, the enabling unit 131 includes a NOT gate O3, a NOR gate U1, a NOT gate O1, a NAND gate U2, and a NOT gate O2, where the NOR gate U1 and the NOT gate O1 are equivalent to an OR gate, and the NAND gate U2 and the NOT gate O2 are equivalent to an AND gate. The NOT gate O3 receives the enabling signal EN to obtain the inverted signal ENB of the enabling signal. The two input terminals of the NOR gate U1 respectively receive the inverted signal ENB of the enabling signal and the first delay signal INDLY1. The output of the NOR gate U1 outputs an intermediate signal X through the NOT gate O1. The output terminal of the NOT gate O1 is connected to one input terminal of the NAND gate U2. The other input terminal of the NAND gate U2 receives the input signal IN, and the output terminal provides the control signal CTRL1 through the NOT gate O2. Then, when the enabling signal EN is invalid, EN = 0, ENB = 1, the intermediate signal X is at a high level, and the output control signal CTRL1 is controlled by the input signal IN, and the primary transistor M0 and the final-stage transistor M1 are turned on simultaneously; when the enabling signal EN is valid, EN = 1, ENB = 0, the output control signal CTRL1 is controlled by the first delay signal INDLY1, and the final-stage transistor M1 is turned on with a delay.

[0050] In other embodiments, when the switching transistor in the first delay unit 121 is an NMOS transistor, the input terminal of the current source A1 is connected to the power supply terminal, the output terminal is connected to the drain of the NMOS transistor, and the source of the NMOS transistor is grounded. At this time, the input terminal of the NMOS transistor receives the inverted signal of the input signal IN, and an additional inverter needs to be connected to the output terminal of the inverter chain in the first delay unit 121 to obtain the first delay signal INDLY1, and then through Figure 6 The enabling unit 131 shown can obtain the control signal. When the switching transistor in the first delay unit 121 is an NMOS transistor, but no additional inverter is connected to the output terminal of the inverter chain, the output terminal of the inverter chain can be directly connected to the enabling unit. At this time, the structure of the enabling unit also needs to be changed. The enabling unit at this time can only include an OR gate and an AND gate. And the OR gate replaces Figure 6 the combination of the NAND gate U2 and the NOT gate O2 in Figure 6 and the AND gate replaces Figure 8 the combination of the NOR gate U1 and the NOT gate O1 in Figure 8 The specific circuit structure of the enabling unit 131 shown can be referred to in the subsequent

[0051] Of course, the first delay unit 121 and the enabling unit 131 can also have other circuit structures and combination forms, which will not be exemplified one by one here. Those skilled in the art can infer according to the above description.

[0052] Figure 7Shows a schematic circuit diagram of a row driving output stage circuit according to a fifth embodiment of the present invention. As Figure 7 shown, in this embodiment, the row driving output stage circuit includes a primary transistor M0, a final stage transistor M1, and a plurality of intermediate stage transistors (M2... Mn). Combining Figures 5 - 7 with the embodiment, an output terminal of the first delay unit 121 and an output terminal of each of the plurality of second delay units 122 are connected to an enable unit 131. That is, the plurality of enable units are respectively connected to the plurality of delay units in a one-to-one correspondence. The plurality of delay units include a first delay unit and at least one second delay unit, and each enable unit is connected between the corresponding delay unit and the control terminal of the corresponding transistor, and receives an input signal, an enable signal, and a delay signal to provide a control signal to the corresponding transistor. The delay signal includes a first delay signal or a second delay signal. Similarly, a driving chain composed of a plurality of serially connected inverters can be connected to the control terminal of each transistor to perform signal enhancement processing on the received signal and then provide it to the control terminal of the transistor. For each enable unit 131, when the enable signal is valid, the enable unit 131 uses the delay signal as the control signal; when the enable signal is invalid, the enable unit 131 uses the input signal as the control signal. Further, the second time in each second delay unit may not be exactly the same, so that the plurality of intermediate stage transistors may not be turned on simultaneously.

[0053] The enable unit in this embodiment may be Figure 6 the circuit structure shown in, or other circuit structures that can achieve similar functions. Here, it is only an example and does not limit the embodiments of the present invention. In this embodiment, the plurality of enable units are respectively controlled by a plurality of enable signals, and by configuring the values of different enable signals EN, the opening speed of the output stage circuit can be adjusted and controlled.

[0054] Figure 8 Shows a schematic circuit diagram of a row driving output stage circuit according to a sixth embodiment of the present invention. The above-mentioned output stage transistors are all NMOS transistors. In actual applications, the output stage transistors can also be all PMOS transistors. When the output stage transistors are all PMOS transistors, the drains of the PMOS transistors are connected together as the output terminal of the output stage circuit to provide an output voltage OUT, and the sources receive the power supply voltage VDD, and the control terminals respectively receive the input signal IN or the delay signal via the driving chain. Figure 8 The circuit structures identical to those in the above embodiments will not be described in detail here.

[0055] As Figure 8As shown, as an example, the row driving output stage circuit 100 includes a primary transistor M0, a final stage transistor M1, a first driving chain 101, a second driving chain 111, a first delay unit 121, and an enabling unit 131. The first delay unit 121 includes a switching transistor N1, a current source A1, a first capacitor C1, and an inverter chain. When the final stage transistor M1 is a PMOS transistor, the switching transistor N1 is, for example, an NMOS transistor. The switching transistor N1 is connected in series with the current source A1, and the source of the switching transistor N1 is grounded, and the drain is connected to the power supply terminal through the current source A1. The first capacitor C1 is connected between the intermediate node of the switching transistor N1 and the current source A1 and the ground terminal, that is, the first capacitor C1 is connected between the drain of the switching transistor N1 and the ground terminal. The inverter chain includes an odd number of inverters, for example, three. The input terminal of the inverter chain is connected to the drain of the switching transistor N1, and the output terminal outputs a first delay signal INDLY1. At this time, the effective transition edge is the falling edge, which is effective during the low level of the input signal IN and invalid during the high level.

[0056] When the final stage transistor M1 is a PMOS transistor, the enabling unit 131 includes an AND gate and an OR gate. The two input terminals of the AND gate respectively receive the enabling signal EN and the first delay signal INDLY1, and the output terminal is connected to one input terminal of the OR gate. The other input terminal of the OR gate receives the input signal IN, and the output terminal provides a control signal CTRL1. In some embodiments, the OR gate can be replaced by a combination of a NOR gate and a NOT gate, and the AND gate can be replaced by a combination of a NAND gate and a NOT gate. For example Figure 8 in, the enabling unit 131 includes a NAND gate U1, a NOT gate O1, a NOR gate U2, and a NOT gate O2, where the NAND gate U1 and the NOT gate O1 are equivalent to an AND gate, and the NOR gate U2 and the NOT gate O2 are equivalent to an OR gate. The two input terminals of the NAND gate U1 respectively receive the enabling signal EN and the first delay signal INDLY1. The output of the NAND gate U1 passes through the NOT gate O1 to obtain an intermediate signal X. The output terminal of the NOT gate O1 is connected to one input terminal of the NOR gate U2. The other input terminal of the NOR gate U2 receives the input signal IN, and the output terminal provides a control signal CTRL1 through the NOT gate O2. Then, when the enabling signal EN is invalid, EN = 0, the intermediate signal X is at a low level, and the output control signal CTRL1 is controlled by the input signal IN, and the primary transistor M0 and the final stage transistor M1 are turned on simultaneously; when the enabling signal EN is valid, EN = 1, the output control signal CTRL1 is controlled by the first delay signal INDLY1, and the final stage transistor M1 is turned on with a delay. Other identical circuit structures will not be described here.

[0057] In other embodiments, Figure 8 the first delay unit 121 in Figure 2The circuit structure of the first delay unit 121 therein. At this time, the switching transistor is a PMOS transistor, the control terminal of the switching transistor receives the inverted signal of the input signal IN, and the output terminal of the inverter chain can be further connected to an inverter. The enable unit still uses Figure 8 The circuit structure shown by the enable unit 131 therein represents. Of course, Figure 8 The first delay unit 121 therein can be replaced with Figure 2 The first delay unit 121 therein. The control terminal of the switching transistor receives the inverted signal of the input signal IN, and the output terminal of the inverter chain is directly connected to the enable unit. At this time, it is necessary to replace Figure 8 The enable unit therein with Figure 2 The circuit structure of the enable unit 131 therein, and connect an inverter to the output terminal of Figure 2 The enable unit 131 to obtain the required control signal CTRL1.

[0058] Of course, the present invention also provides a row driving circuit and a display driving chip. The row driving circuit includes the above Figures 2 - 8 Row driving output stage circuit shown in any embodiment. The display driving chip is used to drive a display panel. The display panel is, for example, an LED panel. The display driving chip can include multiple row driving circuits, and each row driving circuit is connected to the same end of the LED lamp beads in the same row. The display driving chip can also include a power supply and other circuit structures, such as a discharge circuit, a timing controller, etc.

[0059] Figure 9 Shows a partial structural schematic diagram of an LED display device according to an embodiment of the present invention.

[0060] As Figure 9 Shown, this embodiment also provides an LED display device 300. The LED display device 300 includes an LED array 320 and multiple row driving circuits 310. The LED array 320 includes multiple LED lamp beads D arranged in an array. Each row driving circuit 310 correspondingly controls a row of LED lamp beads, and each row driving circuit 310 includes the row driving output stage circuit 100 of the above embodiment. After being fully turned on, the row driving output stage circuit enables a stable driving current to flow through the corresponding row of LED lamp beads.

[0061] Furthermore, the present invention can also provide a terminal electronic device. The terminal electronic device can include the row driving output stage circuit of any of the above embodiments. For example, the terminal electronic device can include Figure 9 The LED display device described. The terminal electronic device can be a mobile phone, a tablet computer, an electronic watch, etc., but is not limited thereto.

[0062] The row driving output stage circuit, display driving chip and LED display device according to the embodiments of the present invention divide the output stage of the row driving circuit into multiple levels, each level includes a transistor, so that the row driving output stage circuit includes at least a primary transistor and a final stage transistor, and a first delay unit is connected to the control end of the final stage transistor. The primary transistor is controlled to conduct first according to the input signal, forming a charge release path for the parasitic capacitance to slowly pull down the voltage of the output node, avoiding current overshoot. The effective transition edge of the input signal is delayed by the first delay unit, so that the final stage transistor conducts after the primary transistor has conducted for a first time, and thus the output stage circuit is fully conducted, which is sufficient to carry a large current, providing a current path for normal operation and sufficient current driving ability for the LED lamp beads at the output end. By the cooperation of the primary transistor and the final stage transistor, the output overshoot at the moment of turning on is avoided, and the output stage can be made to conduct slowly to control the turning-on speed.

[0063] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present application, rather than limiting the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made on the basis of the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present application.

Claims

1. A row driver output stage circuit, located at the output end of the row driver circuit, the output end of the row driver circuit is connected to the same end of a row of LED lamp beads, characterized in that: The row driver output stage circuit comprises: A primary transistor, the control end of which receives an input signal, the output end of which is connected to the output end of the row driving circuit, and is turned on according to a valid transition edge of the input signal; A first delay unit, delaying the effective transition edge of the input signal for a first time to obtain a first delayed signal and then outputting it; a final-stage transistor, a control end receiving the first delayed signal, an output end connected to the output end of the row driving circuit, and turned on after the primary transistor is turned on; and at least one intermediate stage transistor, whose control end is controlled by the input signal, whose output end is connected to the output end of the row driving circuit, and which is turned on before the final stage transistor is turned on, The primary transistor and the final transistor are transistors of the same type, the at least one intermediate transistor and the primary transistor are transistors of the same type, and the effective transition edge represents that the level state of the input signal changes from invalid to valid.

2. The row driver output stage circuit according to claim 1, characterized in that: Also includes: At least one second delay unit is connected to the at least one intermediate stage transistor. Each second delay unit delays the effective transition edge of the input signal for a second time to obtain a second delay signal and then outputs it to the control end of the corresponding intermediate stage transistor.

3. The row driver output stage circuit according to claim 1, characterized in that: The size of the primary stage transistor is smaller than the size of the final stage transistor, and the size of the at least one intermediate stage transistor is smaller than the size of the final stage transistor.

4. The row driver output stage circuit according to claim 2, characterized in that: Also includes: A plurality of enabling units are respectively connected to a plurality of delay units, wherein the plurality of delay units include the first delay unit and the at least one second delay unit. Each enabling unit is connected between the corresponding delay unit and the control terminal of the corresponding transistor, receives the input signal, the enabling signal and the delay signal to provide a control signal to the corresponding transistor, and the delay signal includes the first delay signal or the second delay signal.

5. The row driver output stage circuit according to claim 4, characterized in that: When the enable signal is valid, the enable unit uses the delay signal as the control signal; when the enable signal is invalid, the enable unit uses the input signal as the control signal.

6. The row driver output stage circuit according to claim 4, characterized in that: The enabling unit is a logic circuit composed of a plurality of logic gates, wherein the logic gates include a NAND gate, a NOR gate, a NOT gate, an AND gate, an OR gate or an XOR gate.

7. The row driver output stage circuit according to any one of claims 1 to 6, characterized in that: The control end of each transistor is connected to a plurality of inverters connected in series, so as to perform signal enhancement processing on the received signal and then provide it to the control end of the transistor.

8. The row driver output stage circuit according to claim 2, characterized in that: The first delay unit and each of the second delay units include: A switch tube and a current source connected to each other, wherein a control end of the switch tube receives the input signal; A capacitor connected between an intermediate node between the switch tube and the current source and a ground terminal; and An inverter chain, wherein an input end of the inverter chain is connected to an intermediate node between the switch tube and the current source, and an output end of the inverter chain provides a delayed signal, wherein the delayed signal includes the first delayed signal or the second delayed signal.

9. The row driver output stage circuit according to claim 8, characterized in that: The switch tubes included in the first delay unit and the second delay unit are of the same type, and the area of ​​the capacitor included in the first delay unit is larger than the area of ​​the capacitor included in the second delay unit.

10. The row driver output stage circuit according to claim 1, characterized in that: When the transistors of the same type are NMOS tubes, the effective transition edge is a rising edge; when the transistors of the same type are PMOS tubes, the effective transition edge is a falling edge.

11. A display driver chip, characterized in that: include: power supply; as well as Multiple row drive circuits, each row drive circuit is connected to the same end of the same row of LED lamp beads, Wherein, each of the row driving circuits comprises a row driving output stage circuit according to any one of claims 1-10.

12. An LED display device, characterized in that: include: An LED array, wherein the LED array includes a plurality of LED lamp beads arranged in an array; as well as A plurality of row drive circuits, each row drive circuit correspondingly controls a row of LED lamp beads, Each of the row driving circuits comprises a row driving output stage circuit according to any one of claims 1 to 10, and the row driving output stage circuit allows a stable driving current to flow through the row of LED lamp beads after being fully turned on.

13. A terminal electronic device, characterized in that: include: A row driver output stage circuit according to any one of claims 1 to 10.

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