Visual automatic online detection system and method for semiconductor processing quality

Abstract

The invention discloses a visual automatic online detection system and method for semiconductor processing quality, and relates to the technical field of semiconductor processing. The method comprises the following steps: for a series of feature point combinations in different number states, taking a local image of each feature point in the feature point combinations as an input layer, taking a corresponding electrical property detection result as an output layer, and training a detection model to be converged to obtain the detection model; inputting the local image of each feature point in the series of feature point combinations in different number states into the output layer probability distribution of the corresponding detection model, and screening out the feature point combinations in different number states; and extracting a local image of a specific feature point combination of each chip etching area in the to-be-detected wafer according to the feature point combinations in different number states, and inputting the local image into a corresponding detection model to obtain an electrical property pre-estimation result of each chip etching area in the to-be-detected wafer. According to the invention, the rate of semiconductor visual inspection is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor processing, and in particular relates to a visual automatic online detection system and method for semiconductor processing quality. Background Art

[0002] With the rapid development of semiconductor technology, the requirements for the processing quality of semiconductor products are also increasing. Traditional semiconductor processing quality inspection mostly relies on manual visual inspection and simple mechanical inspection equipment, which is not only inefficient, but also has limited detection accuracy, making it difficult to meet the high standards of the modern semiconductor industry. Summary of the invention

[0003] The object of the present invention is to provide a system and method for automatic online visual inspection of semiconductor processing quality, which improves the rate of semiconductor visual inspection by targeted selection of feature points.

[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a method for automatic online visual inspection of semiconductor processing quality, comprising: Obtain chip etching area within the wafer; Obtain sample images and electrical test results of chip etching areas within sample wafers; For each chip etch area, According to the image feature analysis of each sample image, multiple feature points are obtained. The feature points of different quantity states are combined to obtain a series of feature point combinations under different quantity states. For a series of feature point combinations in different numbers, the local image of each feature point in the feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain a detection model. According to the local image input of each feature point in the series of feature point combinations in different numbers of states, the output layer probability distribution of the detection model is corresponding to the filter out feature point combinations in different numbers of states; Acquire a wafer image of a chip etching area within a wafer to be inspected; The detection model corresponding to the local image input of the specific feature point combination of each chip etching area in the wafer to be detected is extracted according to the feature point combination in different quantity states to obtain the electrical property estimation result of each chip etching area in the wafer to be detected.

[0005] The present invention also discloses a method for automatic online visual inspection of semiconductor processing quality, comprising: Obtain the electrical property estimation results of each chip etching area in the wafer to be tested; Mark chip etch areas where electrical properties are poorly estimated.

[0006] The present invention also discloses a method for automatic online visual inspection of semiconductor processing quality, comprising: Obtain the electrical property estimation results of each chip etching area in the wafer to be tested; The chip etching areas with poor electrical property estimation results are removed.

[0007] The present invention also discloses a semiconductor processing quality automatic online visual detection system. An online detection unit for obtaining chip etching areas within the wafer; Obtain sample images and electrical test results of chip etching areas within sample wafers; For each chip etch area, According to the image feature analysis of each sample image, multiple feature points are obtained. The feature points of different quantity states are combined to obtain a series of feature point combinations under different quantity states. For a series of feature point combinations in different numbers, the local image of each feature point in the feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain a detection model. According to the local image input of each feature point in the series of feature point combinations in different numbers of states, the output layer probability distribution of the detection model is corresponding to the filter out feature point combinations in different numbers of states; Acquire a wafer image of a chip etching area within a wafer to be inspected; The detection model corresponding to the local image input of the specific feature point combination of each chip etching area in the wafer to be detected is extracted according to the feature point combination in different quantity states to obtain the electrical property estimation result of each chip etching area in the wafer to be detected; A defective product marking unit is used to obtain the electrical property estimation results of each chip etching area in the wafer to be inspected; Mark chip etched areas with poor electrical property prediction results; A defective rejection unit is used to obtain the electrical property estimation results of each chip etching area in the wafer to be inspected; The chip etching areas with poor electrical property estimation results are removed.

[0008] The present invention analyzes the sample image and electrical detection results of the chip etching area in the sample wafer through an online detection unit to screen out the feature point combinations in different quantity states of each chip etching area. In the process of identifying the wafer image of the chip etching area in the wafer to be detected, the local image input corresponding to the specific feature point combination of each chip etching area in the wafer to be detected is extracted according to the feature point combination in different quantity states, and the detection model corresponding to the input is obtained. In this process, since fewer feature point combinations are preferentially used for detection and recognition, the online recognition rate is improved while taking into account the recognition accuracy.

[0009] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0011] Figure 1 A schematic diagram of functional units and information flow of a semiconductor processing quality automatic online visual inspection system according to an embodiment of the present invention; Figure 2 A schematic diagram of a step flow of an online detection unit according to an embodiment of the present invention; Figure 3 A schematic diagram of the steps of the bad product marking unit in one embodiment of the present invention; Figure 4 A schematic diagram of the steps of a defective product rejection unit according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the step flow of step S6 in one embodiment of the present invention; Figure 6 A schematic diagram of a step flow chart of step S65 of the present invention in an embodiment; Figure 7 It is a schematic diagram of the step flow of step S652 in one embodiment of the present invention; Figure 8 This is a schematic diagram of the step flow of step S8 in one embodiment of the present invention; Fig. 9 This is a schematic diagram of the step flow of step S83 in one embodiment of the present invention; In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1-Online detection unit, 2-Defective product marking unit, 3-Defective product rejection unit. DETAILED DESCRIPTION

[0012] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0013] It should be noted that the terms "first", "second", etc. in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0014] See also Figures 1 to 4 As shown, the present invention provides a visual automatic online inspection system for semiconductor processing quality, which is divided from the functional units, including an online inspection unit 1, a defective marking unit 2 and a defective rejection unit 3. Since the wafer fab adopts an assembly line method to etch the wafer, the speed of the inspection needs to be maintained during the inspection process, and the accuracy of the inspection also needs to be met. In this solution, the online inspection unit 1 is responsible for quickly and accurately detecting the inspection results of the chip etching area in the wafer, that is, the electrical estimation results of each chip etching area in the wafer to be inspected. Afterwards, the defective marking unit 2 marks the unqualified chip etching area in the wafer, and the defective rejection unit 3 can also reject the unqualified chip etching area in the wafer, which can be specifically scrapped or shielded.

[0015] During the operation of the system, the online detection unit 1 first executes step S1 to obtain the chip etching area in the wafer. This is because multiple chips are usually etched in a wafer, and each chip corresponds to a chip etching area. Next, step S2 can be executed to obtain a sample image and electrical detection results of the chip etching area in the sample wafer. The electrical detection results of the chip usually include DC test, AC test, power consumption test, parameter test, functional test, noise test and failure analysis. DC test includes testing the static parameters such as the input and output voltage, current, and leakage current of the chip. AC test measures the response of the chip under high-frequency signals, such as dynamic performance such as propagation delay, rise time and fall time. Power consumption test measures the power consumption of the chip in different working modes, including static power consumption and dynamic power consumption. Parameter test includes the detection of key circuit parameters such as amplifier gain, bias voltage, input and output impedance. Functional test verifies the function of the chip in actual work, such as logic function verification of logic circuit, memory read and write function, etc. Noise test measures the background noise and signal-to-noise ratio of the chip to determine its signal integrity. Failure analysis conducts in-depth analysis of anomalies found during electrical testing to determine the cause of chip failure, such as short circuit, open circuit, etc.

[0016] In subsequent work, the online detection unit 1 can first perform step S3 for each chip etching area to obtain multiple feature points according to the image feature analysis of each sample image. The feature points here are used to describe special and recognizable points in the image in image processing. They are usually prominent and difficult to change positions in the image, which can help establish correspondence between different images. The detection and matching of feature points is the basis of many computer vision tasks, such as image stitching, target recognition, stereo matching, etc. The feature points in this scheme can be corner points, edge feature points, spot features, scale-invariant feature points, region-based feature points, and angle and direction information in the image.

[0017] After that, the online detection unit 1 can then execute step S4 to combine feature points of different quantity states to obtain a series of feature point combinations under different quantity states. Next, step S5 can be executed to take the local image of each feature point in the feature point combination as the input layer, and the corresponding electrical detection result as the output layer for the series of feature point combinations under different quantity states, and train the detection model until convergence to obtain the detection model. Next, step S6 can be executed to filter out feature point combinations under different quantity states according to the probability distribution of the output layer of the corresponding detection model based on the local image input of each feature point in the series of feature point combinations under different quantity states. Feature point combinations with a larger number of feature points have a faster processing speed, but there may be a phenomenon of low inspection accuracy, so feature point combinations under different feature point quantity states are prepared in this solution.

[0018] During the online detection of the wafer to be detected, step S7 can be first executed to obtain a wafer image of the chip etching area in the wafer to be detected. Then step S8 can be executed to extract the local image of the specific feature point combination of each chip etching area in the wafer to be detected according to the feature point combination in different quantity states, and input the corresponding detection model to obtain the electrical property estimation result of each chip etching area in the wafer to be detected. In the process of online detection, the feature point combination with a smaller number of feature points can be detected first. If the detection accuracy cannot be met, the feature point combination with a larger number of feature points can be detected. In this way, both the detection speed and accuracy can be taken into account.

[0019] The defective marking unit 2 in the system may first execute step S021 to obtain the electrical property prediction result of each chip etching area in the wafer to be inspected, and then execute step S022 to mark the chip etching area with poor electrical property prediction result, thereby marking the defective chips.

[0020] The defective rejection unit 3 in the system can first execute step S031 to obtain the electrical property prediction result of each chip etching area in the wafer to be inspected, and then execute step S032 to reject the chip etching area with poor electrical property prediction results, thereby eliminating the defective chips.

[0021] See also Figure 5 As shown, since there are a large number of feature points in the image of each chip etching area of ​​the wafer, not every feature point is relevant to quality detection, and the relevance is also different. Generally speaking, the more feature points there are, the more accurate the wafer quality detection is. In order to screen out valuable feature point combinations of different quantity states, the online detection unit 1 can first execute step S61 to obtain the total number of feature points. Next, step S62 can be executed to perform gradient division from large to small starting from the total number of all feature points to obtain multiple quantity states. Next, step S63 can be executed to extract feature points of corresponding quantity states from all feature points under each quantity state restriction and combine them to obtain feature point combinations under different quantity states.

[0022] In order to verify the detection accuracy of different feature point combinations, step S64 can be executed next. For each quantity state, the local image of each feature point in each feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain the detection model of each feature point combination under each quantity state. Next, step S65 can be executed to use the sample image of the chip etching area in the wafer and the electrical detection result as test data to test the detection model to obtain the estimated recognition accuracy of the detection model of each feature point combination under each quantity state. Next, step S66 can be executed to obtain the target recognition accuracy, which can be set by the staff. Finally, step S67 can be executed to eliminate the feature point combinations under different quantity states corresponding to the detection model whose estimated recognition accuracy is less than the target recognition accuracy, and screen the feature point combinations under different quantity states. The number of feature point combinations after screening is different, and they are all relevant to wafer quality detection.

[0023] See also Figure 6 As shown, since the wafer detection accuracy of the detection model of different feature point combinations is different, in order to quantify it, for each feature point combination in each quantity state, the online detection unit 1 can first execute step S651 to input the local image of different sample graphics under the feature point combination into the input layer of the corresponding detection model, and obtain the recognition accuracy of the detection model for different sample graphics based on the probability of each output item in the output layer of the detection model. Next, step S652 can be executed to obtain the estimated recognition accuracy of the detection model corresponding to the feature point combination in the quantity state according to the numerical characteristics of the recognition accuracy of the detection model for different sample graphics. Finally, step S653 can be executed to summarize and obtain the estimated recognition accuracy of the detection model for each feature point combination in each quantity state.

[0024] See also Figure 7As shown, since each chip etching area corresponds to multiple sample images, the recognition accuracy of its detection model for different sample graphics is different. If only the mean of the recognition results is taken, it cannot fully represent the recognition accuracy of the detection model. At the same time, if only the minimum value is taken, it is not sufficiently representative. Therefore, in this solution, step S6521 can be first executed to arrange the recognition accuracy of the detection model for different sample graphics in the order of numerical value to obtain a recognition accuracy series. Next, step S6522 can be executed to calculate the mean of the difference between each value and the adjacent value in the recognition accuracy series as the screening step. Next, step S6523 can be executed to select the minimum value in the recognition accuracy series as the estimated participation value. Next, step S6524 can be executed to start from the estimated participation value and calculate the difference with the adjacent values ​​from small to large along the recognition accuracy series. Next, step S6525 can be executed to determine whether the difference is less than the screening step. If so, step S6526 can be executed next to change the adjacent values ​​of the estimated participation value to the estimated participation value, and then step S6524 can be executed to continue calculating the difference. If not, step S6527 can be executed to stop, and the average of all estimated participation values ​​can be used as the estimated recognition accuracy of the detection model corresponding to the feature point combination under this quantity state.

[0025] In short, in this scheme, multiple recognition accuracy rates with lower values ​​are screened out, and the estimated recognition accuracy rate of the detection model is calculated comprehensively based on them.

[0026] In order to supplement the implementation process of the above steps S6521 to S6527, the source code of some functional modules is provided, and the explanation is made in the comment section. In order to avoid the leakage of data involving commercial secrets, some data that does not affect the implementation of the solution are desensitized, the same below.

[0027] #include <iostream> #include <vector> #include <algorithm> #include <numeric> / / Example of the following namespace using namespace std; / / Calculate the mean of the difference between each value and the adjacent value in the recognition accuracy series as the filtering step length double calculateStepSize(const vector <double>& accuracies) { vector <double>differences; for (size_t i = 1; i < accuracies.size(); ++i) { differences.push_back(accuracies[i] - accuracies[i - 1]); } / / Calculate the mean of the differences double stepSize = accumulate(differences.begin(), differences.end(), 0.0) / differences.size(); return stepSize; } / / Calculate the estimated recognition accuracy double estimateAccuracy(const vector <double>& accuracy) { / / Sort the recognition accuracy by numerical value vector <double>sortedAccuracies = accuracies; sort(sortedAccuracies.begin(), sortedAccuracies.end()); / / Calculate the filtering step length double stepSize = calculateStepSize(sortedAccuracies); / / The initial estimated participation value is the minimum value of the sequence double estimateValue = sortedAccuracies.front(); / / Calculate the difference along the recognition accuracy series starting from the minimum value for (size_t i = 1; i < sortedAccuracies.size(); ++i) { double difference = sortedAccuracies[i] - estimateValue; if (difference < stepSize) { / / If the difference is less than the filtering step, update the estimated participation value estimateValue = sortedAccuracies[i]; } else { / / If the difference is greater than or equal to the filter step, stop calculating break; } } / / Return the mean of the estimated participation values ​​as the estimated recognition accuracy double estimatedAccuracy = estimateValue; return estimatedAccuracy; } int main() { / / Example recognition accuracy of different sample graphics vector <double>accuracies = {0.82, 0.85, 0.83, 0.88, 0.87, 0.90}; / / Calculate the estimated recognition accuracy of the detection model corresponding to the feature point combination under this number state double estimatedAccuracy = estimateAccuracy(accuracies); / / Output estimated recognition accuracy cout << "Estimated recognition accuracy: " << estimatedAccuracy < <endl; return 0; } This code implements an algorithm that calculates the estimated recognition accuracy of feature point combinations under a specific number of states by detecting the recognition accuracy series of the model. First, the recognition accuracy series is arranged in order of size, and then the mean of the difference between adjacent values ​​in the series is calculated as the screening step. Starting from the minimum value of the series, the difference between adjacent values ​​is calculated step by step along the series, and it is determined whether it is less than the screening step. Finally, the mean of the values ​​that meet the conditions is used as the estimated recognition accuracy of the feature point combination. This process helps to extract representative accuracy for model evaluation and optimization.

[0028] See also Figure 8 As shown, during the quality inspection of the wafer to be inspected, the online inspection unit 1 can first execute step S81 to obtain each feature point combination in each quantity state for each chip etching area in the wafer to be inspected.

[0029] For each chip etching area in the wafer to be detected, step S82 can be first executed to select each quantity state in order from small to large along the numerical value of the quantity state of the feature point. Next, step S83 can be executed to check the combination of multiple feature points contained in each quantity state to determine whether an electrical property estimation result that reaches the target recognition accuracy can be obtained. If yes, then step S84 can be executed to obtain the electrical property estimation result of the chip etching area in the wafer to be detected.

[0030] If it is not, it means that the number of selected feature points is insufficient for accurate wafer quality judgment. Therefore, step S85 can be executed next to stop the number state selected this time, select the number state with a larger value and iteratively test the multiple feature point combinations contained therein, and then return to execute step S82 to determine whether an electrical property estimation result that reaches the target recognition accuracy can be obtained, until an electrical property estimation result that reaches the target recognition accuracy is obtained, or the number state of all feature points is exhausted. Finally, step S86 can be executed next to summarize the electrical property estimation results of each chip etching area in the wafer to be tested.

[0031] See also Fig. 9 As shown, in the process of testing the multiple feature point combinations contained in each quantity state, it is necessary to continuously determine whether an electrical property estimation result that reaches the target recognition accuracy can be obtained. However, if all feature point combinations in the low quantity state are traversed and tested first, and then all feature point combinations in the high quantity state are tested, it will also affect the speed of wafer online quality inspection. Therefore, step S831 can be first executed to select feature point combinations from large to small according to the numerical value of the estimated recognition accuracy corresponding to each feature point combination as the specific feature point combination. Next, step S832 can be executed to input the local image of the specific feature point into the corresponding detection model to obtain the probability of each output item of the output layer, and calculate the recognition accuracy. Next, step S833 can be executed to determine whether the target recognition accuracy has been achieved. If so, step S834 can be executed to input the local image of the specific feature point into the corresponding detection model to obtain the output result as the electrical property estimation result.

[0032] According to the foregoing, if not, it is not possible to first traverse and test all the feature point combinations in the low number state and then test all the feature point combinations in the high number state. Therefore, step S835 can be first executed to select the feature point combination with a smaller value of the estimated recognition accuracy as the updated specific feature point combination. Next, step S836 can be executed to input the local image of the updated specific feature point into the corresponding detection model to obtain the probability of each output item of the output layer, and calculate the updated recognition accuracy. Next, step S837 can be executed to continuously obtain the updated recognition accuracy and determine whether the value continues to decrease. If not, it means that there is still a necessity to continue testing the detection model in this number state, so step S833 can be executed next to continue to obtain the updated recognition accuracy. If yes, it means that there is no need to continue testing the detection model in the number state, so step S838 can be executed to stop the number state of the feature points selected this time.

[0033] In order to provide additional explanation for the implementation process of the above-mentioned steps S831 to S838, source codes of some functional modules are provided, and comparative explanations are provided in the comments.

[0034] #include <iostream> #include <vector> #include <algorithm> #include<opencv2 / opencv.hpp> / / Example of the following namespace using namespace std; using namespace cv; / / Define the data structure of electrical property estimation results struct ElectricalEstimationResult { double estimatedResistance; double estimatedCapacitance; / / Other electrical parameters }; / / Define the data structure of feature points struct FeaturePoint { Point2f location; Mat localImage; }; / / Define the data structure of feature point combination struct FeaturePointCombination { vector <featurepoint>points; double estimatedAccuracy; / / Estimated recognition accuracy of the detection model }; / / Example detection model function, returning the probability of each output item double applyModelForProbability(const vector <featurepoint>&featurePoints) { / / Sample model application return 0.7 + (rand() % 30) / 100.0; / / Returns the recognition accuracy of the example, a random value between 0.7 and 1.0 } / / Check and return the electrical property estimation result ElectricalEstimationResult validateAndEstimate(const vector <featurepoint>& featurePoints, double targetAccuracy) { double recognitionAccuracy = applyModelForProbability(featurePoints); ElectricalEstimationResult result = {0.0, 0.0}; if (recognitionAccuracy >= targetAccuracy) { / / Example electrical property estimation results result.estimatedResistance = 1.0 + rand() % 10 / 10.0; result.estimatedCapacitance = 0.5 + rand() % 5 / 10.0; } return result; } / / Test multiple feature point combinations within each quantity state and update the specific feature point combination ElectricalEstimationResult evaluateAndUpdateCombinations(vector <featurepointcombination>& combinations, double targetAccuracy) { / / Sort by estimated recognition accuracy from large to small sort(combinations.begin(), combinations.end(), [](constFeaturePointCombination& a, const FeaturePointCombination& b) { return a.estimatedAccuracy > b.estimatedAccuracy; }); double previousAccuracy = -1.0; / / Used to record the last recognition accuracy ElectricalEstimationResult finalResult = {0.0, 0.0}; for (size_t i = 0; i < combinations.size(); ++i) { auto& combination = combinations[i]; / / Use the current feature point combination to estimate electrical properties ElectricalEstimationResult result = validateAndEstimate(combination.points, targetAccuracy); double currentAccuracy = applyModelForProbability(combination.points); / / Determine whether the target recognition accuracy is achieved if (result.estimatedResistance != 0.0 ||result.estimatedCapacitance != 0.0) { return result; / / Achieve target recognition accuracy and return electrical property estimation results } else { / / If the target recognition accuracy is not reached, update to the next feature point combination if (previousAccuracy != -1.0 && currentAccuracy <previousAccuracy) { / / If the recognition accuracy starts to decrease, stop selecting the current quantity state break; } } / / Record the current recognition accuracy previousAccuracy = currentAccuracy; } / / If the goal is not reached, return the default result return finalResult; } int main() { / / Example feature points and estimated recognition accuracy vector <featurepoint>featurePoints; for (int i = 0; i < 10; ++i) { FeaturePoint point; point.location = Point2f(i * 10, i * 10); point.localImage = Mat::zeros(10, 10, CV_8UC1); featurePoints.push_back(point); } / / Example feature point combination and its estimated recognition accuracy vector <featurepointcombination>combinations = { {featurePoints, 0.9}, {featurePoints, 0.85}, {featurePoints, 0.8} }; / / Set target recognition accuracy double targetAccuracy = 0.87; / / Evaluate the combination and get the electrical property estimation result ElectricalEstimationResult finalEstimation =evaluateAndUpdateCombinations(combinations, targetAccuracy); / / Output results cout << "Electrical Estimation Results - Resistance: " << finalEstimation.estimatedResistance << ", Capacitance: " << finalEstimation.estimatedCapacitance << endl; return 0; } The code implements a process of detailed inspection and iterative update of multiple feature point combinations within each quantitative state. The code first sorts the feature point combinations according to the estimated recognition accuracy, and then inputs these feature point combinations one by one into the detection model for recognition. If the current combination cannot achieve the target recognition accuracy, the code will select the next combination with a lower recognition accuracy and continue to iterate until the recognition accuracy no longer decreases or reaches the target recognition accuracy. Finally, the code returns the corresponding electrical property estimation result or the default result. This process ensures that the best combination is selected among the feature point combinations, thereby providing accurate electrical property estimation.

[0035] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the device, system, method and computer program product according to multiple embodiments of the present application. In this regard, each square frame in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the square frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square frames can actually be executed substantially in parallel, and they can also be executed in reverse order sometimes, depending on the functions involved.

[0036] It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented by hardware that performs the corresponding function or action, such as a circuit or ASIC (Application Specific Integrated Circuit), or can be implemented by a combination of hardware and software, such as firmware.

[0037] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0038] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art without departing from the scope of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.< / featurepointcombination> < / featurepoint> < / featurepointcombination> < / featurepoint> < / featurepoint> < / featurepoint> < / algorithm> < / vector> < / iostream> < / double> < / double> < / double> < / double> < / double> < / numeric> < / algorithm> < / vector> < / iostream>

Claims

1. A method for automatic online visual inspection of semiconductor processing quality, characterized in that: include, Obtain chip etching area within the wafer; Obtain sample images and electrical test results of chip etching areas within sample wafers; For each chip etch area, According to the image feature analysis of each sample image, multiple feature points are obtained. The feature points of different quantity states are combined to obtain a series of feature point combinations under different quantity states. For a series of feature point combinations in different numbers, the local image of each feature point in the feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain a detection model. According to the local image input of each feature point in the series of feature point combinations in different numbers of states, the output layer probability distribution of the detection model is corresponding to the filter out feature point combinations in different numbers of states; Acquire a wafer image of a chip etching area within a wafer to be inspected; The detection model corresponding to the local image input of the specific feature point combination of each chip etching area in the wafer to be detected is extracted according to the feature point combination in different quantity states to obtain the electrical property estimation result of each chip etching area in the wafer to be detected.

2. The method according to claim 1, characterized in that The step of selecting feature point combinations in different numbers of states according to the local image input of each feature point in the series of feature point combinations in different numbers of states corresponding to the output layer probability distribution of the detection model, include, Get the total number of feature points; Starting from the total number of all feature points, gradient division is performed from large to small to obtain multiple quantity states; Under each quantity state restriction, feature points of corresponding quantity states are extracted from all feature points and combined to obtain feature point combinations under different quantity states; For each quantity state, the local image of each feature point in each feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain the detection model of each feature point combination under each quantity state; The detection model is tested using sample images and electrical detection results of chip etching areas in the wafer as test data to obtain an estimated recognition accuracy rate of the detection model for each feature point combination under each quantity state; Get the target recognition accuracy; The feature point combinations under different quantity states corresponding to the detection models whose estimated recognition accuracy is less than the target recognition accuracy are eliminated, and the feature point combinations under different quantity states are screened.

3. The method according to claim 2, characterized in that The step of using the sample image and electrical detection result of the chip etching area in the wafer as test data to test the detection model to obtain the estimated recognition accuracy of the detection model for each feature point combination in each quantity state includes: For each feature point combination in each quantity state, perform the following steps respectively: Input the local images of different sample graphics under the feature point combination into the corresponding input layer of the detection model, and obtain the recognition accuracy of the detection model for different sample graphics according to the probability of each output item in the output layer of the detection model. According to the numerical characteristics of the recognition accuracy of the detection model for different sample graphics, the estimated recognition accuracy of the detection model corresponding to the feature point combination in the quantity state is obtained; The estimated recognition accuracy of the detection model for each feature point combination under each quantity state is summarized.

4. The method according to claim 3, characterized in that The step of obtaining the estimated recognition accuracy of the detection model corresponding to the feature point combination under the quantity state according to the numerical characteristics of the recognition accuracy of the detection model for different sample graphics, include, Arranging the recognition accuracy rates of the detection model for different sample graphics in order of numerical values ​​to obtain a recognition accuracy rate series; Calculate and obtain the mean of the difference between each value and the adjacent values ​​in the recognition accuracy series as the screening step length; Selecting the minimum value in the recognition accuracy series as the estimated participation value; Starting from the estimated participation value, the difference with adjacent values ​​is calculated in order from small to large along the recognition accuracy series; Determine whether the difference is less than the screening step length; If yes, then the adjacent value of the estimated participation value is changed to the estimated participation value, and the difference is continuously calculated; If not, stop and take the average of all the estimated participation values ​​as the estimated recognition accuracy of the detection model corresponding to the feature point combination under the quantity state.

5. The method according to claim 1, characterized in that The step of extracting the specific feature point combination of each chip etching area in the wafer to be inspected according to the feature point combination in different quantity states, and inputting the detection model corresponding to the local image of the specific feature point combination of each chip etching area in the wafer to be inspected to obtain the electrical property estimation result of each chip etching area in the wafer to be inspected, include, For each chip etching area in the wafer to be inspected, obtain each feature point combination in each quantity state; For each chip etching area in the wafer to be inspected, perform the following steps respectively: Select each quantity state in order from small to large along the numerical value of the quantity state of the feature point. In each quantitative state, the combination of multiple feature points included is tested to determine whether an electrical property estimation result that can achieve the target recognition accuracy can be obtained; If yes, then the electrical property estimation result of the chip etching area in the wafer to be tested is obtained; If not, stop the number state selected this time, select the number state with a larger value and iteratively test the multiple feature point combinations contained therein to determine whether an electrical property estimation result that reaches the target recognition accuracy can be obtained, until an electrical property estimation result that reaches the target recognition accuracy is obtained, or the number states of all feature points are exhausted; The electrical property estimation results of each chip etching area in the wafer to be tested are summarized.

6. The method according to claim 5, characterized in that The step of testing the combination of multiple feature points contained in each quantity state to determine whether an electrical property estimation result that achieves the target recognition accuracy can be obtained includes: According to the estimated recognition accuracy value corresponding to each feature point combination, the feature point combination is selected in descending order as the specific feature point combination. The local image of the specific feature point is input into the corresponding detection model to obtain the probability of each output item of the output layer, and the recognition accuracy is calculated. Determine whether the target recognition accuracy is achieved. If so, the output result obtained by inputting the local image of the specific feature point into the corresponding detection model is used as the electrical property estimation result.

7. The method according to claim 6, characterized in that The step of testing the combination of multiple feature points contained in each quantity state to determine whether an electrical property estimation result that achieves the target recognition accuracy can be obtained also includes: If not, then select the feature point combination with a smaller value of the estimated recognition accuracy as the updated specific feature point combination; Inputting the updated local image of the specific feature points into the corresponding detection model to obtain the probability of each output item of the output layer, and calculating the updated recognition accuracy; Continue to obtain updated recognition accuracy and determine whether the value continues to decrease; If not, then the updated recognition accuracy rate is continuously obtained; If yes, stop the number state of feature points selected this time.

8. A method for automatic online visual inspection of semiconductor processing quality, characterized in that: include, Obtaining the electrical property estimation result of each chip etching area in the wafer to be inspected in the method for automatic online visual inspection of semiconductor processing quality as described in any one of claims 1 to 7; Mark chip etch areas where electrical properties are poorly estimated.

9. A method for automatic online visual inspection of semiconductor processing quality, characterized in that: include, Obtaining the electrical property estimation result of each chip etching area in the wafer to be inspected in the method for automatic online visual inspection of semiconductor processing quality as described in any one of claims 1 to 7; The chip etching areas with poor electrical property estimation results are removed.

10. A semiconductor processing quality automatic online visual inspection system, characterized in that: An online detection unit for obtaining chip etching areas within the wafer; Obtain sample images and electrical test results of chip etching areas within sample wafers; For each chip etch area, According to the image feature analysis of each sample image, multiple feature points are obtained. The feature points of different quantity states are combined to obtain a series of feature point combinations under different quantity states. For a series of feature point combinations in different numbers, the local image of each feature point in the feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain a detection model. According to the local image input of each feature point in the series of feature point combinations in different numbers of states, the output layer probability distribution of the detection model is corresponding to the filter out feature point combinations in different numbers of states; Acquire a wafer image of a chip etching area within a wafer to be inspected; The detection model corresponding to the local image input of the specific feature point combination of each chip etching area in the wafer to be detected is extracted according to the feature point combination in different quantity states to obtain the electrical property estimation result of each chip etching area in the wafer to be detected; A defective product marking unit is used to obtain the electrical property estimation results of each chip etching area in the wafer to be inspected; Mark the chip etching areas with poor electrical property estimation results; A defective rejection unit is used to obtain the electrical property estimation results of each chip etching area in the wafer to be inspected; The chip etching areas with poor electrical property estimation results are removed.

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