Communication data encryption transmission method and device

Abstract

The invention relates to the field of communication data transmission, in particular to a communication data encryption transmission method and device, which are suitable for a frequency hopping communication data encryption and decryption transmission terminal. The method comprises the following steps: S1, carrying out clock domain transformation on data of an AXI4 bus through a register block; s2, processing the converted data by using a DES algorithm to generate a pseudo-random key ENCKEY to encrypt a frequency hopping sequence, and then performing XOR encryption processing on the converted data by using the ENCKEY; s3, clock domain transformation is carried out on the encrypted data again, and then the data are output through an AXI4 bus; and S4, comparing and detecting the transmitting power of the channel when the output encrypted data is transmitted so as to control the transmitting power of the encrypted data to be maintained at a preset target power value. According to the invention, a communication encryption and decryption function of simultaneously using encryption of a frequency hopping sequence and encryption of transmission data in a high-speed frequency hopping communication system with high reliability is realized, and the anti-interference performance of the high-speed frequency hopping communication system is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of communication data transmission, and more specifically, to a communication data encryption transmission method and device, which are applicable to a frequency hopping communication data encryption and decryption transmission terminal. Background Art

[0002] Frequency hopping communication system encryption technology is a comprehensive communication system that combines frequency hopping technology with encryption technology. It aims to improve the confidentiality, anti-interference ability and security of communication, and provide more reliable data transmission and enhanced anti-interference ability. In the frequency hopping communication system, the application of encryption technology further enhances the security of communication. Specifically, the encryption technology of the frequency hopping communication system mainly includes the following aspects: encryption of the frequency hopping sequence. The frequency hopping sequence is the core of the frequency hopping communication system. It determines the hopping law of the communication frequency. By encrypting the frequency hopping sequence, it can make it difficult for the enemy to predict and intercept the communication signal, thereby improving the confidentiality of the communication; encryption of the transmitted data. In the process of frequency hopping communication, in addition to protecting the communication frequency through frequency hopping technology, the transmitted data can also be encrypted. By using encryption algorithms and keys, the plaintext data is converted into ciphertext data. Even if the enemy intercepts the communication signal, it cannot directly obtain the original information. Comprehensive protection, frequency hopping communication system encryption technology not only focuses on a single encryption method, but also pays attention to the comprehensive use of multiple protection methods. For example, it combines frequency hopping technology, spread spectrum technology, encryption algorithms and other technical means to form a multi-level protection system to cope with various complex communication environments and threats.

[0003] In the prior art, two frequency hopping encryption implementation schemes are proposed: adding an encryption module before information modulation and transforming the frequency hopping sequence through an encryption algorithm to generate a new frequency hopping sequence, which increases the confidentiality and anti-interference performance of the communication system. However, the disadvantages of this method are that it is difficult to ensure the synchronization reliability of frequency hopping communication, reduce the real-time performance of signal transmission, and it is difficult to achieve high-speed frequency hopping communication. In frequency hopping confidential communication, it is a better design scheme to use "encryption of frequency hopping sequence" and "encryption of transmission data" to perform comprehensive encryption protection on the communication system. However, in the specific design of a large-bandwidth high-speed frequency hopping communication system, the real-time performance of data processing is required to be high. Therefore, in a large-bandwidth high-speed frequency hopping communication system, ensuring communication performance while completing complex encryption and decryption calculations has become a key technology for improving the anti-interference performance of a high-speed frequency hopping communication system.

[0004] In view of the above-mentioned defects, the present invention combines the high-speed data transmission capability of the AXI interface and the data parallel processing capability of the FPGA, designs a communication data encryption transmission method and device based on AXI4 bus data transmission, and realizes the communication encryption and decryption functions of "encryption of frequency hopping sequence" and "encryption of transmission data" in a high-reliability high-speed frequency hopping communication system. The method and device have the characteristics of high real-time encryption and decryption calculation, good anti-interference performance and easy engineering implementation, and are applied in engineering practice. Summary of the invention

[0005] The present invention aims to overcome at least one defect (shortcoming) of the above-mentioned prior art and provide a communication data encryption transmission method and device for realizing high-reliability communication encryption and decryption functions of "encryption of frequency hopping sequence" and "encryption of transmission data" in a high-speed frequency hopping communication system at the same time, thereby effectively improving the anti-interference performance of the high-speed frequency hopping communication system.

[0006] The technical solution adopted by the present invention is a communication data encryption transmission method, the method comprising the following steps:

[0007] S1: Transform the clock domain of the AXI4 bus data through the register group;

[0008] S2: Process the converted data using the DES algorithm to generate a pseudo-random key ENC_KEY to encrypt the frequency hopping sequence, and then use ENC_KEY to perform XOR encryption on the converted data;

[0009] S3: The encrypted data is re-transformed in the clock domain and then output through the AXI4 bus;

[0010] S4: performing a comparative detection of the transmission power of the channel when the output encrypted data is transmitted, so as to control the transmission power of the encrypted data to be maintained at a preset target power value.

[0011] In the present application, the system control information is transmitted separately using a serial interface and processed separately and in parallel with the data information, thereby improving the efficiency of the security device in processing data. The data exchange interface uses the AXI4 bus, which greatly improves the real-time performance of digital signal processing, increases the bandwidth of data transmission, ensures the synchronization reliability of frequency hopping communication, and realizes high-speed frequency hopping communication. At the same time, DES is used as a packet encryption method. The process of using DES to construct a frequency hopping code can be regarded as a "packet encryption" transformation of the special "information" sequence TOD, realizing the communication encryption and decryption functions of "encryption of the frequency hopping sequence" and "encryption of the transmitted data", which greatly improves the anti-interference ability of the communication system.

[0012] In addition, the transmission power comparison test is also carried out when the encrypted data is transmitted. Under the premise of ensuring the security of communication data, the channel transmission power is reasonably controlled to meet the signal strength required for data encryption transmission while avoiding unnecessary power consumption, thereby improving energy utilization efficiency. Appropriate adjustment of the channel transmission power can also make the encrypted communication signal resist external interference to a certain extent, while reducing the risk of interception and cracking by unauthorized parties; furthermore, according to the dynamic changes of channel conditions and communication environment, the parameters of data encryption transmission and channel transmission power are adjusted in real time to achieve the best communication performance and security. In wireless communication, channel conditions will change with the changes of time, place and surrounding environment. By monitoring the channel quality in real time and combining the requirements of encrypted transmission, the transmission power and parameters of the encryption algorithm, such as key length, encryption mode, etc., can be dynamically adjusted to ensure efficient and secure communication under different channel conditions. By combining with the upper-layer data encryption transmission technology to form a multi-layer security protection system, it is realized that additional security is provided for communication data encryption transmission at the physical layer.

[0013] Preferably, in step S2, the DES algorithm consists of two processes, namely an encryption process and a key process; wherein,

[0014] The encryption process includes:

[0015] S21: Perform IP substitution on 64-bit plaintext data;

[0016] S22: Divide the plaintext data after IP replacement into two parts, and then perform 16 rounds of iterative operations of standard building blocks to obtain intermediate data;

[0017] S23: Finally, the intermediate data is subjected to an inverse permutation of IP to output a 64-bit ciphertext, which is used as a frequency hopping sequence and a block encryption key;

[0018] The key process includes: inputting different shifted keys when the encryption process performs 16 rounds of iterative operations.

[0019] Among them, in the 16 rounds of iterative calculation of the standard building block in step S22, f(R i-1 ,Ki) is the core function of the standard building block, in which R i-1 The E table is expanded to 48 bits, XORed with the key K and then enters the S box. The S box obtains 32 bits through nonlinear interleaving, and finally the intermediate data is obtained through permutation through the P table;

[0020] The 16-round iterative calculation formula is:

[0021] Ri=f(R i-1 ,Ki)⊕Li-1 i=1,…,16

[0022] Li=R i-1 i=1,…,16.

[0023] In the present application, the DES algorithm is used to generate a pseudo-random code sequence of the frequency hopping sequence, namely the pseudo-random key ENC_KEY, so as to encrypt the frequency hopping sequence, enhance the security of the frequency hopping sequence, make it more concealed and difficult to crack, and by encrypting the frequency hopping sequence with DES, the frequency hopping pattern of the frequency hopping becomes more complex and unpredictable, thereby improving the anti-interference capability of the communication system, and in some communication scenarios with high requirements for concealment, it can also make the communication more difficult to be monitored and cracked, greatly improving the concealment of the communication, thereby improving the security and stability of the entire communication system.

[0024] Preferably, the XOR encryption process includes: using a pseudo-random key and plaintext data to perform XOR operation bit by bit, specifically: ciphertext = plaintext⊕ENC_KEY.

[0025] In the present application, the generated pseudo-random key is used to perform XOR encryption on the data, and each data bit is XOR-operated with the corresponding bit in the pseudo-random code sequence to form encrypted data, making the data unreadable. Unless the other party knows the corresponding pseudo-random code sequence, the original data cannot be restored, thereby achieving double encryption, which not only protects the security of the frequency hopping sequence, but also protects the confidentiality of the data content, improves the security of the entire communication system, and improves the anti-interference and anti-tampering capabilities. In addition, the use of XOR encryption operation is very efficient, and the pseudo-random code sequence can also be used for multiple encryptions, reducing the complexity of multiple key exchanges and management, and improving the efficiency of the entire communication system. At the same time, the same pseudo-random code sequence is used for frequency hopping and data encryption, which not only ensures the consistency between the two, but also simplifies the encryption mechanism in the communication system, making key distribution and management easier.

[0026] Preferably, step S2 includes: using the character-oriented SLIP protocol to transmit external command data, parsing the command type and selecting the corresponding address key number according to the serial port command. By obtaining the corresponding address key number, it can be ensured that the generated pseudo-random key is a frequency hopping sequence that conforms to the current communication address, thereby ensuring the accuracy of data processing.

[0027] Preferably, the step S1 includes:

[0028] S11: Use a dual-stage flip-flop to synchronize the signal to the target clock domain;

[0029] S12: Using a FIFO buffer to temporarily store data, and writing the data into the FIFO buffer in the external clock domain;

[0030] S13: Synchronize the handshake signals of the external clock domain and the target clock domain. After the handshake signals are established, the target clock domain reads data from the FIFO buffer and transmits it according to the AXI4 protocol.

[0031] By performing clock domain transformation, data loss or errors that may occur due to asynchrony between clock domains are solved, ensuring reliable data transmission between different clock domains and improving data security.

[0032] Preferably, the step S4 includes:

[0033] S41: using a DAC conversion device to convert the digital signal carrying the encrypted data generated in step S3 into an analog signal;

[0034] S42: Mixing the zero intermediate frequency signal of the analog signal to the frequency point to be transmitted through a mixer;

[0035] S43: After the control signal of the channel controller is enabled, the transmission frequency point and the channel control parameters are sent to the channel controller;

[0036] S44: the channel controller reads the power control parameters of the transmission frequency point from the storage unit, and waits for the switching frequency enable signal to be valid after the parameter reading is completed;

[0037] S45: When the switching frequency enable signal is valid, the channel controller performs a pre-operation;

[0038] S46: During the power adjustment time, the power detection unit is used to cyclically calculate the power detection value, and compare the real-time power detection value with the target power value after each calculation is completed;

[0039] S47: When the real-time power detection value is equal to the target power value, the power control parameter of the transmission frequency point is stored in the storage unit, and the process goes to S48;

[0040] When the real-time power detection value is not equal to the target power value, the real-time power detection value is adjusted, and then the process returns to S46;

[0041] S48: End the power adjustment control of the frequency point, and transmit the radio waves carrying the encrypted data with stable power through the radio frequency air interface after filtering by the analog filtering unit, thereby realizing the transmission of the encrypted data.

[0042] In the present application, after the data is encrypted, when the encrypted data is sent, the channel transmission power of the digital signal carrying the encrypted data is compared and detected, so that the power of the frequency point is adjusted and controlled, so that the transmission power of the encrypted data is maintained at a preset target power value, which meets the signal strength required for data encryption transmission while avoiding unnecessary power consumption, thereby improving energy utilization efficiency. Appropriate adjustment of the channel transmission power can also make the encrypted communication signal resist external interference to a certain extent, while reducing the risk of interception and cracking by unauthorized parties. In addition, by real-time monitoring of the channel quality and combining the requirements of encrypted transmission, the transmission power and encryption algorithm parameters, such as key length, encryption mode, etc., are dynamically adjusted to ensure efficient and secure communication under different channel conditions. By combining with the upper-layer data encryption transmission technology to form a multi-layer security protection system, additional security protection is provided for the encrypted transmission of communication data at the physical layer.

[0043] On the other hand, the present application also provides a communication data encryption transmission device, the device comprising:

[0044] AXI4 bus input module, used to perform clock domain transformation on input data and encrypted data;

[0045] A command processing module is used to process commands from an external control module and parse out the command type;

[0046] A pseudo-random code generation module, used to execute corresponding commands to generate a frequency hopping code sequence and an encryption key for transmission data;

[0047] A data encryption and decryption module, used to encrypt the data after clock domain transformation according to an encryption key;

[0048] The power control module is used to compare and detect the transmission power of the channel when the output encrypted data is transmitted, so as to control the transmission power of the encrypted data to maintain at a preset target power value.

[0049] This system separates control information from data information and processes them in parallel. The data exchange interface uses the AXI4 bus, which greatly improves the real-time performance of digital signal processing, increases the bandwidth of data transmission, ensures the synchronization reliability of frequency hopping communication, and realizes high-speed frequency hopping communication. At the same time, DES is used as a packet encryption method. The process of using DES to construct a frequency hopping code can be regarded as a "packet encryption" transformation of the special "information" sequence TOD, realizing the communication encryption and decryption functions of "encryption of frequency hopping sequence" and "encryption of transmission data", which greatly improves the anti-interference ability of the communication system.

[0050] In addition, when sending encrypted data, the power control module is used to compare and detect the transmission power of the signal to control the transmission power of the encrypted data to maintain it at a preset target power value, which meets the signal strength required for data encryption transmission while avoiding unnecessary power consumption, thereby improving energy utilization efficiency. Appropriate adjustment of the channel transmission power can also make the encrypted communication signal resistant to external interference to a certain extent, while reducing the risk of interception and cracking by unauthorized parties. In addition, by real-time monitoring of channel quality and combining with the requirements of encrypted transmission, the transmission power and encryption algorithm parameters, such as key length, encryption mode, etc., are dynamically adjusted to ensure efficient and secure communication under different channel conditions. By combining with the upper-layer data encryption transmission technology to form a multi-layer security protection system, additional security guarantees are provided for the encrypted transmission of communication data at the physical layer.

[0051] Preferably, the pseudo-random code generation module includes:

[0052] Interface conversion unit: used for converting serial to parallel interface or parallel to serial interface;

[0053] Pseudo-random code sequence generation unit: used to generate the encryption key of the frequency hopping code sequence and data using the DES algorithm;

[0054] The pseudo-random code sequence generating unit includes an encryption process component and a key process component.

[0055] In the encryption process component, the 64-bit plaintext data is firstly IP permuted, and then the permuted data is divided into two parts, followed by 16 rounds of iterative operations of the standard building blocks, and finally the 64-bit ciphertext is output through IP inverse permutation;

[0056] The key processing component includes inputting different shifted keys when the encryption process component performs 16 rounds of iterative operations.

[0057] In this device, the pseudo-random sequence generated by the DES algorithm is first used to encrypt the frequency hopping sequence, and then it is transmitted as the data encryption key to the data encryption and decryption module for XOR encryption operation, thereby realizing double encryption, which not only protects the security of the frequency hopping sequence, but also protects the confidentiality of the data content, improves the security of the entire communication system, and improves the anti-interference and anti-tampering capabilities.

[0058] Preferably, the clock domain transformation is completed in the AXI4 bus input module by the following units:

[0059] Signal synchronization unit: uses a double-stage trigger to synchronize the signal to the target clock domain;

[0060] FIFO buffer unit: FIFO buffer is used to temporarily store data to solve the problem of rate mismatch between clock domains;

[0061] Handshake signal synchronization unit: used to synchronize control signals to ensure data validity and flow control;

[0062] Data reading and transmission: Read data from the FIFO buffer and transmit it according to the AXI4 protocol.

[0063] In the present application, clock domain transformation is first performed on the data transmitted into the device when performing encryption operations, which effectively solves the data loss or error caused by the lack of synchronization between clock domains, ensures the reliable transmission of data between different clock domains, and improves the security of data.

[0064] Preferably, the command processing module includes:

[0065] Serial port sending and receiving unit: used for mutual conversion between 8-bit parallel data and asynchronous serial data;

[0066] Protocol processing unit: used for the interface to transmit data using the SLIP protocol and parse the command type according to the command byte, perform encrypted operations according to the command, and finally return the execution result to the external control module through the SLIP protocol.

[0067] By parsing the command bytes, the device can flexibly perform encryption or decryption operations according to external instructions, and by using the SLIP protocol to process data, it can also ensure the efficient transmission of encrypted data.

[0068] Compared with the prior art, the present invention has the following beneficial effects:

[0069] (1) In the present invention, system control information and data information are processed separately and in parallel, and the data exchange interface uses the AXI4 bus, which greatly improves the real-time performance of digital signal processing, ensures the synchronization reliability of frequency hopping communication, and realizes high-speed frequency hopping communication.

[0070] (2) The present invention uses a block encryption method to implement a communication encryption and decryption system of "encryption of frequency hopping sequences" and "encryption of transmission data", which greatly improves the anti-interference capability of the communication system.

[0071] (3) When transmitting encrypted data, the present invention satisfies the signal strength required for data encryption transmission while avoiding unnecessary power consumption, thereby improving energy utilization efficiency. Appropriate adjustment of the channel transmission power can also make the encrypted communication signal resist external interference to a certain extent, while reducing the risk of interception and cracking by unauthorized parties. By real-time monitoring of channel quality and combining the requirements of encrypted transmission, the transmission power and parameters of the encryption algorithm, such as key length, encryption mode, etc., are dynamically adjusted to ensure efficient and secure communication under different channel conditions. By combining with the upper-layer data encryption transmission technology to form a multi-layer security protection system, additional security protection is provided for the encrypted transmission of communication data at the physical layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 This is a schematic diagram of the flow of the communication data encryption transmission method provided by the present invention.

[0073] Figure 2 This is a schematic diagram of the DES encryption algorithm flow provided by the present invention.

[0074] Figure 3 This is a schematic diagram of the internal flow of the standard building block provided by the present invention.

[0075] Figure 4 This is a schematic diagram of the internal structure of the S-box provided by the present invention.

[0076] Figure 5 This is a schematic diagram of the structure of the communication data encryption transmission device provided by the present invention.

[0077] Figure 6 This is a schematic diagram of the structure of the power control module provided by the present invention.

[0078] Figure 7 A schematic diagram of a state machine for implementing the power control module control method provided by the present invention.

[0079] Figure 8 This is a flow chart of the control algorithm of the power control module provided by the present invention.

[0080] Fig. 9 This is a block diagram of the static parameter calibration system of the power control module provided by the present invention.

[0081] Fig.10 This is a flow chart of the static parameter calibration algorithm of the power control module provided by the present invention.

[0082] Fig.11 This is a schematic diagram of the external interface and internal structure of the communication data encryption transmission device provided by the present invention.

[0083] Fig.12 A schematic diagram of state transition of the command processing module provided by the present invention.

[0084] Fig.13 A schematic diagram of state transition of the pseudo-random code generation module provided by the present invention.

[0085] Fig.14 This is a schematic diagram of the state transition of the data encryption and decryption module provided by the present invention. DETAILED DESCRIPTION

[0086] The drawings of the present invention are only for illustrative purposes and should not be construed as limiting the present invention. In order to better illustrate the following embodiments, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; it is understandable to those skilled in the art that some well-known structures and their descriptions in the drawings may be omitted.

[0087] Example 1

[0088] like Figure 1 As shown, this embodiment provides a communication data encryption transmission method, the method comprising the following steps:

[0089] Step S1: Perform clock domain transformation on the data of the AXI4 bus through a register group;

[0090] Step S2: Processing the converted data using the DES algorithm to generate a pseudo-random key ENC_KEY to encrypt the frequency hopping sequence, and then using ENC_KEY to perform XOR encryption on the converted data;

[0091] Step S3: The encrypted data is re-transformed in the clock domain and then output through the AXI4 bus:

[0092] Step S4: performing a comparative test on the transmission power of the channel when the output encrypted data is transmitted, so as to control the transmission power of the encrypted data to be maintained at a preset target power value.

[0093] In the present application, the system control information and the data information are processed separately and in parallel, and the data exchange interface uses the AXI4 bus, which greatly improves the real-time performance of digital signal processing, increases the bandwidth of data transmission, ensures the synchronization reliability of frequency hopping communication, and realizes high-speed frequency hopping communication. At the same time, DES is used as a packet encryption method. The process of using DES to construct a frequency hopping code can be regarded as a "packet encryption" transformation of the special "information" sequence TOD, realizing the communication encryption and decryption functions of "encryption of frequency hopping sequence" and "encryption of transmission data", which greatly improves the anti-interference ability of the communication system.

[0094] In addition, the transmission power comparison test is also carried out when the encrypted data is transmitted. Under the premise of ensuring the security of communication data, the channel transmission power is reasonably controlled to meet the signal strength required for data encryption transmission while avoiding unnecessary power consumption, thereby improving energy utilization efficiency. Appropriate adjustment of the channel transmission power can also make the encrypted communication signal resist external interference to a certain extent, while reducing the risk of interception and cracking by unauthorized parties; furthermore, according to the dynamic changes of channel conditions and communication environment, the parameters of data encryption transmission and channel transmission power are adjusted in real time to achieve the best communication performance and security. In wireless communication, channel conditions will change with the changes of time, place and surrounding environment. By monitoring the channel quality in real time and combining the requirements of encrypted transmission, the transmission power and parameters of the encryption algorithm, such as key length, encryption mode, etc., can be dynamically adjusted to ensure efficient and secure communication under different channel conditions. By combining with the upper-layer data encryption transmission technology to form a multi-layer security protection system, it is realized that additional security is provided for communication data encryption transmission at the physical layer.

[0095] Preferably, the step S1 includes:

[0096] Step S11: Use a double-stage trigger to synchronize the signal to the target clock domain; in this embodiment, the received external data is inconsistent with the clock domain for data encryption, because the input data signal needs to be synchronized to the target clock domain first, thereby solving the signal synchronization problem and avoiding the uncertain state caused by the clock mismatch between clock domains.

[0097] Step S12: using a FIFO buffer to temporarily store data, and writing the data into the FIFO buffer in the external clock domain;

[0098] Due to the timing differences between clock domains, direct data transmission may result in data loss or errors. Therefore, a FIFO buffer is usually used to temporarily store data. The data is first temporarily stored in the FIFO, and the target clock domain can read the data at its own rate to avoid loss, thus solving the problem of data transmission rate mismatch between the external clock domain and the target clock domain.

[0099] Step S13: Synchronize the handshake signals of the external clock domain and the target clock domain. After the handshake signal is established, when writing to the clock domain, the external data obtained in the external clock domain is written into the FIFO; when reading the clock domain, the target clock domain reads data from the FIFO buffer and transmits it according to the AXI4 protocol, thereby ensuring that the reading operation of the target clock domain can be synchronized with the writing operation.

[0100] Therefore, by performing clock domain transformation, possible data loss or error caused by asynchrony between clock domains is solved, reliable data transmission between different clock domains is ensured, and data security is improved.

[0101] Preferably, if Figure 2 As shown, Figure 2 The DES encryption algorithm flow chart provided in this embodiment, in step S2, the DES algorithm consists of two processes, namely, the encryption process and the key process; wherein,

[0102] The encryption process includes the following steps:

[0103] Step S21: IP permutation is performed on the 64-bit plaintext data to disrupt the bit order of the plaintext. The 64-bit input data of the plaintext is rearranged according to the rules of the IP table to obtain a 64-bit "initial data block";

[0104] Step S22: Divide the plaintext data after IP substitution into two 32-bit parts, the left half L0 and the right half R0, and then perform 16 rounds of iterative operations of the standard building blocks to obtain intermediate data;

[0105] More preferably, if Figure 3-Figure 4 As shown, in the 16 rounds of iterative operations of the standard building block in step S22, each round will process the current left half and right half, using the core function f(R i-1 ,Ki), in this function R i-1 The E table is expanded to 48 bits, XORed with the key K and then enters the S box. The S box obtains 32 bits through nonlinear interleaving, and finally the intermediate data is obtained through permutation through the P table;

[0106] The 16-round iterative calculation formula is as follows:

[0107] Ri=f(R i-1 ,Ki)⊕Li-1 i=1,…,16

[0108] Li=R i-1 i=1,…,16.

[0109] By performing nonlinear transformations (such as S-box substitution) and linear transformations (such as permutation) in each round, the encryption strength is enhanced, thereby improving the security of communications.

[0110] Step S23: Finally, the intermediate data is subjected to an inverse permutation of IP to output a 64-bit ciphertext, which is used as a frequency hopping sequence and a block encryption key;

[0111] The above steps are as follows:

[0112] First, the right half Ri-1 It is expanded from 32 bits to 48 bits through an extended permutation operation, and then the expanded right half is XORed with the subkey of the current round. The subkey is generated by the key process, and a different subkey is used in each round; then S-Box substitution is performed, and the XOR result is passed to 8 S-Boxes (substitution boxes) for substitution. Each S-Box maps 6 bits of input to 4 bits of output, and the entire operation converts 48 bits of input to 32 bits of output; the substituted 32-bit data is permuted through the P-Box, which specifies how to rearrange these bits to further increase confusion; the permuted right half is XORed with the left half to obtain a new left half. The right half is passed directly to the next round; after each round of iteration, the values ​​of the left and right halves are exchanged and enter the next round of encryption process. Finally, after 16 rounds of iterations, the left and right halves are merged and inversely permuted (IP-1), and a predefined inverse permutation table is used to restore the 64-bit data to the encrypted ciphertext format, thereby generating a pseudo-random key ENC_KEY.

[0113] Preferably, if Figure 2 As shown, the key process includes: deriving 16 subkeys from the initial key, each subkey is used for one round of encryption, and different shifted keys are input when the encryption process performs 16 rounds of iterative operations. The specific steps are as follows:

[0114] ① Initial key input: The input key is a 64-bit binary number, which contains 8 check bits (each 8 bits is a check bit). Therefore, the effective key actually used for encryption is 56 bits (excluding 8 check bits).

[0115] ② Initial permutation: First, perform an initial permutation (PC-1) on the input 56-bit key, dividing it into two 32-bit parts: C0 (left half): the first 32 bits; D0 (right half): the last 32 bits. The purpose of PC-1 permutation is to scramble the key and remove the check bit.

[0116] ③ Circular left shift: Next, C0 and D0 will be circularly shifted left respectively: in the first and second rounds, C0 and D0 are circularly shifted left by 1 bit respectively; from the third to the eighth round (and the ninth to the sixteenth round), C0 and D0 are circularly shifted left by 2 bits respectively. After each round of left shift operation, the number of bits of C and D will be updated, and after the circular left shift, the C and D parts will be combined into a 56-bit intermediate result.

[0117] ④PC-2 permutation: After the circular left shift, the C and D parts are permuted by PC-2 to generate a 48-bit subkey. PC-2 is a fixed permutation rule that selects 48 bits from 56 bits and removes the extra 8 bits. This 48-bit subkey will be used in each iteration of the DES encryption algorithm.

[0118] ⑤16 subkeys: Repeat the above steps 16 times, generating a different 48-bit subkey (K1, K2, ..., K16) each time. Each subkey is used in the corresponding round of DES encryption.

[0119] Therefore, in the present application, the DES algorithm is used to generate a pseudo-random code sequence of the frequency hopping sequence, namely the pseudo-random key ENC_KEY, so as to encrypt the frequency hopping sequence, enhance the security of the frequency hopping sequence, make it more concealed and difficult to crack, and by encrypting the frequency hopping sequence with DES, the frequency hopping pattern of the frequency hopping becomes more complex and unpredictable, thereby improving the anti-interference ability of the communication system, and in some communication scenarios with high requirements for concealment, it can also make the communication more difficult to be monitored and cracked, greatly improving the concealment of the communication, thereby improving the security and stability of the entire communication system.

[0120] Preferably, the XOR encryption process includes: using a pseudo-random key and plaintext data to perform XOR operation bit by bit, specifically: ciphertext = plaintext⊕ENC_KEY.

[0121] In the present application, the generated pseudo-random key is used to perform XOR encryption on the data, and each data bit is XOR-operated with the corresponding bit in the pseudo-random code sequence to form encrypted data, making the data unreadable. Unless the other party knows the corresponding pseudo-random code sequence, the original data cannot be restored, thereby achieving double encryption, which not only protects the security of the frequency hopping sequence, but also protects the confidentiality of the data content, improves the security of the entire communication system, and improves the anti-interference and anti-tampering capabilities. In addition, the use of XOR encryption operation is very efficient, and the pseudo-random code sequence can also be used for multiple encryptions, reducing the complexity of multiple key exchanges and management, and improving the efficiency of the entire communication system. At the same time, the same pseudo-random code sequence is used for frequency hopping and data encryption, which not only ensures the consistency between the two, but also simplifies the encryption mechanism in the communication system, making key distribution and management easier.

[0122] Further preferably, the step S2 includes: using the character-oriented SLIP protocol to transmit external command data, parsing the command type and selecting the corresponding address key number according to the serial port command. By obtaining the corresponding address key number, it can be ensured that the generated pseudo-random key is a frequency hopping sequence that conforms to the current communication address, thereby ensuring the accuracy of data processing.

[0123] Preferably, the step S4 includes:

[0124] S41: using a DAC conversion device to convert the digital signal carrying the encrypted data generated in step S3 into an analog signal;

[0125] S42: Mixing the zero intermediate frequency signal of the analog signal to the frequency point to be transmitted through a mixer;

[0126] S43: After the control signal of the channel controller is enabled, the transmission frequency point and the channel control parameters are sent to the channel controller;

[0127] S44: the channel controller reads the power control parameters of the transmission frequency point from the storage unit, and waits for the switching frequency enable signal to be valid after the parameter reading is completed;

[0128] S45: When the switching frequency enable signal is valid, the channel controller performs a pre-operation;

[0129] S46: During the power adjustment time, the power detection unit is used to cyclically calculate the power detection value, and compare the real-time power detection value with the target power value after each calculation is completed;

[0130] S47: When the real-time power detection value is equal to the target power value, the power control parameter of the transmission frequency point is stored in the storage unit, and the process goes to S48;

[0131] When the real-time power detection value is not equal to the target power value, the real-time power detection value is adjusted, and then the process returns to S46;

[0132] S48: End the power adjustment control of the frequency point, and transmit the radio waves carrying the encrypted data with stable power through the radio frequency air interface after filtering by the analog filtering unit, thereby realizing the transmission of the encrypted data.

[0133] In the present application, after the data is encrypted, when the encrypted data is sent, the channel transmission power of the digital signal carrying the encrypted data is compared and detected, so that the power of the frequency point is adjusted and controlled, so that the transmission power of the encrypted data is maintained at a preset target power value, which meets the signal strength required for data encryption transmission while avoiding unnecessary power consumption, thereby improving energy utilization efficiency. Appropriate adjustment of the channel transmission power can also make the encrypted communication signal resist external interference to a certain extent, while reducing the risk of interception and cracking by unauthorized parties. In addition, by real-time monitoring of the channel quality and combining the requirements of encrypted transmission, the transmission power and encryption algorithm parameters, such as key length, encryption mode, etc., are dynamically adjusted to ensure efficient and secure communication under different channel conditions. By combining with the upper-layer data encryption transmission technology to form a multi-layer security protection system, additional security protection is provided for the encrypted transmission of communication data at the physical layer.

[0134] Since in the working process of the communication system, the statically stored control parameters are often the parameter values ​​under normal working conditions, and when the working environment changes, each time the static control parameters are called, real-time feedback control is required to achieve the power flatness requirement, which will further shorten the control time of the ALC control system and result in a slow response speed. Therefore, the storage unit in step S44 includes a static storage unit and a dynamic storage unit; specifically,

[0135] Each frequency point of the device is calibrated with power static parameters before leaving the factory, and the power calibration value is stored in the static storage unit; the power control parameters after startup are stored in the dynamic storage unit.

[0136] Therefore, in this embodiment, by introducing dynamic storage combined with static storage, after each power-on, the control value for achieving the flatness requirement of the power in the feedback control of each transmission frequency point is dynamically stored. When switching to the frequency point again, the dynamic parameter value is called, and the flatness requirement of the power transmission can be quickly achieved, and the power output can be controlled more accurately and quickly to adapt to different working environments, and the maintenance process of the staff is simplified.

[0137] Since the static power parameters stored in the static storage unit are calibrated at the factory and used as the reference value, the storage content of the static storage unit will not be lost after the device is powered off, ensuring the persistence and accuracy of the reference parameter value, reducing the workload and complexity of the staff, and enhancing the stability of the communication system. The power parameters of the dynamic storage unit are real-time power control parameters. Since the rate of the frequency hopping signal is very fast, the parameters are dynamically generated according to the current working environment, so there is no need to continuously store the dynamic storage unit. The dynamic storage content will lose data after power failure, which can more flexibly adapt to changes in the working environment and improve the robustness of the system.

[0138] When the transmitting frequency point is the transmitting frequency point sent down for the first time after the power is turned on, the channel controller reads the power control parameter of the transmitting frequency point from the static storage unit;

[0139] When the transmitting frequency point is not the transmitting frequency point sent for the first time after the power is turned on, the channel controller reads the power control parameter of the transmitting frequency point from the dynamic storage unit.

[0140] In order to achieve accurate control of the channel transmitting device to ensure that the signal can be accurately transmitted to the predetermined evaluation point, it is necessary to perform pre-operation on the channel transmitting device after powering on. The pre-operation in step S45 includes:

[0141] The channel controller controls the mixer to mix the transmission frequency to the corresponding frequency point to meet the communication system's precise requirements for signal frequency. At the same time, it controls the DAC converter to output the initial control voltage of the variable gain amplifier to achieve flexible adjustment of the signal gain to adapt to different working environments and transmission distance requirements, and writes the initial data attenuation parameters to the digitally controlled attenuator to accurately control the attenuation degree of the signal, thereby optimizing the transmission effect and reception quality of the signal.

[0142] like Figure 5-7 As shown, after power-on, the digital signal carrying encrypted data to be transmitted is first input into the DAC conversion unit, and the digital signal is converted into an analog signal. The analog signal is mixed with a zero intermediate frequency signal to the frequency point to be transmitted through a mixer, and then the analog signal transmission power is adjusted to the target value through a variable gain amplifier unit and a digitally controlled attenuation unit. Finally, the signal is processed by the analog filter unit and a radio wave carrying encrypted data with stable power is transmitted through the RF air interface.

[0143] Before the transmission frequency switching is enabled, the control parameters are sent to the controller of the signal device. The controller calculates the mixing frequency control data according to the control parameters, reads the initial variable gain amplifier unit, the control parameters of the digital control attenuation unit and the target power value of the power detection unit of the transmission frequency, controls the mixer switching frequency at the effective moment of the transmission power switching enable, outputs the control parameters of the variable gain amplifier unit and the digital control attenuation unit, and then detects the signal transmission power value through the power detection unit within the specified channel adjustment time, controls the variable gain amplifier unit and the digital control attenuation unit in real time, and realizes stable channel power control.

[0144] like Figure 8As shown, when the power is on, it is judged in real time whether the channel transmission control signal is enabled. If it is enabled, the channel control device enters the transmission control state and receives the transmission frequency point and channel control parameters sent by the system. Then it is judged whether the frequency point is the first transmission frequency point sent after the power is turned on. If it is the first transmission frequency point sent, the channel controller reads the power control parameters of the frequency point from the static storage unit. If it is not the first transmission frequency point sent, the channel controller reads the power control parameters of the frequency point from the dynamic storage unit. After the parameter reading is completed, wait for the switching frequency enable signal to be valid. When the switching frequency enable signal is valid, the mixer is controlled to mix the transmission frequency to the corresponding frequency point, the DAC converter is controlled to output the initial control voltage of the variable gain amplifier, and the initial data attenuation parameter is written to the digital control attenuator. Then, the power detection value of the power detection unit is cyclically calculated within the power adjustment time specified by the communication system algorithm. After each calculation is completed, the real-time detection value is compared with the target power value stored in the storage unit. When the power detection value is less than the target value, it is determined whether the digital controlled attenuator has an attenuation value. If the attenuation value exists, the digital controlled attenuator is controlled to reduce the attenuation value according to the difference between the detection value and the target power value, and then the power detection value of the power detection unit is calculated. If the attenuation value does not exist, the variable gain amplifier is controlled to increase the signal amplification factor and then the power detection value of the power detection unit is calculated. When the power detection value is greater than the target value, it is determined whether the digital controlled attenuator reaches the maximum attenuation value. If the maximum attenuation value is not reached, the digital controlled attenuator is controlled to increase the attenuation value according to the difference between the detection value and the target power value, and then the power detection value of the power detection unit is calculated. If the maximum attenuation value is reached, the variable gain amplifier is controlled to reduce the signal amplification factor and then the power detection value of the power detection unit is calculated. When the power detection value is equal to the target value, the power control parameter of the frequency point is stored in the dynamic storage unit, and the power adjustment control of the frequency point is ended.

[0145] Preferably, in a communication or signal processing system, in order to realize automatic power regulation of a signal and ensure that the output power of the signal is stably maintained near a preset target power value, the comparison of the real-time power detection value with the target power value in step S46 further includes:

[0146] S46.1: When the real-time power detection value is greater than the target value, the state of the digital controlled attenuator is determined:

[0147] S46.11: When the digital controlled attenuator has not reached the maximum attenuation value, the digital controlled attenuator is controlled to increase the attenuation value according to the difference between the real-time power detection value and the target power value;

[0148] S46.12: When the digital control attenuation value reaches the maximum attenuation value, the variable gain amplifier is controlled to reduce the signal amplification factor;

[0149] S46.2: When the real-time power detection value is less than the target value, the state of the digital controlled attenuator is determined:

[0150] S46.21: When there is an attenuation value in the digital controlled attenuator, the digital controlled attenuator is controlled to reduce the attenuation value according to the difference between the real-time power detection value and the target value;

[0151] S46.22: When there is no attenuation value in the digital controlled attenuator, control the variable gain amplifier to increase the signal amplification factor;

[0152] S46.3: Return the detection value of the calculated power detection unit.

[0153] By monitoring the signal power in real time and dynamically adjusting the parameters of the digitally controlled attenuator and variable gain amplifier based on the difference between the real-time power detection value and the target power value, the channel transmit power control can automatically compensate for power changes caused by environmental changes, equipment aging, or signal source fluctuations, thereby improving the stability and reliability of power control.

[0154] like Fig. 9 As shown in the figure, the calibration system automatically performs frequency sweep power calibration on the device before it leaves the factory. The entire calibration system consists of a power frequency sweep calibration device and a channel transmission control device. The power frequency sweep calibration device includes a frequency sweep control human-machine interface, a power detection device, and a signal generator. During the system power calibration process, the frequency sweep control human-machine interface exchanges control information with the power detection device and the signal generator through the Ethernet interface, and the power frequency sweep calibration device exchanges information with the channel transmission control device through the serial port protocol.

[0155] Preferably, the frequency sweep power calibration algorithm includes:

[0156] S51: The frequency sweep control human-machine interface sends the output signal power value to the signal generator;

[0157] S52: The serial port control protocol sends the calibration frequency point and the initial value of the digital controlled attenuator to the channel transmission control device;

[0158] S53: reading the power value of the output signal of the radio frequency output port of the power detection device through the interface;

[0159] S54: adjusting the attenuation value of the digital controlled attenuator and the amplification value of the variable gain amplifier according to the real-time power value;

[0160] S55: controlling the output power within the range required by the target power flatness through closed-loop control;

[0161] S56: When the power output reaches the target value, the attenuation value, the control value of the variable gain and the analog voltage value of the power detection unit obtained by the frequency point calibration are stored in the static storage unit;

[0162] S57: Repeat the calibration of the next frequency point until the calibration and storage of the transmission frequency points of the entire frequency band are completed.

[0163] The static parameters are automatically calibrated through the swept frequency power calibration algorithm to reduce manual intervention and improve the efficiency and accuracy of calibration. Automatic parameter calibration can also provide calibration data recording and tracing functions to facilitate subsequent analysis and troubleshooting.

[0164] The frequency sweep control human-machine interface exchanges control information with the power detection device and the signal generator via an Ethernet interface.

[0165] like Fig. 9 The figure shows the block diagram of the static parameter calibration system of the channel transmission power control device. The calibration system automatically performs frequency sweep power calibration on the channel transmission device before it leaves the factory. The entire calibration system consists of a power frequency sweep calibration device and a channel transmission control device. The power frequency sweep calibration device includes a frequency sweep control human-machine interface, a power detection device, and a signal generator. During the system power calibration process, the frequency sweep control human-machine interface exchanges control information with the power detection device and the signal generator through the Ethernet interface, and the power frequency sweep calibration device exchanges information with the channel transmission control device through the serial port protocol.

[0166] like Fig.10 As shown, the system starts working after power-on. The sweep frequency control human-machine interface first sends the output signal power value to the signal generator to control the signal generator to output a signal with stable power; then, the calibration frequency point and the initial value of the digital attenuator are sent to the channel transmission control device through the serial port control protocol, and the channel module mixer is controlled to work at this frequency point. The power value of the output signal of the RF output port is detected by the power detection device through the Ethernet interface, and the attenuation value of the digital attenuator and the amplification value of the variable gain are adjusted according to the real-time power value. The output power is controlled within the range required by the target power flatness through closed-loop control. When the power output reaches the target value, the sweep frequency control human-machine interface stores the attenuation value of the frequency point calibration, the control value of the variable gain, and the analog voltage value detected by the power detection unit in the static storage unit (EEPROM memory, which is not lost when the power is off) of the channel transmission control device through the serial port protocol, and then calibrates the next frequency point, and repeats continuously until the calibration and storage of the transmission frequency points of the entire frequency band are completed. The algorithm design is realized by software. In the entire calibration process of the transmission power of the channel transmission control device, only the initial parameters need to be set, and the entire process will be automatically calibrated and stored.

[0167] Example 2

[0168] like Figure 5-6 As shown, based on the method provided in Example 1, this embodiment provides a communication data encryption transmission device, the device comprising:

[0169] AXI4 bus input module, used to perform clock domain transformation on input data and encrypted data;

[0170] A command processing module is used to process commands from an external control module and parse out the command type;

[0171] A pseudo-random code generation module, used to execute corresponding commands to generate a frequency hopping code sequence and an encryption key for transmission data;

[0172] A data encryption and decryption module, used to encrypt the data after clock domain transformation according to an encryption key;

[0173] The power control module is used to compare and detect the transmission power of the channel when the output encrypted data is transmitted, so as to control the transmission power of the encrypted data to maintain at a preset target power value.

[0174] In this device, the data of the AXI4 bus is first transformed in the clock domain through the register group in the AXI4 bus input module, and then the converted data is sent to the pseudo-random code generation module and the data encryption and decryption module for processing. The data after data calculation is finally output from the AXI4 bus through clock domain conversion.

[0175] This system separates control information from data information and processes them in parallel. The data exchange interface uses the AXI4 bus, which greatly improves the real-time performance of digital signal processing, increases the bandwidth of data transmission, ensures the synchronization reliability of frequency hopping communication, and realizes high-speed frequency hopping communication. At the same time, DES is used as a packet encryption method. The process of using DES to construct a frequency hopping code can be regarded as a "packet encryption" transformation of the special "information" sequence TOD, realizing the communication encryption and decryption functions of "encryption of frequency hopping sequence" and "encryption of transmission data", which greatly improves the anti-interference ability of the communication system.

[0176] In addition, when sending encrypted data, the power control module is used to compare and detect the transmission power of the signal to control the transmission power of the encrypted data to maintain it at a preset target power value, which meets the signal strength required for data encryption transmission while avoiding unnecessary power consumption, thereby improving energy utilization efficiency. Appropriate adjustment of the channel transmission power can also make the encrypted communication signal resistant to external interference to a certain extent, while reducing the risk of interception and cracking by unauthorized parties. In addition, by real-time monitoring of channel quality and combining with the requirements of encrypted transmission, the transmission power and encryption algorithm parameters, such as key length, encryption mode, etc., are dynamically adjusted to ensure efficient and secure communication under different channel conditions. By combining with the upper-layer data encryption transmission technology to form a multi-layer security protection system, additional security guarantees are provided for the encrypted transmission of communication data at the physical layer.

[0177] Preferably, the clock domain transformation is completed in the AXI4 bus input module by the following units:

[0178] Signal synchronization unit: uses a double-stage trigger to synchronize the signal to the target clock domain;

[0179] FIFO buffer unit: FIFO buffer is used to temporarily store data to solve the problem of rate mismatch between clock domains;

[0180] Handshake signal synchronization unit: used to synchronize control signals to ensure data validity and flow control;

[0181] Data reading and transmission: Read data from the FIFO buffer and transmit it according to the AXI4 protocol.

[0182] In the present application, clock domain transformation is first performed on the data transmitted into the device when performing encryption operations, which effectively solves the data loss or error caused by the lack of synchronization between clock domains, ensures the reliable transmission of data between different clock domains, and improves the security of data.

[0183] Preferably, if Fig.11 As shown, the command processing module includes:

[0184] Serial port sending and receiving unit: used for mutual conversion between 8-bit parallel data and asynchronous serial data;

[0185] Protocol processing unit: used for the interface to transmit data using the SLIP protocol and parse the command type according to the command byte, perform encrypted operations according to the command, and finally return the execution result to the external control module through the SLIP protocol.

[0186] In this embodiment, the serial port sending and receiving unit mainly realizes the collection of asynchronous serial communication data, converts the serial data into 8-bit parallel data and sends it to the protocol processing unit; the protocol processing unit is mainly responsible for identifying commands and performing corresponding processing, and its interface is an asynchronous serial port, which uses the character-oriented SLIP protocol to transmit data, and checks and modifies the parameters of the encryption device through the parsed multiple commands, thereby completing the control of the encryption device by the external control module, including self-test, key query, key area selection, communication device ID number query and other functions. Finally, the serial port sending and receiving unit converts the data to be returned from 8-bit parallel data into asynchronous serial data, and the state conversion of the command processing module is as follows: Fig.12 As shown, in the present device, the data processing state machine conversion in each module unit has a high-efficiency data processing capability, meeting the processing requirements of real-time data in high-speed frequency hopping communication.

[0187] Thus, by parsing the command bytes, the device can flexibly perform encryption or decryption operations according to external instructions, and by using the SLIP protocol to process data, it can also ensure efficient transmission of encrypted data.

[0188] Preferably, if Figure 11-12 As shown, in the pseudo-random code generation module, the address key number that meets the encryption device is selected according to the command parsed by the command processing module, and then the pseudo-random code generation module generates a frequency hopping sequence that meets the communication address according to the address key number, and the TOD input end of the pseudo-random code generation module communicates using the AXI4 bus protocol according to the specification, and the 8-bit frequency hopping code generated by the pseudo-random code generation module is also sent back to the external control module by the AXI4 bus. At the same time, the same hopping pseudo-random sequence code, that is, the pseudo-random key ENC_KEY, is transmitted to the data encryption and decryption module as a data encryption key to encrypt the data.

[0189] Specifically, the state transition of the pseudo-random code generation module is as follows: Fig.13 As shown, the pseudo-random code generation module includes:

[0190] Interface conversion unit: used for converting serial to parallel interface or parallel to serial interface;

[0191] Pseudo-random code sequence generation unit: used to generate the encryption key of the frequency hopping code sequence and data using the DES algorithm;

[0192] The pseudo-random code sequence generation unit is the core of the pseudo-random code generation module. The performance of the frequency hopping code generated by the pseudo-random code directly affects the anti-interception, anti-interference, synchronization and other performances of the frequency hopping radio station and the networking capability of the system.

[0193] Specifically, the pseudo-random code sequence generating unit includes an encryption process component and a key process component, such as Figure 2-4 As shown,

[0194] In the encryption process component, the 64-bit plaintext data is firstly IP permuted, and then the permuted data is divided into two parts, followed by 16 rounds of iterative operations of the standard building blocks, and finally the 64-bit ciphertext is output through IP inverse permutation;

[0195] In the 16-round iteration of the standard building block, f(R i-1 ,Ki) is the core function of the standard building block, in which R i-1 The E table is expanded to 48 bits, XORed with the key K and then enters the S box. The S box obtains 32 bits through nonlinear interleaving, and finally the intermediate data is obtained through permutation through the P table;

[0196] The 16-round iterative calculation formula is:

[0197] Ri=f(R i-1 ,Ki)⊕Li-1 i=1,…,16

[0198] Li=R i-1 i=1,…,16

[0199] Specifically:

[0200] First, the right half R i-1 It is expanded from 32 bits to 48 bits through an extended permutation operation, and then the expanded right half is XORed with the subkey of the current round. The subkey is generated by a key process, and a different subkey is used in each round; then S-Box substitution is performed, and the XOR result is passed to 8 S-Boxes (substitution boxes) for substitution. Each S-Box maps 6 bits of input to 4 bits of output, and the entire operation converts 48 bits of input into 32 bits of output; the substituted 32-bit data is permuted through a P-Box, which specifies how to rearrange these bits to further increase confusion; the permuted right half is XORed with the left half to obtain a new left half. The right half is passed directly to the next round; after each round of iteration, the values ​​of the left and right halves are exchanged and enter the next round of encryption. Finally, after 16 rounds of iterations, the left and right halves are merged and the inverse initial permutation (IP -1 ), restore the 64-bit data to the encrypted ciphertext format through a predefined inverse permutation table, thereby generating a pseudo-random key ENC_KEY.

[0201] The key processing component includes inputting different shifted keys when the encryption process component performs 16 rounds of iterative operations. Specifically:

[0202] ① Initial key input: The input key is a 64-bit binary number, which contains 8 check bits (each 8 bits is a check bit). Therefore, the effective key actually used for encryption is 56 bits (excluding 8 check bits).

[0203] ② Initial permutation: First, perform an initial permutation (PC-1) on the input 56-bit key, dividing it into two 32-bit parts: C0 (left half): the first 32 bits; D0 (right half): the last 32 bits. The purpose of PC-1 permutation is to scramble the key and remove the check bit.

[0204] ③ Circular left shift: Next, C0 and D0 will be circularly shifted left respectively: in the first and second rounds, C0 and D0 are circularly shifted left by 1 bit respectively; from the third to the eighth round (and the ninth to the sixteenth round), C0 and D0 are circularly shifted left by 2 bits respectively. After each round of left shift operation, the number of bits of C and D will be updated, and after the circular left shift, the C and D parts will be combined into a 56-bit intermediate result.

[0205] ④PC-2 permutation: After the circular left shift, the C and D parts are permuted by PC-2 to generate a 48-bit subkey. PC-2 is a fixed permutation rule that selects 48 bits from 56 bits and removes the extra 8 bits. This 48-bit subkey will be used in each iteration of the DES encryption algorithm.

[0206] ⑤16 subkeys: Repeat the above steps 16 times, generating a different 48-bit subkey (K1, K2, ..., K16) each time. Each subkey is used in the corresponding round of DES encryption.

[0207] Therefore, in this device, the pseudo-random sequence generated by the DES algorithm is first used to encrypt the frequency hopping sequence, and then it is transmitted as the data encryption key to the data encryption and decryption module for XOR encryption operation, thereby realizing double encryption, which not only protects the security of the frequency hopping sequence, but also protects the confidentiality of the data content, improves the security of the entire communication system, and improves the anti-interference and anti-tampering capabilities.

[0208] Preferably, the encryption and decryption operations of baseband data are mainly completed in the data encryption and decryption module, because the probability and random characteristics of the ciphertext generated by the DES algorithm meet the requirements of the pseudo-random code sequence, so it can be used as a frequency hopping sequence and data encryption key. In addition, the baseband data received from the external control module also adopts the AXI4 bus protocol communication, and the output encrypted data is the result of the encryption operation of the baseband data and ENC_KEY. Its state transition diagram is as follows: Fig.14 Specifically, the encryption key and the plaintext data are subjected to bit-by-bit XOR operation, and the formula is: ciphertext = plaintext ⊕ ENC_KEY.

[0209] Preferably, for the power control module, the method steps implemented therein are consistent with the relevant technical contents of step S4 in embodiment 1, and are not described again here.

[0210] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solution of the present invention, and are not intended to limit the specific implementation methods of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the claims of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A communication data encryption transmission method, characterized in that: The method comprises the following steps: S1: Transform the clock domain of the AXI4 bus data through the register group; S2: Process the converted data using the DES algorithm to generate a pseudo-random key ENC_KEY to encrypt the frequency hopping sequence, and then use ENC_KEY to perform XOR encryption on the converted data; S3: The encrypted data is re-transformed in the clock domain and then output through the AXI4 bus; S4: performing a comparative detection of the transmission power of the channel when the output encrypted data is transmitted, so as to control the transmission power of the encrypted data to be maintained at a preset target power value.

2. A communication data encryption transmission method according to claim 1, characterized in that: In step S2, the DES algorithm consists of two processes, namely, an encryption process and a key process; wherein, The encryption process includes: S21: Perform IP substitution on 64-bit plaintext data; S22: Divide the plaintext data after IP replacement into two parts, and then perform 16 rounds of iterative operations of standard building blocks to obtain intermediate data; S23: Finally, the intermediate data is subjected to an inverse permutation of IP to output a 64-bit ciphertext, which is used as a frequency hopping sequence and a block encryption key; The key process includes: inputting different shifted keys when the encryption process performs 16 rounds of iterative operations; Among them, in the 16 rounds of iterative calculation of the standard building block in step S22, f(R i-1 ,Ki) is the core function of the standard building block, in which R i-1 Expanded to 48 bits through the E table, XORed with the key K and entered into the S box, the S box obtains 32 data through nonlinear interleaving, and finally obtains the intermediate data through the P table permutation; The 16-round iterative calculation formula is: Li=R i-1 i=1,…,16.

3. A communication data encryption transmission method according to claim 2, characterized in that: The XOR encryption process includes: using a pseudo-random key and plain text data to perform XOR operations on a bit-by-bit basis, specifically: ciphertext = plain text ⊕ ENC_KEY.

4. A communication data encryption transmission method according to claim 3, characterized in that: The step S2 includes: using the character-oriented SLIP protocol to transmit external command data, parsing the command type and selecting the corresponding address key number according to the serial port command.

5. A communication data encryption transmission method according to any one of claims 1 to 4, characterized in that: The step S1 includes: S11: Use a dual-stage flip-flop to synchronize the signal to the target clock domain; S12: Using a FIFO buffer to temporarily store data, and writing the data into the FIFO buffer in the external clock domain; S13: Synchronize the handshake signals of the external clock domain and the target clock domain. After the handshake signals are established, the target clock domain reads data from the FIFO buffer and transmits it according to the AXI4 protocol.

6. A communication data encryption transmission method according to claim 1, characterized in that: The step S4 comprises: S41: using a DAC conversion device to convert the digital signal carrying the encrypted data generated in step S3 into an analog signal; S42: Mixing the zero intermediate frequency signal of the analog signal to the frequency point to be transmitted through a mixer; S43: After the control signal of the channel controller is enabled, the transmission frequency point and the channel control parameters are sent to the channel controller; S44: the channel controller reads the power control parameters of the transmission frequency point from the storage unit, and waits for the switching frequency enable signal to be valid after the parameter reading is completed; S45: When the switching frequency enable signal is valid, the channel controller performs a pre-operation; S46: During the power adjustment time, the power detection unit is used to cyclically calculate the power detection value, and compare the real-time power detection value with the target power value after each calculation is completed; S47: When the real-time power detection value is equal to the target power value, the power control parameter of the transmission frequency point is stored in the storage unit, and the process goes to S48; When the real-time power detection value is not equal to the target power value, the real-time power detection value is adjusted, and then the process returns to S46; S48: End the power adjustment control of the frequency point, and transmit the radio wave carrying the encrypted data with stable power through the radio frequency air interface after filtering by the analog filtering unit.

7. An encrypted transmission device according to any one of claims 1 to 6, characterized in that: The device comprises: AXI4 bus input module, used to perform clock domain transformation on input data and encrypted data; A command processing module is used to process commands from an external control module and parse out the command type; A pseudo-random code generation module, used to execute corresponding commands to generate a frequency hopping code sequence and an encryption key for transmission data; A data encryption and decryption module, used to encrypt the data after clock domain transformation according to an encryption key; The power control module is used to compare and detect the transmission power of the channel when the output encrypted data is transmitted, so as to control the transmission power of the encrypted data to maintain at a preset target power value.

8. A communication data encryption transmission device according to claim 7, characterized in that: The pseudo-random code generation module includes: Interface conversion unit: used for converting serial to parallel interface or parallel to serial interface; Pseudo-random code sequence generation unit: used to generate the encryption key of the frequency hopping code sequence and data using the DES algorithm; The pseudo-random code sequence generating unit includes an encryption process component and a key process component. In the encryption process component, the 64-bit plaintext data is firstly IP permuted, and then the permuted data is divided into two parts, followed by 16 rounds of iterative operations of the standard building blocks, and finally the 64-bit ciphertext is output through IP inverse permutation; The key processing component includes inputting different shifted keys when the encryption process component performs 16 rounds of iterative operations.

9. A communication data encryption transmission device according to claim 7, characterized in that: The clock domain transformation is accomplished in the AXI4 bus input module by the following units: Signal synchronization unit: uses a double-stage trigger to synchronize the signal to the target clock domain; FIFO buffer unit: FIFO buffer is used to temporarily store data to solve the problem of rate mismatch between clock domains; Handshake signal synchronization unit: used to synchronize control signals to ensure data validity and flow control; Data reading and transmission: Read data from the FIFO buffer and transmit it according to the AXI4 protocol.

10. A communication data encryption transmission device according to claim 7, characterized in that: The command processing module includes: Serial port sending and receiving unit: used for mutual conversion between 8-bit parallel data and asynchronous serial data; Protocol processing unit: used for the interface to transmit data using the SLIP protocol and parse the command type according to the command byte, perform encrypted operations according to the command, and finally return the execution result to the external control module through the SLIP protocol.

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