Thin film transistor panel and test method and preparation method thereof

Abstract

The invention discloses a thin film transistor panel and a test method and a preparation method thereof, and the thin film transistor panel comprises a substrate which is provided with a first surface; the first surface comprises at least one pixel region and comprises a plurality of first transistors arranged in an array; in the first transistors in the same row, grids of the first transistors are connected with the same scanning line, and sources are connected with different signal lines; the at least one transistor group is arranged on the first surface, the transistor group comprises a plurality of transistor subgroups which are arranged in sequence, and each transistor subgroup comprises a second transistor; in the same transistor group, the grid electrode of the second transistor is connected with the same first wire, the source electrode is connected with the same second wire, and the drain electrode is connected with the same third wire; the first wire, the second wire and the third wire are respectively connected with a bonding pad; the second transistor and the first transistor are arranged on the same layer; at least one side edge of the pixel area is parallel and opposite to a transistor group, and the arrangement direction of transistor subgroups in the transistor group is parallel to the length direction of the parallel and opposite side edges.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a thin film transistor panel and a testing method and a preparation method thereof. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] The display panel is the main component of an electronic device to realize the display function. The display panel needs to control the pixels to display images through the pixel circuit constructed by thin film transistors. In order to ensure the reliability of the display panel, it is necessary to perform performance tests on the transistors in the thin film transistor panel used in the preparation of the display panel. Summary of the invention

[0004] In view of the above problems, the present application provides a thin film transistor panel and a testing method and a manufacturing method thereof, so as to achieve the purpose of testing the performance of the thin film transistors in the panel. The specific scheme is as follows:

[0005] A first aspect of the present application provides a thin film transistor panel, comprising:

[0006] A substrate having a first surface; the first surface includes at least one pixel area, the pixel area includes a plurality of first transistors arranged in an array; in the same row of first transistors, the gates of the first transistors are connected to the same scan line, and the sources of the first transistors are connected to different signal lines;

[0007] At least one transistor group is arranged on the first surface, the transistor group includes a plurality of transistor sub-groups arranged in sequence, and the transistor sub-group includes a second transistor; in the same transistor group, the gate of the second transistor is connected to the same first routing line, the source of the second transistor is connected to the same second routing line, and the drain of the second transistor is connected to the same third routing line; the first routing line, the second routing line and the third routing line are respectively connected to at least one pad; the second transistor is arranged on the same layer as the first transistor;

[0008] Wherein, at least one side of the pixel region is parallel to and opposite to a transistor group, and an arrangement direction of transistor subgroups in the transistor group is parallel to a length direction of the parallel to and opposite to the side.

[0009] It can be known from the above description that in the thin film transistor panel provided by the present application, there is a pixel area and a transistor group on the first surface of the substrate. The pixel area is provided with a plurality of first transistors arranged in an array, and the first transistor can be used to control the pixel for image display. The transistor group includes a plurality of transistor subgroups, and the transistor subgroup includes a second transistor on the same layer as the first transistor. Based on the first routing, the second routing and the third routing, it is possible to achieve parallel connection between a plurality of second transistors in the transistor group, and based on the pads connected to the first routing, the second routing and the third routing, it is possible to access the test signal and obtain the sampling signal for the transistor group. Since the second transistor is arranged on the same layer as the first transistor, the performance of the first transistor in the pixel area can be characterized based on the sampling signal obtained by the second transistor, and the performance test of the first transistor is achieved to determine whether there is a faulty first transistor in the pixel area.

[0010] A second aspect of the present application provides a method for testing the above-mentioned thin film transistor panel, comprising:

[0011] For the same transistor group, a pad connected to the first wiring is used to connect the first test signal to the gate of the second transistor, a second pad connected to the second wiring is used to provide a second test signal to the source of the second transistor, and a sampling signal is obtained through a pad connected to the third signal;

[0012] It is determined whether there is a faulty first transistor in the pixel region based on the sampling signal.

[0013] From the above description, it can be seen that the test method provided in the present application can access the test signal and obtain the sampling signal for the transistor group through the wiring connected to the second transistor, and can characterize the performance of the first transistor in the pixel area based on the sampling signal obtained by the second transistor, thereby realizing the performance test of the first transistor to determine whether there is a faulty first transistor in the pixel area.

[0014] A third aspect of the present application provides a method for preparing a thin film transistor panel, comprising:

[0015] Providing a substrate having a first surface; the first surface includes at least one pixel area;

[0016] A first transistor and a transistor group are formed on a substrate; the pixel area includes a plurality of first transistors arranged in an array; in the same row of first transistors, the gates of the first transistors are connected to the same scan line, and the sources of the first transistors are connected to different signal lines; the transistor group includes a plurality of transistor sub-groups arranged in sequence, and the transistor sub-groups include second transistors; in the same transistor group, the gates of the second transistors are connected to the same first routing line, the sources of the second transistors are connected to the same second routing line, and the drains of the second transistors are connected to the same third routing line; the first routing line, the second routing line, and the third routing line are respectively connected to at least one pad; the second transistors are arranged on the same layer as the first transistors;

[0017] Wherein, at least one side of the pixel region is parallel to and opposite to a transistor group, and an arrangement direction of transistor subgroups in the transistor group is parallel to a length direction of the parallel to and opposite to the side.

[0018] From the above description, it can be known that the preparation method provided in the present application can prepare the above-mentioned thin film transistor panel, and can test the performance of the first transistor through the second transistor in the thin film transistor panel to determine whether there is a faulty first transistor in the pixel area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0020] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0021] Figure 1 is a top view of a thin film transistor panel;

[0022] Figure 2 for Figure 1 A schematic structural diagram of an electrical testing unit in a thin film transistor panel is shown;

[0023] Figure 3 A top view of a thin film transistor panel provided in an embodiment of the present application;

[0024] Figure 4a is an equivalent circuit diagram of a transistor group opposite to the first side;

[0025] Figure 4b is an equivalent circuit diagram of a row of pixels in a pixel area and the first transistors connected thereto;

[0026] Figure 5 A layout of a transistor group opposite to the first side;

[0027] Figure 6 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0028] Figure 7 A layout of a transistor group opposite to the second side;

[0029] Figure 8 is an equivalent circuit diagram of a transistor group opposite to the second side;

[0030] Fig. 9 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0031] Fig.10 A layout of a transistor group parallel to and opposite to a pixel region in a column direction provided in an embodiment of the present application;

[0032] Fig.11 A layout of a transistor group parallel to and opposite to a pixel region in a row direction provided in an embodiment of the present application;

[0033] Fig.12 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0034] Fig.13 A top view of a local area of ​​a thin film transistor panel provided in an embodiment of the present application;

[0035] Fig.14 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0036] Fig.15 A cross-sectional view of a transistor group at a wiring position provided in an embodiment of the present application;

[0037] Fig.16 An equivalent circuit diagram of a transistor group provided in an embodiment of the present application;

[0038] Fig.17 An equivalent circuit diagram of another transistor group provided in an embodiment of the present application;

[0039] Fig.18 An equivalent circuit diagram of another transistor group provided in an embodiment of the present application;

[0040] Fig.19 An equivalent circuit diagram of a thin film transistor panel provided in an embodiment of the present application;

[0041] Fig. 20 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0042] Fig.21 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0043] Fig. 22A top view of another thin film transistor panel provided in an embodiment of the present application;

[0044] Fig.23 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0045] Fig.24 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0046] Fig.25 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0047] Fig.26 A top view of another thin film transistor panel provided in an embodiment of the present application;

[0048] Fig. 27 A flow chart of a testing method provided in an embodiment of the present application;

[0049] Fig.28 A flow chart of a method for determining a first transistor having a fault based on a binary test method provided in an embodiment of the present application;

[0050] Fig.29 A schematic flow chart of a method for preparing a thin film transistor panel provided in an embodiment of the present application.

[0051] Reference numerals:

[0052] 10-pixel; 11-substrate; 111-first surface; 12-pixel area; 120-target side; 121-first side; 122-second side; 123-third side; 124-fourth side; 13-electrical test unit; 14-pad; 141-first pad; 142-second pad; 143-third pad; 15-transistor group; 151-transistor subgroup; 161-first routing; 162-second routing; 163-third routing; 17-cutting position; 18-set Fixed position; 19-control switch; 20-scan line; 21-shift register circuit; 22-panel area; 221-first area; 222-second area; 23-spacer area; 24-fourth routing line; 241-hollow area; 25-signal line; Q1-first transistor; Q2-second transistor; G-gate; S-source; D-drain; X-row direction; Y-column direction; W1-preset distance; W2-spacing; F1-first arrangement direction; F2-second arrangement direction; BB-border area. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0054] As described in the background art, in order to ensure the reliability of the display panel, it is necessary to perform performance tests on the transistors in the thin film transistor panel used to prepare the display panel. Figure 1 As shown, an electrical test unit (Test Element Group, TEG for short) may be provided in the thin film transistor panel to perform a performance test on the transistors in the thin film transistor panel.

[0055] refer to Figure 1 and Figure 2 , Figure 1 is a top view of a thin film transistor panel, Figure 2 for Figure 1 The schematic diagram of the structure of an electrical test unit in the thin film transistor panel shown in the figure, the thin film transistor panel shown in the figure includes:

[0056] The substrate 11 has a first surface 111, the first surface 111 includes a plurality of pixel areas 12, the pixel area 12 includes a plurality of first transistors arranged in an array, and the first transistors are used to connect pixels to control the pixels to display images; Figure 1 The first transistor is not shown;

[0057] A plurality of electrical testing units 13 are disposed on the first surface 111; one electrical testing unit 13 is disposed at each of the four corners of each pixel region 12, and adjacent corners of two adjacent pixel regions 12 may share the same electrical testing unit 13. The electrical testing unit 13 includes a second transistor Q2, and a gate G, a source S, and a drain D of the second transistor Q2 are respectively connected to a pad 14.

[0058] The second transistor Q2 of the electrical testing unit 13 is disposed in the same layer as the first transistor in the pixel area 12 .

[0059] exist Figure 1 and Figure 2 In the method shown, since some points are evenly selected in the thin film transistor panel to layout the second transistor Q2 respectively, the number of test points and the corresponding second transistor Q2 is small, and the test range is small. Only the performance of the first transistor in a smaller area directly opposite the pixel area 12 can be tested, and the performance of the first transistor in the pixel area 12 cannot be accurately reflected.

[0060] In view of this, an embodiment of the present application provides a thin film transistor panel, including:

[0061] A substrate having a first surface; the first surface includes at least one pixel area, the pixel area includes a plurality of first transistors arranged in an array; in the same row of first transistors, the gates of the first transistors are connected to the same scan line, and the sources of the first transistors are connected to different signal lines;

[0062] At least one transistor group is arranged on the first surface, the transistor group includes a plurality of transistor sub-groups arranged in sequence, and the transistor sub-group includes a second transistor; in the same transistor group, the gate of the second transistor is connected to the same first routing line, the source of the second transistor is connected to the same second routing line, and the drain of the second transistor is connected to the same third routing line; the first routing line, the second routing line and the third routing line are respectively connected to at least one pad; the second transistor is arranged on the same layer as the first transistor;

[0063] Wherein, at least one side of the pixel region is parallel to and opposite to a transistor group, and an arrangement direction of transistor subgroups in the transistor group is parallel to a length direction of the parallel to and opposite to the side.

[0064] In the thin film transistor panel provided in the present application, there is a pixel area and a transistor group on the first surface of the substrate. The pixel area is provided with a plurality of first transistors arranged in an array, and the first transistor can be used to control the pixel for image display. The transistor group includes a plurality of transistor subgroups, and the transistor subgroup includes a second transistor on the same layer as the first transistor. Based on the first routing, the second routing and the third routing, it is possible to achieve parallel connection between a plurality of second transistors in the transistor group, and based on the pads connected to the first routing, the second routing and the third routing, it is possible to access the test signal and obtain the sampling signal for the transistor group. Since the second transistor is arranged on the same layer as the first transistor, the performance of the first transistor in the pixel area can be characterized based on the sampling signal obtained by the second transistor, and the performance test of the first transistor is achieved to determine whether there is a faulty first transistor in the pixel area.

[0065] In addition, since the transistor group can perform a performance test on the first transistor in the pixel area through a plurality of transistor sub-groups arranged in sequence, in the arrangement direction of the transistor sub-groups, the second transistors in each transistor sub-group can be respectively used to perform a performance test on the first transistor in the opposite area in the pixel area. Therefore, the transistor group can test the performance of the first transistor in the opposite area of ​​the pixel area through a plurality of long-range parallel second crystals in the arrangement direction of the transistor sub-group. The transistor group can test the performance of the first transistor in a larger range in the pixel area, thereby increasing the test range and improving the accuracy of the performance test of the first transistor.

[0066] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0067] refer to Figure 3-Figure 5 , Figure 3 A top view of a thin film transistor panel provided in an embodiment of the present application, Figure 4a is an equivalent circuit diagram of the transistor group opposite to the first side, Figure 4b is an equivalent circuit diagram of a row of pixels in a pixel area and the first transistors connected thereto, Figure 5 is a layout of the transistor group opposite to the first side, Figure 3-Figure 5 In the illustrated embodiment, an LCD display panel is used for illustration. The pixel array in the display panel includes a plurality of pixels 10 arranged in an array. Each pixel 10 is connected to a first transistor Q1 .

[0068] like Figure 3-Figure 5 As shown, the thin film transistor panel includes:

[0069] A substrate 11, the substrate 11 has a first surface 111; the first surface 111 includes at least one pixel area 12, the pixel area 12 includes a plurality of first transistors Q1 arranged in an array; in the same row of first transistors Q1, the gates of the first transistors Q1 are connected to the same scan line 20, and the sources of the first transistors Q1 are connected to different signal lines 25; wherein the scan line 20 is used to provide a scan signal to the first transistors Q1 to control the conduction state of the first transistors Q1;

[0070] At least one transistor group 15 is disposed on the first surface 111, the transistor group 15 includes a plurality of transistor sub-groups 151 arranged in sequence, and the transistor sub-group 151 includes a second transistor Q2; in the same transistor group 15, the gate G of the second transistor Q2 is connected to the same first wiring 161, the source S of the second transistor Q2 is connected to the same second wiring 162, and the drain of the second transistor Q2 is connected to the same third wiring 163; the first wiring 161, the second wiring 162 and the third wiring 163 are respectively connected to at least one pad 14; the second transistor Q2 is disposed on the same layer as the first transistor Q1;

[0071] At least one side of the pixel region 12 is parallel to a transistor group 15, and the arrangement direction of the transistor subgroups 151 in the transistor group 15 is parallel to the length direction of the parallel and opposite side. The second transistor Q2 can have the same structure as the first transistor Q1, and the sampling signal obtained by the second transistor Q2 can represent the performance of the first transistor Q1, so as to perform a performance test on the first transistor Q1 through the second transistor Q2.

[0072] According to the function of the first transistor Q1 in the pixel circuit, the signal line 25 can be used to provide any one of a data signal, a reset signal and a power supply voltage to the first transistor Q1, and the embodiment of the present application does not limit the signal connected to the signal line 25. If the display panel is an LCD panel, the signal line 25 can be a data line for providing a data signal, and the drain of the first transistor Q1 can be connected to the pixel electrode of the pixel 10.

[0073] In the thin film transistor panel, the second transistor Q2 is arranged in the same layer as the first transistor Q1. The first transistor and the second transistor Q2 can be prepared through a process flow, and the two have the same structure, so the performance of the first transistor Q1 can be characterized by the second transistor Q2.

[0074] It should be noted that Figure 4b Taking the LCD panel as an example, a simple schematic diagram of the equivalent circuit of the pixel 10 and the first transistor Q1 connected thereto is provided. For other types of display panels, such as an LED panel or an OLED panel, the structure and layout of the first transistor Q1 in the pixel area 12 and the signal line 25 and the scanning line 20 connected thereto can refer to the scheme of the pixel circuit in the existing display panel, and the embodiments of the present application are not limited to this.

[0075] In the embodiment of the present application, the thin film transistor panel can be used to prepare an array substrate of a display panel. The display panel can be an LCD panel, an OLED panel, or an LED panel, etc. The display panel includes a pixel array. The array substrate includes a pixel circuit connected to the pixels in the pixel array. The pixel circuit may include one or more pixel transistors. Different first transistors in the pixel area 12 are respectively located in different pixel circuits.

[0076] Optionally, the first transistor Q1 and the second transistor Q2 are both IGZO (Indium Gallium Zinc Oxide) transistors, and the performance of the IGZO transistor in the pixel area 12 can be tested by the second transistor Q2 in the transistor group 15. At this time, the pixel circuit includes at least one IGZO transistor, and one IGZO transistor in each pixel circuit forms a plurality of array-arranged first transistors Q1 in the pixel area 12.

[0077] In other embodiments, the first transistor Q1 and the second transistor Q2 may both be LTPS (Low Temperature Poly-Silicon) transistors, and the performance of the LTPS transistor in the pixel area 12 can be tested by the second transistor Q2 in the transistor group 15. In this case, the pixel circuit includes at least one LTPS transistor, and one LTPS transistor in each pixel circuit forms a plurality of first transistors Q1 arranged in an array in the pixel area 12.

[0078] In one embodiment, the first transistor Q1 and the second transistor Q2 may also be amorphous silicon (a-Si) transistors, and the performance of the a-Si transistors in the pixel area 12 can be tested by the second transistor Q2 in the transistor group 15. In this case, the pixel circuit includes at least one a-Si transistor, and one a-Si transistor in each pixel circuit forms a plurality of array-arranged first transistors Q1 in the pixel area 12.

[0079] In the embodiment of the present application, a transistor group 15 may be disposed opposite to one side of the pixel region 12, or a transistor group 15 may be disposed on each of multiple sides. In the same transistor group 15, the first wiring 161, the second wiring 162, and the third wiring 163 may be disposed in parallel, and the extension direction of the three wirings is parallel to the arrangement direction of the transistor subgroups 151 in the transistor group 15.

[0080] The row direction X and the column direction Y of the array where the first transistor Q1 is located are both parallel to the first surface 111. Figure 3 In the illustrated manner, a transistor group 15 is provided relative to the first side 121 in the pixel region 12 as an example for illustration, the length direction of the first side 121 may be parallel to the row direction X, and in the corresponding transistor group 15, each transistor sub-group 151 is sequentially arranged along the row direction X, and the first wiring 161, the second wiring 162 and the third wiring 163 all extend along the row direction X. In other manners, the length direction of the first side 121 may also be parallel to the column direction Y.

[0081] In the thin film transistor panel provided in the embodiment of the present application, a pixel area 12 and a transistor group 15 are provided on the first surface 111 of the substrate 11. The pixel area 12 is provided with a plurality of first transistors Q1 arranged in an array, and the first transistor Q1 can be used to control the pixel for image display. The transistor group 15 includes a plurality of transistor subgroups, and the transistor subgroup 151 includes a second transistor Q2 on the same layer as the first transistor Q1. Based on the first wiring 161, the second wiring 162 and the third wiring 163, it is possible to achieve parallel connection between the plurality of second transistors Q2 in the transistor group 15, and based on the pad 14 connected to the first wiring 161, the second wiring 162 and the third wiring 163, it is possible to access the test signal and obtain the sampling signal for the transistor group 15. Since the second transistor Q2 is arranged on the same layer as the first transistor Q1, the performance of the first transistor in the pixel area can be characterized based on the sampling signal obtained by the second transistor Q2, and the performance test of the first transistor Q1 is achieved to determine whether there is a faulty first transistor Q1 in the pixel area.

[0082] Furthermore, since the transistor group 15 can perform a performance test on the first transistor Q1 in the pixel area through a plurality of transistor sub-groups 151 arranged in sequence, in the arrangement direction of the transistor sub-groups 151, the second transistors Q2 in each transistor sub-group 151 can be respectively used to perform a performance test on the first transistor Q1 in the opposite area in the pixel area 12. Therefore, the transistor group 15 can test the performance of the first transistor Q1 in the opposite area in the pixel area 12 through a plurality of long-range parallel second transistors Q2 in the arrangement direction of the transistor sub-groups 151. The transistor group 15 can test the performance of the first transistor Q1 in a larger range in the pixel area 12, thereby increasing the test range and improving the accuracy of the performance test of the first transistor Q1.

[0083] refer to Figure 6-Figure 8 , Figure 6 A top view of another thin film transistor panel provided in an embodiment of the present application, Figure 7 is a layout of the transistor group opposite to the second side, Figure 8 is an equivalent circuit diagram of the transistor group opposite to the second side, based on the above implementation mode, Figure 6-Figure 8 The thin film transistor panel shown includes: the pixel area 12 includes a first side 121 and a second side 122, the first side 121 is parallel to the row direction X of the array, and the second side 122 is parallel to the column direction Y of the array; wherein, a transistor group 15 is disposed parallel to and opposite to the first side 121 and the second side 122. The layout and equivalent circuit diagram of the transistor group 15 opposite to the first side 121 can refer to the above embodiment. Figure 4a and Figure 5 shown.

[0084] exist Figure 6-Figure 8 In the illustrated manner, a transistor group 15 is respectively arranged opposite to the first side 121 and the second side 122 intersecting the pixel area 12. Based on the transistor group 15 opposite to the first side 121, along the row direction X, each transistor subgroup 151 can respectively perform a performance test on the first transistor Q1 in the opposite region of the pixel area 12. Based on the transistor group 15 opposite to the second side 122, along the column direction Y, each transistor subgroup 151 can respectively perform a performance test on the first transistor Q1 in the opposite region of the pixel area 12. Based on the transistor groups 15 respectively arranged opposite to the first side 121 and the second side 122, the position of the first transistor Q1 with a fault in the pixel area 12 can be accurately located.

[0085] For example, the pixel region 12 has m rows and n columns of first transistors Q1, and m and n are both positive integers greater than 1. When a faulty transistor is detected in the i-th column by the transistor group 15 opposite to the first side 121, and a faulty transistor is detected in the j-th row by the transistor group 15 opposite to the second side 122, the test results of the two transistor groups 15 intersect horizontally and vertically, and it can be determined that the first transistor Q1 in the i-th column and j-th row in the pixel region 12 is faulty. i is a positive integer not greater than n, and j is a positive integer not greater than m.

[0086] refer to Fig. 9 , Fig. 9 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above implementation, Fig. 9 In the thin film transistor panel shown, the pixel area 12 further includes a third side 123 opposite to the first side 121 and a fourth side 124 opposite to the second side 122 ; a transistor group 15 is disposed parallel to at least one of the third side 123 and the fourth side 124 .

[0087] Fig. 9 In the figure, the third side 123 and the fourth side 124 are each provided with a transistor group 15 arranged opposite to each other. In other embodiments, a transistor group 15 may be arranged parallel to and opposite to one of the third side 123 and the fourth side 124.

[0088] The transistor group 15 disposed opposite to the third side 123 and the transistor group 15 disposed opposite to the first side 121 may have the same layout and the same equivalent circuit diagram. If the third side 123 has a transistor group 15 disposed opposite to each other, the equivalent circuit diagram and layout of the transistor group 15 may refer to the above-mentioned embodiment. Figure 4a and Figure 5 shown.

[0089] The transistor group 15 disposed opposite to the fourth side 124 and the transistor group 15 disposed opposite to the second side 122 may have the same layout and the same equivalent circuit diagram. If the fourth side has a transistor group 15 disposed opposite to each other, the equivalent circuit diagram and layout of the transistor group 15 may refer to the above embodiment. Figure 7 and Figure 8 shown.

[0090] For the transistor group 15 opposite to the first side 121, since the third side 123 is away from the transistor group 15, the test accuracy of the transistor group 15 on the first transistor Q1 close to the third side 123 is low. When a transistor group 15 is respectively arranged opposite to the first side 121 and the third side 123, the performance of the first transistor Q1 close to the third side 123 can be accurately tested by the transistor group 15 opposite to the third side 123, and the test accuracy of the transistor group 15 on the first transistors Q1 at the two opposite sides of the pixel area 12 in the column direction Y can be improved.

[0091] For the transistor group 15 opposite to the second side 122, since the fourth side 124 is away from the transistor group 15, the test accuracy of the transistor group 15 near the fourth side 124 is low. When a transistor group 15 is respectively arranged opposite to the second side 122 and the fourth side 124, the performance of the first transistor Q1 near the fourth side 124 can be accurately tested by the transistor group 15 opposite to the fourth side 124, and the test accuracy of the transistor group 15 on the first transistor Q1 at the two opposite edges of the pixel area 12 in the row direction X can be improved.

[0092] As described above, the pixel area 12 can be set to have m rows and n columns of first transistors Q1, where m and n are both positive integers greater than 1; if a transistor group 15 is parallel to the side of the pixel area 12 extending along the row direction X, the transistor group 15 has n transistor sub-groups, and each transistor sub-group 151 corresponds to a column of first transistors Q1; if a transistor group 15 is parallel to the side of the pixel area 12 extending along the column direction Y, the transistor group 15 has m transistor sub-groups, and each transistor sub-group 151 corresponds to a row of first transistors Q1.

[0093] For a side edge extending along the row direction X (such as the first side edge 121 or the third side edge 123), the transistor group 15 corresponding to the side edge has n transistor sub-groups, so that each column of the first transistors Q1 in the pixel area 12 can be arranged opposite to a transistor sub-group 151 in the transistor group 15 in the column direction Y, and each column of the first transistors Q1 can be performance tested based on the corresponding transistor sub-group 151 in the transistor group 15, which can improve the accuracy of the performance test of the first transistors Q1.

[0094] For a side edge extending along the column direction Y (such as the second side edge 122 and the fourth side edge 124), the transistor group 15 corresponding to the side edge has m transistor sub-groups, so that the first transistors Q1 of each row in the pixel area 12 are respectively arranged relative to a transistor sub-group 151 in the transistor group 15 in the row direction X. The performance of the first transistors Q1 of each row can be tested based on the relative transistor sub-group 151 in the transistor group 15, which can improve the accuracy of the performance test of the first transistors Q1.

[0095] Alternatively, if Fig.10 or Fig.11 As shown, in the same transistor group 15, the first routing line 161, the second routing line 162 and the third routing line 163 all extend along the arrangement direction of the transistor sub-group 151; the pads 14 connected to the first routing line 161, the second routing line 162 and the third routing line 163 are the first pad 141, the second pad 142 and the third pad 143 in sequence; in the arrangement direction, multiple positions of the first routing line 161 are respectively connected to the first pad 141, multiple different positions of the second routing line 162 are respectively connected to the second pad 142, and multiple different positions of the third routing line 163 are respectively connected to the third pad 143. In this way, each routing line is set to be connected to multiple pads 14, and the same routing line can be used to input test signals at different positions, or output sampling signals at different positions, so as to facilitate the performance test of the first transistor Q1 in the pixel area 12 through the second transistor Q2.

[0096] In the embodiment of the present application, the pad 14 may be located in the same metal layer as the connected routing wire, and the pad 14 and the connected routing wire are an integrated structure. For example, the first pad 141 and the first routing wire 161 are located in the same metal layer, the second pad 142 and the second routing wire 162 are located in the same metal layer, and the third pad 143 and the third routing wire 163 are located in the same metal layer. Optionally, the first routing wire 161, the second routing wire 162 and the third routing wire 163 may be located in the same metal layer, and in other embodiments, at least two of the first routing wire 161, the second routing wire 162 and the third routing wire 163 are in different layers.

[0097] refer to Fig.10 , Fig.10A layout of a transistor group parallel to and opposite to a pixel region in a column direction is provided in an embodiment of the present application. In this method, for the same transistor group 15, the arrangement direction of the transistor subgroup 151 is parallel to the row direction X, and the transistor group 15 can be parallel to and opposite to the first side 121 or the third side 123. In the transistor group 15, the first routing line 161, the second routing line 162 and the third routing line 163 all extend along the row direction X. In the row direction X, multiple positions of the first routing line 161 are respectively connected to the first pad 141, multiple different positions of the second routing line 162 are respectively connected to the second pad 142, and multiple different positions of the third routing line 163 are respectively connected to the third pad 143.

[0098] refer to Fig.11 , Fig.11 A layout of a transistor group parallel to and opposite to a pixel region in a row direction is provided in an embodiment of the present application. In this method, for the same transistor group 15, the arrangement direction of the transistor subgroup 151 is parallel to the column direction Y, and the transistor group 15 can be parallel to and opposite to the second side 122 or the fourth side 124. In the transistor group 15, the first routing line 161, the second routing line 162 and the third routing line 163 are all along the column direction Y. In the column direction Y, multiple positions of the first routing line 161 are respectively connected to the first pad 141, multiple different positions of the second routing line 162 are respectively connected to the second pad 142, and multiple different positions of the third routing line 163 are respectively connected to the third pad 143.

[0099] Optionally, for the same transistor group 15, in the arrangement direction, the transistor subgroups 151 are respectively connected to a first pad 141, a second pad 142 and a third pad 143. In this embodiment, Fig. 9 or Fig.10 As shown, for the same transistor group 15, the first wiring 161 may be set to have a first pad 141 corresponding to the transistor sub-group 151, the second wiring 162 may be set to have a second pad 142 corresponding to the transistor sub-group 151, and the third wiring 163 may be set to have a third pad 143 corresponding to the transistor sub-group 151. At this time, when the first transistor Q1 is tested through the transistor group 15, if the sampling signal indicates that there is a faulty first transistor Q1 in the pixel area 12, the binary test method may be performed multiple times, and the transistor group 15 may be split for multiple times to determine the position of the faulty first transistor Q1 in the pixel area 12.

[0100] refer to Fig.12 , Fig.12 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above implementation, Fig.12In the thin film transistor panel shown, for the same transistor group 15, adjacent transistor subgroups 151 have a preset distance W1 in the arrangement direction. In the same transistor group 15, the arrangement direction of the transistor subgroup 151 is set to the first arrangement direction F1. Based on the preset distance W1, the transistor group 15 can be cut off at a position corresponding to the preset distance W1. Optionally, the preset distance W1 is greater than 3μm. If the transistor group 15 is parallel to the side of the pixel area 12 parallel to the row direction X, the arrangement direction F1 is parallel to the row direction X, and if the transistor group 15 is parallel to the side of the pixel area 12 parallel to the column direction Y, the arrangement direction F1 is parallel to the column direction Y.

[0101] For the same transistor group 15, when it is determined through the transistor group 15 that there is a first transistor Q1 with a fault in the pixel area 12, the transistor group 15 can be cut into two parts at a preset distance W1 between any two adjacent transistor sub-groups 151, and then the two parts of the transistor group 15 are tested separately to determine the position of the first transistor Q1 with a fault in the pixel area 12. The first wiring 161, the second wiring 162 and the third wiring 163 can all be cut at the preset distance W1 to achieve the purpose of cutting the transistor group 15.

[0102] In the embodiment of the present application, the preset distance W1 is set to be greater than 3 μm, so that sufficient cutting space can be reserved between two adjacent transistor sub-groups 151 to facilitate segmentation of the transistor group 15 based on the preset distance W1.

[0103] At present, laser cutting is widely used in the field of display panel preparation. In the embodiment of the present application, when the performance of the first transistor Q1 is tested, the transistor group can be divided by laser. Specifically, at the preset distance W1 between two adjacent transistor sub-groups 151, the first wiring 161, the second wiring 162 and the third wiring 163 are all cut off by laser. By setting the preset distance W1 to be greater than 3μm, sufficient laser cutting space can be reserved between two adjacent transistor sub-groups 151 so that the laser can divide the transistor group 15 based on the preset distance W1.

[0104] refer to Fig.13 , Fig.13 A top view of a local area of ​​a thin film transistor panel provided in an embodiment of the present application, based on the above implementation, Fig.13In the illustrated method, the preset distance W1 is equal to the spacing W2 between two adjacent first transistors Q1 in the arrangement direction. In this method, along the arrangement direction, the preset distance W1 between adjacent transistor subgroups 151 is set to be equal to the distance W2 between adjacent first transistors Q1, so that the first transistors Q1 and the transistor subgroups 151 can be arranged one-to-one opposite to each other in the arrangement direction, and the position of the first transistor Q1 with a fault can be accurately tested by the transistor subgroups 151 that are one-to-one opposite to the first transistors Q1.

[0105] Fig.13 The arrangement direction of the middle transistor subgroup 151 is parallel to the target side 120 in the pixel area 12. If the target side 120 is parallel to the row direction X, the target side 120 can be the first side 121 or the third side 123, and the arrangement direction is parallel to the row direction X; if the target side 120 is parallel to the column direction Y, the target side 120 can be the second side 122 or the fourth side 124, and the arrangement direction is parallel to the column direction Y.

[0106] refer to Fig.14 , Fig.14 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above implementation, Fig.14 In the thin film transistor panel shown, for the same transistor group 15, within the area of ​​the preset distance W1, the first routing line 161, the second routing line 162 and the third routing line 163 are all provided with a cutting position 17, and the line width of the cutting position is smaller than the line width outside the cutting position. In this manner, based on the cutting position 17, it is convenient to locate the dividing position when the transistor group 15 is divided, and based on the smaller line width of the cutting position 17, it is also convenient to divide the transistor group 15.

[0107] refer to Fig.15 , Fig.15 A cross-sectional view of a transistor group at a wiring position provided in an embodiment of the present application, Fig.15 Taking the first line 161 having the setting position 18 as an example for illustration, Fig.15 FIG. 4 shows a partial cross-sectional view of the first wiring 161 along the length direction in the area of ​​the preset distance W1. Fig.15 The section shown is parallel to the arrangement direction of the transistor subgroups 151 in the transistor group 15 and parallel to the first direction Z. The first direction Z is perpendicular to the first surface 111 .

[0108] Fig.15In the illustrated manner, within the region of the preset distance W1, at least one of the first routing line 161, the second routing line 162, and the third routing line 163 has a set position 18, and the routing thickness of the set position 18 is less than the routing thickness outside the set position 18. Optionally, the first routing line 161, the second routing line 162, and the third routing line 163 may be respectively provided with a set position 18 within the region of the preset distance W1.

[0109] Optionally, for a routing line having a set position 18 , the routing line can be set to have a groove at the set position 18 , with the groove located on a surface of the routing line facing away from the substrate 11 , so that the routing thickness at the set position 18 is smaller than the routing thickness outside the set position 18 .

[0110] exist Fig.15 In the illustrated embodiment, the setting position 18 with a smaller wiring thickness facilitates the positioning of the segmentation position when the transistor group 15 is segmented. Meanwhile, the setting position 18 with a smaller wiring thickness also facilitates the segmentation of the transistor group 15 .

[0111] refer to Fig.16 , Fig.16 An equivalent circuit diagram of a transistor group provided in an embodiment of the present application, for the same transistor group 15, adjacent transistor sub-groups 151 are connected in parallel based on a control switch 19. Based on the control switch 19, the transistor group 15 can be disconnected at different positions. When the performance of the first transistor Q1 is tested based on the transistor group 15, the transistor group 15 can be disconnected at a desired position by controlling the switch 19, without physically dividing the transistor group 15.

[0112] Fig.16 In the figure, the transistor group 15 is parallel to the side of the pixel area 12 whose length direction is the row direction X. In this case, the arrangement direction of the transistor sub-group 151 is parallel to the row direction X. For the transistor group 15 parallel to the side of the pixel area 12 whose length direction is the column direction Y, it can also be as follows Fig.16 As shown, the parallel connection between adjacent transistor subgroups 151 is achieved by controlling the switch 19 .

[0113] Optionally, for the same transistor group 15, at least one of the first routing 161, the second routing 162, and the third routing 163 between two adjacent transistor sub-groups 151 may be provided with a control switch 19. Further, the first routing 161, the second routing 162, and the third routing 163 between two adjacent transistor sub-groups 151 may be provided with a control switch 19. In this manner, by providing a control switch 19 at a position where each routing is located between two adjacent transistor sub-groups 151, the transistor group 15 may be disconnected between any two transistor sub-groups 151 through the control switch 19, so as to facilitate accurate positioning of the position of the faulty first transistor Q1 in the pixel area 12 through the binary test method.

[0114] refer to Fig.17 , Fig.17 Another equivalent circuit diagram of a transistor group provided in an embodiment of the present application is based on the above implementation mode. Fig.17 In the illustrated embodiment, the transistor subgroup 151 includes a second transistor Q2. For the same transistor group 15, a row of second transistors Q2 are sequentially arranged along the arrangement direction. The circuit structure of the transistor group 15 is simple, which is convenient for the process preparation of the thin film transistor panel.

[0115] refer to Fig.18 , Fig.18 Another equivalent circuit diagram of a transistor group provided in an embodiment of the present application is based on the above implementation mode. Fig.18 In the illustrated manner, the transistor subgroup 151 includes a plurality of second transistors Q2 arranged in sequence; for the same transistor group 15, the arrangement direction (first arrangement direction F1) of the plurality of second transistors Q2 in the transistor subgroup 151 is perpendicular to the arrangement direction of the transistor subgroups in the transistor group 15. In the same transistor subgroup 151, the arrangement direction of the plurality of second transistors Q2 is the second arrangement direction F2. In the same transistor group 15, the first arrangement direction F1 is perpendicular to the second arrangement direction F2, and both are parallel to the first surface 111.

[0116] exist Fig.18 In the shown manner, a transistor sub-group 151 is provided to include a plurality of second transistors Q2 arranged in sequence, and a gate G of each second transistor Q2 in the same transistor sub-group 151 is connected to a first wiring 161, a source S is connected to a second wiring 162, and a drain D is connected to a third wiring 163. The second transistors Q2 can be connected in parallel, and the currents in the second transistors Q2 can be superimposed to improve the current capacity, and the on-resistance can be reduced to reduce the test power consumption, thereby improving the test sensitivity of the transistor group 15.

[0117] On the basis of the above-mentioned implementation, in the thin film transistor panel provided in the embodiment of the present application, the second transistor Q2 can be set to have the same shape as the first transistor Q1, and the spacing between adjacent second transistors Q2 can be the same as the spacing between adjacent first transistors Q1. If the transistor group 15 is parallel to the side extending along the row direction X in the pixel area 12, in the row direction X, the spacing between two adjacent second transistors Q2 in the transistor group 15 and two adjacent first transistors Q1 is the same. If the transistor group 15 is parallel to the side extending along the column direction Y in the pixel area 12, in the column direction Y, the spacing between two adjacent second transistors Q2 in the transistor group 15 and two adjacent first transistors Q1 is the same. In this way, the spacing between the second transistors Q2 in the transistor group 15 is set to be the same as the spacing between the first transistors Q1 in the pixel area 12, and the first transistor Q1 can be better characterized by the second transistor Q2, so as to more accurately test the performance of the first transistor Q1 through the second transistor Q2.

[0118] refer to Fig.19 , Fig.19 An equivalent circuit diagram of a thin film transistor panel provided in an embodiment of the present application, Fig.19 1 shows a row of first transistors Q1 adjacent to the target side 120 in the pixel area 12 and a transistor group 15 parallel to and opposite to the target side 120. The transistor group 15 includes a plurality of second transistors Q2 arranged in sequence along the first arrangement direction F1. The first wiring 161, the second wiring 162 and the third wiring 163 in the transistor group 15 are all floating; the first transistor Q1 is connected to the shift register circuit 21 based on the scan line 20. In other ways, the first transistor Q1 can also be directly connected to the drive circuit (gate drive chip) through the scan line 20.

[0119] exist Fig.19 In the manner shown, the first routing line 161, the second routing line 162 and the third routing line 163 are all floating. When the first transistor Q1 is tested through the transistor group 15, the test signal can be connected to the transistor group 15 and the sampling signal can be obtained based on the pads 14 connected to each routing line. There is no need to set a test signal input circuit for connecting the transistor group 15 in the thin film transistor panel, and no additional layout space of the panel will be occupied.

[0120] Moreover, compared with the solution of directly setting up a test signal input circuit connected to the transistor group 15 in the panel, the method of inputting test signals and outputting sampling signals through the pad 14 in the embodiment of the present application will not be limited by the layout position of the test signal input circuit, so that the panel can test the first transistor Q1 through the binary test method, and the transistor group 15 can be cut off as needed.

[0121] refer to Fig. 20 , Fig. 20A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above embodiment, Fig. 20 In the illustrated embodiment, the first surface 111 includes at least one panel area 22, and the panel area 22 includes a pixel area 12 and a frame area BB surrounding the pixel area 12. For the same panel area 22, the transistor groups 15 parallel to the sides of the pixel area 12 are located in the frame area BB. Fig. 20 In the figure, the first side 121 of the pixel region 12 is illustrated as an example in which the first side 121 of the pixel region 12 has parallel and opposite transistor groups 15. As described above, other sides of the pixel region 12 may also have parallel and opposite transistor groups 15. Among them, a panel area 22 can be used to prepare an array substrate of a display panel.

[0122] When the border area BB of the panel area 22 has sufficient space, Fig. 20 As shown, the transistor group 15 is set in the border area BB of the panel area 22. The redundant space in the border area BB can be used to layout the transistor group 15 for testing the first transistor Q1. The transistor group 15 can be made closer to the pixel area 12, so that the first transistor Q1 can be tested more accurately through the second transistor Q2.

[0123] refer to Fig.21 , Fig.21 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above embodiment, Fig.21 In the shown manner, the border area BB includes a first area 221 surrounding the pixel area 12 and a second area 222 surrounding the first area 221, the first area 221 is used to set a pseudo pixel and a pseudo pixel circuit corresponding to the pseudo pixel; the pixel area 12 is provided with a display pixel and a pixel circuit connected to the display pixel, the pixel circuit includes a first transistor Q1; the transistor group 15 is located in the first area 221, the thin film transistor in the pseudo pixel circuit serves as the second transistor Q2, and the pseudo pixel is disconnected from the pseudo pixel circuit.

[0124] Fig.21 The display pixel area in the pixel area 12 and the first transistor Q1 connected thereto, and the dummy pixel in the first area 221 and the dummy pixel circuit connected thereto are not shown. These structures may be the same as those in the existing display panel, and will not be described in detail in the embodiments of the present application.

[0125] exist Fig.21In the shown manner, the transistor in the pseudo-pixel circuit is reused as the second transistor Q2, so that the transistor group 15 is set in the first area 221, which can minimize the distance between the second transistor Q2 and the pixel area 12, so that the first transistor Q1 can be tested more accurately through the second transistor Q2; in addition, since the transistor in the pseudo-pixel circuit is reused as the second transistor Q2, there is no need to prepare the second transistor Q2 separately and additional layout space.

[0126] When the transistor group 15 is arranged in the border area BB, the transistor group 15 is not limited to being arranged in the first area 221. In other methods, the transistor group 15 can also be arranged in the second area 222. This method can use the second area 222 of the border area BB outside the dummy pixel circuit to layout the transistor group 15, and can use the redundant space in the second area 222 to layout the transistor group 15, so as to perform performance testing on the first transistor Q1 in the pixel area 12.

[0127] refer to Fig. 22 , Fig. 22 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above embodiment, Fig. 22 In the illustrated embodiment, a side frame region BB of the pixel region 12 has a shift register circuit 21 , and an opposite side frame region BB has a transistor group 15 . Fig. 22 In the illustrated embodiment, a transistor group 15 is provided in a side frame area BB adjacent to the first side 121 in the pixel area 12 as an example for illustration. The transistor group 15 is parallel to the first side 121 , and correspondingly, a shift register circuit 21 is provided in a side frame area BB adjacent to the third side 123 .

[0128] exist Fig. 22 In the manner shown, the transistor group 15 and the shift register circuit 21 are respectively arranged in the border area BB on the opposite sides of the pixel area 12. This can avoid the problem that when the two are located in the same side border area BB, the shift register circuit 21 needs to connect to the first transistor Q1 by changing the line because the transistor group 15 is located between the shift register circuit 21 and the pixel area 12.

[0129] refer to Fig.23 , Fig.23 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above embodiment, Fig.23 In the shown manner, the first surface 111 includes a plurality of panel areas 22 arranged in an array, with a spacing area 23 between adjacent panel areas 22, a spacing area 23 between two adjacent panel areas 22 in the row direction X and between two adjacent panel areas 22 in the column direction Y; transistor groups 15 are respectively provided in the border areas BB of the panel areas 22.

[0130] As described above, each panel region 22 is used to prepare an array substrate of a display panel. The panel region 22 includes a pixel region 12 and a frame region BB surrounding the pixel region 12. Fig.23 In the illustrated embodiment, a large-sized thin film transistor panel is divided in the spacing area 23 to form a plurality of array substrates.

[0131] exist Fig.23 In the illustrated embodiment, since the transistor group 15 of each pixel region 12 is located in the frame area BB in the corresponding panel area 22 , each pixel region 12 needs to set a transistor group 15 in its own frame area BB to perform performance tests on the first transistor Q1 in each pixel region 12 .

[0132] Fig.23 In the illustrated method, the four sides of each pixel area 12 are respectively provided with parallel and opposite transistor groups 15 as an example for illustration, and at this time, four transistor groups 15 are provided in the frame area BB of each panel area 22. In other methods, the transistor group 15 can also be provided only in the frame area BB of any one side of the panel area 22, or the transistor group 15 can be provided only in the frame areas BB of any two sides of the panel area 22, or the transistor group 15 can be provided only in the frame areas BB of any three sides of the panel area 22.

[0133] On the basis of the above-mentioned embodiment, when the transistor group 15 is located in the border area BB of the panel area 22, the structure of the thin film transistor panel can also be as follows: Fig.24 shown.

[0134] refer to Fig.24 , Fig.24 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above embodiment, Fig.24 In the illustrated embodiment, the frame area BB of the panel area 22 has a fourth wiring 24 surrounding the pixel area 12, and the fourth wiring 24 is used to access a fixed voltage; wherein the fourth wiring 24 has a hollow area 241, and the transistor group 15 is located in the hollow area. Fig.24 In order to facilitate illustration, only one end of the fourth wiring 24 in the local frame area BB on one side of the pixel area 12 is taken as an example for illustration.

[0135] The fourth line 24 can be a common voltage line for accessing a common voltage. Taking an LCD panel as an example, a circle of common voltage lines surrounding the pixel area 12 needs to be arranged at the edges of the frame area BB to provide a common voltage. Since the common voltage line is relatively wide, it can be hollowed out, and the hollow area 241 in the common voltage line can be used to arrange the transistor group 15, so that the transistor group 15 does not need to occupy the panel space alone, which can save the panel space.

[0136] refer to Fig.25 , Fig.25 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above embodiment, Fig.25 In the illustrated method, the first surface 111 includes at least one panel area 22, the panel area 22 includes a pixel area 12 and a frame area BB surrounding the pixel area; the transistor group 15 is located outside the frame area BB. For products with a small layout space in the frame area BB, this method sets the transistor group 15 outside the panel area 22 without occupying the layout space of the panel area 22.

[0137] Fig.25 In the illustrated manner, the first side 121 is illustrated as an example in which the transistor groups 15 are parallel to each other, and the transistor groups 15 are located outside the panel area 22. As described above, other sides of the pixel area 12 may also have transistor groups 15 parallel to each other, and the transistor groups 15 parallel to each other on each side are all located outside the panel area 22.

[0138] refer to Fig.26 , Fig.26 A top view of another thin film transistor panel provided in an embodiment of the present application, based on the above embodiment, Fig.26 In the illustrated method, when there are multiple panel areas 22, there is a spacing area 23 between adjacent panel areas 22, and the transistor group is located in the spacing area 23; the adjacent panel areas 22 share the same transistor group 15. This method is based on a large-sized thin film transistor panel, which is divided in the spacing area 23 to form multiple array substrates.

[0139] exist Fig.26 In the illustrated embodiment, since the transistor group 15 parallel to the side of the pixel region 12 is located outside the panel region 22 where the pixel region 12 is located, the transistor group 15 can be arranged in the spacing region 23 between two adjacent panel regions 22 without occupying the layout space in the panel region 22.

[0140] It should be noted that in the implementation of the present application, if the transistor group 15 is located in the border area BB, after the test of the first transistor Q1 is completed based on the second transistor Q2, the transistor group 15 remains in the border area BB, and further remains in the array substrate prepared based on the panel area 22. If the transistor group 15 is located in the spacing area 23 between adjacent panel areas 22, after the test of the first transistor Q1 is completed based on the second transistor Q2, the transistor group 15 can be cut and separated from the panel area 22 when the thin film transistor panel is cut into a plurality of separate panel areas 22 (each panel area 22 can be used as an array substrate) based on the spacing area 23. At this time, the transistor group 15 is cut and separated from the array substrate prepared based on the panel area 22.

[0141] Based on the thin film transistor panel provided in the above embodiment, another embodiment of the present application further provides a testing method for the above thin film transistor panel. The testing method can be as follows: Fig. 27 shown.

[0142] refer to Fig. 27 , Fig. 27 A flow chart of a test method provided in an embodiment of the present application, wherein the test method includes:

[0143] Step S11: For the same transistor group 15, the first pad 141 connected through the first routing line 161 is used to connect the first test signal to the gate G of the second transistor Q2, the second pad 142 connected through the second routing line 162 is used to provide a second test signal to the source S of the second transistor Q2, and the third pad 143 connected through the third routing line 163 is used to obtain a sampling signal.

[0144] The sampling signal may be a current signal output by the transistor group 15 through the third pad 143 .

[0145] Step S12: determining whether there is a faulty first transistor Q1 in the pixel region based on the sampling signal.

[0146] As described above, since the second transistor Q2 is arranged in a layer-through manner with the first transistor Q1 and the two have the same structure, the performance of the first transistor Q1 can be guaranteed by the second transistor Q2. Therefore, the sampling signal obtained by the second transistor Q2 can be used to characterize the performance of the first transistor Q1 to detect whether there is a faulty first transistor Q1 in the pixel area 12.

[0147] Optionally, judging whether there is a faulty first transistor Q1 in the pixel region based on the sampling signal includes: if the sampling signal is greater than a set threshold, the pixel region has a faulty first transistor Q1.

[0148] For the panel area 22 determined by the design parameters, the size and layout of the first transistor Q1 in the pixel area 12 are determined. If there is no faulty first transistor Q1, the sampling signal of the second transistor Q2 in the corresponding transistor group 15 is a certain value, which can be pre-calibrated by a standard panel and used as a set threshold. When there is a faulty first transistor Q1, the sampling signal will increase, so by comparing the sampling signal with the set threshold, it can be determined whether there is a faulty first transistor Q1.

[0149] Hereinafter, in the process of determining whether there is a faulty first transistor Q1 by the binary test method, the set thresholds required for comparison of different numbers of transistor sub-groups 151 divided by the transistor group 15 can be pre-calibrated based on the corresponding calibration panel.

[0150] Optionally, for the same transistor group 15, when the sampling signal is greater than a set threshold, the testing method further includes: in the arrangement direction of the transistor sub-group 151 in the transistor group 15, based on the binary testing method, performing split testing on the transistor group 15 multiple times to determine the position of the faulty first transistor Q1 in the pixel area 12.

[0151] As described above, it is assumed that the pixel area 12 has m rows and n columns of first transistors Q1. For example, the transistor subgroup 151 in the transistor group 15 is a second transistor Q2, and the arrangement direction of the transistor subgroup 151 is parallel to the row direction X. At this time, the transistor group 15 has n second transistors Q2 arranged in sequence in the row direction X; each second transistor Q2 is arranged opposite to a column of first transistors Q1 in the column direction Y; along the row direction X, the n second transistors Q2 are sequentially the 1st test transistor to the nth test transistor. Based on this, the method for determining whether there is a faulty first transistor Q1 based on the binary test method is as follows: Fig.28 shown.

[0152] For the same transistor group 15, since the plurality of second transistors Q2 are connected in parallel based on the first wiring 161, the second wiring 162 and the third wiring 163, the plurality of second transistors Q2 in the same transistor group 15 can be tested simultaneously to test whether there is a faulty first transistor Q1 in the pixel area 12 as a whole. When it is determined that there is a faulty first transistor Q1, further testing can be performed based on the binary test method to determine the position of the faulty first transistor Q1 in the pixel area 12. Therefore, compared with the transistor test solution that is separated by multiple separation points, the technical solution of the present application can reduce the number of tests and improve the test efficiency.

[0153] Furthermore, in the embodiment of the present application, the arrangement of the second transistors Q2 in the transistor group 15 can be set to be the same as the arrangement of the first transistors Q1 in the pixel area. Specifically, the size of the second transistor Q2 can be set to be the same as the size of the first transistor Q1, and in the length direction of the parallel opposite sides, the spacing of the second transistors Q2 is the same as the spacing of the first transistors Q1, and the second transistors Q2 in the transistor group 15 correspond one-to-one to a row and / or a column of first transistors Q1, so that the performance of the first transistors Q1 in the pixel area 12 can be more accurately characterized by the second transistors Q2 in the transistor group 15, so as to more accurately test whether there is a faulty first transistor Q1 in the pixel area 12, and when determining that the first transistor Q1 has a fault, determine the position of the faulty first transistor Q1 in the pixel area 12.

[0154] refer to Fig.28 , Fig.28 A flow chart of a method for determining a first transistor having a fault based on a binary test method provided in an embodiment of the present application, wherein the method includes:

[0155] Step S21: When the sampling signal acquired by the transistor group 15 indicates that there is a faulty first transistor Q1 in the pixel area 12, the transistor group 15 is divided into two parts between the pth test transistor and the p+1th test transistor. p is a positive integer less than n.

[0156] Step S22: A first test signal is input based on the first pad 141 connected to the first test transistor to the p-th test transistor, a second test signal is input based on the second pad 142 connected to the first test transistor to the p-th test transistor, and a sampling signal is obtained based on the third pad 143 connected to the first test transistor to the p-th test transistor, and a comparison result of the sampling signal with the corresponding set threshold is used to determine whether there is a faulty first transistor Q1 in the first column to the p-th column in the pixel area 12.

[0157] Based on the same method, whether the p+1th to nth columns have a faulty first transistor Q1 is tested through the p+1th to nth test transistors.

[0158] If there is a faulty first transistor Q1 in the 1st to p+1th columns, the 1st to pth test transistors are divided into two parts based on the same method, and based on the two parts, it is determined whether there is a faulty first transistor Q1 in the corresponding columns in the pixel area 12.

[0159] If there is a faulty first transistor Q1 in the p+1th to nth columns, the p+1th to nth test transistors are divided into two parts based on the same method, and based on the two parts, it is determined whether there is a faulty first transistor Q1 in the corresponding columns in the pixel area 12.

[0160] Based on the above-mentioned segmentation method, the transistor group 15 is continuously segmented until it is determined whether there is a faulty first transistor Q1 in each column of the pixel area 12. Therefore, the transistor group 15 whose arrangement direction of the transistor sub-group 151 is the row direction X can determine whether there is a faulty first transistor Q1 in each column of the pixel area 12. Similarly, based on the transistor group 15 whose arrangement direction of the transistor sub-group 151 is the column direction Y, it can be determined whether there is a faulty first transistor Q1 in each row of the pixel area 12. Based on two transistor groups 15 whose arrangement directions of the transistor sub-group 151 are perpendicular, the position of the faulty first transistor Q1 in the pixel area 12 can be determined by the positioning method of crossing rows and columns.

[0161] As described above, the first transistor Q1 and the second transistor Q2 can both be IGZO transistors. The IGZO transistors in the pixel area 12 are prone to failures caused by conductivity or other abnormal characteristics. The embodiment of the present application can test whether the IGZO transistors in the pixel area 12 have failures based on the transistor group 15.

[0162] Take the test of whether the IGZO transistor in the pixel area 12 has a conductor problem as an example. The off-state current of the unit device in the transistor group 15 is 10×10 -14 A level, when the conductor is 10×10 -6 If the transistor group 15 has N second transistors Q2, the channel width-to-length ratio of the second transistor Q2 is M, and the off-state current of the transistor group 15 is I, then the off-state current of the unit device is equal to I / (N*M).

[0163] Taking the area of ​​the substrate 11 as 2600mm*2250mm, when the distance between two display pixels in the pixel area 12 is in the range of 0.1mm-0.2mm, a panel area 22 with 3 rows and 4 columns can be prepared. The long side direction of the substrate 11 contains at most 2600mm÷(0.1mm-0.2mm)*3=39000-78000 transistors in parallel, if there is no conductor problem. The off-state current of the unit device after parallel connection is about 10×10 -10 A level, which is 10×10 -6There is a significant magnitude difference in the magnitude of A. If the device characteristics show that some devices are conductive, it can be found that the off-state current is abnormally large. Therefore, in the embodiment of the present application, the sampling signal in the transistor group 15 can be the off-state current of the device. Based on the comparison structure of the off-state current obtained by sampling and the calibrated set threshold, it can be determined whether there is a conductive IGZO transistor in the pixel area 12.

[0164] In the embodiment of the present application, the source-drain current I of the IGZO transistor can be obtained based on the sampling of the transistor group 15. DS After that, combined with the gate-source voltage V applied to the IGZO transistor during the test GS , you can draw an IV curve. If there is a conductor problem, then I DS It will be too large. Since the transistor group 15 includes a plurality of second transistors Q2 arranged in sequence, the IGZO transistors measured in a single time involve a small range, which can improve the efficiency of the IGZO transistor conductor detection.

[0165] As described above, in the embodiment of the present application, since the transistor group 15 includes a plurality of second transistors Q2 arranged in sequence along the first arrangement direction F1, it is possible to measure at one time whether there are conductorization problems with the corresponding plurality of first transistors Q1 in the pixel area 12. If there is a conductorization problem, the transistor group 15 is cut off based on the binary test method and measured again until the row and column where the conductorized first transistor Q1 is located are determined. This can quickly and accurately locate the area where the conductorized first transistor Q1 is located on the large-size substrate 11, thereby improving the efficiency of conductorization detection and quickly locating the conductorized position.

[0166] Based on the thin film transistor panel and the testing method thereof provided in the above embodiments, another embodiment of the present application further provides a method for preparing a thin film transistor. The preparation method can be as follows: Fig.29 shown.

[0167] refer to Fig.29 , Fig.29 A schematic flow chart of a method for preparing a thin film transistor panel provided in an embodiment of the present application, wherein the method comprises:

[0168] Step S31 : providing a substrate 11 having a first surface 111 ; the first surface 111 includes at least one pixel region 12 .

[0169] Step S32: forming a first transistor Q1 and a transistor group 15 on the substrate 11; the pixel area 12 includes a plurality of first transistors Q1 arranged in an array; in the same row of first transistors Q1, the gate of the first transistor Q1 is connected to the same scan line, and the source of the first transistor Q1 is connected to different signal lines; the transistor group 15 includes a plurality of transistor sub-groups 151 arranged in sequence, and the transistor sub-group 151 includes a second transistor Q2; in the same transistor group 15, the gate of the second transistor Q2 is connected to the same first wiring 161, the source of the second transistor Q2 is connected to the same second wiring 162, and the drain of the second transistor Q2 is connected to the same third wiring 163; the first wiring 161, the second wiring 162 and the third wiring 163 are respectively connected to at least one pad 14; the second transistor Q2 is arranged on the same layer as the first transistor Q1;

[0170] At least one side of the pixel region 12 is parallel to and opposite to a transistor group 15 , and the arrangement direction of the transistor subgroups 151 in the transistor group 15 is parallel to the length direction of the parallel to and opposite to the side.

[0171] The manufacturing method provided in the embodiment of the present application can manufacture the above-mentioned thin film transistor panel, and can test the performance of the first transistor Q1 by the second transistor Q2 in the thin film transistor panel to determine whether there is a faulty first transistor Q1 in the pixel area 12.

[0172] Taking the case where the channel width-to-length ratio of the transistor in the thin film transistor panel is 4:5.5 and the pad size is 20μm*10μm as an example, the width occupied by a transistor group 15 is 50μm, and the transistor group 15 can be placed outside the panel area 22, that is, located in the spacing area 23 for cutting between the panel area 22 and the panel area 22, or located in the hollow area within the wider routing in the border area BB, or located in the area where the pseudo pixels are laid out in the border area BB. Since the width of the transistor group 15 is small (about 50μm), the different layout methods of the transistor group 15 have little impact on the border area BB.

[0173] Optionally, during the manufacturing process, the first wiring 161, the second wiring 162, and the third wiring 163 are connected to an electrostatic discharge circuit. During the manufacturing process of the thin film transistor panel, the first wiring 161, the second wiring 162, and the third wiring 163 are connected to an electrostatic discharge circuit to prevent static electricity from damaging the wiring and transistors in the transistor group 15 during the panel manufacturing process.

[0174] In the embodiment of the present application, the electrostatic discharge circuit includes a transistor. The transistor in the electrostatic discharge circuit, the first transistor Q1, and the second transistor Q2 can be arranged in the same layer and prepared synchronously based on the same process flow. After the preparation of the transistor in the panel is completed, the signal lines and electrode structures, such as the touch line and the ITO electrode layer, are sequentially arranged above the transistor. Adjacent conductive layers are isolated by an insulating layer.

[0175] Optionally, the preparation method further includes: disconnecting the first wiring 161, the second wiring 162, and the third wiring 163 from the electrostatic discharge circuit; and testing the first transistor Q1 based on the transistor group 15. After disconnecting the electrostatic discharge circuit from the wiring in the transistor group 15, the performance of the first transistor Q1 can be tested using the second transistor Q2 in the transistor group 15 based on the test method provided in the above embodiment to determine whether there is a faulty first transistor Q1 in the pixel area 12.

[0176] As described in the above embodiments of the thin film transistor panel, the transistor group 15 can be disposed in the border area BB of the panel area 22 , or outside the panel area 22 .

[0177] If the transistor group 15 is arranged outside the panel area 22, the preparation method further includes: after testing the first transistor Q1 based on the transistor group 15, cutting and removing the transistor group 15. In this way, after completing the test of the first transistor Q1 based on the transistor group 15, the transistor group 15 can be cut and removed, and the transistor group 15 will not occupy the layout space of the panel area 22 after cutting. The array substrate formed based on the panel area 22 has the transistor group 15, which can reduce the influence of the transistor group 15 on the reliability of the display panel.

[0178] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0179] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0180] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0181] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0182] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A thin film transistor panel, characterized in that: include: A substrate having a first surface; the first surface includes at least one pixel area, and the pixel area includes a plurality of first transistors arranged in an array; In the first transistors in the same row, the gates of the first transistors are connected to the same scan line, and the sources of the first transistors are connected to different signal lines; At least one transistor group is arranged on the first surface, the transistor group includes a plurality of transistor sub-groups arranged in sequence, the transistor sub-group includes a second transistor; in the same transistor group, the gate of the second transistor is connected to the same first routing line, the source of the second transistor is connected to the same second routing line, and the drain of the second transistor is connected to the same third routing line; the first routing line, the second routing line and the third routing line are respectively connected to at least one pad; the second transistor is arranged on the same layer as the first transistor; Wherein, at least one side of the pixel region is parallel to and opposite to one of the transistor groups, and an arrangement direction of the transistor sub-groups in the transistor group is parallel to a length direction of the parallel to and opposite to the side.

2. The thin film transistor panel according to claim 1, characterized in that: The pixel area comprises a first side and a second side, the first side is parallel to the row direction of the array, and the second side is parallel to the column direction of the array; Wherein, one transistor group is disposed on the first side and the second side in parallel and opposite to each other.

3. The thin film transistor panel according to claim 2, characterized in that: The pixel area further includes a third side opposite to the first side and a fourth side opposite to the second side; and a transistor group is disposed parallel to and opposite to at least one of the third side and the fourth side.

4. The thin film transistor panel according to claim 1, characterized in that: The pixel area has m rows and n columns of the first transistors, and m and n are both positive integers greater than 1; If one of the transistor groups is parallel to and opposite to the side of the pixel region extending in the row direction, the transistor group has n transistor subgroups, and each transistor subgroup corresponds to a column of the first transistors; If one of the transistor groups is parallel to and opposite to a side of the pixel region extending along a column direction, the transistor group has m transistor subgroups, and each of the transistor subgroups corresponds to a row of the first transistors.

5. The thin film transistor panel according to claim 1, characterized in that: In the same transistor group, the first routing line, the second routing line and the third routing line all extend along the arrangement direction of the transistor sub-group; the pads connected to the first routing line, the second routing line and the third routing line are the first pad, the second pad and the third pad in sequence; In the arrangement direction, multiple positions of the first routing line are respectively connected to the first pad, multiple different positions of the second routing line are respectively connected to the second pad, and multiple different positions of the third routing line are respectively connected to the third pad.

6. The thin film transistor panel according to claim 5, characterized in that: For the same transistor group, in the arrangement direction, the transistor sub-groups are respectively connected to one first pad, one second pad and one third pad.

7. The thin film transistor panel according to claim 1, characterized in that: For the same transistor group, adjacent transistor sub-groups have a preset distance in the arrangement direction, and the preset distance is greater than 3 μm.

8. The thin film transistor panel according to claim 7, characterized in that: The preset distance is equal to the spacing between two adjacent first transistors in the arrangement direction.

9. The thin film transistor panel according to claim 7, characterized in that: In the area of ​​the preset distance, at least one of the first routing line, the second routing line and the third routing line has a set position, and the routing thickness at the set position is smaller than the routing thickness outside the set position.

10. The thin film transistor panel according to claim 1, characterized in that: For the same transistor group, adjacent transistor sub-groups are connected in parallel based on control switches.

11. The thin film transistor panel according to claim 10, characterized in that: For the same transistor group, at least one of the first routing, the second routing and the third routing between two adjacent transistor sub-groups is provided with the control switch.

12. The thin film transistor panel according to claim 1, characterized in that: The transistor subgroup includes one second transistor.

13. The thin film transistor panel according to claim 1, characterized in that: The transistor subgroup includes a plurality of the second transistors arranged in sequence; For the same transistor group, an arrangement direction of the plurality of second transistors in the transistor sub-group is perpendicular to an arrangement direction of the transistor sub-group in the transistor group.

14. The thin film transistor panel according to claim 1, characterized in that: The second transistor has the same shape as the first transistor, and a distance between adjacent second transistors is the same as a distance between adjacent first transistors.

15. The thin film transistor panel according to claim 1, characterized in that: The first routing line, the second routing line and the third routing line are all floating; The first transistor is connected to a shift register circuit or a driving circuit based on the scan line.

16. The thin film transistor panel according to any one of claims 1 to 15, characterized in that: The first surface includes at least one panel area, and the panel area includes one pixel area and a frame area surrounding the pixel area; For the same panel area, the transistor groups parallel to and opposite to the sides of the pixel area are located in the border area.

17. The thin film transistor panel according to claim 16, characterized in that: The frame area includes a first area surrounding the pixel area and a second area surrounding the first area, the first area is used to set a dummy pixel and a dummy pixel circuit corresponding to the dummy pixel; the pixel area is provided with a display pixel and a pixel circuit connected to the display pixel, and the pixel circuit includes the first transistor; The transistor group is located in the first region, the thin film transistor in the dummy pixel circuit serves as the second transistor, and the dummy pixel is disconnected from the dummy pixel circuit.

18. The thin film transistor panel according to claim 17, characterized in that: The border area on one side of the pixel area has a shift register circuit, and the border area on the other side opposite to the pixel area has the transistor group.

19. The thin film transistor panel according to claim 16, characterized in that: The frame area includes a first area surrounding the pixel area and a second area surrounding the first area, the first area is used to set a dummy pixel and a dummy pixel circuit corresponding to the dummy pixel; The transistor group is located in the second region.

20. The thin film transistor panel according to claim 16, characterized in that: The first surface includes a plurality of panel areas arranged in an array, and there are spacing areas between adjacent panel areas; The transistor groups are respectively arranged in the frame areas of the panel region.

21. The thin film transistor panel according to claim 16, characterized in that: The frame area has a fourth wiring surrounding the pixel area, and the fourth wiring is used to access a fixed voltage; The fourth wiring has a hollow area, and the transistor group is located in the hollow area.

22. The thin film transistor panel according to any one of claims 1 to 15, characterized in that: The first surface includes at least one panel area, and the panel area includes one pixel area and a frame area surrounding the pixel area; The transistor group is located outside the border area.

23. The thin film transistor panel according to claim 22, characterized in that: When there are a plurality of the panel regions, there is a spacing region between adjacent panel regions, and the transistor group is located in the spacing region; and the adjacent panel regions share the same transistor group.

24. A method for testing a thin film transistor panel according to any one of claims 1 to 23, characterized in that: include: For the same transistor group, a first test signal is connected to the gate of the second transistor through a first pad connected to the first routing line, a second test signal is provided to the source of the second transistor through a second pad connected to the second routing line, and a sampling signal is obtained through a third pad connected to the third routing line; It is determined whether the pixel region has a failed first transistor based on the sampling signal.

25. The testing method according to claim 24, characterized in that: The method of determining whether the pixel region has a faulty first transistor based on the sampling signal comprises: If the sampling signal is greater than a set threshold, the pixel region has a faulty first transistor.

26. The testing method according to claim 25, characterized in that: For the same transistor group, when the sampling signal is greater than the set threshold, the method further comprises: In the arrangement direction of the transistor sub-groups in the transistor group, the transistor group is subjected to split testing multiple times based on a binary testing method to determine the position of the failed first transistor in the pixel area.

27. A method for preparing a thin film transistor panel, characterized in that: include: Providing a substrate having a first surface; the first surface includes at least one pixel area; forming a first transistor and a transistor group on the substrate; The pixel area includes a plurality of first transistors arranged in an array; in the same row of the first transistors, the gates of the first transistors are connected to the same scan line, and the sources of the first transistors are connected to different signal lines; the transistor group includes a plurality of transistor sub-groups arranged in sequence, and the transistor sub-groups include second transistors; in the same transistor group, the gates of the second transistors are connected to the same first routing, the sources of the second transistors are connected to the same second routing, and the drains of the second transistors are connected to the same third routing; the first routing, the second routing, and the third routing are each connected to at least one pad; the second transistor is arranged on the same layer as the first transistor; Wherein, at least one side of the pixel region is parallel to and opposite to one of the transistor groups, and an arrangement direction of the transistor sub-groups in the transistor group is parallel to a length direction of the parallel to and opposite to the side.

28. The preparation method according to claim 27, characterized in that: During the preparation process, the first wiring, the second wiring and the third wiring are connected to an electrostatic discharge circuit.

29. The preparation method according to claim 28, characterized in that: Also includes: Disconnecting the first wiring, the second wiring, and the third wiring from the electrostatic discharge circuit; Based on the transistor group, the first transistor group is tested.

30. The preparation method according to claim 27, characterized in that: Also includes: Based on the transistor group, after testing the first transistor group, the transistor group is cut and removed.

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