Communication system capable of improving signal delay and slave device and operation method thereof
By using two different ports to output and receive delayed clock signals in the main device of the SPI interface, the time delay problem between the clock signal and the reading data at high frequencies of the SPI interface is solved, and the effect of improving the maximum operating frequency is achieved.
Patent Information
- Application Number
- CN202410630611.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-26
- Filing Date
- 2024-05-21
- Publication Date
- 2025-04-29
AI Technical Summary
The four-wire serial peripheral interface (SPI) has a time delay between the clock signal and the read data at high operating frequency, resulting in invalid time compression of the setting time of the main device latch MISO data, limiting the maximum operational frequency of the SPI interface.
By outputting clock signals and receiving delayed clock signals on two different SPI ports of the main device, the signal time delay is eliminated and the maximum operating frequency of the SPI interface is improved.
Effectively eliminates the time delay between the clock signal and the read data, improves the maximum operating frequency of the SPI interface, and avoids the compression of the setting time of the main device latch reading data during high-speed operation.
Smart Images
Figure CN119903000A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a communication interface, and more particularly to a communication system using a serial peripheral interface and an operating method thereof, which can improve the system operating frequency by reducing signal time delay. Background Art
[0002] Please refer to Figure 1 , which is a connection diagram of a known four-wire serial peripheral interface (4-wire SPI). The master device and the slave device are connected to each other through a chip select line (NCS / SS line), a master input slave input line (MOSI line), a clock line (SCLK line) and a master input slave output line (MISO line).
[0003] Please also refer to Figure 2 As shown in FIG. 1 , when the master device performs a read operation, the master device first asserts the chip select line to a low level, then drives the read address on its MOSI pin and drives 8 clocks on its SCLK pin. After waiting for a time Tsrad, the master device drives another 8 clocks to allow the slave device to drive the read data on its MISO pin. There is no specific limit to the length of Tsrad.
[0004] Please refer to Figure 3 As shown, it is Figure 2 A magnified view of the rectangular box WOI. Figure 3 Shows the three time delays that exist when the master performs a read operation, including the clock transmission delay t sclk , Slave device circuit delay t sclk2miso and data transmission delay t miso , which together form an invalid time. At the falling edge of the clock signal SCLK, the slave device clocks out the MISO data (shown as read data), and the master device latches the MISO data at the rising edge of the clock signal SCLK. Generally speaking, the master device requires a setup time to latch the MISO data.
[0005] When the operating frequency (ie, clock frequency) of the SPI interface increases, the period of the clock signal SCLK will be shortened. Due to the above-mentioned inactive time, it will compress the setup time of the master device latching MISO data, thereby limiting the maximum operating frequency of the SPI interface. Summary of the invention
[0006] In view of this, the present invention provides a communication system and an operating method thereof which can eliminate the above three time delays to increase the maximum operating frequency of the SPI interface.
[0007] The present invention provides a communication system and an operation method thereof for outputting clock signals and receiving delayed clock signals at two different SPI ports of a master device respectively, so as to eliminate the problem of invalid time compression of the setup time of the master device latch MISO data due to signal time delay during high operating frequency reading operation.
[0008] The present invention provides a communication system including a master device and a slave device. The master device includes a first interface port and a second interface port. The slave device is used to receive a clock signal from the first interface port through a first clock line, and output a delayed clock signal of the clock signal to the second interface port through a second clock line.
[0009] The present invention also provides a slave device using a serial peripheral interface. The slave device comprises a first clock pin, a clock generating circuit, a second clock pin and a master input slave output pin. The first clock pin is used to receive a clock signal. The clock generating circuit is used to generate a delayed clock signal of the clock signal. The second clock pin is used to output the delayed clock signal. The master input slave output pin is used to output read data.
[0010] The present invention also provides an operation method of a communication system using a serial peripheral interface. The communication system includes a master device and a slave device. The operation method includes: the slave device receives address data from the master device through a master-out slave-in line and receives a clock signal from the master device through a clock line; when it is determined that the address data indicates a read operation, the clock generating circuit of the slave device outputs a delayed clock signal of the clock signal to the master device; and when it is determined that the address data indicates a write operation, the clock generating circuit stops outputting the delayed clock signal.
[0011] In order to make the above and other purposes, features and advantages of the present invention more obvious, the following will be described in detail with reference to the accompanying drawings. In addition, in the description of the present invention, the same components are represented by the same symbols, which are hereby described together. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 It is a connection diagram of a known four-wire serial peripheral interface;
[0013] Figure 2 is a schematic diagram of a read operation of a known four-wire serial peripheral interface;
[0014] Figure 3 yes Figure 2 A magnified view of the rectangular frame WOI, which shows the signal time delay of the read operation;
[0015] Figure 4 is a connection diagram of a communication system according to an embodiment of the present invention;
[0016] Figure 5 is a schematic diagram of signal time delay when a clock signal is sent back from an input / output pad of a device in a communication system according to an embodiment of the present invention;
[0017] Figure 6 is a block diagram of a clock generating circuit of a slave device of a communication system according to an embodiment of the present invention;
[0018] Figure 7 is a schematic diagram of a time delay element of a slave device of a communication system according to an embodiment of the present invention;
[0019] Figure 8 is a read operation signal timing diagram of a communication system according to an embodiment of the present invention, which shows a delayed clock signal and read data transmitted from a device; and
[0020] Fig. 9 is a flow chart of an operating method of a communication system according to an embodiment of the present invention; and
[0021] Fig.10 is a connection diagram of a communication system according to another embodiment of the present invention;.
[0022] Description of Reference Numerals
[0023] 400 Communication System
[0024] 41 Main device
[0025] 411 First interface port
[0026] 412 Secondary interface port
[0027] 43 Slave Device
[0028] 430 Input and output pads
[0029] 4301 Multiplexer
[0030] 431 Digital Core
[0031] 4311 Clock Generation Circuit DETAILED DESCRIPTION
[0032] An object of the present invention is to provide a communication system that reduces or even eliminates the time delay between a clock signal (SCLK) and read data when a serial peripheral interface (SPI) performs a read operation. A clock generator is additionally provided in a slave device of the SPI interface to generate a delayed clock signal and transmit it to a master device through an additional clock pin (SCLK pin) to eliminate the time delay, thereby increasing the maximum operating frequency of the SPI interface.
[0033] Please refer to Figure 4 , which is a connection diagram of a communication system 400 according to an embodiment of the present invention. The communication system 400 includes a master device 41 and a slave device 43, which are connected via a chip select line (e.g., shown as an NCS line), a master-out slave-in line (e.g., shown as a MOSI line), a first clock line (e.g., shown as an SCLK line I), a second clock line (e.g., shown as an SCLK line II), and a master-in slave-out line (e.g., shown as a MISO line). The master device 41 and the slave device 43 of the present invention communicate via five connection lines.
[0034] The slave device 43 may be a human input device, such as an optical navigation detection device, a mouse, a keyboard, a joystick, or other devices applicable to the SPI interface, without specific limitations. The master device 41 is a computer device connected to the slave device 43, such as a processor, a microcontroller unit, a desktop computer, a laptop computer, a workstation, or other computer devices applicable to the SPI interface, without specific limitations.
[0035] In one embodiment, the master device 41 includes a first interface port 411 and a second interface port 412. The first interface port 411 is connected to the NCS line, the MOSI line, and the SCLK line I. The second interface port 412 is connected to the SCLK line II and the MISO line. The first interface port 411 and the second interface port 412 are serial peripheral interface ports (SPI ports). When running, the first interface port 411 runs in a master mode, and the second interface port 412 runs in a slave mode.
[0036] The slave device 43 includes an I / O pad 430 and a digital core 431. The I / O pad 430 is used to receive signals / data through the connection lines and transmit them to the digital core 431, and output the signals / data generated by the digital core 431 to the master device 41 through the connection lines.
[0037] The input / output pads 430 include a chip select pin (e.g., shown as an NCS pin), a master-output slave-input pin (e.g., shown as a MOSI pin), a first clock pin (e.g., shown as an SCLK pin I), a second clock pin (e.g., shown as an SCLK pin II), and a master-input slave-output pin (e.g., shown as a MISO pin).
[0038] The chip select pin is connected to the chip select line for receiving a chip select signal NCS from the host device 41 (see, for example, Figure 8 ). The method of sending the chip selection signal NCS from the master device to the slave device in the serial peripheral interface is well known, so it will not be described in detail here.
[0039] The master-out slave-in pin is connected to the master-out slave-in line for receiving MOSI data, such as address data and write data, from the master device 41. The method of sending MOSI data from the master device to the slave device in the serial peripheral interface is well known and will not be described in detail here.
[0040] The first clock pin is connected to the first clock line for receiving the clock signal SCLK from the first interface port 411 of the master device 41. The method of sending the clock signal SCLK from the master device to the slave device in the serial peripheral interface is well known and will not be described in detail here.
[0041] The second clock pin is connected to the second clock line, and is used to output a delayed clock signal of the clock signal SCLK (e.g., shown as delayed SCLK) to the second interface port 412 of the host device 41. In the present invention, the delayed SCLK is generated by the clock generating circuit 4311 according to the clock signal SCLK and the read data, which will be described below with examples.
[0042] The master input slave output pin is connected to the master input slave output line, and is used to output the read data to the second interface port 412 of the master device 41 when the address data from the MOSI pin indicates a read operation. In the serial peripheral interface, the method of the slave device sending the read data to the master device according to the read address is well known, so it will not be repeated here.
[0043] In one embodiment, the clock generating circuit 4311 is included in the digital core 431, and its function is to make the time delay between the delayed clock signal and the clock signal SCLK be, for example, 10% to 40% of the period of the clock signal SCLK, so as to reduce the time difference between the falling edge of the clock signal SCLK and the reading of data, for example, referring to Figure 3 Preferably, the clock generating circuit 4311 can make the time delay of the delayed clock signal and the clock signal SCLK equal to the signal delay of the read data (for example, shown as t sclk2miso ) is the same as, for example, refer to Figure 8 , to eliminate the time difference between the falling edge of the clock signal SCLK and the reading of data.
[0044] The clock generating circuit 4311 has a preset delay time for the clock signal SCLK. Figure 3 The inactive time shown is intended to mitigate the compression effect on the setup time and has no specific restrictions.
[0045] Please refer to Figure 6 As shown, it is an implementation of the clock generating circuit 4311. The clock generating circuit 4311 includes a first flip-flop 61, a second flip-flop 62, a third flip-flop 63 and an XNOR gate 64. The S terminals of the first flip-flop 61, the second flip-flop 62 and the third flip-flop 63 respectively receive the same chip selection signal NCS from the master device 41.
[0046] The input terminal D of the first flip-flop 61 is connected to the shift register of the slave device 43, and is used to receive the read data output by the shift register. The clock input terminal of the first flip-flop 61 receives the inverted signal of the clock signal SCLK. The output terminal Q of the first flip-flop 61 outputs the read data according to the inverted signal of the clock signal SCLK, for example, displayed as MISO_int. MISO_int is transmitted to the master device 41 through the MISO line.
[0047] The output terminal Q of the second flip-flop 62 is connected to the input terminal D thereof through a NOT gate 621, and outputs a signal temp_1. The clock input terminal of the second flip-flop 62 receives an inverted signal of the clock signal SCLK.
[0048] The output terminal Q of the third flip-flop 63 is connected to the input terminal D thereof through the NOT gate 631, and outputs the signal temp_2. The clock input terminal of the third flip-flop 63 receives the clock signal SCLK.
[0049] XNOR gate 64 is connected to the output terminals Q of second flip-flop 62 and third flip-flop 63 to receive output signals temp_1 and temp_2 respectively, and performs XNOR operation according to output signals temp_1 and temp_2 to output a delayed clock signal, such as SCLK_int, which is transmitted to master device 41 via SCLK line II.
[0050] Please refer to the receiving signals (including NCS and SCLK) and output signals (including temp_1, temp_2, MISO_int, SCLK_int) of the first trigger 61, the second trigger 62 and the third trigger 63. Figure 8Since the delayed clock signal SCLK_int and the read data MISO_int are transmitted to the second interface port 412 of the master device 41 through the second clock line SCLK line II and the MISO line respectively, when the time delay of the delayed clock signal SCLK_int is the same as the signal delay of the read data MISO_int, the master device 41 does not sample the read data MISO_int as shown in FIG. Figure 3 The delay shown.
[0051] In one implementation, an EDA place and route and timing tool may be used in advance to configure the wiring of the clock generation circuit 4311 so that MISO_int and SCLK_int have substantially the same phase. Figure 8 The phases of the output signals temp_1 and temp_2 are determined by the wiring of the clock generating circuit 4311.
[0052] Once the manufacturing is completed, the wiring of the clock generating circuit 4311 is fixed. In another embodiment, the slave device 43 further includes a first delay element 65 and a second delay element 66. Figure 6 The first delay element 65 is connected to the output terminal Q of the first trigger 61 and is used to fine-tune the signal delay of the read data MISO_int. Figure 8 The second delay element 66 is connected to the output end of the XOR gate 64 and is used to fine-tune the time delay between the delayed clock signal SCLK_int and the clock signal SCLK. Figure 8 .
[0053] Please refer to Figure 7 As shown in FIG. 1 , it is an implementation of the first delay element 65 and the second delay element 66, which includes a series combination of multiple NOT gates as multiple input terminals of the multiplexer MUX. According to the delay control signal of the multiplexer MUX, which is, for example, a control signal using an electronic fuse (EFUSE) or a buffer (register), a programmable delay element can be formed. During operation, MISO_int and SCLK_int are respectively adjusted through different numbers of NOT gates (determined by the delay control) to adjust their delay times. It is preferred to use elements 65 and 66 to achieve the following. Figure 8 As shown, there is no phase difference between MISO_int and SCLK_int.
[0054] The purpose of the present invention is to reduce or even eliminate the time difference between the clock signal SCLK and the read data. In one embodiment, when it is determined that the address data from the master device 41 indicates a write operation, the slave device 43 does not output the delayed clock signal. The method of using address data to indicate a read operation or a write operation is known, so it will not be described in detail here.
[0055] Please refer to Figure 4 As shown, in one embodiment, the input and output pads 430 of the slave device 43 further include a multiplexer 4301, whose input end is connected to the first clock pin and the clock generating circuit 4311. The output end of the multiplexer 4301 is connected to the second clock pin. Thereby, the multiplexer 4301 can switch to output a delayed clock signal (e.g., displayed as delayed SCLK) or a loopback clock signal (e.g., displayed as loopback SCLK) to the master device 41. Please also refer to Figure 5 As shown, the purpose of looping back SCLK can eliminate Figure 3 The transmission delay t sclk and t miso , but the circuit delay t of the slave device 43 sclk2miso It cannot be eliminated by the return SCLK. However, since the invalid time is shortened, it can also shorten the time difference between the clock signal SCLK and the read data. In the present invention, the multiplexer 4301 can be controlled to output the return SCLK or delay the SCLK to the second interface port 412 of the master device 41 according to different applications.
[0056] Preferably, the wiring transmission delay of the return SCLK matches the wiring transmission delay of the read data. In one embodiment, the multiplexer 4301 and the return SCLK can be selectively implemented. In another embodiment, the multiplexer 4301 and the clock generation circuit 4311 are not configured. Fig.10 The communication system 1000 is shown to eliminate Figure 3 The transmission delay t sclk and t miso And only Figure 5 The circuit delay t sclk2miso .that is, Fig.10 In the embodiment, there is no delay on SCLK. Fig.10 In, with Figure 4 The same elements are marked with the same reference numerals and are not described in detail.
[0057] Please refer to Fig. 9 As shown, it is an operating method of a communication system using a serial peripheral interface according to an embodiment of the present invention. The communication system is, for example, Figure 4The communication system 400 shown in the figure. The operation method includes: receiving address data from the master device 41 (more specifically, its first interface port 411) through the master-out slave-in line by the slave device 43 and receiving the clock signal SCLK from the master device 41 through the clock line (step S91); when it is determined that the address data indicates a read operation (i.e., a read address), outputting a delayed clock signal of the clock signal SCLK to the master device 41, more specifically, its second interface port 412, by the clock generating circuit 4311 of the slave device 43 (step S92); and when it is determined that the address data indicates a write operation (i.e., a write address), stopping outputting the delayed clock signal by the clock generating circuit 4311.
[0058] The details of this operation mode have been explained above, so I will not repeat them here. One of the purposes of this operation mode is also to make Figure 8 The SCLK_int and MISO_int have the same phase.
[0059] In an embodiment of the present invention, the master device 41 includes a first processor, such as a microprocessor unit (MCU) that executes its operations with hardware, software and / or firmware, for example, the first interface port 411 and the second interface port 412 are included in the first processor; the slave device 43 includes a second processor, such as a digital signal processor (DSP) or a specific user integrated circuit (ASIC) that executes its operations with hardware, software and / or firmware, for example, the digital core 431 is included in the second processor.
[0060] It must be noted that the time relationship of signals in the description of the present invention, such as time delay and signal delay, is only used for illustration and is not intended to limit the present invention.
[0061] In summary, when the conventional four-wire serial peripheral interface performs a read operation, there is a time delay between the clock signal and the read data, which compresses the setting time of the master device latching the read data under high-speed operation, thereby limiting the maximum operating frequency of the serial peripheral interface. Therefore, the present invention further provides a communication system 400 (refer to Figure 4 ) and its operation method (refer to Fig. 9 ), which is additionally configured with a clock signal line to return a clock signal or a delayed clock signal to a master device, so that the master device can sample the read data according to the returned clock signal or the delayed clock signal, thereby reducing or even eliminating the time delay between the clock signal and the read data, and eliminating the limitation of the setup time of the master device latching the read data under high-speed operation, thereby increasing the maximum operating frequency of the communication system.
[0062] Although the present invention has been disclosed through the above examples, they are not intended to limit the present invention. Any person skilled in the art with ordinary knowledge in the art to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.
Claims
1. A communication system, comprising: a host device, the host device comprising a first interface port and a second interface port; and A slave device is used to receiving a clock signal from the first interface port via a first clock line, and A delayed clock signal of the clock signal is output to the second interface port through a second clock line.
2. The communication system according to claim 1, wherein: The first interface port and the second interface port are serial peripheral interface ports, The first interface port is configured to operate in a master control mode, and The second interface port is used to operate in a slave control mode.
3. The communication system according to claim 1, wherein: The slave device is also used to transmit read data to the master device via a master-in slave-out line, and The time delay between the delayed clock signal and the clock signal is close to or the same as the signal delay of the read data.
4. The communication system according to claim 3, wherein: The digital core of the slave device includes a clock generation circuit for generating the delayed clock signal, and the clock generation circuit includes: A first trigger, the input end of which is connected to the shift register of the slave device, the clock input end of which receives the inverse signal of the clock signal, and the output end of which outputs the read data; A second flip-flop, the output end of the second flip-flop is connected to the input end thereof through a NOT gate, and the clock input end thereof receives an inverted signal of the clock signal; A third trigger, the output terminal of the third trigger is connected to the input terminal thereof through a NOT gate, and the clock input terminal thereof receives the clock signal; and An XNOR gate is connected to the output ends of the second flip-flop and the third flip-flop to output the delayed clock signal.
5. The communication system according to claim 4, wherein: The S terminals of the first trigger, the second trigger and the third trigger respectively receive chip selection signals from the master device.
6. The communication system according to claim 4, wherein: The slave device further comprises: a first delay element connected to the output terminal of the first trigger for fine-tuning the signal delay; and A second delay element is connected to the output end of the XOR gate and is used to fine-tune the time delay.
7. The communication system according to claim 4, wherein: The input and output pads of the slave device include: A first clock pin connected to the first clock line; A second clock pin connected to the second clock line; and A multiplexer, wherein the input end of the multiplexer is connected to the first clock pin and the clock generating circuit, and the output end of the multiplexer is connected to the second clock pin.
8. The communication system according to claim 1, wherein: The time delay between the delayed clock signal and the clock signal is 10% to 40% of the period of the clock signal.
9. The communication system according to claim 1, wherein: The slave device receives address data via the master-out slave-in line, and When it is determined that the address data indicates a write operation, the slave device does not output the delayed clock signal.
10. A slave device using a serial peripheral interface, the slave device comprising: A first clock pin, the first clock pin is used to receive a clock signal; A clock generating circuit, the clock generating circuit is used to generate a delayed clock signal of the clock signal; A second clock pin, the second clock pin is used to output the delayed clock signal; as well as The master input slave output pin is used to output read data.
11. The slave device according to claim 10, wherein: The clock generating circuit comprises: A first trigger, the input end of which is connected to the shift register of the slave device, the clock input end of which receives the inverse signal of the clock signal, and the output end of which outputs the read data; A second flip-flop, the output end of the second flip-flop is connected to the input end thereof through a NOT gate, and the clock input end thereof receives an inverted signal of the clock signal; A third trigger, the output terminal of the third trigger is connected to the input terminal thereof through a NOT gate, and the clock input terminal thereof receives the clock signal; and An XNOR gate is connected to the output ends of the second flip-flop and the third flip-flop to output the delayed clock signal.
12. The slave device according to claim 11, wherein: The S terminals of the first trigger, the second trigger and the third trigger are used to receive a chip selection signal.
13. The slave device according to claim 11, further comprising: A first delay element connected to the output terminal of the first trigger for fine-tuning a signal delay of the read data; and The second delay element is connected to the output end of the XOR gate and is used to fine-tune the time delay between the delayed clock signal and the clock signal.
14. The slave device according to claim 10, further comprising: A multiplexer, wherein the input end of the multiplexer is connected to the first clock pin and the clock generating circuit, and the output end of the multiplexer is connected to the second clock pin.
15. The slave device according to claim 10, wherein: The time delay between the delayed clock signal and the clock signal is 10% to 40% of the period of the clock signal.
16. The slave device according to claim 10, wherein: The slave device further comprises a master-out slave-in pin for receiving address data, and When it is determined that the address data indicates a write operation, the slave device does not output the delayed clock signal.
17. A method for operating a communication system using a serial peripheral interface, the communication system comprising a master device and a slave device, the method comprising: The slave device receives address data from the master device via a master-out slave-in line and receives a clock signal from the master device via a clock line; When it is determined that the address data indicates a read operation, the clock generating circuit of the slave device outputs a delayed clock signal of the clock signal to the master device; as well as When it is determined that the address data indicates a write operation, the clock generating circuit stops outputting the delayed clock signal.
18. The operating method according to claim 14, wherein: The time delay between the delayed clock signal and the clock signal is 10% to 40% of the period of the clock signal.
19. The operating method according to claim 17, wherein: The slave device includes a multiplexer, and the operating method further includes: The multiplexer is used to switch and output the delayed clock signal or to feed back the clock signal to the master device.
20. The operating method according to claim 17, wherein: The main device includes a first interface port and a second interface port, and the operating method further includes: outputting the clock signal via the first interface port; and The delayed clock signal is received at the second interface port.