Array substrate, display panel, display device and repair method

Abstract

The embodiments of the present disclosure provide an array substrate, a display panel, a display device, and a repair method. The array substrate includes: a plurality of gate line groups; a plurality of data lines; a plurality of transistors, wherein the transistors include: a first electrode of a transistor and a second electrode of a transistor; a portion of the orthographic projection of the substrate of the second electrode of the transistor is located between the orthographic projections of two gate lines of the same gate line group on the substrate; a plurality of pixel electrode groups; the pixel electrode groups include: two pixel electrodes distributed along the first direction; a plurality of first common routing lines, wherein the orthographic projection of the substrate of the first common routing lines is located between the orthographic projections of two gate lines of the same gate line group on the substrate, and at least a portion of the orthographic projection of the substrate of the first common routing lines overlaps with at least a portion of the orthographic projection of the transistor second electrode on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, a display device and a repair method. Background Art

[0002] Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has a variety of commonly used display modes, such as twisted nematic (TN), vertically aligned (VA), fringe field switching (FFS), and in-plane switching (IPS). VA offers better dark state performance and contrast compared to other display modes. Summary of the Invention

[0003] The present disclosure provides an array substrate, a display panel, a display device, and a repair method. The array substrate includes:

[0004] An array substrate, comprising:

[0005] substrate;

[0006] A plurality of gate line groups are located on one side of the substrate and extend along a first direction, wherein the gate line group includes: two gate lines extending along the first direction;

[0007] a plurality of data lines extending along a second direction, wherein the second direction intersects the first direction;

[0008] a plurality of transistors, each transistor comprising: a first transistor electrode electrically connected to the data line, and a second transistor electrode; the second transistor electrode being located at a portion of an orthographic projection of the substrate and between two gate lines of the same gate line group and an orthographic projection of the substrate;

[0009] a plurality of pixel electrode groups, wherein at least a portion of the pixel electrode groups, as an orthographic projection of the substrate, is located at an area formed by the intersection of the gate line group and the data line; the pixel electrode group comprises: two pixel electrodes distributed along the first direction;

[0010] A plurality of first common routing lines, wherein the orthographic projections of the first common routing lines on the substrate are located between the orthographic projections of two gate lines of the same gate line group on the substrate, and at least a portion of the orthographic projection of the first common routing lines on the substrate overlaps with at least a portion of the orthographic projection of the second electrode of the transistor on the substrate.

[0011] In a possible embodiment, the pixel electrode includes: a pixel electrode body, and a pixel electrode overlapping portion extending from one end of the pixel electrode body; the pixel electrode overlapping portion is located between the orthographic projections of two gate lines of the same gate line group on the substrate;

[0012] The pixel electrode overlapping portion overlaps at least a portion of the orthographic projection of the substrate with the second electrode of the transistor.

[0013] In a possible embodiment, the pixel electrode overlapping portion includes: a first sub-overlapping portion extending along the second direction, and a second sub-overlapping portion extending along the first direction; one end of the first sub-overlapping electrode is electrically connected to the pixel electrode body, and the other end is electrically connected to the second sub-overlapping portion;

[0014] The orthographic projection of the second sub-overlapping portion on the substrate is located between the orthographic projections of two gate lines of the same gate line group on the substrate.

[0015] In a possible implementation manner, the two pixel electrodes in the same pixel electrode group are electrically connected to the same data line through the transistor;

[0016] In the same pixel electrode group, the second sub-bridge portions of the two pixel electrodes both extend from the first sub-bridge portion toward the electrically connected data line.

[0017] In a possible implementation manner, the two second sub-overlapping portions of the two adjacent pixel electrodes in the second direction extend from the first sub-overlapping portion in opposite directions.

[0018] In a possible implementation, the array substrate includes: a first axis located between adjacent pixel electrodes and extending along the second direction;

[0019] In the first direction, at least parts of at least two adjacent second overlapping sub-portions are symmetrical about the first axis.

[0020] In a possible implementation, the plurality of transistors include: a first transistor and a second transistor; in the same pixel electrode group, one pixel electrode is electrically connected to the data line via the first transistor, and another pixel electrode is electrically connected to the data line via the second transistor;

[0021] The array substrate includes: a second axis passing through the center of the pixel electrode and extending along the first direction; the first transistor and the second transistor electrically connected to the same pixel electrode group, the second pole of the first transistor and the second pole of the second transistor being symmetrical about the second axis.

[0022] In a possible implementation, in the first transistor and the second transistor electrically connected to the same pixel electrode group, the second electrode of the first transistor and the second electrode of the second transistor are both located between the first axis and the electrically connected data line.

[0023] In a possible implementation manner, in the second direction, at least partially adjacent second electrodes of two transistors are symmetrical about the second axis.

[0024] In a possible implementation, the second electrode of the transistor includes: a second electrode first portion extending along the second direction, and a second electrode second portion connected to the second electrode first portion and extending along the first direction;

[0025] In the second direction, the second electrode first portions of at least two adjacent second electrodes of the transistors extend from the second electrode second portions toward the side of the pixel electrode body to which they are electrically connected.

[0026] In a possible implementation manner, in the first direction, the second electrode first portions of at least some of the adjacent two second electrodes of the transistors extend in opposite directions from the second electrode second portions.

[0027] In a possible implementation manner, in the first direction, the second portions of at least some of the second electrodes of two adjacent transistors are symmetrical about the first axis.

[0028] In one possible implementation, the transistor further includes an active pattern; the active pattern includes a first active outer edge extending along the second direction, and a second active outer edge; in the same transistor, an orthographic projection of the second active outer edge on the substrate is located on a side of the first active outer edge away from the data line connected to the transistor;

[0029] The first electrode of the transistor includes: a first electrode first portion extending along the second direction, and a first electrode second portion connecting the first electrode first portion and the data line;

[0030] At least part of the orthographic projection of the first active outer edge on the substrate overlaps with at least part of the orthographic projection of the outer edge of the first pole first portion on the side away from the second pole first portion on the substrate; at least part of the orthographic projection of the second active outer edge on the substrate overlaps with at least part of the orthographic projection of the second pole first portion on the side away from the first pole first portion on the substrate.

[0031] In a possible implementation manner, the array substrate further includes: a first insulating layer located between the layer where the pixel electrode group is located and the layer where the second electrode of the transistor is located;

[0032] The first insulating layer includes a first via hole, and the pixel electrode overlapping portion is electrically connected to the second electrode of the transistor through the first via hole.

[0033] In a possible implementation manner, the first common trace overlaps at least a portion of the orthographic projection of the substrate with the first via hole.

[0034] In a possible implementation, the array substrate further includes: a color resist layer located on a side of the layer where the pixel electrodes are located that faces the substrate;

[0035] The first insulating layer includes the color resist layer.

[0036] In a possible implementation, the array substrate further includes: a plurality of first spacers and a plurality of second spacers; the length of the first spacers in a direction perpendicular to the substrate is greater than the length of the second spacers in a direction perpendicular to the substrate;

[0037] The orthographic projection shape of the first spacer on the substrate is different from the orthographic projection shape of the second spacer on the substrate.

[0038] In a possible implementation manner, a maximum length of the second spacer in the second direction is greater than a maximum length of the first spacer in the second direction.

[0039] In a possible implementation manner, the distribution density of the second spacers is greater than the distribution density of the first spacers.

[0040] In one possible implementation, the first common routing line includes: a first sub-common routing line portion and a second sub-common routing line portion arranged along the first direction; at least a portion of the first sub-common routing line portion overlaps with at least a portion of an orthographic projection of the data line on the substrate; at least a portion of the orthographic projection of the second sub-common routing line on the substrate overlaps with at least a portion of an orthographic projection of the pixel electrode overlapping portion on the substrate;

[0041] A maximum length of the first sub-common routing portion in the second direction is smaller than a maximum length of the second sub-common routing portion in the second direction.

[0042] In a possible implementation manner, the array substrate further includes: a first conductive layer located on a side of the data line facing away from the substrate;

[0043] The first conductive layer includes: a plurality of first wirings extending along the second direction, and second wirings electrically connected to the first wirings and extending along the first direction; the second wirings are disconnected at positions intersecting with the pixel electrode overlapping portions;

[0044] At least part of the orthographic projection of the first routing line on the substrate overlaps with at least part of the orthographic projection of the data line on the substrate; at least part of the orthographic projection of the second routing line on the substrate overlaps with at least part of the orthographic projection of the gate line on the substrate.

[0045] In a possible implementation, the second routing line includes: a plurality of second routing sub-portions sequentially distributed along the first direction; the second sub-route portion is electrically connected to the first routing line; the first conductive layer further includes: a third routing line extending along the second direction;

[0046] The orthographic projection of the third routing line on the substrate is located between the orthographic projections of the two pixel electrodes of the pixel electrode group on the substrate; one end of the third routing line is electrically connected to the second routing sub-portion on one side of the pixel electrode, and the other end is connected to the second routing sub-portion on the other side of the pixel electrode and connected to the adjacent first routing line.

[0047] In a possible implementation manner, an orthographic projection of the third wiring on the substrate does not overlap with an orthographic projection of the pixel electrode overlapping portion on the substrate.

[0048] In a possible implementation manner, the second wiring is located in a portion of an orthographic projection of the substrate, in a gap between the gate line and the pixel electrode.

[0049] In a possible embodiment, the array substrate includes: a display area, and a non-display area located outside the display area; the first conductive layer also includes: a fourth line located in the non-display area and extending along the first direction, and the fourth line has multiple first hollows.

[0050] In a possible implementation, the first conductive layer further includes: a transition portion located on a side of the fourth wiring away from the display area, the transition portion having a plurality of second hollows.

[0051] In a possible implementation, the maximum length of the first hollowing along the second direction is greater than the maximum length along the first direction; the maximum length of the second hollowing along the second direction is greater than the maximum length along the first direction.

[0052] In a possible implementation manner, the maximum length of the first hollow in the first direction is less than or equal to the minimum distance between the pixel electrode and the first wiring in the first direction;

[0053] A maximum length of the second hollow in the first direction is less than or equal to a minimum distance between the pixel electrode and the first wiring in the first direction.

[0054] In a possible implementation manner, the first conductive layer and the pixel electrode are in the same layer.

[0055] This public embodiment also provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and further includes: an opposite substrate arranged opposite to the array substrate, and the opposite substrate is provided with a common electrode layer.

[0056] This public embodiment also provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0057] This public embodiment also provides a method for repairing the array substrate provided in the embodiment of the present disclosure, which includes:

[0058] testing the array substrate;

[0059] When it is determined that the pixel emits light abnormally, the transistor electrically connected to the pixel electrode in the pixel is electrically connected to the first common wiring.

[0060] In a possible implementation, electrically connecting the transistor in the pixel electrically connected to the pixel electrode to the first common wiring includes:

[0061] At the location of the first via hole, the second electrode of the transistor is electrically connected to the first common wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1A This is one of the schematic top views of the array substrate provided in the embodiment of the present disclosure;

[0063] Figure 1B for Figure 1A Schematic diagram of a single film layer in the middle gate line layer;

[0064] Figure 1C for Figure 1A Schematic diagram of a single film layer in the active layer;

[0065] Figure 1D for Figure 1A Schematic diagram of a single film layer in the data line layer;

[0066] Figure 1E for Figure 1A Schematic diagram of a single film layer of the pixel electrode layer;

[0067] Figure 1F for Figure 1A Schematic diagram of the cross section along the dotted line A-A';

[0068] Figure 1G for Figure 1A Schematic diagram of the cross section along the dotted line BB';

[0069] Figure 1H for Figure 1A One of the cross-sectional schematic diagrams corresponding to the dotted line C-C';

[0070] Figure 1I for Figure 1A The enlarged schematic diagram corresponding to the middle dashed line frame S1;

[0071] Figure 1J Can be Figure 1I Schematic diagram after darkening;

[0072] Figure 1K for Figure 1A The second cross-sectional diagram along the dotted line C-C';

[0073] Figure 2A One of the step-by-step schematic diagrams of the first spacer and the second spacer provided in the embodiment of the present disclosure;

[0074] Figure 2B The second schematic diagram of the first and second spacers provided in the embodiment of the present disclosure;

[0075] Figure 3A A second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0076] Figure 3B for Figure 3A Schematic diagram of a single film layer of the pixel electrode layer;

[0077] Figure 4 An equivalent circuit diagram provided for an embodiment of the present disclosure;

[0078] Figure 5 Schematic diagram of liquid crystal orientation in different regions provided by the embodiment of the present disclosure;

[0079] Figure 6 This is one of the schematic diagrams showing the principle of head shake wrinkles;

[0080] Figure 7 This is the second schematic diagram of the principle of head shake lines;

[0081] Figure 8 This is a schematic diagram of head shake wrinkles;

[0082] Figure 9 A schematic diagram of a repair process for an array substrate provided in an embodiment of the present disclosure;

[0083] Figure 10 A schematic diagram of the display panel structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. The implementation methods can be implemented in multiple different forms. Ordinary technicians in the relevant technical field can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following implementation methods. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0085] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0086] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%. In this specification, "approximately the same" may refer to values ​​that are within 10% of each other.

[0087] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0088] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0089] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0090] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0091] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0092] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0093] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0094] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0095] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0096] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0097] During pixel patching and darkening, the transistor drain must be welded to the common wiring, ensuring that the pixel electrode's potential remains at the common (Vcom) potential, resulting in a dark spot. In conventional pixel designs, this darkening via is located in the center of the pixel aperture. Due to process requirements, the metal area (transistor drain) is relatively large, significantly impacting the pixel aperture ratio. With the dual-gate architecture, compared to the conventional single-gate architecture, one additional gate line is added, further reducing the pixel aperture ratio. With the implementation of color filter on array (COA) technology, the darkening via cannot be located in the center of the pixel aperture because the color resist layer corresponding to the via requires an opening. After the opening, the color resist layer must be shielded from light by a light-shielding layer. Therefore, to maximize the pixel aperture ratio, the via must be moved as close to the gate line as possible. The darkening vias corresponding to the transistors on the upper and lower sides of the same pixel electrode are located separately, further compromising the aperture ratio.

[0098] In view of this, see Figure 1A-Figure 1H As shown, Figure 1A This is one of the schematic top views of the array substrate provided in the embodiment of the present disclosure. Figure 1B for Figure 1A Schematic diagram of a single film layer in the middle gate line layer. Figure 1C for Figure 1A Schematic diagram of a single film layer with active layer, Figure 1D for Figure 1A Schematic diagram of a single film layer in the data line layer, Figure 1E for Figure 1A Schematic diagram of a single film layer of the pixel electrode layer, Figure 1F for Figure 1A Schematic diagram of the cross section along the dotted line A-A', Figure 1G for Figure 1A Schematic diagram of the cross section along the dotted line BB', Figure 1H for Figure 1A A schematic cross-sectional view corresponding to the dotted line CC' shows that an embodiment of the present disclosure provides an array substrate, comprising:

[0099] Substrate 1;

[0100] A plurality of gate line groups 2 are located on one side of the substrate 1 and extend along a first direction X. The gate line group 2 includes two gate lines 20 extending along the first direction X. Specifically, the gate line group 2 can be located in a gap between adjacent rows of pixel electrodes 40. Specifically, the two gate lines 20 of the gate line group 2 can be a first gate line 21 and a second gate line 22.

[0101] The plurality of data lines 3 extend along a second direction Y, the second direction X intersecting the first direction Y; optionally, the second direction X is perpendicular to the first direction Y; specifically, the first direction X may be a direction of pixel electrode rows, and the second direction Y may be a direction of pixel electrode columns;

[0102] a plurality of transistors T, each transistor T including: a first transistor electrode TA electrically connected to the data line 3, and a second transistor electrode TB; a portion of the orthographic projection of the second transistor electrode TB on the substrate 1 being located between two gate lines 20 of the same gate line group 2 on the substrate 1; specifically, the first transistor electrode TA may be a source electrode, and the second transistor electrode TB may be a drain electrode;

[0103] A plurality of pixel electrode groups 4, wherein at least a portion of the pixel electrode groups 4 has an orthographic projection on the substrate 1 located at an area formed by the intersection of the gate line group 2 and the data line 3; the pixel electrode group 4 includes two pixel electrodes 40 distributed along a first direction X; specifically, the two pixel electrodes 40 in the same pixel electrode group 4 may be a first pixel electrode 41 and a second pixel electrode 42, respectively; specifically, the second pixel electrode 42 may be located on a side of the first pixel electrode 41 away from the electrically connected data line 3; specifically, the two pixel electrodes 40 in the same pixel electrode group 4 may be electrically connected to the same data line 3 via different transistors T;

[0104] Multiple first common routing lines 51, the orthographic projection of the first common routing line 51 on the substrate 1 is located between the orthographic projections of two gate lines 20 of the same gate line group 2 on the substrate 1, and at least part of the orthographic projection of the first common routing line 51 on the substrate 1 overlaps with at least part of the orthographic projection of the second terminal TB of the transistor on the substrate 1.

[0105] In the embodiment of the present disclosure, the part of the orthographic projection of the second electrode TB of the transistor on the substrate 1 is located between the orthographic projections of the two gate lines 20 of the same gate line group 2 on the substrate 1, and the orthographic projection of the first common wiring 51 on the substrate 1 is located between the orthographic projections of the two gate lines 20 of the same gate line group 2 on the substrate 1, and at least part of the orthographic projection of the first common wiring 51 on the substrate 1 overlaps with at least part of the orthographic projection of the second electrode TB of the transistor on the substrate 1, and then when the darkening process is performed, the second electrode TB of the transistor can be connected to the first common wiring 51, and the conductive via can be located between the orthographic projections of the two gate lines 20 on the substrate 1. Since a light-shielding layer (such as a black matrix) is usually provided between the two gate lines 20 and the area between the two gate lines 20, the darkening via can be hidden in the area where the light-shielding layer is located, thereby solving the dual The transmittance loss caused by the low aperture ratio of the gate pixel and the contrast reduction caused by the metal reflection in the opening area; moreover, compared with the conventional array substrate that sets common wiring on both sides of the gate line group 2, the embodiment of the present disclosure can also reduce one common wiring, reduce the width of the light-shielding layer (such as the black matrix), and the aperture ratio improvement effect is more obvious. In addition, compared with the conventional array substrate, the via holes usually have the alignment liquid not sticking, resulting in display abnormalities, thereby affecting the quality and yield. In the embodiment of the present disclosure, the first via K1 is located in the area where the light-shielding layer (such as the black matrix) is located, and the display abnormality area is effectively blocked by the light-shielding layer (such as the black matrix), which can increase the edge (Margin) width of the alignment liquid coating process and reduce the difficulty of the process.

[0106] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, the pixel electrode 40 includes: a pixel electrode body PA, and a pixel electrode overlap portion PB extending from one end of the pixel electrode body PA; the portion of the pixel electrode overlap portion PB projected on the substrate 1 is located between the two gate lines of the same gate line group 2 projected on the substrate 1; the portion of the pixel electrode overlap portion PB projected on the substrate 1 at least partially overlaps with the orthographic projection of the transistor second electrode TB projected on the substrate 1. In the disclosed embodiment, the portion of the pixel electrode overlap portion PB projected on the substrate 1 at least partially overlaps with the orthographic projection of the transistor second electrode TB projected on the substrate 1, so that the pixel electrode overlap portion PB and the transistor second electrode TB can be electrically connected at the overlapping position through a via, thereby realizing electrical connection between the pixel electrode 40 and the transistor T.

[0107] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, the orthographic projection of the pixel electrode body PA on the substrate 1 may be a rectangle. The length of the orthographic projection of the pixel electrode body PA on the substrate 1 along the second direction Y may be greater than the length along the first direction X. In one possible embodiment, Figure 1A and with Figure 1EAs shown in FIG. 1 , the pixel electrode overlapping portion PB extending from one end of the pixel electrode body PA may be a pixel electrode overlapping portion PB extending from a corner of the rectangular pixel electrode body PA.

[0108] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, at least part of the pixel electrode group 4 is projected on the substrate 1 and is located in the area formed by the intersection of the gate line group 2 and the data line 3. It can be that the pixel electrode body PA of the pixel electrode group 4 is projected on the substrate 1 and is located in the area formed by the intersection of the gate line group 2 and the data line 3.

[0109] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, the pixel electrode overlapping portion PB includes a first sub-overlapping portion PB1 extending along the second direction Y, and a second sub-overlapping portion PB2 extending along the first direction X. One end of the first sub-overlapping electrode PB1 is electrically connected to the pixel electrode body PA, and the other end is electrically connected to the second sub-overlapping portion PB2. The orthographic projection of the second sub-overlapping portion PB2 on the substrate 1 is located between the orthographic projections of two gate lines 20 of the same gate line group 2 on the substrate 1. In this way, the second sub-overlapping portion PB2 can be electrically connected to the second terminal TB of the transistor through a via at the overlapping position, thereby achieving electrical connection between the pixel electrode 40 and the transistor T.

[0110] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, the part of the positive projection of the pixel electrode overlapping portion PB on the substrate 1 overlaps at least partially with the positive projection of the transistor second electrode TB on the substrate 1, which can be the positive projection of the second sub-overlap portion PB2 on the substrate 1, overlapping with the positive projection of the transistor second electrode TB on the substrate 1.

[0111] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, the part of the pixel electrode overlapping portion PB on the orthographic projection of the substrate 1 is located between the orthographic projections of two gate lines of the same gate line group 2 on the substrate 1 20, which may be the orthographic projection of the second sub-overlapping portion PB2 on the substrate 1, located between the orthographic projections of two gate lines of the same gate line group 2 on the substrate 1 20.

[0112] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, the orthographic projection shape of the first sub-bridge portion PB1 on the substrate 1 can be a strip.

[0113] In one possible embodiment, combining Figure 1A and with Figure 1EAs shown, the second sub-bridge portion PB2 may further include: a third sub-bridge portion PB21 and a fourth sub-bridge portion PB4, which are sequentially distributed along the first direction X. One end of the third sub-bridge portion PB3 is electrically connected to the first sub-bridge portion PB1, and the other end is electrically connected to the fourth sub-bridge portion PB4. A maximum length d2 of the fourth sub-bridge portion PB4 along the second direction Y is greater than a maximum length d1 of the third sub-bridge portion PB3 along the second direction Y. In this manner, the pixel electrode 40 is electrically connected to the second terminal TB of the transistor at the fourth sub-bridge portion PB4.

[0114] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, two pixel electrodes 40 in the same pixel electrode group 4 are electrically connected to the same data line 3 through a transistor T; in the same pixel electrode group 4, the second sub-bridge portions PB2 of the two pixel electrodes 40 both extend from the first sub-bridge portion PB1 toward the electrically connected data line 3. Specifically, as Figure 1E In the first complete pixel electrode row from top to bottom, the second pixel electrode 40 from the left and the third pixel electrode 40 from the left are both electrically connected to the same data line 3 on their right sides. The second sub-overlapping portion PB2 of the second pixel electrode 40 from the left extends from the first sub-overlapping portion PB1 toward the side of the data line 3 electrically connected to the right side. The second sub-overlapping portion PB2 of the third pixel electrode 40 from the left also extends from the first sub-overlapping portion PB1 toward the side of the data line 3 electrically connected to the right side. In this way, while the array substrate hides the darkened via hole in the light-shielding layer, the multiple second overlapping portions PB of the entire array substrate can be regularly and neatly distributed, resulting in an aesthetically pleasing layout and space saving.

[0115] In one possible embodiment, combining Figure 1A and with Figure 1E As shown, the two second sub-bridge portions PB2 of the two adjacent pixel electrodes 40 in the second direction Y extend from the first sub-bridge portion PB1 in opposite directions. Figure 1E In the first complete pixel electrode row, the second sub-overlapping portion PB2 of the third pixel electrode 40 from the left extends to the right from the first sub-overlapping portion PB1; in the second complete pixel electrode row, the second sub-overlapping portion PB2 of the third pixel electrode 40 from the left extends to the left from the first sub-overlapping portion PB1. In this way, while the array substrate hides the darkened via hole in the light-shielding layer, the multiple second overlapping portions PB of the entire array substrate can be regularly and neatly distributed, resulting in an aesthetically pleasing layout and space saving.

[0116] In one possible embodiment, combining Figure 1A and with Figure 1EAs shown, the array substrate includes a first axis e1 extending along the second direction Y between adjacent pixel electrodes 40. At least portions of at least two adjacent second sub-overlapping portions PB2 are symmetrical about the first axis e1 in the first direction X. This allows the array substrate to conceal the darkened vias within the light-shielding layer while also allowing the multiple second overlapping portions PB throughout the array substrate to be regularly and evenly distributed, resulting in an aesthetically pleasing layout and space conservation.

[0117] Dual gate design poses significant challenges to panel design and manufacturing, primarily: 1. The reduction in the number of dates and the increase in the number of gate lines make charging the panel more difficult; 2. The smaller the pixel area, the smaller the pixel storage capacitor Ccs, while the pixel's parasitic capacitance remains almost unchanged, making it susceptible to parasitic capacitance (for example, coupling capacitance Cgs (the capacitance between the gate and the pixel, where the pixel can be understood as the pixel electrode and other structures electrically connected to the pixel electrode)), resulting in head shake defects; and for VA products, the storage capacitance is further reduced compared to ADS products, making VA dual gate products even more susceptible to parasitic capacitance, resulting in head shake and other defects.

[0118] Specifically, in a dual gate design, such as Figure 6 As shown, the signal loaded by the long pixel is the same as the data line adjacent to the long pixel (such as Figure 6 The polarity of the signal loaded by the first long pixel from left to right and the leftmost data line is opposite. When the data line (Data) signal is coupled with the common electrode signal (COM) and fluctuates, the long pixel will be brighter. The signal loaded by the short pixel is opposite to the polarity of the data line adjacent to the short pixel (such as Figure 6 The first short pixel from left to right and the second data line from left to right have the same signal polarity. When the data line (Data) signal is coupled with the common electrode signal (COM) and fluctuates, the short pixel will appear dark. Half of the colors in space have the same polarity, so the effect cannot be averaged. Time averaging is required. However, when the head moves, several frames may be lost, further deteriorating the spatial averaging effect. Figure 7 When the head shakes left and right, you can see rolling vertical lines on the screen, which are called head shaking lines. Figure 8 shown.

[0119] In view of this, in a possible implementation, combined with Figure 1A and with Figure 1DAs shown, the plurality of transistors T include: a first transistor T1, and a second transistor T2; in the same pixel electrode group 4, one pixel electrode 40 is electrically connected to the data line 3 via the first transistor T1, and the other pixel electrode 40 is electrically connected to the data line 3 via the second transistor T2; the array substrate includes: a second axis e2 passing through the center of the pixel electrode 40 and extending along the first direction X; in the first transistor T1 and the second transistor T2 electrically connected to the same pixel electrode group 4, the second electrode TB of the first transistor T1 is symmetrical with the second electrode TB of the second transistor T2 about the second axis e2. Specifically, for example, in combination Figure 1A and with Figure 1D As shown, the first transistor T1 marked by the dotted circle and the second transistor T2 marked by another dotted circle are the first transistor T1 and the second transistor T2 electrically connected to the same pixel electrode group 4, and the transistor second pole TB of the first transistor T1 marked by the dotted circle and the transistor second pole TB of the second transistor T2 marked by another dotted circle are symmetrical about the second axis e2.

[0120] In the embodiment of the present disclosure, in the first transistor T1 and the second transistor T2 electrically connected to the same pixel electrode group 4, the transistor second electrode TB of the first transistor T1 is symmetrical with the transistor second electrode TB of the second transistor T2 about the second axis e2, and can adapt to the distribution position of the second sub-lap portion PB2 of the first pixel electrode 41 and the second sub-lap portion PB2 of the second pixel electrode 42, so as to realize the electrical connection between the transistor second electrode TB and the pixel electrode 40, and can make the multiple transistor second electrodes TB of the entire array substrate be regularly and neatly distributed, with an aesthetically pleasing layout and space saving; moreover, in the embodiment of the present disclosure, in the first transistor T1 and the second transistor T2 electrically connected to the same pixel electrode group 4, The second electrode TB of the first transistor T1 is symmetrical with the second electrode TB of the second transistor T2 about the second axis e2, so that the first capacitor C1 and the second capacitor C2 can be roughly equal, wherein the first capacitor C1 is the capacitor formed by the gate line 20 and the first pixel structure, and the second capacitor C2 is the capacitor formed by the gate line 20 and the second pixel structure (the first pixel structure may include: a first pixel electrode 41, and a second electrode TB of the transistor connected to the first pixel electrode 41; the second pixel structure may include: a second pixel electrode 42, and a second electrode TB of the transistor connected to the second pixel electrode 42), thereby improving the problem of bad shaking head wrinkles in the dual-gate structure display panel of the prior art.

[0121] It should be noted that, in the actual manufacturing process, it may be difficult to make the first capacitor C1 and the second capacitor C2 completely equal. Therefore, in the embodiment of the present invention, the difference between the first capacitor C1 and the second capacitor C2 can be within the range of 0F to 0.0001F, that is, the two are considered to be approximately equal. Specifically, for example, the difference between the two is within the range of 0F to 0.00007F; specifically, for example, the difference between the two is 0; specifically, for example, the difference between the two is 0.00007F; specifically, for example, the difference between the two is 0.000061F; specifically, the difference between the two is 0.000036F. Specifically, for the first capacitor C1 and the second capacitor C2 in the embodiment of the present invention, before manufacturing the array substrate, they can be obtained through software simulation.

[0122] Specifically, the transistor may further include an active pattern 8, and the first pixel structure may further include: an active pattern 8 of a transistor T connected to the first pixel electrode 41; the second pixel structure may further include: an active pattern 8 of a transistor T connected to the second pixel electrode 42. Specifically, the capacitance generated by the gate line 20 and the active pattern 8 may exist only when the transistor is on. During the transistor off period, it can be considered that the capacitance generated by the gate line 20 and the active pattern 8 does not affect the first capacitor C1 or the second capacitor C2. When the transistor is turned on, the active pattern 8 of the transistor is electrically connected to the second electrode TB of the transistor, and the second electrode 32 is electrically connected to the first pixel electrode 41. At this time, the first capacitor C1 may include the capacitance formed between the gate line 20 and the first pixel electrode 41, between the gate line 20 and the second electrode TB of the transistor, and between the gate line 20 and the active pattern 8; when the transistor T is turned on, the active pattern 8 of the transistor T is electrically connected to the second electrode TB of the transistor, and the second electrode TB of the transistor is electrically connected to the second pixel electrode 42. At this time, the second capacitor C2 includes the capacitance formed between the gate line 20 and the second pixel electrode 42, between the gate line 20 and the second electrode TB of the transistor, and between the gate line 20 and the active pattern 8.

[0123] In one possible embodiment, combining Figure 1A and with Figure 1D As shown, in the same pixel electrode group 4, one pixel electrode 40 is electrically connected to the data line 3 through the first transistor T1, and the other pixel electrode 40 is electrically connected to the data line 3 through the second transistor T2. It can be that the first pixel electrode 41 in the same pixel electrode group 4 is electrically connected to the data line 3 through the first transistor T1, and the second pixel electrode 41 in the same pixel electrode group 4 is electrically connected to the data line 3 through the second transistor T2.

[0124] In one possible embodiment, combining Figure 1A and with Figure 1DAs shown, in the first transistor T1 and the second transistor T2 electrically connected to the same pixel electrode group 4, the second electrode TB2 of the first transistor T1 and the second electrode TB2 of the second transistor T2 are both located between the first axis e1 and the electrically connected data line 3. Specifically, for example, Figure 1A and with Figure 1D As shown, the first transistor T1 marked with a dotted circle and the second transistor T2 marked with another dotted circle are the first transistor T1 and the second transistor T2 electrically connected to the same pixel electrode group 4. The second transistor TB of the first transistor T1 marked with a dotted circle and the second transistor TB of the second transistor T2 marked with another dotted circle are both located between the first axis e1 and the electrically connected data line 3. In this way, by adapting the distribution position of the second sub-bridge portion PB2 of the first pixel electrode 41 and the second sub-bridge portion PB2 of the second pixel electrode 42, the electrical connection between the second transistor TB and the pixel electrode 40 is achieved, and the multiple second transistors TB of the entire array substrate can be regularly and neatly distributed, resulting in an aesthetically pleasing layout and saving space, which is conducive to improving the problem of bad shaking head wrinkles in the dual-gate structure display panel of the prior art.

[0125] In one possible embodiment, combining Figure 1A and with Figure 1D As shown, in the second direction Y, at least part of the second electrodes TB2 of two adjacent transistors are symmetrical about the second axis e2. Specifically, for example, Figure 1D In the figure, the first transistor second electrode TB2 on the left side of the right data line 3 from top to bottom is symmetrical with the second transistor second electrode TB2 on the left side from top to bottom about the second axis e2. For another example, the first transistor second electrode TB2 on the right side of the left data line 3 from top to bottom is symmetrical with the second transistor second electrode TB2 on the right side from top to bottom about the second axis e2.

[0126] In one possible embodiment, combining Figure 1A and with Figure 1D As shown, the transistor second electrode TB2 includes: a second electrode first portion TB1 extending along the second direction Y, and a second electrode second portion TB2 connected to the second electrode first portion TB1 and extending along the first direction X; in the second direction Y, the second electrode first portions TB1 of at least two adjacent transistor second electrodes TB are both extended from the second electrode second portion TB2 toward the side of the pixel electrode body PA that is electrically connected. Specifically, for example, in combination Figure 1A and with Figure 1DThe first transistor second pole TB2 from top to bottom on the left side of the right data line 3 and the second transistor second pole TB2 from top to bottom are both electrically connected to the pixel electrode group 4 in the first complete pixel electrode row from top to bottom (the pixel electrode group 4 includes the second pixel electrode 40 and the third pixel electrode 40 from left to right). Then the first second pole first part TB1 from top to bottom and the second second pole first part TB1 from top to bottom on the left side of the right data line 3 both extend from the second pole second part TB2 toward the side of the electrically connected pixel electrode body PA.

[0127] In one possible embodiment, combining Figure 1A and with Figure 1D As shown, in the first direction X, the second electrode first portion TB1 of at least two adjacent transistors TB extends in opposite directions from the second electrode second portion TB2. Figure 1D As shown, one of the two adjacent second-terminal first portions TB1 in the second row extends downward from the second-terminal second portion TB2, and the other extends upward from the second-terminal second portion TB2. This allows two diagonally opposite pixel electrodes 40 to be electrically connected to different data lines 3, and allows the multiple transistor second electrodes TB of the entire array substrate to be distributed regularly and evenly, resulting in an aesthetically pleasing layout and space conservation.

[0128] In one possible embodiment, combining Figure 1A and with Figure 1D As shown, in the first direction X, the second portions TB2 of at least two adjacent transistors T are symmetrical about the first axis e1. Specifically, for example, Figure 1D In the second row, the second second electrode second portion TB2 and the third second electrode second portion TB2 are symmetrical about the first axis e1. This allows the array substrate to conceal the darkened vias within the light shielding layer, while also allowing the multiple transistor second electrodes TB across the entire array substrate to be distributed in a regular and orderly manner, resulting in an aesthetically pleasing layout and space conservation.

[0129] In one possible embodiment, combining Figure 1A 、 Figure 1C 、 Figure 1D and with Figure 1IAs shown, the transistor further includes: an active pattern 8; the active pattern 8 includes: a first active outer edge f1 extending along the second direction Y, and a second active outer edge f2; in the same transistor T, the orthographic projection of the second active outer edge f2 on the substrate 1 is located on the side of the first active outer edge f1 away from the data line 3 connected to the transistor T; the transistor first electrode TA includes: a first electrode first portion TA1 extending along the second direction X, and a first electrode second portion TA2 connecting the first electrode first portion to the data line 3; at least a portion of the orthographic projection of the first active outer edge f1 on the substrate 1 overlaps with at least a portion of the orthographic projection of the outer edge of the first electrode first portion TA1 on the side away from the second electrode first portion TB1 on the substrate 1; at least a portion of the orthographic projection of the second active outer edge f2 on the substrate 1 overlaps with at least a portion of the orthographic projection of the outer edge of the second electrode first portion TB1 on the side away from the first electrode first portion TA1 on the substrate 1. Specifically, for example, Figure 1I In the embodiment, at least a portion of the orthographic projection of the first active outer edge f1 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the right edge of the first portion TA1 of the first electrode onto the substrate 1; at least a portion of the orthographic projection of the second active outer edge f2 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the left edge of the second portion TB1 of the second electrode onto the substrate 1. This minimizes the line width of the first portion TA1 of the first electrode and the first portion TB1 of the second electrode, reduces the parasitic capacitance between the layer containing the data line 3 and the layer containing the gate line 20, and achieves a high brush charge rate.

[0130] In one possible embodiment, combining Figure 1A and Figure 1H As shown, the array substrate further includes: a first insulating layer F1 located between the layer where the pixel electrode group 4 is located and the layer where the transistor second terminal TB2 is located; the first insulating layer F1 includes: a first via hole K1, and the pixel electrode lap portion PB is electrically connected to the transistor second terminal TB through the first via hole K1.

[0131] In one possible embodiment, combining Figure 1A 、 Figure 1H and Figure 1J As shown, Figure 1J Can be Figure 1I In the schematic diagram after darkening, when a pixel has poor light emission, the second terminal TB of the transistor can be connected to the first common wiring 51 directly below, so that the pixel is always at the common (Vcom) potential and displayed as a dark spot.

[0132] In one possible embodiment, combining Figure 1A 、 Figure 1H and Figure 1JAs shown, at least a portion of the orthographic projection of the darkened via K2 on the substrate 1 may overlap at least a portion of the orthographic projection of the first via K1 on the substrate 1. In one possible embodiment, the entire orthographic projection of the darkened via K2 on the substrate 1 may overlap the entire orthographic projection of the first via K1 on the substrate 1.

[0133] In one possible embodiment, combining Figure 1A and Figure 1H As shown, the orthographic projection of the first common trace 51 on the substrate 1 at least partially overlaps with the orthographic projection of the first via K1 on the substrate 1. In one possible embodiment, the orthographic projection of the first common trace 51 on the substrate 1 may cover the orthographic projection of the first via K1 on the substrate 1.

[0134] In one possible embodiment, combining Figure 1A 、 Figure 1F ,and Figure 1G Figure 1H As shown, the array substrate further includes: a color resist layer 6 located on the side of the layer where the pixel electrodes 40 are located that faces the substrate 1; and the first insulating layer F1 includes the color resist layer 6. In the disclosed embodiment, the array substrate further includes the color resist layer 6. On the one hand, because the color resist layer is thicker, it can increase the distance between the data line 3 and the layer where the pixel electrodes 40 are located, thereby reducing the parasitic capacitance between the data line 3 and the pixel electrodes 40. On the other hand, for curved products, when the color resist layer 6 is provided on the array substrate, the pixel electrodes 40 and the color resist layer 6 move simultaneously when the array substrate is bent, thereby avoiding color mixing problems.

[0135] In one possible embodiment, combining Figure 1A 、 Figure 1F 、 Figure 1G and Figure 1H As shown, the layer where the data line 3 is located can be located on the side of the layer where the gate line 20 is located away from the substrate 1, the layer where the pixel electrode 40 is located can be located on the side of the layer where the data line 3 is located away from the layer where the gate line 20 is located, and the active pattern 8 can be located between the layer where the data line 3 is located and the layer where the gate line 20 is located ( Figure 1A 、 Figure 1F 、 Figure 1G and Figure 1H (not shown in the figure), a gate insulating layer 11 may be provided between the layer where the gate line 20 is located and the layer where the active pattern 8 is located, a passivation layer 12 may be provided between the layer where the data line 3 is located and the layer where the pixel electrode 4 is located, and a flat layer 13 may be provided between the passivation layer 12 and the layer where the pixel electrode 40 is located.

[0136] In one possible embodiment, combining Figure 1A 、 Figure 1F 、 Figure 1G and Figure 1HAs shown, the first insulating layer F1 may further include a passivation layer 12 located on the side of the color resist layer 6 facing the substrate 1 , and a planarization layer 13 located on the side of the color resist layer facing away from the substrate 1 .

[0137] In one possible implementation, the planarization layer 13 may be an organic film layer; in one possible implementation, the passivation layer 12 may be a PVX layer, for example, including a silicon nitride material layer.

[0138] In one possible embodiment, combining Figure 1A 、 Figure 1H and Figure 1K As shown, the first via K1 can be a sleeve hole design, and the first via K1 can include a flat layer via K11 located in the flat layer 13, a color resist layer via K12 located in the color resist layer 6, and a passivation layer via K13 located in the passivation layer 12, wherein the orthographic projection of the flat layer via K11 on the substrate 1 can coincide with the orthographic projection of the passivation layer via K13 on the substrate 1; the orthographic projection of the color resist layer via K12 on the substrate 1 can cover the orthographic projection of the flat layer via K11 on the substrate 1; the orthographic projection area of ​​the color resist layer via K12 on the substrate 1 can be larger than the orthographic projection area of ​​the flat layer via K11 on the substrate 1.

[0139] In one possible embodiment, combining Figure 1A 、 Figure 1H 、 Figure 1J and Figure 1K As shown, the orthographic projection of the black matrix 91 on the substrate 1 can cover the orthographic projection of the first via K1 on the substrate 1; the orthographic projection of the black matrix 91 on the substrate 1 can cover the orthographic projection of the darkened via K2 on the substrate 1; in this way, the first via K1 that conducts the pixel electrode 40 and the transistor T, and the darkened via K2 are both arranged in the area covered by the black matrix 91, which can avoid the need to set up separate light-shielding layers for the first via K1 and the darkened via K2, thereby improving the aperture ratio of the display panel.

[0140] In one possible embodiment, combining Figure 1A 、 Figure 1F 、 Figure 1G 、 Figure 1H 、 Figure 1K 、 Figure 2A and Figure 2BAs shown, the color resist layer 6 may include: a plurality of color resist strips 60 extending along the second direction, and the plurality of color resist strips 60 may include: a first color resist 61, a second color resist 62, and a third color resist 63; the first color resist 61 may extend along the second direction Y, and its orthographic projection on the substrate 1 may cover the orthographic projection of a column of pixel electrodes 40 on the substrate 1; the second color resist 62 may extend along the second direction Y, and its orthographic projection on the substrate 1 may cover the orthographic projection of a column of pixel electrodes 40 on the substrate 1; the third color resist 63 may extend along the second direction Y, and its orthographic projection on the substrate 1 may cover the orthographic projection of a column of pixel electrodes 40 on the substrate 1; the first color group 61, the second color resist 62, and the third color resist 63 may be alternately arranged along the first direction X.

[0141] In a possible implementation, the first color resist 61 may be a red color resist, the second color resist 62 may be a green color resist, and the third color resist 63 may be a blue color resist.

[0142] In one possible embodiment, combining Figure 1A 、 Figure 1F and Figure 1G As shown, a color block overlap portion 64 may be provided between adjacent first color blocks 61 and second color blocks 62, a color block overlap portion 64 may be provided between adjacent second color blocks 62 and third color groups 63, and a color block overlap portion 64 may be provided between adjacent third color blocks 63 and first color groups 61. In a possible embodiment, in combination with Figure 1A 、 Figure 1F and Figure 1G As shown, at least a portion of the orthographic projection of the color-resist overlapping portion 64 on the substrate 1 may overlap with at least a portion of the orthographic projection of the data line 3 on the substrate 1 .

[0143] In one possible embodiment, combining Figure 2A and Figure 2B As shown, the array substrate further includes: a plurality of first spacers PS1, and a plurality of second spacers PS2; the length of the first spacers PS1 in a direction perpendicular to the substrate 1 is greater than the length of the second spacers PS2 in a direction perpendicular to the substrate 1, that is, the first spacers PS1 can be tall spacers, and the second spacers PS2 can be short spacers; the orthographic projection shape of the first spacers PS1 on the substrate 1 is different from the orthographic projection shape of the second spacers PS2 on the substrate 1. In the disclosed embodiment, the array substrate further includes a plurality of first spacers PS1, and a plurality of second spacers PS2, and the orthographic projection shape of the first spacers PS1 on the substrate 1 is different from the orthographic projection shape of the second spacers PS2 on the substrate 1, that is, the first spacers PS1 and the second spacers PS2 are located on the array substrate, facing each other, and the facing substrate has a higher flatness than the array substrate, thereby avoiding the generation of broken bright spots when tapped; the second spacer PS2 has the largest projected area when it is made into a rectangle, which increases the contact area when pressed and provides a better support effect.

[0144] In one possible embodiment, the first spacer PS1 may be a main spacer; the second spacer PS2 may be an auxiliary spacer. Figure 2A and Figure 2B As shown, the distribution density of the first spacers PS1 may be smaller than that of the second spacers PS2 , that is, in a region with the same area, the number of the first spacers PS1 may be smaller than that of the second spacers PS2 .

[0145] In one possible embodiment, combining Figure 2B As shown, the maximum length h2 of the second spacer PS2 in the second direction Y is greater than the maximum length h1 of the first spacer PS1 in the second direction Y. In a possible embodiment, Figure 2A and Figure 2B As shown, the maximum length h3 of the second spacer PS2 in the first direction X is greater than the maximum length h4 of the first spacer PS1 in the first direction X. In a possible embodiment, Figure 2A and Figure 2B As shown, the orthographic projection area of ​​the second spacer PS2 on the substrate 1 is larger than the orthographic projection area of ​​the first spacer PS1 on the substrate 1 .

[0146] In one possible embodiment, the length h4 of the orthographic projection of the first spacer PS1 on the substrate 1 along the first direction X may be equal to the length h1 along the second direction Y; the length h3 of the orthographic projection of the second spacer PS2 on the substrate 1 along the first direction X may be less than the length h2 along the second direction Y.

[0147] In one possible embodiment, combining Figure 2A and Figure 2B As shown, the orthographic projection of the first spacer PS1 on the substrate 1 may be an octagon, and the orthographic projection of the second spacer PS2 on the substrate 1 may be a rectangle. In a possible embodiment, the orthographic projection of the first spacer PS1 on the substrate 1 may also be a pentagon, a hexagon, or a decagon.

[0148] In one possible embodiment, combining Figure 2A and Figure 2B As shown, the second spacer PS2 may be located in the area where the first color resist 61 and the second color resist 62 are located, and the first spacer PS1 may be located in the area where the third color resist 63 is located.

[0149] In one possible embodiment, combining Figure 2A As shown, 4 columns*8 rows of pixels (each pixel includes three sub-pixels: red, green and blue) are used as a unit, and each unit is provided with two first spacers PS1, wherein one first spacer PS1 (such as Figure 2AIn the figure, the first spacer PS1 on the left is an inspection spacer (which can be used to specifically identify the pixel position. For example, when the first spacer PS1 is found, it can be determined that the position of the green sub-pixel is on its left). In order to facilitate production line inspection, the green sub-pixel next to the first spacer PS1 can be omitted from the second spacer PS2.

[0150] In one possible embodiment, combining Figure 2A As shown, in a unit of 4 columns * 8 rows of pixels (each pixel includes three sub-pixels: red, green, and blue), in a column of first color resist 61, a second spacer PS2 can be configured at a position corresponding to each red sub-pixel, and in a column of second color resist 61, a second spacer PS2 can be configured at a position corresponding to each green sub-pixel; in a column of third color resist 63, a first spacer PS1 can be configured only at the position of one of the blue sub-pixels.

[0151] In one possible embodiment, at least a portion of the orthographic projection of the first spacer PS1 on the substrate 1 may not overlap with at least a portion of the orthographic projection of the transistor T on the substrate 1, and at least a portion of the orthographic projection of the second spacer PS2 on the substrate 1 may not overlap with at least a portion of the orthographic projection of the transistor T on the substrate 1. In this way, it is avoided that when the first spacer PS1 and the second spacer PS2 are set in the area where the transistor T is located, the performance of the transistor T may be affected.

[0152] In one possible embodiment, combining Figure 2A and Figure 2B As shown, the color filter strips 60 may include a third axis e3 extending along the second direction Y; in at least some adjacent color filter strips 60, the second spacers PS2 are located on different sides of the third axis e3 at the center of the orthographic projection of the substrate 1, for example, Figure 2A In the second row of color-stop strips 60 from the right, the center of the second spacer PS2's orthographic projection onto the substrate 1 is located to the left of the third axis e3. In the third row of color-stop strips 60 from the right, the center of the second spacer PS2's orthographic projection onto the substrate 1 is located to the right of the third axis e3. This adapts the position of the transistor T and avoids the potential impact on transistor T's performance when the first and second spacers PS1 and PS2 are placed in the area where the transistor T is located.

[0153] In one possible embodiment, combining Figure 2A and Figure 2B As shown, the color-resistance strip 60 may include a third axis e3 extending along the second direction Y; in at least some adjacent color-resistance strips 60, the center of the color-resistance layer via K12 in the orthographic projection of the substrate 1 is located on different sides of the third axis e3, for example, Figure 2AIn the second column of color-block strips 60 from the right, the color-block layer via K12 is located on the right side of the third axis e3 at the center of the orthographic projection of the substrate 1, while in the third column of color-block strips 60 from the right, the color-block layer via K12 is located on the left side of the third axis e3 at the center of the orthographic projection of the substrate 1.

[0154] In one possible embodiment, combining Figure 2A and Figure 2B As shown, a portion of the outer edge of the orthographic projection of the second spacer PS2 on the substrate 1 coincides with a portion of the outer edge of the orthographic projection of the color-resist layer via K12 on the substrate 1 .

[0155] In one possible embodiment, at least a portion of the orthographic projection of the first spacer PS1 on the substrate 1 overlaps with at least a portion of the orthographic projection of the first common routing line 51 on the substrate 1; at least a portion of the orthographic projection of the second spacer PS2 on the substrate 1 overlaps with at least a portion of the orthographic projection of the first common routing line 51 on the substrate 1.

[0156] In one possible embodiment, at least part of the orthographic projection of the black matrix 91 on the substrate 1 overlaps with at least part of the orthographic projection of the first spacer PS1 on the substrate 1, and at least part of the orthographic projection of the black matrix 91 on the substrate 1 overlaps with at least part of the orthographic projection of the second spacer PS2 on the substrate 1; in one possible embodiment, the orthographic projection of the black matrix 91 on the substrate 1 covers the orthographic projection of the first spacer PS1 on the substrate 1, and the orthographic projection of the black matrix 91 on the substrate 1 covers the orthographic projection of the second spacer PS2 on the substrate 1.

[0157] In one possible embodiment, at least a portion of the orthographic projection of the first spacer PS1 on the substrate 1 overlaps with at least a portion of the orthographic projection of the gap between adjacent pixel electrode rows on the substrate 1; at least a portion of the orthographic projection of the second spacer PS2 on the substrate 1 overlaps with at least a portion of the orthographic projection of the gap between adjacent pixel electrode rows on the substrate 1; in one possible embodiment, the gap between adjacent pixel electrode rows covers the orthographic projection of the first spacer PS1 on the substrate 1; the orthographic projection of the gap between adjacent pixel electrode rows on the substrate 1 covers the orthographic projection of the second spacer PS2 on the substrate 1.

[0158] In one possible implementation, see Figure 1A and Figure 1BAs shown, the first common routing line 51 includes: a first sub-common routing line portion 511 and a second sub-common routing line portion 512 arranged along the first direction X; at least a portion of the first sub-common routing line portion 511 on the substrate 1 overlaps with at least a portion of the orthographic projection of the data line 3 on the substrate 1; at least a portion of the orthographic projection of the second sub-common routing line portion 512 on the substrate 1 overlaps with at least a portion of the orthographic projection of the pixel electrode lap portion PB on the substrate 1; the maximum length a1 of the first sub-common routing line portion 511 in the second direction Y is less than the maximum length a2 of the second sub-common routing line portion 512 in the second direction Y. In the embodiment of the present disclosure, the maximum length a1 of the first sub-common routing portion 511 in the second direction Y is smaller than the maximum length a2 of the second sub-common routing portion 512 in the second direction Y, that is, the first common routing 51 is narrowed at the intersection with the data line 3 to avoid a large overlapping area between the first common routing 51 and the data line 3, which would cause a large load on the data line 3 and affect the signal transmission of the data line 3; and the first common routing 51 is widened at the overlapping position with the pixel electrode lap portion PB so that the first common routing 51 has a wider area and can be electrically connected to the pixel electrode 40 through punching.

[0159] In one possible implementation, see Figure 1A and Figure 1B As shown, the first common routing line 51 has a first common gap 513 on the side facing the first gate line 21 and at the position overlapping with the data line 3; the first common routing line 51 has a second common gap 514 on the side facing the second gate line 22 and at the position overlapping with the data line 3; in this way, the first common routing line 51 is narrowed at the position where it intersects with the data line 3.

[0160] In one possible implementation, see Figure 1A and Figure 1B As shown, the center area of ​​the first common gap 513 does not overlap with the center area of ​​the second common gap 514 to avoid the first common trace 51 being too thin at the intersection with the data line 3 and causing the risk of disconnection.

[0161] In one possible implementation, see Figure 1A and Figure 1BAs shown, the first gate line 21 has a first gate line notch 211 on the side facing the first common wiring 51 and at the position intersecting with the data line 3; the second gate line 22 has a second gate line notch 221 on the side facing the first common wiring 51 and at the position intersecting with the data line 3. In this way, the position where the first gate line 21 and the data line 3 intersect can be made narrower, and the position where the second gate line 22 and the data line 3 intersect can be made narrower, thereby avoiding a large overlapping area between the first gate line 21, the second gate line 22 and the data line 3, resulting in a large load generated by the first gate line 21, the second gate line 22, and the data line 3, affecting the signal transmission of the first gate line 21, the second gate line 22, and the data line 3.

[0162] In one possible implementation, see Figure 1A and Figure 1B As shown, the array substrate further includes: a second common signal line group 52 located between adjacent gate line groups 2 and extending along the second direction Y, the second common signal line group including two second common signal lines 520 located on different sides of the data line 3; in a possible embodiment, see Figure 1A and Figure 1B As shown, the orthographic projection of the second common signal line 520 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 40 on the substrate 1. In this way, a first storage capacitor is formed by the second common signal line 520 and the pixel electrode 40.

[0163] In one possible implementation, see Figure 1A and Figure 1B As shown, the array substrate includes: a third common signal line 53 located between adjacent gate line groups 2 and extending along the second direction Y, and at least a portion of the third common signal line 53 on the orthographic projection of the substrate 1 is located between the orthographic projection of the first pixel electrode 41 on the substrate 1 and the orthographic projection of the second pixel electrode 42 on the substrate 1.

[0164] In one possible implementation, see Figure 1A and Figure 1B As shown, the orthographic projection of the third common signal line 53 on the substrate 1 partially overlaps with the orthographic projection of the pixel electrode 40 on the substrate 1. In this way, a second storage capacitor is formed by the third common signal line 53 and the pixel electrode 40.

[0165] In one possible implementation, see Figure 1A and Figure 1B As shown, the array substrate includes: a fourth common signal line 54 located between adjacent gate line groups 2 and extending along the first direction X; the orthographic projection of the fourth common signal line 54 on the substrate 1 passes through the center of the orthographic projection of the pixel electrode 40 on the substrate 1. The fourth common signal line 54 and the orthographic projection of the pixel electrode 40 on the substrate 1 overlap, thereby forming a third storage capacitor through the fourth common signal line 54 and the pixel electrode 40.

[0166] In one possible implementation, see Figure 1A and Figure 1B As shown, the second common signal line 520 and the third common signal line 53 between adjacent gate line groups 2 are electrically connected to the fourth common signal line 54 .

[0167] In a possible embodiment, the array substrate further includes: an overlapping portion on a different layer from the third common signal line 53, and the third common signal lines 53 on both sides of the same gate line group 2 can be electrically connected through the overlapping portion. Specifically, the third common signal line 53 and the overlapping portion can be conductively connected through a half-hanging hole. Specifically, there can be a second insulating layer between the layer where the third common signal line 53 is located and the layer where the overlapping portion is located, and the second insulating layer can have a second via hole, the second via hole partially exposes the third common signal line 53 and partially exposes the substrate, and the overlapping portion is in contact with the third common signal line 53 and partially contacts the substrate 1 at the second via hole, so that the two third common signal lines 53 on both sides of the gate line group 2 are electrically connected through the integrated overlapping portion. In the embodiment of the present disclosure, the third common signal line 53 and the overlapping portion are conductively connected through the half-hanging hole, so that a step structure is formed inside the second via hole, which has a drainage effect on the alignment liquid, prevents the alignment liquid from not sticking, and improves the uniformity of the array substrate of the alignment liquid, avoids the technical effect of the moiré phenomenon on the screen, and improves the display quality.

[0168] In a possible implementation, the second insulating layer may include: at least one or a combination of: a gate insulating layer 11 , a passivation layer 12 , a planarization layer 13 , and a color resist layer 6 .

[0169] In a possible implementation, the overlapping portion may be located in the same layer as the pixel electrode 40 .

[0170] In a possible embodiment, the array substrate may further include in the non-display area: a fifth common routing line surrounding the display area; at least one of the second common signal line 520, the third common signal line 53, and the fourth common signal line 54 is electrically connected to the fifth common routing line; and the first common routing line 51 can specifically be connected to the fifth common routing line.

[0171] In one possible implementation, see Figure 1A and Figure 1B As shown, the width of the third common signal line 53 in the first direction X is greater than the width of the second common signal line 520 in the first direction X.

[0172] Specific, combined Figure 4As shown, the first storage capacitor, the second storage capacitor and the third storage capacitor can form a storage capacitor Ccs, which is used to drive the deflection of the liquid crystal; the second electrode TB of the transistor and the structure electrically connected to the second electrode TB of the transistor (such as the pixel electrode 40, the active pattern 8), and the gate line 20 can form a coupling capacitor Cgs, and Clc can be the capacitance generated by the liquid crystal between the array substrate and the opposite substrate, which is used to drive the deflection of the liquid crystal.

[0173] In one possible implementation, see Figure 1A and Figure 1B As shown, the first common trace 51, the second common trace 52, the third common trace 53, and the fourth common trace 54 are formed in the same layer and material as the gate line 20. In this way, the first common trace 51, the second common trace 52, the third common trace 53, and the fourth common trace 54 can be formed at the same time as the gate line 20 is formed, thereby simplifying the manufacturing process of the array substrate and reducing the manufacturing cost of the array substrate.

[0174] In one possible implementation, see Figure 1A and Figure 1E As shown, the array substrate also includes: a first conductive layer 7 located on the side of the data line 3 facing away from the substrate 1; the first conductive layer 7 includes: a plurality of first traces 71 extending along the second direction Y, and a second trace 72 electrically connected to the first trace 71 and extending along the first direction X; the second trace 72 is disconnected at a position where it intersects with the pixel electrode overlap portion PB; at least a portion of the orthographic projection of the first trace 71 on the substrate 1 overlaps with at least a portion of the orthographic projection of the data line 3 on the substrate 1; at least a portion of the orthographic projection of the second trace 72 on the substrate 1 overlaps with at least a portion of the orthographic projection of the gate line 20 on the substrate 1.

[0175] In the embodiment of the present disclosure, the array substrate further includes: a first conductive layer 7 located on a side of the data line 3 facing away from the substrate 1; the first conductive layer 7 includes: a plurality of first traces 71 extending along the second direction Y, and second traces 72 electrically connected to the first traces 71 and extending along the first direction X; at least a portion of the orthographic projection of the first trace 71 on the substrate 1 overlaps at least a portion of the orthographic projection of the data line 3 on the substrate 1, thereby shielding the electric field on the data line 3 and preventing light leakage, thereby eliminating the need for a black matrix directly above the data line 3 and improving the pixel aperture ratio. Moreover, compared to a conventional black matrix-less structure (DBS) above the data line 3, the embodiment of the present disclosure eliminates the DBS trace above the second terminal TB of the transistor, thereby reducing the load on the data line 3 and improving the product charging rate; at least a portion of the orthographic projection of the second trace 72 on the substrate 1 overlaps at least a portion of the orthographic projection of the gate line 20 on the substrate 1, thereby shielding the signal of the gate line 20 and preventing light leakage at the gate line 20 of the array substrate. The width of the black matrix directly above the gate line 20 can be reduced to a certain extent, thereby improving the pixel aperture ratio.

[0176] In one possible embodiment, combining Figure 1I As shown, the orthographic projection of the gate line 20 on the substrate 1 has an overlapping area with the orthographic projection of the second trace 72 on the substrate 1, and the minimum spacing c1 of the overlapping area in the second direction Y is small (for example, it can be 0.5μm). This small spacing will cause light leakage at this location when the patterns of the two film layers are offset during the process. In one possible embodiment, when forming the patterned black matrix, the width of the black matrix at this location can be increased by an overexposure process, and the spacing c2 between the outer edge of the gate line 2 and the outer edge of the black matrix can be increased. For example, the spacing c2 between the outer edge of the gate line 2 and the outer edge of the black matrix can be greater than or equal to 8.25μm.

[0177] In one possible implementation, see Figure 1A and Figure 1E As shown, the first conductive layer 7 and the pixel electrode 40 are located in the same layer.

[0178] In one possible implementation, see Figure 1A and Figure 1E As shown, at least part of the orthographic projection of the first routing line 71 on the substrate 1 overlaps with at least part of the orthographic projection of the data line 3 on the substrate 1 , that is, the orthographic projection of the first routing line 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1 .

[0179] In one possible implementation, see Figure 1A and Figure 1E As shown, the second routing line 72 includes: a plurality of second routing sub-portions 720 sequentially distributed along the first direction X; the second sub-routing portion 720 is electrically connected to the first routing line 71; the first conductive layer 7 also includes: a third routing line 73 extending along the second direction Y; the third routing line 73 is an orthographic projection of the substrate 1, and is located between the orthographic projections of the two pixel electrodes 40 of the pixel electrode group 4 on the substrate 1; one end of the third routing line 73 is electrically connected to the second routing sub-portion 720 on one side of the pixel electrode 40, and the other end is connected to the second routing sub-portion 720 on the other side of the pixel electrode 40 and connected to the adjacent first routing line 71. Specifically, for example, in combination Figure 1F In the first pixel electrode row, one end of the third routing line 73 is electrically connected to the second routing line sub-portion 720 on the upper side of the third pixel electrode 40 from the left (i.e., the first pixel electrode 41), and the other end is connected to the second routing line sub-portion 720 on the lower side of the second pixel electrode 40 from the left (i.e., the second pixel electrode 42).

[0180] In the embodiment of the present disclosure, the first conductive layer 7 also includes: a third routing line 73 extending along the second direction Y; one end of the third routing line 73 is electrically connected to the second routing sub-portion 720 on one side of the pixel electrode 40, and the other end is connected to the second routing sub-portion 720 on the other side of the pixel electrode 40 and connected to the adjacent first routing line 71, so that the first conductive layer 7 in the entire display area can present a special mesh structure, so that the first conductive layer 7 in the display area has better signal stability.

[0181] In one possible implementation, see Figure 1A and Figure 1E As shown, the width of the portion of the first wiring 71 located between two adjacent pixel electrode bodies PA in the first direction X may be greater than the width of the third wiring 73 in the first direction X; in a possible embodiment, see Figure 1A and Figure 1E As shown, the width of the first line 71 at the intersection with the gate line 2 in the first direction X may be smaller than the width of the first line 71 between two adjacent pixel electrode bodies PA in the first direction X.

[0182] In one possible implementation, see Figure 1A and Figure 1E As shown, the orthographic projection of the third wiring 73 on the substrate 1 does not overlap with the orthographic projection of the pixel electrode bridging portion PB on the substrate 1. This prevents the first conductive layer 7 from being electrically connected to the pixel electrode 40 and affecting the normal display of the pixel electrode 40.

[0183] In one possible implementation, see Figure 1A and Figure 1E As shown, the orthographic projection of the second wiring 72 on the substrate 1 is located in the gap between the gate line 20 and the pixel electrode 40. In this way, the signal of the gate line 20 can be shielded to prevent light leakage from the gate line 20 of the array substrate, and the second wiring 72 can be prevented from being too close to the pixel electrode bridging portion PB, which may cause the second wiring 72 and the pixel electrode bridging portion PB to be electrically connected to each other.

[0184] In one possible implementation, see Figure 3A and Figure 3B As shown, Figure 3B Can be Figure 3A Schematic diagram of a single film layer of a pixel electrode, the array substrate includes: a display area AA, and a non-display area BB located outside the display area; the first conductive layer 7 also includes: a fourth trace 74 located in the non-display area BB and extending along the first direction X, the fourth trace 74 having a plurality of first hollows L1.

[0185] In this public embodiment, under the premise of ensuring that the fourth line 74 is not disconnected, a plurality of first hollows L1 are set on the outer periphery of the fourth line 74 on the side without the floating (Dummy) pixel electrode, and the area where the photoresist (PR) is accumulated is moved outward from the display area AA to ensure the problem of abnormal display caused by short circuits between connections between different patterns, that is, to improve the problem that the floating (Dummy) pixel electrode cannot be configured when the space on the opposite side of the display panel on the binding side is tight, and compared with the non-display area BB, the spacing between adjacent pixel electrodes 40 (or, the pixel electrodes and the various lines of the first conductive layer 7) close to the non-display area BB and located in the display area is smaller, and it is easy for photoresist (PR) to accumulate, resulting in short circuits (Short) between patterns, thereby causing display abnormalities.

[0186] In one possible implementation, see Figure 3A and Figure 3B As shown, the first conductive layer 7 further includes a transition portion 75 located on the side of the fourth trace 74 away from the display area. The transition portion 75 has multiple second hollows L2. In the disclosed embodiment, the transition portion 75 also has multiple second hollows L2, which can further move the PR accumulation area away from the display area AA, thereby preventing short circuits and display anomalies caused by connections between different patterns.

[0187] In one possible implementation, see Figure 3A and Figure 3B As shown, the transfer portion 75 can be used as an intermediate electrode when different layers of signal routing are jumpered. For example, it can be an intermediate electrode when the routing of the gate line layer 20 is jumpered with the routing of the data line layer 3.

[0188] In one possible implementation, see Figure 3A and Figure 3B As shown, the maximum length b1 of the first hollow L1 along the second direction Y is greater than the maximum length b2 along the first direction X; the maximum length b3 of the second hollow L2 along the second direction Y is greater than the maximum length b4 along the first direction X. In the disclosed embodiment, the maximum length b1 of the first hollow L1 along the second direction Y is greater than the maximum length b2 along the first direction X; the maximum length b3 of the second hollow L2 along the second direction Y is greater than the maximum length b4 along the first direction X. That is, the major diameter direction of the first hollow L1 and the second hollow L2 is the same as the long direction of the pixel electrode 40. During patterning, this is conducive to the uniform distribution of the photoresist along the long direction of the pixel electrode 40, thereby avoiding the problem of short circuits (shorts) between patterns caused by photoresist (PR) accumulation, thereby avoiding display abnormalities.

[0189] In one possible implementation, see Figure 3A and Figure 3BAs shown, the maximum length b2 of the first hollow L1 in the first direction X is less than or equal to the minimum spacing b5 between the pixel electrode 40 and the first wiring 71 in the first direction X; the maximum length b4 of the second hollow L2 in the first direction X is less than or equal to the minimum spacing b5 between the pixel electrode 40 and the first wiring 71 in the first direction X. In this way, the location of the photoresist accumulation can be shifted from the display area to outside the display area.

[0190] In one possible embodiment, the material of the active pattern 8 may include: amorphous silicon, low-temperature polycrystalline silicon, or metal oxide semiconductors, etc.; wherein the metal oxide semiconductor material may include: any one or more of: amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxide (RE-OS), wherein the rare earth element-doped metal oxide may include lanthanide-doped metal oxide (Ln-OS); the crystalline state of the active layer material may be amorphous, partially crystalline, or polycrystalline; the material of the active pattern 8 is a rare earth element-doped metal oxide, and the active pattern 8 can have stable performance even when exposed to light, and thus no light-shielding layer is required in the light-transmitting area, which can further improve the aperture ratio of the display panel.

[0191] In a possible implementation, the material of the first conductive layer 7 may be the same layer and material as that of the pixel electrode 40 .

[0192] In a possible embodiment, the material of the pixel electrode 40 may include metal oxide (eg, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0193] In a possible embodiment, the material of the first conductive layer 7 may include: metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0194] In one possible embodiment, the material of the data line 3 may include: any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0195] In a possible implementation manner, the first common wiring 51 , the second common wiring 52 , the third common wiring 53 , and the fourth common wiring 54 are made of the same layer and material as the gate line 20 .

[0196] In one possible embodiment, the material of the gate line 20 may include: any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0197] In a possible embodiment, the materials of the first common routing 51, the second common routing 52, the third common routing 53, and the fourth common routing 54 may include: any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0198] In some examples, the substrate 1 may be a flexible substrate or a rigid substrate. For example, the rigid substrate may include a glass substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The material of the semiconductor layer may be amorphous silicon (a-Si). However, the embodiments of the present disclosure are not limited to this.

[0199] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and further includes: an opposite substrate arranged opposite to the array substrate, the opposite substrate being provided with a common electrode layer.

[0200] In a possible embodiment, a liquid crystal layer may be provided between the array substrate and the counter substrate. The liquid crystal layer has multiple liquid crystal regions in the area where the pixel electrode 40 is located. The liquid crystal layers in different liquid crystal regions have different orientations in the initial state. Figure 5As shown, for example, the liquid crystal layer has four liquid crystal regions in the area where the pixel electrode 40 is located. The orthographic projections of the four liquid crystal regions on the substrate 1 can be respectively located in the first region and the second region on one side of the orthographic projection of the fourth common signal line 54 on the substrate 1, and the third region and the fourth region on the other side of the orthographic projection of the fourth common signal line 54 on the substrate 1. Specifically, the array substrate can also have a first alignment film layer 81, and the opposing substrate can be provided with a second alignment film layer 82. The orientations of the first alignment film layer 81 and the second alignment film layer 82 in different areas can be as follows: Figure 5 As shown, the orientation of the first alignment film layer 81 may be perpendicular to the orientation of the second alignment film layer 82 .

[0201] Specifically, the initial state of the liquid crystal layers in different liquid crystal regions can be understood as the deflection state of the liquid crystal layers in different liquid crystal regions when no electric field is applied, that is, the state when no voltage is formed between the pixel electrode 40 and the common electrode layer.

[0202] In one possible embodiment, the common electrode layer of the counter substrate and the first common traces 51, the second common traces 52, the third common traces 53, and the fourth common traces 54 provided on the array substrate transmit the same common signal. Optionally, the first common traces 51, the second common traces 52, the third common traces 53, and the fourth common traces 54 may also carry different signals from the common electrode layer of the counter substrate.

[0203] Figure 10 FIG. 1 is a schematic diagram of the structure of a display panel according to at least one embodiment of the present disclosure. Figure 10 As shown, the display panel may include: a timing controller 20, a data driver 40, a gate driving circuit, and a sub-pixel array 10. The gate driving circuit may include at least one driver, for example, a scan driver 30. The timing controller 20, the data driver 40, and the gate driving circuit may be located in a non-display area outside the display area of ​​the display panel. The sub-pixel array 10 located in the display area may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driver 30 may be configured to provide scan signals to the sub-pixels PX along scan lines; the data driver 40 may be configured to provide data signals to the sub-pixels PX along data lines; and the timing controller 20 may be configured to control the scan driver 30 and the data driver 40.

[0204] In some examples, the timing controller 20 may provide grayscale values ​​and control signals suitable for the specifications of the data driver 40 to the data driver 40. The timing controller 20 may also provide clock signals, initial signals, and other signals suitable for the specifications of the scan driver 30 to the scan driver 30. The data driver 40 may use the grayscale values ​​and control signals received from the timing controller 20 to generate data voltages to be supplied to the data lines D1 to Dn. For example, the data driver 40 may use the clock signal to sample the grayscale values ​​and apply data signals corresponding to the grayscale values ​​to the data lines D1 to Dn on a sub-pixel row basis. The scan driver 30 may use the clock signal, initial signals, and other signals received from the timing controller 20 to generate scan signals to be supplied to the scan lines G1 to Gm. For example, the scan driver 30 may sequentially supply scan signals having on-level pulses to the scan lines. In some examples, the scan driver 30 may include a shift register that sequentially transmits scan initial signals provided in the form of on-level pulses to the next stage of circuitry under the control of the clock signal to generate the scan signals. Where n and m are both natural numbers.

[0205] In some examples, the gate driver circuit can be directly provided on the substrate. For example, the gate driver can be provided in the peripheral areas on the left and right sides of the display area. In some examples, the gate driver can be formed together with the sub-pixel in the process of forming the sub-pixel. However, this embodiment does not limit the location or formation method of the gate driver. In some examples, the gate driver can be provided on a separate chip or printed circuit board to connect to the pads or pads formed on the substrate.

[0206] In some examples, the data driver 40 can be provided on a separate chip or printed circuit board, and connected to the sub-pixels PX via signal access pins provided on the substrate. For example, the data driver 40 can be provided using a chip on glass, a chip on plastic, a chip on film, etc., and connected to the signal access pins on the substrate. The timing controller 20 can be provided separately from the data driver 40 or integrated with the data driver 40. However, this embodiment is not limited to this.

[0207] Based on the same inventive concept, the present disclosure also provides a display device, which includes the display panel provided in the present disclosure. The implementation of the display device can refer to the above-mentioned display panel embodiment, and the repeated parts are not repeated here.

[0208] In one possible implementation, the display panel provided by the embodiment of the present disclosure may be a curved display panel. In one possible implementation, the display device provided by the embodiment of the present disclosure may be a curved display device.

[0209] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0210] Based on the same inventive concept, the present disclosure also provides a method for repairing an array substrate as provided in the present disclosure, see Figure 9 As shown, including:

[0211] Step S100: testing the array substrate;

[0212] Step S200: When it is determined that the pixel emits light abnormally, the transistor electrically connected to the pixel electrode in the pixel is electrically connected to the first common wiring.

[0213] In a possible implementation, regarding step S200, electrically connecting the transistor in the pixel electrically connected to the pixel electrode to the second common wiring includes:

[0214] At the location of the first via hole, the second electrode of the transistor is electrically connected to the first common wiring.

[0215] In the embodiment of the present disclosure, the part of the orthographic projection of the second electrode TB of the transistor on the substrate 1 is located between the orthographic projections of the two gate lines 20 of the same gate line group 2 on the substrate 1, and the orthographic projection of the first common wiring 51 on the substrate 1 is located between the orthographic projections of the two gate lines 20 of the same gate line group 2 on the substrate 1, and at least part of the orthographic projection of the first common wiring 51 on the substrate 1 overlaps with at least part of the orthographic projection of the second electrode TB of the transistor on the substrate 1, and then when the darkening process is performed, the second electrode TB of the transistor can be connected to the first common wiring 51, and the conductive via can be located between the orthographic projections of the two gate lines 20 on the substrate 1. Since a light-shielding layer (such as a black matrix) is usually provided between the two gate lines 20 and the area between the two gate lines 20, the darkening via can be hidden in the area where the light-shielding layer is located, thereby solving the dual The transmittance loss caused by the low aperture ratio of the gate pixel and the contrast reduction caused by the metal reflection in the opening area; moreover, compared with the conventional array substrate that sets common wiring on both sides of the gate line group 2, the embodiment of the present disclosure can also reduce one common wiring, reduce the width of the light-shielding layer (such as the black matrix), and the aperture ratio improvement effect is more obvious. In addition, compared with the conventional array substrate, the via holes usually have the alignment liquid not sticking, resulting in display abnormalities, thereby affecting the quality and yield. In the embodiment of the present disclosure, the first via K1 is located in the area where the light-shielding layer (such as the black matrix) is located, and the display abnormality area is effectively blocked by the light-shielding layer (such as the black matrix), which can increase the edge (Margin) width of the alignment liquid coating process and reduce the difficulty of the process.

[0216] It should be noted that in this disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0217] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0218] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate line groups are located on one side of the substrate and extend along a first direction, wherein the gate line group includes: two gate lines extending along the first direction; a plurality of data lines extending along a second direction, wherein the second direction intersects the first direction; a plurality of transistors, each transistor comprising: a first transistor electrode electrically connected to the data line, and a second transistor electrode; the second transistor electrode being located at a portion of an orthographic projection of the substrate and between two gate lines of the same gate line group and an orthographic projection of the substrate; a plurality of pixel electrode groups, wherein at least a portion of the pixel electrode groups, as an orthographic projection of the substrate, is located at an area formed by the intersection of the gate line group and the data line; the pixel electrode group comprises: two pixel electrodes distributed along the first direction; A plurality of first common routing lines, wherein the orthographic projections of the first common routing lines on the substrate are located between the orthographic projections of two gate lines of the same gate line group on the substrate, and at least a portion of the orthographic projection of the first common routing lines on the substrate overlaps with at least a portion of the orthographic projection of the second electrode of the transistor on the substrate.

2. The array substrate according to claim 1, wherein: The pixel electrode comprises: a pixel electrode body, and a pixel electrode overlap portion extending from one end of the pixel electrode body; the pixel electrode overlap portion is located between the orthographic projections of two gate lines of the same gate line group on the substrate; The pixel electrode overlapping portion overlaps at least a portion of the orthographic projection of the substrate with the second electrode of the transistor.

3. The array substrate according to claim 1 or 2, wherein: The pixel electrode overlapping portion includes: a first sub-overlapping portion extending along the second direction, and a second sub-overlapping portion extending along the first direction; one end of the first sub-overlapping portion is electrically connected to the pixel electrode body, and the other end is electrically connected to the second sub-overlapping portion; The orthographic projection of the second sub-overlapping portion on the substrate is located between the orthographic projections of two gate lines of the same gate line group on the substrate.

4. The array substrate according to claim 3, wherein: The two pixel electrodes in the same pixel electrode group are electrically connected to the same data line through the transistor; In the same pixel electrode group, the second sub-bridge portions of the two pixel electrodes both extend from the first sub-bridge portion toward the electrically connected data line.

5. The array substrate according to claim 4, wherein: The two second sub-bridging portions of the two pixel electrodes adjacent to each other in the second direction extend from the first sub-bridging portion in opposite directions.

6. The array substrate according to any one of claims 3 to 5, wherein: The array substrate comprises: a first axis extending along the second direction between adjacent pixel electrodes; In the first direction, at least parts of at least two adjacent second overlapping sub-portions are symmetrical about the first axis.

7. The array substrate according to claim 6, wherein: The plurality of transistors include: a first transistor and a second transistor; in the same pixel electrode group, one pixel electrode is electrically connected to the data line via the first transistor, and another pixel electrode is electrically connected to the data line via the second transistor; The array substrate includes: a second axis passing through the center of the pixel electrode and extending along the first direction; the first transistor and the second transistor electrically connected to the same pixel electrode group, the second pole of the first transistor and the second pole of the second transistor being symmetrical about the second axis.

8. The array substrate according to claim 7, wherein: In the first transistor and the second transistor electrically connected to the same pixel electrode group, the second electrode of the first transistor and the second electrode of the second transistor are both located between the first axis and the electrically connected data line.

9. The array substrate according to claim 7 or 8, wherein: In the second direction, at least partially adjacent second electrodes of two transistors are symmetrical about the second axis.

10. The array substrate according to any one of claims 7 to 9, wherein: The second electrode of the transistor includes: a second electrode first portion extending along the second direction, and a second electrode second portion connected to the second electrode first portion and extending along the first direction; In the second direction, the second electrode first portions of at least two adjacent second electrodes of the transistors extend from the second electrode second portions toward the side of the pixel electrode body to which they are electrically connected.

11. The array substrate according to claim 10, wherein: In the first direction, the second electrode first portions of at least some adjacent two transistor second electrodes extend in opposite directions from the second electrode second portions.

12. The array substrate according to claim 10 or 11, wherein: In the first direction, the second portions of the second electrodes of at least some adjacent two transistors are symmetrical about the first axis.

13. The array substrate according to any one of claims 10 to 12, wherein: The transistor further includes an active pattern; the active pattern includes a first active outer edge extending along the second direction, and a second active outer edge; in the same transistor, an orthographic projection of the second active outer edge on the substrate is located on a side of the first active outer edge away from the data line connected to the transistor; The first electrode of the transistor includes: a first electrode first portion extending along the second direction, and a first electrode second portion connecting the first electrode first portion and the data line; At least part of the orthographic projection of the first active outer edge on the substrate overlaps with at least part of the orthographic projection of the outer edge of the first pole first portion on the side away from the second pole first portion on the substrate; at least part of the orthographic projection of the second active outer edge on the substrate overlaps with at least part of the orthographic projection of the second pole first portion on the side away from the first pole first portion on the substrate.

14. The array substrate according to any one of claims 2 to 13, wherein: The array substrate further includes: a first insulating layer located between the layer where the pixel electrode group is located and the layer where the second electrode of the transistor is located; The first insulating layer includes a first via hole, and the pixel electrode overlapping portion is electrically connected to the second electrode of the transistor through the first via hole.

15. The array substrate according to claim 14, wherein: The first common trace overlaps at least a portion of the orthographic projection of the substrate with the first via hole.

16. The array substrate according to claim 14 or 15, wherein: The array substrate further comprises: a color resist layer located on a side of the layer where the pixel electrodes are located facing the substrate; The first insulating layer includes the color resist layer.

17. The array substrate according to claim 16, wherein: The array substrate further includes: a plurality of first spacers and a plurality of second spacers; the length of the first spacers in a direction perpendicular to the substrate is greater than the length of the second spacers in a direction perpendicular to the substrate; The orthographic projection shape of the first spacer on the substrate is different from the orthographic projection shape of the second spacer on the substrate.

18. The array substrate according to claim 17, wherein: The maximum length of the second spacer in the second direction is greater than the maximum length of the first spacer in the second direction.

19. The array substrate according to claim 17 or 18, wherein: The distribution density of the second spacers is greater than the distribution density of the first spacers.

20. The array substrate according to any one of claims 2 to 19, wherein: The first common routing line includes: a first sub-common routing line portion and a second sub-common routing line portion arranged along the first direction; the first sub-common routing line portion overlaps at least partially with an orthographic projection of the data line on the substrate in at least a portion of the substrate; and the second sub-common routing line overlaps at least partially with an orthographic projection of the pixel electrode overlapping portion on the substrate in at least a portion of the substrate; A maximum length of the first sub-common routing portion in the second direction is smaller than a maximum length of the second sub-common routing portion in the second direction.

21. The array substrate according to any one of claims 2 to 20, wherein: The array substrate further comprises: a first conductive layer located on a side of the data line facing away from the substrate; The first conductive layer includes: a plurality of first wirings extending along the second direction, and second wirings electrically connected to the first wirings and extending along the first direction; the second wirings are disconnected at positions intersecting with the pixel electrode overlapping portions; At least part of the orthographic projection of the first routing line on the substrate overlaps with at least part of the orthographic projection of the data line on the substrate; at least part of the orthographic projection of the second routing line on the substrate overlaps with at least part of the orthographic projection of the gate line on the substrate.

22. The array substrate according to claim 21, wherein: The second routing line includes: a plurality of second routing sub-portions sequentially distributed along the first direction; the second routing sub-portions are electrically connected to the first routing line; the first conductive layer further includes: a third routing line extending along the second direction; The orthographic projection of the third routing line on the substrate is located between the orthographic projections of the two pixel electrodes of the pixel electrode group on the substrate; one end of the third routing line is electrically connected to the second routing sub-portion on one side of the pixel electrode, and the other end is connected to the second routing sub-portion on the other side of the pixel electrode and connected to the adjacent first routing line.

23. The array substrate according to claim 22, wherein: The orthographic projection of the third wiring on the substrate does not overlap with the orthographic projection of the pixel electrode overlapping portion on the substrate.

24. The array substrate according to any one of claims 21 to 23, wherein: The second wiring is located in the gap between the gate line and the pixel electrode on the orthographic projection portion of the substrate.

25. The array substrate according to any one of claims 21 to 24, wherein: The array substrate includes a display area and a non-display area located outside the display area. The first conductive layer further includes a fourth wiring located in the non-display area and extending along the first direction. The fourth wiring has a plurality of first hollows.

26. The array substrate according to claim 25, wherein: The first conductive layer further includes a transfer portion located on a side of the fourth wiring away from the display area, and the transfer portion has a plurality of second hollows.

27. The array substrate according to claim 26, wherein: The maximum length of the first hollow along the second direction is greater than the maximum length along the first direction; the maximum length of the second hollow along the second direction is greater than the maximum length along the first direction.

28. The array substrate according to any one of claims 26 to 27, wherein: The maximum length of the first hollow in the first direction is less than or equal to the minimum distance between the pixel electrode and the first wiring in the first direction; A maximum length of the second hollow in the first direction is less than or equal to a minimum distance between the pixel electrode and the first wiring in the first direction.

29. The array substrate according to claim 21, wherein: The first conductive layer is in the same layer as the pixel electrode.

30. A display panel, wherein: The array substrate comprises the array substrate according to any one of claims 1 to 29, further comprising: an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

31. A display device, wherein: Comprising the display panel as claimed in claim 30.

32. A method for repairing an array substrate according to any one of claims 1 to 29, wherein: include: testing the array substrate; When it is determined that the pixel emits light abnormally, the transistor electrically connected to the pixel electrode in the pixel is electrically connected to the first common wiring.

33. The repair method according to claim 32, wherein: The array substrate further includes: a first insulating layer located between the layer where the pixel electrode group is located and the layer where the second electrode of the transistor is located; the first insulating layer includes: a first via hole; The step of electrically connecting the transistor in the pixel electrically connected to the pixel electrode to the first common wiring includes: At the location of the first via hole, the second electrode of the transistor is electrically connected to the first common wiring.

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