Memory, storage system, and operating method of memory

Abstract

Embodiments of the present application disclose a memory, a storage system and an operating method of the memory, and belong to the technical field of storage. In the method, before ISPP programming is performed on the memory cells in the selected memory cell row, a first pre-programming pulse is provided to the selected word line to pre-program the first type of memory cells in the selected memory cell row. On the one hand, since the first type of memory cells are programmed to be close to the first target programming state first, the programming speed is prevented from being too fast during subsequent ISPP programming, and thus the +3σ tail of the threshold voltage distribution is improved. On the other hand, since the first type of memory cells are programmed to be close to the first target programming state first, and then ISPP programming is performed, the IVS is much less, and thus the -3σ tail of the threshold voltage distribution is improved. By improving the +3σ tail and the -3σ tail of the threshold voltage distribution, the range of the threshold voltage distribution is reduced, and thus the effect of increasing the read window is achieved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a storage system, and a method for operating the memory. Background Technology

[0002] When programming (i.e. writing data) memory cells in 3D NAND (NAND gate) and other memories, in order to improve the accuracy of subsequent data reading, the threshold voltage distribution range of each memory cell that reaches the same target programming state is usually minimized. This increases the distance between the threshold voltage distribution ranges of two adjacent target programming states, that is, increases the read window. Summary of the Invention

[0003] This application provides a memory, a memory system, and a method for operating the memory, which can increase the read window. The technical solution is as follows:

[0004] In a first aspect, a memory is provided, the memory comprising:

[0005] A storage array comprising multiple rows of storage cells;

[0006] Multiple word lines, each word line being coupled to one of the multiple rows of memory cells; and

[0007] Peripheral circuitry, coupled to the plurality of word lines and configured to:

[0008] A first preprogramming pulse is provided to a selected word line to preprogram a first type of memory cell in a selected memory cell row. The target programming state of the first type of memory cell is a first target programming state. After the first preprogramming pulse is provided, the threshold voltage of the first type of memory cell is less than the first target threshold voltage. The first target threshold voltage is the threshold voltage corresponding to the first target programming state.

[0009] The programming pulse is delivered to the selected word line using the step programming pulse (ISPP) method to program the memory cells of the selected memory cell row.

[0010] Optionally, the peripheral circuit is further configured as follows:

[0011] A second preprogramming pulse is provided to the selected word line to preprogram the second type of memory cells in the selected memory cell row;

[0012] Wherein, the target programming state of the second type of memory cell is the second target programming state, and after the second preprogramming pulse is provided, the threshold voltage of the second type of memory cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

[0013] Optionally, the distance between the state of the first type of memory cell before the first preprogramming pulse and the first target programming state is provided to be greater than the distance between the state of at least one other memory cell in the selected memory cell row and their respective target programming states.

[0014] Optionally, the difference between the voltage of the first preprogramming pulse and the first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on the programming voltage required to reach the first target programming state of the first type of memory cell.

[0015] Optionally, the peripheral circuit is further configured as follows:

[0016] The first preprogrammed pulse is determined based on the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage.

[0017] Optionally, the peripheral circuit is configured as follows:

[0018] If the difference between the current threshold voltage and the first target threshold voltage of at least one of the first type of memory cells exceeds the second difference threshold, then the first preprogrammed pulse is configured for the first type of memory cell.

[0019] Optionally, the peripheral circuit is configured as follows:

[0020] In response to a programming instruction from the controller, a first preprogramming pulse is provided to the selected word line to preprogram the first type of memory cell in the selected memory cell row.

[0021] Optionally, the storage cells in the memory are three-level cell (TLC).

[0022] Optionally, the peripheral circuit is configured as follows:

[0023] In response to a programming instruction from the controller, a programming pulse is provided to the selected word line using the ISPP method to perform the first programming of the memory cells in the selected memory cell row;

[0024] Provide the first preprogramming pulse to the selected word line to preprogram the first type of memory cells in the selected memory cell row;

[0025] The ISPP method is used to provide programming pulses to the selected word line to perform a second programming of the memory cells in the selected memory cell row;

[0026] The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

[0027] Optionally, the storage cells in the memory are four-level cells (QLC).

[0028] In a second aspect, a storage system is provided, the storage system including a memory and a controller coupled to the memory and configured to control the memory;

[0029] The memory is configured as follows:

[0030] A first preprogramming pulse is provided to a selected word line to preprogram a first type of memory cell in a selected memory cell row. The target programming state of the first type of memory cell is a first target programming state. After the first preprogramming pulse is provided, the threshold voltage of the first type of memory cell is less than the first target threshold voltage. The first target threshold voltage is the threshold voltage corresponding to the first target programming state.

[0031] The programming pulse is delivered to the selected word line using the step programming pulse (ISPP) method to program the memory cells of the selected memory cell row.

[0032] Optionally, the controller is configured to send programming instructions to the memory;

[0033] The memory is configured to: in response to a programming instruction from the controller, provide a first preprogramming pulse to the selected word line to preprogram the first type of memory cells in the selected memory cell row.

[0034] Optionally, the controller is configured to send programming instructions to the memory;

[0035] The memory is also configured to:

[0036] In response to a programming instruction from the controller, a programming pulse is provided to the selected word line using the ISPP method to perform the first programming of the memory cells in the selected memory cell row;

[0037] Provide the first preprogramming pulse to the selected word line to preprogram the first type of memory cells in the selected memory cell row;

[0038] The ISPP method is used to provide programming pulses to the selected word line to perform a second programming of the memory cells in the selected memory cell row;

[0039] The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

[0040] Optionally, the memory is further configured to:

[0041] A second preprogramming pulse is provided to the selected word line to preprogram the second type of memory cells in the selected memory cell row;

[0042] Wherein, the target programming state of the second type of memory cell is the second target programming state, and after the second preprogramming pulse is provided, the threshold voltage of the second type of memory cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

[0043] Optionally, the distance between the state of the first type of memory cell before the first preprogramming pulse and the first target programming state is provided to be greater than the distance between the state of at least one other memory cell in the selected memory cell row and their respective target programming states.

[0044] Optionally, the difference between the voltage of the first preprogramming pulse and the first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on the programming voltage required to reach the first target programming state of the first type of memory cell.

[0045] Optionally, the memory is further configured to:

[0046] The first preprogrammed pulse is determined based on the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage.

[0047] Optionally, the memory is configured as follows:

[0048] If the difference between the current threshold voltage and the first target threshold voltage of at least one of the first type of memory cells exceeds the second difference threshold, then the first preprogrammed pulse is configured for the first type of memory cell.

[0049] Optionally, the memory is configured as follows:

[0050] In response to a programming instruction from the controller, a first preprogramming pulse is provided to the selected word line to preprogram the first type of memory cell in the selected memory cell row.

[0051] Optionally, the storage cells in the memory are three-level cell (TLC).

[0052] Optionally, the memory is configured as follows:

[0053] In response to a programming instruction from the controller, a programming pulse is provided to the selected word line using the ISPP method to perform the first programming of the memory cells in the selected memory cell row;

[0054] Provide the first preprogramming pulse to the selected word line to preprogram the first type of memory cells in the selected memory cell row;

[0055] The ISPP method is used to provide programming pulses to the selected word line to perform a second programming of the memory cells in the selected memory cell row;

[0056] The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

[0057] Optionally, the storage cells in the memory are four-level cells (QLC).

[0058] Thirdly, a method for operating a memory is provided, the method comprising:

[0059] A first preprogramming pulse is provided to a selected word line to preprogram a first type of memory cell in a selected memory cell row. The target programming state of the first type of memory cell is a first target programming state. After the first preprogramming pulse is provided, the threshold voltage of the first type of memory cell is less than the first target threshold voltage. The first target threshold voltage is the threshold voltage corresponding to the first target programming state.

[0060] The programming pulse is delivered to the selected word line using the step programming pulse (ISPP) method to program the memory cells of the selected memory cell row.

[0061] Optionally, before providing programming pulses to the selected word line using the step programming (ISPP) method to program the memory cells of the selected memory cell row, the method further includes:

[0062] A second preprogramming pulse is provided to the selected word line to preprogram the second type of memory cells in the selected memory cell row;

[0063] Wherein, the target programming state of the second type of memory cell is the second target programming state, and after the second preprogramming pulse is provided, the threshold voltage of the second type of memory cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

[0064] Optionally, the distance between the state of the first type of memory cell before the first preprogramming pulse and the first target programming state is provided to be greater than the distance between the state of at least one other memory cell in the selected memory cell row and their respective target programming states.

[0065] Optionally, the difference between the voltage of the first preprogramming pulse and the first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on the programming voltage required to reach the first target programming state of the first type of memory cell.

[0066] Optionally, before providing the first preprogrammed pulse to the selected word line, the method further includes:

[0067] The first preprogrammed pulse is determined based on the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage.

[0068] Optionally, determining the first preprogrammed pulse based on the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage includes:

[0069] If the difference between the current threshold voltage and the first target threshold voltage of at least one of the first type of memory cells exceeds the second difference threshold, then the first preprogrammed pulse is configured for the first type of memory cell.

[0070] Optionally, providing a first preprogramming pulse to a selected word line to preprogram the first type of memory cells in the selected memory cell row includes:

[0071] In response to a programming instruction from the controller, a first preprogramming pulse is provided to the selected word line to preprogram the first type of memory cell in the selected memory cell row.

[0072] Optionally, the storage cells in the memory are three-level cell (TLC).

[0073] Optionally, before providing a first preprogramming pulse to a selected word line to preprogram the first type of memory cells in the selected memory cell row, the method further includes:

[0074] In response to a programming instruction from the controller, a programming pulse is provided to the selected word line using the ISPP method to perform the first programming of the memory cells in the selected memory cell row;

[0075] The step-programming (ISPP) method of providing programming pulses to the selected word line to program the selected memory cell row includes:

[0076] The ISPP method is used to provide programming pulses to the selected word line to perform a second programming of the memory cells in the selected memory cell row;

[0077] The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

[0078] Optionally, the storage cells in the memory are four-level cells (QLC).

[0079] On the one hand, by programming the first type of memory cell to the vicinity of the first target programming state first, subsequent ISPP programming can gradually bring the first type of memory cell to the first target programming state, avoiding excessively fast programming speeds. This improves the +3σ tail of the threshold voltage distribution. On the other hand, by programming the first type of memory cell to the vicinity of the first target programming state first, subsequent ISPP programming requires only a small number of electrons to program the first memory cell to the first target programming state, resulting in significantly fewer IVS (Inverting Vibration Sequences). This further improves the -3σ tail of the threshold voltage distribution. By improving both the +3σ and -3σ tails of the threshold voltage distribution, the range of the threshold voltage distribution can be reduced, thereby increasing the read window. Attached Figure Description

[0080] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0081] Figure 1 This is a schematic diagram of a storage system 10 provided in an embodiment of this application;

[0082] Figure 2 This is a schematic diagram of a storage device provided in an embodiment of this application;

[0083] Figure 3 This is a schematic diagram of another storage device provided in an embodiment of this application;

[0084] Figure 4 This is a schematic diagram of a memory 100 provided in an embodiment of this application;

[0085] Figure 5 This is a cross-sectional schematic diagram of a storage array 110 including storage strings 111 provided in an embodiment of this application;

[0086] Figure 6 This is a schematic diagram of a peripheral circuit provided in an embodiment of this application;

[0087] Figure 7 This is a schematic diagram of the threshold voltage distribution of a TLC provided in an embodiment of this application;

[0088] Figure 8 This is a flowchart of an operation method for a memory provided in an embodiment of this application;

[0089] Figure 9 This is a schematic diagram of a programming flow using the ISPP method provided in an embodiment of this application;

[0090] Figure 10 This application provides a programming voltage (V) during the programming process. PGM A schematic diagram showing the correspondence between the threshold voltage (Vt) of the memory cell and the threshold voltage of the memory cell;

[0091] Figure 11 This is a schematic diagram of a -3σ tail for improving threshold voltage distribution provided in an embodiment of this application;

[0092] Figure 12 This is a schematic diagram of pulse comparison provided during the programming process for Scheme 1 and Scheme 2 provided in the embodiments of this application;

[0093] Figure 13 This is a flowchart of another memory operation method provided in an embodiment of this application;

[0094] Figure 14 This is a schematic diagram of the programming state distribution during a TLC programming process provided in an embodiment of this application;

[0095] Figure 15 This is a schematic diagram comparing threshold voltage distribution provided in an embodiment of this application;

[0096] Figure 16 This is a flowchart of another memory operation method provided in an embodiment of this application;

[0097] Figure 17 This is a schematic diagram of the programming state distribution in a QLC programming process provided in an embodiment of this application;

[0098] Figure 18 This is another comparative schematic diagram of threshold voltage distribution provided in the embodiments of this application;

[0099] Figure 19 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Detailed Implementation

[0100] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0101] Figure 1 This is a schematic diagram of a storage system 10 provided in an embodiment of this application. For example... Figure 1 As shown, the storage system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100.

[0102] Controller 200 can be configured to control operations performed by memory 100, such as read, erase, and program operations. Controller 200 can also be configured to manage various functions related to data stored or to be stored in memory 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. Optionally, controller 200 can also be configured to handle error correcting codes (ECCs) for data read from or written to memory 100. Controller 200 can also perform any other suitable functions, such as formatting memory 100.

[0103] The controller 200 can also communicate with external devices according to a specific communication protocol. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. Interface protocols may include Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Development Environment (IDE), FireWire, etc.

[0104] In some embodiments, the controller 200 and one or more memories 100 can be integrated into various types of electronic devices. These electronic devices may be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In such a scenario, such as... Figure 1 As shown, the storage system 10 also includes a host 300. A controller 200 is coupled to the host 300. The controller 200 can manage the data stored in the memory 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0105] In other embodiments, the controller 200, and one or more memories 100, can be integrated into various types of storage devices.

[0106] As an example, such as Figure 2 As shown, the controller 200 and a single memory 100 can be integrated into the memory card 400. The memory card 400 may include PCMCIA (PC) cards, CompactFlash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 400 may also include a connector 410 for coupling the memory card 400 to the host.

[0107] As another example, such as Figure 3 As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 500. The solid-state drive 500 may also include a connector 510 for coupling the solid-state drive 500 to the host. The storage capacity and / or operating speed of the solid-state drive 500 is greater than that of the memory card 400.

[0108] also, Figures 1 to 3 The memory 100 can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be explained below.

[0109] Figure 4 This is a schematic diagram of a memory 100 provided in an embodiment of this application. Figure 4 As shown, the memory 100 includes:

[0110] Storage array 110, which includes multiple rows of storage cells;

[0111] Multiple word lines 120 are coupled to multiple rows of memory cells;

[0112] Peripheral circuitry 130 is coupled to a plurality of word lines 120 and configured to perform operations such as programming (i.e., writing data) or reading data on a selected memory cell line among a plurality of memory cell lines, wherein the selected memory cell line is the memory cell line coupled to the selected word line, wherein, in order to perform operations such as programming or reading data, peripheral circuitry 130 is configured to perform the memory operation method provided in the embodiments of this application.

[0113] Storage array 110 can be a NAND flash memory storage array. For example... Figure 1 As shown, the NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, each memory string 111 extending vertically above the substrate (not shown). In some embodiments, each memory string 111 includes a plurality of memory cells 112 that are coupled in series and stacked vertically.

[0114] like Figure 4 As shown, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called the bottom select gate (BSG) or source selector, and the drain select gate is also called the top select gate (TSG) or drain selector. The source select gate 113 and the drain select gate 114 can be configured to activate the selected memory string 111 during read and program operations.

[0115] In some embodiments, the drain selection gate 114 of each memory string 111 is coupled to a corresponding bit line 115, and data can be read from or written to the bit line 115 via an output bus (not shown).

[0116] In some embodiments, each memory string 111 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0117] like Figure 4 As shown, the storage string 111 can be organized into multiple blocks 140. For any one of the multiple blocks 140, the block 140 can have a source line (SL) 118. The sources of all storage strings 111 in the block 140 are coupled through the source line 118. The source line is also called the common source line or array common source (ACS).

[0118] The source line 118 can be used for grounding, so that the source of each memory cell in the memory string of block 140 can be grounded in some subsequent operations. Optionally, in some other operations, the source of each memory cell in the memory string of block 140 can also be connected to a high voltage through the source line 118.

[0119] Each block 140 is the basic data unit used for the erase operation, meaning that all memory cells 112 on the same block 140 are erased simultaneously. To erase memory cells 112 in a selected block, an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)) can be biased and coupled to the source line of the selected block.

[0120] It should be understood that, in other embodiments, erasure operations may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level with any suitable number of blocks or blocks.

[0121] like Figure 4 As shown, the same layer of storage cells 112 of adjacent storage strings 111 in the same block 140 can be coupled through word lines 120. Word lines 120 are used to select which layer of storage cells 112 in the block 140 is affected by read and program operations.

[0122] In some embodiments, each word line 120 is coupled to a page 150 to which the memory cell 112 belongs, and the page 150 is a basic data unit for programming operations. The size of the page 150 may be related to the number of memory strings 111 coupled by word lines 120 in a block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in the corresponding page 150. It is understood that a memory cell row consists of multiple memory cells 112 located on the same page 150.

[0123] It should be noted that within a block of 140, storage units at the same level correspond to the same word line, but storage units at the same level can be divided into one or more pages. That is, a word line can couple to one or more pages. For example, for SLC, a word line couples to one page, and for MLC, a word line couples to two pages.

[0124] Figure 5 This is a cross-sectional schematic diagram of a storage array 110 including storage strings 111, provided in an embodiment of this application. Figure 5 As shown, the storage string 111 may extend vertically over the substrate 101 and through the stacked layer 102. The substrate 101 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0125] The stacked layer 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the stacked layer 102 can determine the number of memory cells 112 in the memory array 110.

[0126] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. Furthermore, each gate conductive layer 103 may include a control gate surrounding the memory cell 112, and may extend laterally at the top of the stacked layer 102 as a DSG line 116, at the bottom of the stacked layer 102 as an SSG line 117, or between the DSG line 116 and the SSG line 117 as a word line 120.

[0127] like Figure 5As shown, the memory string 111 includes a channel structure 105 extending vertically through the stacked layer 102. In some embodiments, the channel structure 105 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). The semiconductor channel includes silicon, such as polycrystalline silicon. The memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer.

[0128] In some embodiments, the channel structure 105 has a cylindrical shape (e.g., a pillar shape). The layers in the semiconductor channel and the memory film are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order.

[0129] It should be understood that, despite Figure 5 As not shown, the memory array 110 may also include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0130] Return to reference Figure 4 The peripheral circuitry 130 can be coupled to the memory array 110 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116. The peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 110 by applying voltage and / or current signals to and sensing voltage and / or current signals from the memory cells 112 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116.

[0131] Peripheral circuitry 130 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry 130 is shown, including a page buffer / sensor amplifier 131, a column decoder / bit line (BL) driver 132, a row decoder / word line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0132] Page buffer / sensor amplifier 131 can be configured to read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic unit 135. For example, page buffer / sensor amplifier 131 can store a page of programming data (write data) to be programmed into a page 130 of memory array 110. Page buffer / sensor amplifier 131 can also perform a verification operation to ensure that data has been correctly programmed into memory cell 112 coupled to selected word line 120. Page buffer / sensor amplifier 131 can also sense a low-power signal from bit line 115, which represents a data bit stored in memory cell 112, and amplify a small voltage swing to a recognizable logic level during read operations.

[0133] The column decoder / bit line driver 132 can be configured to be controlled by the control logic unit 135 and to select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134.

[0134] The row decoder / word line driver 133 can be configured to be controlled by the control logic unit 135 and to select / deselect block 140 of the memory array 110 and to select / deselect word lines 120 of block 140. The row decoder / word line driver 133 can also be configured to drive word lines 120 using word line voltages (VWL) generated from a voltage generator 134. In some embodiments, the row decoder / word line driver 133 can also select / deselect and drive SSG lines 117 and DSG lines 116. As described in detail below, the row decoder / word line driver 133 is configured to perform erase operations on memory cells 112 coupled to one or more selected word lines 120.

[0135] Voltage generator 134 can be configured to be controlled by control logic unit 135 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 110.

[0136] The control logic unit 135 can be coupled to various circuits in the peripheral circuitry described above and is configured to control the operation of each circuit.

[0137] Register 136 can be coupled to control logic unit 135. The register may include a status register, a command register, and an address register to store status information, command opcodes (OP codes), and command addresses for controlling the operation of each circuit in the peripheral circuit.

[0138] Interface (I / F) 137 can be coupled to control logic unit 135 and act as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 135, as well as to buffer status information received from control logic unit 135 and relay it to the host. Interface 137 can also be coupled to column decoder / bit line driver 132 via data bus 138 and act as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.

[0139] The above description of the memory-related hardware embodiments has similar beneficial effects to the following method embodiments. For technical details not disclosed in the memory-related hardware embodiments, please refer to the description of the method embodiments in this application for understanding.

[0140] In the above Figures 1 to 6 In this context, memory cell 112 can be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor. When the data stored in these types of memory cells is different, the number of electrons trapped in the memory cell will be different, resulting in different threshold voltages for the memory cells. Based on this, the amount of data stored in the memory cell is subsequently determined by determining the threshold voltage of the memory cell. Furthermore, when the data stored in the memory cell is different, the memory cell is in different states; that is, the memory cell corresponds to different states, and different states indicate that the data stored in the memory cell is different.

[0141] In some embodiments, the storage unit 112 can be a single-level cell (SLC). An SLC has two possible states for storing one bit of data, namely 0 and 1. The state corresponding to storing data 1 is called the erase state, and the state corresponding to storing data 0 is called the programmable state.

[0142] In other embodiments, storage unit 112 can be a multi-level cell (MLC). An MLC has four possible states for storing two bits of data: 00, 01, 10, and 11. The state corresponding to storing data 11 is called the erase state, and the states corresponding to storing data 00, 01, and 10 are called the programming states. That is, for an MLC, there is one erase state and three programming states.

[0143] In other embodiments, storage unit 2 can be a Triple-Level Cell (TLC). A TLC has eight possible states for storing three bits of data: 000, 100, 010, 001, 110, 101, 011, and 111. The state corresponding to storing data 111 is called the erase state, and the states corresponding to storing the other seven bits are called the programming states. That is, a TLC has one erase state and seven programming states.

[0144] In other embodiments, storage unit 112 can be a Quad-Level Cell (QLC). A QLC has sixteen possible states for storing four bits of data; the specific four bits of data stored are not listed here. The state corresponding to storing data 1111 is called the erase state, and the states corresponding to storing the other fifteen data bits are called the programming states. That is, for a QLC, there is one erase state and fifteen programming states.

[0145] Figure 7 This is a schematic diagram of the threshold voltage distribution of a TLC provided in an embodiment of this application. For example... Figure 7 As shown, TLC includes eight states from left to right, with the leftmost one being the erase state, followed by seven programming states, labeled P1 to P7.

[0146] like Figure 7 As shown, each programming state corresponds to a threshold voltage (Vth) range. During programming, if the threshold voltage of a memory cell falls within the threshold voltage range corresponding to a certain programming state, it indicates that the memory cell has reached that programming state. Based on this, when reading data, the programming state corresponding to the memory cell is determined based on the threshold voltage of that memory cell, that is, the data stored in that memory cell is read.

[0147] In addition, such as Figure 7 As shown, the distance between the right boundary of the leftmost programming state and the left boundary of the rightmost programming state in two adjacent programming states can be called the read window. After programming the memory, the larger the read window between two adjacent programming states, the more beneficial it is for subsequent data reading.

[0148] Based on this, embodiments of this application provide a method for operating a memory. The method provided by these embodiments can increase the read window between two adjacent programming states after programming.

[0149] The operation method of the memory provided in the embodiments of this application will be explained below.

[0150] Figure 8 This is a flowchart illustrating a memory operation method provided in an embodiment of this application. The method is applied to... Figure 1-6 The peripheral circuitry of the memory shown is exemplarily applied to a control logic unit within the peripheral circuitry. Subsequent embodiments will be explained using the peripheral circuitry as the execution entity. For example... Figure 8 As shown, the method includes the following steps.

[0151] Step 801: Provide a first preprogramming pulse to the selected word line to preprogram the first type of memory cell in the selected memory cell row. The target programming state of the first type of memory cell is the first target programming state. After providing the first preprogramming pulse, the threshold voltage of the first type of memory cell is less than the first target threshold voltage. The first target threshold voltage is the threshold voltage corresponding to the first target programming state.

[0152] The first type of storage unit can be understood as: a collection of multiple storage units in the selected storage unit row whose target programming state is the first target programming state.

[0153] The first target threshold voltage can be understood as the statistical result of each threshold voltage in the threshold voltage distribution corresponding to the first target programming state. This statistical result can be the average value, the maximum value, or the minimum value of each threshold voltage, etc. It should be noted that, in the embodiments of this application, the target threshold voltage corresponding to different target programming states is determined in the same way, for example, the average value of each threshold voltage in the threshold voltage distribution corresponding to the target programming state is used as the target threshold voltage.

[0154] After preprogramming the first type of memory cell by providing a first preprogramming pulse to the selected word line, the threshold voltage of the first type of memory cell is less than the first target threshold voltage, meaning the current state of the first type of memory cell has not yet reached the first target programming state. Preprogramming the first type of memory cell inevitably causes its threshold voltage to shift towards the first target threshold voltage. In other words, the distance between the state of the first type of memory cell after providing the first preprogramming pulse and the first target programming state is less than the distance between the state of the first type of memory cell before providing the first preprogramming pulse and the first target programming state. Therefore, after preprogramming the first type of memory cell by providing the first preprogramming pulse, the threshold voltage of the first type of memory cell is closer to the first target threshold voltage; in other words, the current state of the first type of memory cell is closer to the first target programming state.

[0155] Step 802: Use the ISPP method to provide programming pulses to the selected word line to program the memory cells of the selected memory cell row.

[0156] Figure 9This is a schematic diagram of a programming flow using the increment step programming pulse (ISPP) method provided in an embodiment of this application. Figure 9 As shown, the programming process includes: progressively providing a series of programming pulses (PPs) with gradually increasing amplitudes to the selected word line. The voltage amplitude of the first programming pulse is V. PGM-START The increment of each step in the programming pulse is ΔISPP. Where V PGM-START The duration of ΔISPP and a single programming pulse can be pre-configured. After each programming pulse is provided, it can be verified whether the memory cell in the selected memory cell row has reached the target programming state, that is, a program verify (PV) operation is performed on the memory cell. The PV operation is implemented by providing one or more PV pulses. Figure 9 The PV pulse is not shown. If the memory cell does not reach the corresponding target programming state, the verification of the memory cell continues after the next programming pulse is provided until the memory cell reaches the target programming state, and then the programming of the memory cell is terminated.

[0157] For ease of explanation, the process of selecting a memory cell row using ISPP programming will be referred to as ISPP programming.

[0158] In this embodiment, before programming the memory cells in the selected memory cell row using the ISPP method, a first pre-programming pulse corresponding to the first target programming state is provided. This ensures that the state of the first type of memory cells in the selected memory cell row, whose target programming state is the first target programming state, approaches the first target programming state. This programming method achieves the following technical effects:

[0159] On the one hand, since the first type of memory cell is programmed to the vicinity of the first target programming state first, when the ISPP method is used for subsequent programming, the first type of memory cell can be programmed to the first target programming state slowly, avoiding the programming speed being too fast. Therefore, the +3σ tail of the threshold voltage distribution can be improved.

[0160] On the other hand, since the first type of memory cell is first programmed to the vicinity of the first target programming state, when the ISPP method is used for subsequent programming, only a small number of electrons need to be injected to program the first memory cell to the first target programming state. This results in a much smaller initial threshold voltage shift (IVS), which can improve the -3σ tail of the threshold voltage distribution.

[0161] By improving the +3σ tail and -3σ tail of the threshold voltage distribution, the range of the threshold voltage distribution can be reduced, thereby increasing the reading window.

[0162] based on Figure 7 As shown, the threshold voltage distribution corresponding to any programming state typically follows a normal distribution, and σ can be understood as the standard deviation of this normal distribution. Correspondingly, the +3σ tail of the threshold voltage distribution can be understood as the data points in the normal distribution that fall to the right of μ+3σ, where μ is the axis of symmetry of the normal distribution. Improving the +3σ tail of the threshold voltage distribution can be understood as minimizing the number of data points in the normal distribution that fall to the right of μ+3σ.

[0163] Correspondingly, the -3σ tail of the threshold voltage distribution can be understood as: data points in the normal distribution that lie to the left of μ-3σ. Improving the -3σ tail of the threshold voltage distribution can be understood as minimizing the number of data points in the normal distribution that fall to the left of μ-3σ.

[0164] Figure 10 This application provides a programming voltage (V) during the programming process. PGM A schematic diagram showing the correspondence between the threshold voltage (Vt) of the memory cell and the threshold voltage of the memory cell. Figure 10 The slope in the equation can represent programming speed. For example... Figure 10 As shown, the closer the initial threshold voltage of the memory cell is to the target threshold voltage, the slower the programming speed. Therefore, pre-programming the first type of memory cell to the vicinity of the first target programming state before performing ISPP programming can improve the +3σ tail of the threshold voltage distribution corresponding to the first target programming state.

[0165] Figure 11 This is a schematic diagram of a -3σ tail for improving threshold voltage distribution provided in an embodiment of this application. Figure 11 As shown, one programming method involves directly programming the memory cell from the erase state to the target programming state via ISPP programming. Another method involves first programming the memory cell from the erase state to near the target programming state via pre-programming, and then programming the memory cell from near the target programming state to the target programming state via ISPP programming. The threshold voltage distribution obtained by the ISPP direct programming method is shown in the figure. Figure 11 As shown by the solid line on the right, the threshold voltage distribution obtained by the method of pre-programming followed by ISPP programming is as follows. Figure 11 As shown by the dotted line on the right. Figure 11 As shown, the -3σ tail of the threshold voltage distribution obtained by the method of pre-programming followed by ISPP programming is significantly shorter than the -3σ tail of the threshold voltage distribution obtained by the method of direct ISPP programming.

[0166] In some embodiments, the distance between the state of a first type of memory cell before the first preprogramming pulse and the first target programming state is greater than the distance between the state of at least one other memory cell in the selected memory cell row and their respective target programming states.

[0167] In other words, before ISPP programming, memory cells that are far from the target programming state in the current state are pre-programmed. The farther the current state is from the target programming state, the more severe the IVS (Inverse Functionality) during the ISPP programming process. Therefore, pre-programming memory cells that are far from the target programming state in the current state can improve the IVS during the subsequent ISPP programming process.

[0168] The distance between the state of a memory cell and its corresponding target programmed state can be understood as the distance between the threshold voltage of the memory cell and the threshold voltage distribution corresponding to the target programmed state. For example, in Figure 7 In this context, the distance between the state of a memory cell and the corresponding target programming state can be: the distance between the threshold voltage of the memory cell and the central axis or left boundary of the threshold voltage distribution corresponding to the target programming state.

[0169] Optionally, in scenarios where erase and programming states are named using consecutive numbers, the distance between the state of a memory cell and the corresponding target programming state can be understood as the difference between the number corresponding to the current state of the memory cell and the number corresponding to the target programming state.

[0170] For example, for Figure 7 The threshold voltage distribution shown is such that, assuming the erase state is marked as P0 and the seven programming states are marked as P1 to P7, the distance between the state of the memory cell and the target programming state can be determined by the distance between the threshold voltage of the memory cell and the threshold voltage distribution corresponding to the target programming state, or by the difference between the number corresponding to the current state of the memory cell and the number corresponding to the target programming state.

[0171] Based on this, for Figure 7 The threshold voltage distribution of the TLC shown indicates that all memory cells are in an erased state before the TLC is programmed. In this scenario, the first type of memory cell can be a type of memory cell with a target programming state of P7.

[0172] In addition, in some embodiments, the difference between the voltage of the first preprogramming pulse and the first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on the programming voltage required to reach the first target programming state of the programming state of the first type of memory cell.

[0173] The first difference threshold is a small value, so the voltage of the first preprogramming pulse is close to the first target programming voltage, so that the state of the first type of memory cell after preprogramming is close to the first target programming state.

[0174] The first target programming voltage, based on the programming state of the first type of memory cell, can be set by a technician using the voltage of programming pulses historically provided by programming the first type of memory cell via ISPP. For example, the maximum value among the voltages of programming pulses historically provided by programming the first type of memory cell via ISPP can be used as the first target programming voltage. Alternatively, several larger voltages among the voltages of programming pulses historically provided by programming the first type of memory cell via ISPP can be selected, and the average value of these larger voltages can be used as the first target programming voltage. This application does not limit the method of determining the first target programming voltage, and will not provide further examples here.

[0175] Since the target programming states of each memory cell in the selected memory cell row are different, the first type of memory cells that need to be preprogrammed can be selected from the selected memory cell row before providing the preprogramming pulse.

[0176] In some embodiments, the first type of memory cells to be preprogrammed can be selected from the selected memory cell rows by determining the first preprogramming pulse based on the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage.

[0177] Based on the foregoing, in the embodiments of this application, memory cells whose current state is far from the target programming state can be pre-programmed before ISPP programming. Therefore, in some embodiments, it can be determined whether to configure a first pre-programming pulse for the first type of memory cell based on the difference between the current threshold voltage and the first target threshold voltage of at least one memory cell in the first type of memory cell.

[0178] For example, if the difference between the current threshold voltage and the first target threshold voltage of at least one memory cell in the first type of memory cells exceeds a second difference threshold, then a first pre-programmed pulse is configured for the first type of memory cell.

[0179] The second difference threshold is a pre-set value that can be set by a technician based on experience. If the difference between the current threshold voltage and the first target threshold voltage of at least one memory cell in the first type of memory cell exceeds the second difference threshold, it indicates that the current state of the first type of memory cell is far from the target programming state, and therefore a first pre-programming pulse can be configured for the first type of memory cell.

[0180] Accordingly, if the difference between the current threshold voltage and the first target threshold voltage of at least one memory cell in the first type of memory cell does not exceed the second difference threshold, it indicates that the current state of the first type of memory cell is close to the target programming state, and therefore there is no need to configure the first preprogramming pulse for the first type of memory cell.

[0181] Optionally, for different types of memory cells corresponding to different target programming states in the selected memory cell row, the difference between the current threshold voltage of each type of memory cell and the target threshold voltage of the corresponding target programming state can be determined. Then, the multiple types of memory cells are sorted in descending order of the determined differences. The first type of memory cell in the sorting result is selected as the first type of memory cell, and a first pre-programming pulse is configured for the first type of memory cell.

[0182] The current threshold voltage of each type of memory cell can be understood as the average value of the threshold voltages of each memory cell in that type of memory cell, or other statistical results.

[0183] The above describes pre-programming a first type of memory cell with a first target programming state before ISPP programming to improve the ±3σ tail of the threshold voltage distribution corresponding to the first target programming state. In this embodiment, a second type of memory cell with a second target programming state can also be pre-programmed before ISPP programming to improve the ±3σ tail of the threshold voltage distribution corresponding to the second target programming state.

[0184] Based on this, in some embodiments, a second preprogramming pulse is provided to the selected word line before step 802 to preprogram the second type of memory cells in the selected memory cell row; wherein, the target programming state of the second type of memory cells is the second target programming state, and after the second preprogramming pulse is provided, the threshold voltage of the second type of memory cells is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

[0185] In other words, in the embodiments of this application, multiple types of memory cells with different target programming states can be pre-programmed before ISPP programming to improve the ±3σ tail of the threshold voltage distribution corresponding to the target programming state.

[0186] The voltage of the second preprogrammed pulse can be implemented with reference to the voltage of the first preprogrammed pulse mentioned above, and will not be repeated here.

[0187] Alternatively, the second type of memory cell can be a type of memory cell where the current state is far from the target programming state before ISPP programming. That is, the distance between the state of the second type of memory cell and the second target programming state before the second preprogramming pulse is provided is greater than the distance between the state of at least one other memory cell in the selected memory cell row and their respective target programming states.

[0188] For example, for Figure 7The threshold voltage distribution of the TLC shown indicates that all memory cells are in an erased state before the TLC is programmed. In this scenario, the first type of memory cell can be a type of memory cell with a target programming state of P7, and the second type of memory cell can be a type of memory cell with a target programming state of P6.

[0189] The above description uses the first and second types of storage units as examples. In the embodiments of this application, more types of storage units can be pre-programmed and then programmed using ISPP.

[0190] For example, before performing ISPP programming, multiple types of memory cells that need to be pre-programmed can be identified, each type of memory cell corresponding to a target programming state. The distance between the current state of each of these multiple types of memory cells and the target programming state is greater than the distance between the current state of other types of memory cells in the selected row and the target programming state. Then, a pre-programming pulse is provided to each of these multiple types of memory cells for pre-programming. After pre-programming these multiple types of memory cells, ISPP programming is then performed on the memory cells in the selected row.

[0191] For example, for Figure 7 The threshold voltage distribution of the TLC shown indicates that all memory cells are in an erased state before the TLC is programmed. Figure 7 As shown, for the four types of memory cells with target programming states P4, P5, P6, and P7, the distance between the current state of these four types of memory cells and the target programming state is greater than the distance between the current state of other types of memory cells and the target programming state. Therefore, these four types of memory cells can be selected as the memory cells that need to be pre-programmed. Then, a pre-programming pulse is provided for each of these four types of memory cells to perform pre-programming. After pre-programming these four types of memory cells, ISPP programming is then performed on the memory cells in the selected memory cell row.

[0192] It should be noted that the above explanation uses the example of pre-programming memory cells whose current state is far from the target programming state. Optionally, in the embodiments of this application, screening can be omitted, and each type of memory cell can be pre-programmed directly. After pre-programming, ISPP programming can be performed on the memory cells in the selected memory cell row. This will not be described in detail here.

[0193] The following is based on Figure 12 To further illustrate the difference between the programming scheme provided in this application embodiment and the scheme of directly performing ISPP programming on selected memory cell rows, the following example will be used. For ease of subsequent explanation, the programming scheme provided in this application embodiment will be referred to as Scheme 1, and the scheme of directly performing ISPP programming on selected memory cell rows will be referred to as Scheme 2. Figure 12This is a schematic diagram illustrating the pulse comparison provided during the programming process for Scheme 1 and Scheme 2, as provided in the embodiments of this application. Figure 12 As shown, Figure 12 The upper part represents the programming pulse provided for the selected memory cell row in Scheme 2. For ease of subsequent explanation, the programming pulse provided in ISPP programming will be referred to as the ISPP programming pulse. Figure 12 As shown in the upper part, in Scheme 2, after each PP is provided, one or more PV pulses are provided to verify whether the memory cells in the selected memory cell row have reached the corresponding target programming state. Figure 12 The lower part is used to represent the programming pulse provided for the selected memory cell row in Scheme 1. For example... Figure 12 As shown in the lower part, before providing the ISPP programming pulse to the selected memory cell row, a pre-programming pulse is also provided for each type of memory cell in the selected memory cell row to implement the programming scheme provided in the embodiments of this application.

[0194] In summary, in this embodiment, before programming the selected memory cell row using the ISPP method, the first type of memory cells in the selected memory cell row are pre-programmed. On one hand, because the first type of memory cells are programmed to the vicinity of the first target programming state first, subsequent ISPP programming can gradually program the first type of memory cells to the first target programming state, avoiding excessively fast programming speeds and thus improving the +3σ tail of the threshold voltage distribution. On the other hand, because the first type of memory cells are programmed to the vicinity of the first target programming state first, subsequent ISPP programming requires only a small amount of electron injection to program the first memory cells to the first target programming state, resulting in significantly fewer IVS (Inverting Vibration Spectra) and thus improving the -3σ tail of the threshold voltage distribution. By improving the +3σ and -3σ tails of the threshold voltage distribution, the range of the threshold voltage distribution can be reduced, thereby increasing the read window.

[0195] Currently, there are two methods for ISPP programming of memory: one-step ISPP programming and the other-two-step ISPP programming. Figure 8 The illustrated embodiments can be applied to both one-step and two-step ISPP programming. One-step ISPP programming can be understood as achieving the target programming state for each memory cell in a selected memory cell row through a single ISPP programming operation. Two-step ISPP programming can be understood as achieving the target programming state for each memory cell in a selected memory cell row through two ISPP programming operations.

[0196] The following two examples will illustrate this point.

[0197] Figure 13This is a flowchart of another memory operation method provided in an embodiment of this application, which is applied to one-step ISPP programming. Figure 13 As shown, the method includes the following steps.

[0198] Step 1301: The controller sends programming instructions to the memory.

[0199] Step 1302: In response to a programming instruction from the controller, the memory provides a first preprogramming pulse to the selected word line to preprogram the first type of memory cells in the selected memory cell row.

[0200] Step 1303: The memory uses the step programming (ISPP) method to provide programming pulses to the selected word line to program the memory cells in the selected memory cell row.

[0201] exist Figure 13 In the method shown, when the memory receives a programming instruction from the controller, it preprograms the first type of memory cells in the selected memory cell row before performing one-step ISPP programming on the selected memory cell row, in order to improve the +3σ tail and -3σ tail of the threshold voltage distribution of the first target programming state.

[0202] Optionally, in Figure 13 In the method shown, before performing one-step ISPP programming on the selected memory cell row, each type of memory cell row within the selected memory cell row can be pre-programmed separately to improve the +3σ tail and -3σ tail of the threshold voltage distribution of their respective target programmed states. For specific implementation details, please refer to [reference needed]. Figure 8 The embodiments shown will not be described in detail here.

[0203] It should be noted that, Figure 13 The execution order of the steps in the operation method shown can be adjusted appropriately. The step numbers do not constitute a limitation on the execution order of each step. Any variation that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application, and therefore will not be described in detail.

[0204] in addition, Figure 13 The memory in the method shown can be, for example, a TLC. In other words, when the TLC receives programming instructions from the controller, it first pre-programs at least one type of memory cell in the memory cell row, and then programs the selected memory cell row through one-step ISPP programming.

[0205] For example, when the TLC receives a programming instruction from the controller, it first preprograms the four types of memory cells with target programming states of P4, P5, P6 and P7 respectively with a preprogramming pulse, so that these four types of memory cells reach the vicinity of the corresponding target programming state. Then, it programs the selected memory cell row through ISPP programming so that all memory cells in the selected memory cell row reach the corresponding target programming state.

[0206] Figure 14 This is a schematic diagram of the programming state distribution during a TLC programming process provided in an embodiment of this application. For example... Figure 14 As shown, a pre-programming pulse is first applied to each of the four types of memory cells with target programming states of P4, P5, P6, and P7 for pre-programming. The threshold voltage distribution of these four types of memory cells after pre-programming is as follows. Figure 14 The upper half is shown by the dashed line. Then, an ISPP programming pulse is provided to the selected memory cell row. After providing the ISPP programming pulse, the threshold voltage distribution of the memory cells in the selected memory cell row is as follows. Figure 14 As shown in the lower half. Figure 14 As shown in the comparison above and below, the threshold voltage distribution of the four types of memory cells with target programming states of P4, P5, P6 and P7 after preprogramming has not yet reached the corresponding target programming state, but is located near the corresponding target programming state, and only reaches the corresponding target programming state after ISPP programming.

[0207] Figure 15 This is a schematic diagram comparing threshold voltage distribution provided in an embodiment of this application. Figure 15 The solid lines corresponding to each programming state are schematic diagrams of the threshold voltage distribution of TLC obtained by directly programming the selected memory cell row based on one-step ISPP programming, that is, the threshold voltage distribution of TLC obtained directly based on one-step ISPP programming without pre-programming. Figure 15 The solid lines corresponding to programming states P0-P3 and the dashed lines corresponding to programming states P4-P7 are through Figure 14 The diagram shows the threshold voltage distribution of a TLC obtained by the programming method shown, that is, the threshold voltage distribution of a TLC obtained by first pre-programming and then programming based on the one-step ISPP method.

[0208] like Figure 15 As shown, before the one-step ISPP programming, a pre-programming pulse is provided to each of the four types of memory cells with target programming states of P4, P5, P6 and P7 for pre-programming. Therefore, the threshold voltage distribution of these four types of memory cells in the final threshold voltage distribution is much narrower, which improves the +3σ tail and -3σ tail of the threshold voltage distribution of these four types of memory cells.

[0209] It should be noted that, Figure 14 and Figure 15 This explanation uses TLC as an example. Optionally, Figure 13 The embodiments shown can also be applied to other types of memory, which will not be illustrated here.

[0210] Figure 16 This is a flowchart of another memory operation method provided in an embodiment of this application, which is applied to two-step ISPP programming. Figure 16 As shown, the method includes the following steps.

[0211] Step 1601: The controller sends programming instructions to the memory.

[0212] Step 1602: In response to the programming instruction from the controller, the memory provides a programming pulse to the selected word line in the ISPP mode to perform the first programming of the memory cell in the selected memory cell row.

[0213] Step 1603: The memory provides a first preprogramming pulse to the selected word line to preprogram the first type of memory cells in the selected memory cell row.

[0214] Step 1604: The memory uses the ISPP method to provide programming pulses to the selected word line to perform a second programming of the memory cells in the selected memory cell row.

[0215] In the second programming iteration, the number of programmed states in the threshold voltage distribution of the selected memory cell row is greater than the number of programmed states in the first programming iteration. In other words, the first programming first programs the selected memory cell row to a smaller number of programmed states, and then the second programming programs it to a larger number of programmed states. Therefore, the first programming iteration is also called ISPP coarse programming, and the second programming iteration is also called ISPP fine programming.

[0216] It should be noted that, Figure 16 The execution order of the steps in the operation method shown can be adjusted appropriately. The step numbers do not constitute a limitation on the execution order of each step. Any variation that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application, and therefore will not be described in detail.

[0217] Furthermore, the two-step ISPP programming method is typically suitable for memories with a large number of programmable states. For example, in a QLC memory, before programming the QLC, all memory cells are in the erase state. Considering the total number of target programmable states for all memory cells is 16, to avoid severe IVS during the one-step ISPP programming process, the QLC can be programmed a first time using ISPP. This ensures that the threshold voltage distribution of the QLC after the first programming includes the 4 programmable states of an MLC or the 8 programmable states of a TLC. Then, a second programming step is performed using ISPP to ensure that the threshold voltage distribution of the QLC after the second programming includes all 16 programmable states. This process is also known as: first programming the memory as an MLC or TLC, then programming the MLC or TLC as a QLC.

[0218] exist Figure 16 In the method shown, when the memory receives a programming instruction from the controller, it first performs the first programming in the two-step ISPP programming on the selected memory cell row. After the first programming, it preprograms the first type of memory cells in the selected memory cell row, and then performs the second programming in the two-step ISPP programming on the selected memory cell row.

[0219] Optionally, when the memory receives a programming instruction from the controller, it first performs the first programming step of the two-step ISPP programming on the selected memory cell row. After the first programming, it pre-programs the various types of memory cells in the selected memory cell row separately, and then performs the second programming step of the two-step ISPP programming on the selected memory cell row. For specific implementation details, please refer to [reference needed]. Figure 8 The embodiments shown will not be described in detail here.

[0220] Figure 17 This is a schematic diagram of the programming state distribution in a QLC programming process provided in an embodiment of this application. For example... Figure 17 As shown, the memory cells in the selected memory cell row are first divided into four categories: one category includes memory cells P0-P3 in the target programming state; another category includes memory cells P4, P5, P8, and P9 in the target programming state; another category includes memory cells P6, P7, P10, and P15 in the target programming state; and the third category includes memory cells P11, P12, P13, and P14 in the target programming state. After the first programming (i.e., after the ISPP rough programming), the current state of the memory cells P0-P3 in the target programming state is still... Figure 17 In the first line, P0 represents the current state of memory locations P4, P5, P8, and P9 in the target programming state. Figure 17 In the first line, P1 represents the current state of memory cells P6, P7, P10, and P15 in the target programming state. Figure 17In the first line, P2, the current state of the memory units P11, P12, P13, and P14 in the target programming state is... Figure 17 P3 in the first row. That is, after the first programming, the threshold voltage distribution of the selected memory cell row includes four programming states.

[0221] After the first programming, the target programming state is the current state of memory cells P8 and P9. Figure 17 The distance between P1 in the first line and the corresponding target programming state is still relatively far. The target programming state is the current state of the memory cells P10 and P15. Figure 17 The distance between P2 in the first line and the corresponding target programming state is still relatively far. The target programming state is the current state of the memory cells P13 and P14. Figure 17 The distance between P3 in the first line and the corresponding target programming state is still relatively far. Therefore, a pre-programming pulse is provided for each of the six types of memory cells to adjust the current state of each type of memory cell (e.g., P3 in the first line) to the corresponding target programming state. Figure 17 (As shown in the second line) it reaches the vicinity of the corresponding target programming state.

[0222] After pre-programming, a second programming (ISPP fine-tuning) is performed on each memory cell in the selected memory cell row to bring the state of each memory cell in the selected memory cell row to the corresponding target programming state. For example... Figure 17 As shown in the third row, after the second programming, the threshold voltage distribution of the selected memory cell row of the QLC includes 16 programming states.

[0223] Figure 18 This is another schematic diagram comparing threshold voltage distribution provided in the embodiments of this application. Figure 18 The solid lines corresponding to each programming state are schematic diagrams of the threshold voltage distribution of the QLC obtained by directly programming the selected memory cell line based on the two-step ISPP method, that is, the threshold voltage distribution of the QLC obtained by programming directly based on the two-step ISPP method without pre-programming. Figure 18 The solid lines corresponding to programming states P0-P7 and P11-P12, and the dashed lines corresponding to programming states P8-P10 and P13-P15, are for passing through. Figure 17 The schematic diagram of the threshold voltage distribution of the QLC obtained by the programming method shown is that the first programming in the two-step ISPP programming is performed, then pre-programming is performed, and finally the second programming in the two-step ISPP programming is performed to obtain the threshold voltage distribution of the QLC.

[0224] like Figure 18As shown, before the second programming in the two-step ISPP programming, a preprogramming pulse is provided for each of the six types of memory cells with target programming states of P8, P9, P10, P13, P14, and P15 for preprogramming. Therefore, the threshold voltage distribution of these six types of memory cells in the final threshold voltage distribution is much narrower, which improves the +3σ tail and -3σ tail of the threshold voltage distribution of these six types of memory cells.

[0225] The programming state that each storage unit needs to reach after the first programming is related to the pre-set Gray code. The embodiments of this application do not limit the specific form of the Gray code.

[0226] It should be noted that, Figure 17 and Figure 18 This explanation uses QLC as an example. Optionally, Figure 16 The embodiments shown can also be applied to other types of memory, which will not be illustrated here.

[0227] in addition, Figure 13 and Figure 16 This application uses one-step and two-step ISPP programming as examples to illustrate its application scenarios. Optionally, Figure 8 The examples shown can be applied to many other types of ISPP programming, which will not be illustrated here.

[0228] based on Figures 8-18 The embodiments shown in this application also provide a memory, which includes: a memory array including a plurality of memory cell rows; a plurality of word lines respectively coupled to the plurality of memory cell rows; and peripheral circuitry coupled to the plurality of word lines and configured to implement the operation method of the memory provided in this application.

[0229] Specifically, the peripheral circuit is configured to: provide a first preprogramming pulse to a selected word line to preprogram a first type of memory cell in a selected memory cell row, wherein the target programming state of the first type of memory cell is a first target programming state, and the threshold voltage of the first type of memory cell is less than a first target threshold voltage after the first preprogramming pulse is provided, wherein the first target threshold voltage is the threshold voltage corresponding to the first target programming state; and provide a programming pulse to the selected word line using a step programming (ISPP) method to program the selected memory cell row.

[0230] For details on how the functions of the aforementioned peripheral circuits are implemented, please refer to [reference needed]. Figure 8-18 The embodiments shown will not be described in detail here.

[0231] In addition, embodiments of this application also provide a storage system including a memory and a controller coupled to the memory and configured to control the memory.

[0232] The memory is configured to provide a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row. The target programming state of the first type of memory cell is a first target programming state. After providing the first pre-programming pulse, the threshold voltage of the first type of memory cell is less than the first target threshold voltage, which is the threshold voltage corresponding to the first target programming state. A programming pulse is provided to the selected word line using an ISPP (Incremental Programming Protocol) method to program the selected memory cell row.

[0233] The implementation methods of the above-mentioned controller and memory functions can be referred to Figure 13 and Figure 16 The embodiments shown will not be described in detail here.

[0234] Figure 19 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Figure 19 As shown, the controller 1900 includes a processing unit 1901 and a memory 1902. The memory 1902 is used to store computer instructions, and the processing unit 1901 is used to execute the computer instructions to implement the operation methods provided in the embodiments of this application. The processing unit 1901 may, for example, be an MCU (microcontroller unit) or the like.

[0235] The controller 1900 is used to implement the functions of the controller in the aforementioned embodiments, so as to realize the storage system provided in this application embodiment. For specific implementation details, please refer to... Figure 13 or Figure 16 The embodiments shown will not be described in detail here.

[0236] In addition, embodiments of this application also provide a peripheral circuit, wherein the control logic unit of the peripheral circuit includes at least one software module, which is used to implement... Figure 8-18 Any step in the memory operation method of the illustrated embodiment.

[0237] In addition, embodiments of this application also provide a computer storage medium on which instructions are stored, which are executed by peripheral circuits in the memory. Figure 8-18 Any step in the memory operation method of the illustrated embodiment.

[0238] On the other hand, a computer program product containing instructions is provided, which is implemented when the instructions are executed in the peripheral circuit. Figure 8-18Any step in the memory operation method of the illustrated embodiment.

[0239] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0240] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory, characterized in that, The memory includes: A storage array comprising multiple rows of storage cells; Multiple word lines, each word line being coupled to one of the multiple rows of memory cells; and Peripheral circuitry, coupled to the plurality of word lines and configured to: A first preprogramming pulse is provided to a selected word line to preprogram a first type of memory cell in a selected memory cell row. The target programming state of the first type of memory cell is a first target programming state. After the first preprogramming pulse is provided, the threshold voltage of the first type of memory cell is less than the first target threshold voltage. The first target threshold voltage is the threshold voltage corresponding to the first target programming state. The programming pulse is provided to the selected word line using the step programming pulse (ISPP) method to program the memory cells of the selected memory cell row; The peripheral circuit is configured as follows: In response to a programming instruction from the controller, a programming pulse is provided to the selected word line using the ISPP method to perform the first programming of the memory cells in the selected memory cell row; Provide the first preprogramming pulse to the selected word line to preprogram the first type of memory cells in the selected memory cell row; The ISPP method is used to provide programming pulses to the selected word line to perform a second programming of the memory cells in the selected memory cell row; The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

2. The memory as claimed in claim 1, characterized in that, The peripheral circuit is also configured to: A second preprogramming pulse is provided to the selected word line to preprogram the second type of memory cells in the selected memory cell row; Wherein, the target programming state of the second type of memory cell is the second target programming state, and after the second preprogramming pulse is provided, the threshold voltage of the second type of memory cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

3. The memory as claimed in claim 1, characterized in that, The distance between the state of the first type of memory cell and the first target programming state before the first preprogramming pulse is provided is greater than the distance between the state of at least one other memory cell in the selected memory cell row and their respective target programming states.

4. The memory as claimed in claim 1, characterized in that, The difference between the voltage of the first preprogramming pulse and the first target programming voltage is less than a first difference threshold. The first target programming voltage is set based on the programming state of the first type of memory cell to achieve the first target programming state.

5. The memory as claimed in claim 1, characterized in that, The peripheral circuit is also configured to: The first preprogrammed pulse is determined based on the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage.

6. The memory as claimed in claim 5, characterized in that, The peripheral circuit is configured as follows: If the difference between the current threshold voltage and the first target threshold voltage of at least one of the first type of memory cells exceeds the second difference threshold, then the first preprogrammed pulse is configured for the first type of memory cell.

7. The memory as claimed in claim 1, characterized in that, The memory cells in the memory are four-level cells (QLC).

8. A storage system, characterized in that, The storage system includes a memory and a controller coupled to the memory and configured to control the memory; The memory is configured as follows: A first preprogramming pulse is provided to a selected word line to preprogram a first type of memory cell in a selected memory cell row. The target programming state of the first type of memory cell is a first target programming state. After the first preprogramming pulse is provided, the threshold voltage of the first type of memory cell is less than the first target threshold voltage. The first target threshold voltage is the threshold voltage corresponding to the first target programming state. The programming pulse is provided to the selected word line using the step programming pulse (ISPP) method to program the memory cells of the selected memory cell row; Wherein, it is characterized by, The controller is configured to send programming instructions to the memory; The memory is also configured to: In response to a programming instruction from the controller, a programming pulse is provided to the selected word line using the ISPP method to perform the first programming of the memory cells in the selected memory cell row; Provide the first preprogramming pulse to the selected word line to preprogram the first type of memory cells in the selected memory cell row; The ISPP method is used to provide programming pulses to the selected word line to perform a second programming of the memory cells in the selected memory cell row; The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

9. A method for operating a memory, characterized in that, The method includes: A first preprogramming pulse is provided to a selected word line to preprogram a first type of memory cell in a selected memory cell row. The target programming state of the first type of memory cell is a first target programming state. After the first preprogramming pulse is provided, the threshold voltage of the first type of memory cell is less than the first target threshold voltage. The first target threshold voltage is the threshold voltage corresponding to the first target programming state. The programming pulse is provided to the selected word line using the step programming pulse (ISPP) method to program the memory cells of the selected memory cell row; Before providing a first preprogramming pulse to a selected word line to preprogram the first type of memory cells in the selected memory cell row, the method further includes: In response to a programming instruction from the controller, a programming pulse is provided to the selected word line using the ISPP method to perform the first programming of the memory cells in the selected memory cell row; The step-programming (ISPP) method of providing programming pulses to the selected word line to program the selected memory cell row includes: The ISPP method is used to provide programming pulses to the selected word line to perform a second programming of the memory cells in the selected memory cell row; The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

10. The method as described in claim 9, characterized in that, Before providing programming pulses to the selected word line using the step programming (ISPP) method to program the memory cells of the selected memory cell row, the method further includes: A second preprogramming pulse is provided to the selected word line to preprogram the second type of memory cells in the selected memory cell row; Wherein, the target programming state of the second type of memory cell is the second target programming state, and after the second preprogramming pulse is provided, the threshold voltage of the second type of memory cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

11. The method as described in claim 9, characterized in that, The distance between the state of the first type of memory cell and the first target programming state before the first preprogramming pulse is provided is greater than the distance between the state of at least one other memory cell in the selected memory cell row and their respective target programming states.

12. The method as described in claim 9, characterized in that, The difference between the voltage of the first preprogramming pulse and the first target programming voltage is less than a first difference threshold. The first target programming voltage is set based on the programming voltage required to reach the first target programming state of the first type of memory cell.

13. The method as described in claim 9, characterized in that, Before providing the first preprogrammed pulse to the selected word line, the method further includes: The first preprogrammed pulse is determined based on the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage.

14. The method as described in claim 13, characterized in that, Determining the first pre-programmed pulse based on the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage includes: If the difference between the current threshold voltage and the first target threshold voltage of at least one memory cell in the first type of memory cell exceeds the second difference threshold, then the first preprogrammed pulse is configured for the first type of memory cell.

15. The method as described in claim 9, characterized in that, The memory cells in the memory are four-level cells (QLC).

Images