Mapping between PRACH preamble and PUSCH resource units for 2-step RACH

Abstract

The present disclosure relates to mapping between a PRACH preamble and a PUSCH resource unit for a 2-step RACH. It is described that a 4-step RACH procedure is improved by using a 2-step RACH procedure. The UE transmits a PRACH preamble and an associated MsgA physical uplink shared channel (PUSCH) on the configured time and frequency resources. After successfully detecting the PRACH preamble and decoding the MsgA PUSCH, the gNB transmits the MsgB in a second step. In general, mapping is used between a PRACH preamble of a 2-step RACH and a PUSCH resource unit. The present disclosure describes mapping of a two-step RACH.

Description

[0001] This application is a divisional application of an invention patent application with an international application date of May 1, 2020, a national application number of 202080046002.8 (international application number PCT / US2020 / 031027), and an invention name of “Mapping between PRACH preamble code and PUSCH resource unit of 2-step RACH”.

[0002] Priority claim

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 843,276, filed on May 3, 2019, entitled “SYSTEM AND METHODS ON THE MAPPING BETWEEN PRACH PREAMBLE AND PUSCH RESOURCE UNIT FOR 2-STEP RACH,” and U.S. Provisional Patent Application No. 62 / 846,496, filed on May 10, 2019, entitled “SYSTEM AND METHODSON THE MAPPING BETWEEN PRACH PREAMBLE AND PUSCH RESOURCE UNIT FOR 2-STEPRACH,” the entire contents of each of which are incorporated herein by reference. Technical Field

[0004] The present disclosure generally relates to configuring communications between a radio link control entity and user equipment. Background Art

[0005] The use of wireless communication systems is growing rapidly. In addition, wireless communication technology has evolved from voice-only communications to also include the transmission of data (such as the Internet and multimedia content) to various devices. In order to accommodate the increasing number of devices that transmit both voice and data signals, many wireless communication systems share available communication channel resources between devices. Summary of the invention

[0006] Mobile communications have evolved significantly from early voice systems to today's highly complex integrated communications platforms. The next generation of wireless communication systems, 5G or New Radio (NR), provides access to information and data sharing anytime, anywhere for a variety of users and applications. NR is expected to be a unified network / system designed to meet very different and sometimes conflicting performance dimensions and services. Such different multi-dimensional requirements are driven by different services and applications. In general, NR will evolve based on 3GPP LTE-Advanced with the addition of potential new radio access technologies (RATs), enriching people's lives with better simple and seamless wireless connectivity solutions. NR will enable everything to be connected wirelessly and provide fast, rich content and services.

[0007] In general terms, a process for generating a mapping between a physical random access channel (PRACH) preamble and a physical uplink shared channel (PUSCH) resource element by a user equipment (UE) in a fifth generation (5G) new radio (NR) network includes configuring a first number of PRACH opportunities, each associated with a PUSCH opportunity. The process includes configuring a second number of contention-based preambles for each PRACH opportunity for each PUSCH opportunity. The process includes configuring a third number of preambles associated with a PUSCH resource element of at least one PUSCH opportunity. The process includes receiving a message including preamble data and message data from a user equipment (UE). The process includes sending a response message to the UE according to the first number, the second number, and the third number, the response message including random access response (RAR) data and contention resolution data.

[0008] In an implementation scheme, the preambles in the third number of preambles are sorted based on: an increasing order of preamble indices within a single PRACH opportunity; an increasing order of frequency resource indices, where the PRACH opportunity is a frequency multiplexing opportunity; an increasing order of time resource indices, where the PRACH opportunity is a time multiplexing opportunity; an increasing order of indices of PRACH time slots; or a combination thereof.

[0009] In an embodiment, at least one PUSCH opportunity includes a fourth number of PUSCH resource units. The fourth number of PUSCH resource units are ordered based on: an increasing order of a demodulation reference signal (DMRS) port or sequence within the at least one PUSCH opportunity; an increasing order of a frequency resource index, wherein the at least one PUSCH opportunity is frequency multiplexed; an increasing order of a time resource index, wherein the at least one PUSCH opportunity is for time multiplexing within a PUSCH slot; an increasing order of an index of a MsgA PUSCH slot; or a combination thereof.

[0010] In an embodiment, the at least one PUSCH opportunity includes a plurality of PUSCH opportunities. The process also includes: determining a plurality of disjoint sets of PUSCH opportunities based on a start and length indicator value (SLIV) of each PUSCH opportunity in the plurality of PUSCH opportunities. The ordering of time resource indexes of time multiplexed PUSCH opportunities in the plurality of PUSCH opportunities is based on the plurality of disjoint sets of PUSCH opportunities.

[0011] In an embodiment, a synchronization signal block (SSB) is associated with at least two PRACH opportunities. For a fifth number of consecutive valid PRACH opportunities associated with the SSB, a preamble index associated with a PUSCH resource unit is mapped starting from a given preamble in a third number of preambles, wherein the fifth number is inversely proportional to the first number of PRACH opportunities.

[0012] In an embodiment, a plurality of SSBs are associated with each PRACH opportunity in a first number of PRACH opportunities, wherein the method further comprises mapping a preamble index to a PUSCH resource element of a PUSCH opportunity based on a function of, for an SSB in the plurality of SSBs, a third number of preambles and a number of synchronization signal / physical broadcast channel (SS / PBCH) blocks associated with a PRACH opportunity in the first number of PRACH opportunities.

[0013] In an embodiment, the process includes mapping preamble indexes associated with PUSCH opportunities for a third number of preambles in a consecutive order. In an embodiment, the process includes mapping DMRS port indexes associated with PRACH opportunities in a first number of PRACH opportunities in a consecutive order. In an embodiment, the PRACH opportunities in the first number of PRACH opportunities have a one-to-one association with the PUSCH opportunities, and the method further includes: mapping the PUSCH resource elements or DMRS antenna ports associated with the PRACH opportunities starting from 0 and continuously increasing. In an embodiment, the individual preamble indexes of the PRACH opportunities indicate the corresponding modulation and coding scheme (MCS) or transport block size TBS used for transmission of the MsgA PUSCH by the UE.

[0014] In general terms, a process includes: for generating a mapping between a physical random access channel (PRACH) preamble and a physical uplink shared channel (PUSCH) resource unit by a next generation node (gNB) in a fifth generation (5G) new radio (NR) network, mapping one or more PRACH opportunities to one or more PUSCH resource units; and generating one or more PUSCH resource units based on the mapping.

[0015] In an embodiment, the process includes acquiring one or more PRACH opportunities. In an embodiment, the process includes determining, by the gNB, one or more rules for mapping one or more PRACH opportunities to one or more PUSCH resource units. In an embodiment, the one or more rules for mapping are used to convert a 4-step RACH process into a 2-step RACH process. In an embodiment, one or more PRACH opportunities respectively include multiple PRACH preambles. In an embodiment, the multiple PRACH preambles include N synchronization signal / physical broadcast channel (SS / PBCH) blocks, wherein R contention-based preambles are associated with each SS / PBCH block in the N SS / PBCH blocks. In an embodiment, the N SS / PBCH blocks and the R contention-based preambles are configured by ssb-perRACH-OccasionAndCB-PreamblesPerSSB.

[0016] In an implementation scheme, the action includes sorting or causing sorting of multiple PRACH preamble codes according to the following order: an increasing order of corresponding preamble code indices within a single PRACH opportunity; an increasing order of frequency resource indices of a frequency multiplexed PRACH opportunity; an increasing order of time resource indices of a time multiplexed PRACH opportunity within a PRACH time slot; or an increasing order of indices of PRACH time slots.

[0017] In an embodiment, the process includes sorting or causing sorting of multiple PRACH preambles according to: decreasing order of corresponding preamble indices within a single PRACH opportunity; decreasing order of frequency resource indices of a frequency multiplexed PRACH opportunity; decreasing order of time resource indices of a time multiplexed PRACH opportunity within a PRACH time slot; or decreasing order of indices of PRACH time slots.

[0018] In an implementation scheme, the process includes sorting one or more PUSCH resource units according to the following order: an increasing order of demodulation reference signal (DMRS) ports or DMRS sequences within a single PUSCH opportunity; an increasing order of frequency resource indices of frequency-multiplexed MsgAPUSCH opportunities; an increasing order of time resource indices of time-multiplexed MsgA PUSCH opportunities within an MsgA PUSCH time slot; or an increasing order of indices of MsgA PUSCH time slots.

[0019] The details of one or more specific implementations are set forth in the drawings and description below. Other features and advantages will be apparent from the detailed description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 An exemplary wireless communication system is shown.

[0021] Figure 2 An example of infrastructure equipment is shown.

[0022] Figure 3 Examples of platforms or devices are shown.

[0023] Figure 4 Exemplary components of baseband circuitry and radio front-end circuitry are shown.

[0024] Figure 5 Exemplary components of a cellular communications circuit are shown.

[0025] Figure 6 Exemplary protocol functions that may be implemented in a wireless communication system are shown.

[0026] Figure 7 A block diagram is shown of components capable of reading instructions from a machine-readable medium or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methodologies discussed herein, according to some exemplary embodiments.

[0027] Figure 8 An example of a 4-step Random Access Channel (RACH) procedure is shown.

[0028] Fig. 9 An example of a 2-step Random Access Channel (RACH) procedure is shown.

[0029] Figures 10 to 17 An exemplary mapping is shown.

[0030] Fig.18 An exemplary process for generating a mapping between a physical random access channel (PRACH) preamble and a physical uplink shared channel (PUSCH) resource element for a 2-step RACH is shown.

[0031] Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION

[0032] The present disclosure describes a process for mapping a 4-step Random Access Channel (RACH) procedure for initial access to a 2-step RACH procedure. The 4-step RACH procedure is defined in 3GPP TS 36.231 Section 5.1, Version 15.4.0 Rel.15, April 2019 and 3GPP TS 38.213 Section 8, Version 15.4.0 Release 15, April 2019, each of which is incorporated by reference in its entirety. In a first step, a user equipment (UE) transmits a physical random access channel (PRACH) in the uplink by randomly selecting a preamble signature, which allows the next generation node (gNB) to estimate the delay between the node (eNB) and the UE for subsequent uplink (UL) timing adjustment. Subsequently, in a second step, the gNB responds with a random access response (RAR) that carries timing advance (TA) command information and an uplink grant for uplink transmission in a third step. The UE expects to receive a RAR within a time window, the start and end of which are configured by the gNB via the System Information Block (SIB). The UE adjusts the UL timing based on the RAR and sends a Layer 2 or Layer 3 (L2 / L3) MsgBack to the gNB. The gNB can respond with contention resolution.

[0033] In some embodiments, the above-described 4-step RACH process may be improved by a 2-step RACH process. More specifically, in the first step, the UE transmits a PRACH preamble and an associated MsgA physical uplink shared channel (PUSCH) on the configured time and frequency resources. The MsgA PUSCH may carry at least the equivalent content of the third message in the previously described 4-step RACH. In addition, after successfully detecting the PRACH preamble and decoding the MsgA PUSCH, the gNB transmits MsgB in the second step. MsgB may carry the equivalent content of the second message and the fourth message in the 4-step RACH. In general, a mapping is used between the PRACH preamble and the PUSCH resource elements of the 2-step RACH. The present disclosure subsequently describes the mapping of the 2-step RACH.

[0034] Figure 1 An exemplary wireless communication system 100 is shown. For convenience and not limitation, the exemplary system 100 is described in the context of LTE and 5G NR communication standards defined by the Third Generation Partnership Project (3GPP) technical specifications. However, the techniques described herein may also be implemented in other communication systems using other communication standards such as other 3GPP standards or IEEE 802.16 protocols (e.g., WMAN or WiMAX).

[0035] System 100 includes UE 101a and UE 101b (collectively referred to as "UE 101"). In this example, UE 101 is shown as a smartphone (eg, a handheld, touch-screen mobile computing device that can connect to one or more cellular networks). In other examples, any of the multiple UEs 101 may include other mobile computing devices or non-mobile computing devices, such as consumer electronic devices, cellular phones, smart phones, feature phones, tablet computers, wearable computer devices, personal digital assistants (PDAs), pagers, wireless handheld devices, desktop computers, laptop computers, in-vehicle infotainment (IVI), in-car entertainment (ICE) devices, instrument clusters (ICs), heads-up display (HUD) devices, on-board diagnostic (OBD) devices, on-board mobile equipment (DME), mobile data terminals (MDTs), electronic engine management systems (EEMS), electronic / engine control units (ECUs), electronic / engine control modules (ECMs), embedded systems, microcontrollers, control modules, engine management systems (EMS), networked or "smart" appliances, machine type communication (MTC) devices, machine-to-machine (M2M) devices, Internet of Things (IoT) devices, or combinations thereof, etc.

[0036] In some examples, any of the plurality of UEs 101 may be an IoT UE, which may include a network access layer designed for low-power IoT applications utilizing short-term UE connections. The IoT UE may utilize technologies such as M2M or MTC to exchange data with an MTC server or device utilizing, for example, a public land mobile network (PLMN), a short-range service (ProSe), a device-to-device (D2D) communication, a sensor network, an IoT network, or a combination thereof. The M2M or MTC data exchange may be a machine-initiated data exchange. The IoT network describes interconnected IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure) with short-lived connections. The IoT UE may execute background applications (e.g., keep-alive messages or status updates) to facilitate connectivity to the IoT network.

[0037] UE 101 is configured to connect (e.g., be communicatively coupled) to an access network (AN) or radio access network (RAN) 110. In some examples, RAN 110 may be a next generation RAN (NG RAN), an evolved UMTS terrestrial radio access network (E-UTRAN), or a legacy RAN, such as a UMTS terrestrial radio access network (UTRAN) or a GSM EDGE radio access network (GERAN). As used herein, the term "NG RAN" may refer to a RAN 110 operating in a 5G NR system 100, while the term "E-UTRAN" may refer to a RAN 110 operating in an LTE or 4G system 100.

[0038] In order to connect to RAN 110, multiple UEs 101 utilize connections (or channels) 103 and 104, respectively, each of which may include a physical communication interface or layer, as described below. In this example, connections 103 and 104 are shown as air interfaces to achieve communication coupling, and may be consistent with cellular communication protocols, such as global system for mobile communications (GSM) protocols, code division multiple access (CDMA) network protocols, push-to-talk (PTT) protocols, cellular PTT (POC) protocols, universal mobile telecommunications system (UMTS) protocols, 3GPP LTE protocols, 5G NR protocols, or combinations thereof, as well as other communication protocols. In some examples, multiple UEs 101 may use interfaces 105 such as ProSe interfaces to directly exchange communication data. Interface 105 may alternatively be referred to as sidelink interface 105 and may include one or more logical channels, such as physical sidelink control channel (PSCCH), physical sidelink shared channel (PSSCH), physical sidelink downlink channel (PSDCH) or physical sidelink broadcast channel (PSBCH) or combinations thereof, etc.

[0039] UE 101b is shown configured to access access point (AP) 106 (also referred to as "WLAN node 106", "WLAN 106", "WLAN termination 106", "WT 106", etc.) using connection 107. Connection 107 may include a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein AP 106 will include wireless fidelity Router. In this example, AP 106 is shown connected to the Internet without being connected to the core network of the wireless system, as described in further detail below. In various examples, UE 101b, RAN 110 and AP 106 may be configured to use LTE-WLAN aggregation (LWA) operation or LTW / WLAN radio level operation integrated with IPsec tunnel (LWIP). LWA operation may involve UE 101b in RRC_CONNECTED state being configured by RAN nodes 111a, 111b to utilize radio resources of LTE and WLAN. LWIP operation may involve UE 101b using IPsec protocol tunnel to use WLAN radio resources (e.g., connection 107) to authenticate and encrypt packets (e.g., IP packets) sent through connection 107. IPsec tunnel transmission may include encapsulating the entire original IP packet and adding a new packet header, thereby protecting the original header of the IP packet.

[0040] The RAN 110 includes one or more AN nodes or RAN nodes 111a and 111b (collectively referred to as "RAN nodes 111") that enable connections 103 and 104. As used herein, the terms "access node", "access point", etc. may describe equipment that provides radio baseband functions for data or voice connections or both between a network and one or more users. These access nodes may be referred to as base stations (BS), gNodeBs, gNBs, eNodeBs, eNBs, NodeBs, RAN nodes, road side units (RSUs), transmit receive points (TRxPs or TRPs), etc., and may include ground stations (e.g., terrestrial access points) or satellite stations that provide coverage within a geographic area (e.g., a cell), etc. As used herein, the terms "NG RAN nodes" and the like may refer to RAN nodes 111 (e.g., gNBs) operating in a 5G NR system 100, while the term "E-UTRAN node" may refer to RAN nodes 111 (e.g., eNBs) operating in an LTE or 4G system 100. In some examples, multiple RAN nodes 111 may be implemented as one or more of dedicated physical devices such as macrocell base stations or low power (LP) base stations for providing femtocells, picocells, or other similar cells with smaller coverage areas, smaller user capacity, or higher bandwidth than macrocells.

[0041] In some examples, some or all of the multiple RAN nodes 111 may be implemented as one or more software entities running on a server computer as part of a virtual network that may be referred to as a cloud RAN (CRAN) or a virtual baseband unit pool (vBBUP). The CRAN or vBBUP may implement RAN functional partitioning, such as a packet data convergence protocol (PDCP) partitioning, where the radio resource control (RRC) and PDCP layers are operated by the CRAN / vBBUP, and other layer 2 (e.g., data link layer) protocol entities are operated by individual RAN nodes 111; a medium access control (MAC) / physical layer (PHY) partitioning, where the RRC, PDCP, MAC, and radio link control (RLC) layers are operated by the CRAN / vBBUP, and the PHY layer is operated by individual RAN nodes 111; or a "lower PHY" partitioning, where the RRC, PDCP, RLC, and MAC layers and the upper portion of the PHY layer are operated by the CRAN / vBBUP, and the lower portion of the PHY layer is operated by individual RAN nodes 111. This virtualization framework allows idle processor cores of the RAN nodes 111 to execute, for example, other virtualized applications. In some examples, individual RAN nodes 111 may represent nodes using respective F1 interfaces ( Figure 1 In some examples, the gNB-DU may include one or more remote radio heads or RFEMs (see, e.g., Figure 2 ), and the gNB-CU may be operated by a server (not shown) located in the RAN 110 or by a server pool in a manner similar to the CRAN / vBBUP. In addition or alternatively, one or more of the RAN nodes 111 may be a next generation eNB (ng-eNB), including a RAN node that provides E-UTRA user plane and control plane protocol terminals to the UE 101 and is connected to a 5G core network (e.g., the core network 120) using a next generation interface.

[0042] In a vehicle-to-everything (V2X) scenario, one or more of the RAN nodes 111 may be or act as an RSU. The term "roadside unit" or "RSU" refers to any traffic infrastructure entity used for V2X communication. The RSU may be implemented in or by a suitable RAN node or a stationary (or relatively stationary) UE, wherein an RSU implemented in or by a UE may be referred to as a "UE-type RSU", an RSU implemented in or by an eNB may be referred to as an "eNB-type RSU", an RSU implemented in or by a gNB may be referred to as a "gNB-type RSU", and so on. In some examples, the RSU is a computing device coupled to a radio frequency circuit located on the road side that provides connectivity support to a passing vehicle UE 101 (vUE 101). The RSU may also include internal data storage circuitry for storing intersection map geometry, traffic statistics, media, and applications or other software for sensing and controlling ongoing vehicle and pedestrian traffic. The RSU may operate on the 5.9 GHz Direct Short Range Communications (DSRC) band to provide extremely low latency communications required for high-speed events, such as collision avoidance, traffic warnings, and the like. In addition or alternatively, the RSU may operate on the cellular V2X band to provide the aforementioned low latency communications as well as other cellular communications services. In addition or alternatively, the RSU may operate as a Wi-Fi hotspot (2.4 GHz band) or provide connectivity to one or more cellular networks to provide uplink and downlink communications, or both. Some or all of the computing device and the RSU's RF circuitry may be packaged in a weather-resistant enclosure suitable for outdoor installation, and may include a network interface controller to provide a wired connection (e.g., Ethernet) to a traffic signal controller or a backhaul network, or both.

[0043] Any of the RAN nodes 111 may serve as an endpoint for the air interface protocol and may be the first point of contact for the UE 101. In some examples, any of the multiple RAN nodes 111 may perform various logical functions of the RAN 110, including but not limited to functions of a radio network controller (RNC), such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[0044] In some examples, multiple UEs 101 may be configured to communicate with each other or with any of multiple RAN nodes 111 over a multi-carrier communication channel using orthogonal frequency division multiplexing (OFDM) communication signals according to various communication techniques, such as, but not limited to, OFDMA communication techniques (e.g., for downlink communications) or SC-FDMA communication techniques (e.g., for uplink and ProSe or sidelink communications), although the scope of the techniques described herein is not limited in this respect. The OFDM signal may include multiple orthogonal subcarriers.

[0045] In some examples, a downlink resource grid may be used for downlink transmissions from any of a plurality of RAN nodes 111 to a plurality of UEs 101, while uplink transmissions may utilize similar techniques. The grid may be a time-frequency grid, referred to as a resource grid or a time-frequency resource grid, which is a physical resource in the downlink in each time slot. For OFDM systems, such a time-frequency plane representation is common practice, which makes wireless resource allocation intuitive. Each column and each row of the resource grid corresponds to an OFDM symbol and an OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to a time slot in a radio frame. The smallest time-frequency unit in the resource grid is represented as a resource element. Each resource grid includes a plurality of resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block includes a set of resource elements; in the frequency domain, this may represent the minimum amount of resources that can currently be allocated. Such resource blocks are used to transmit several different physical downlink channels.

[0046] In some examples, multiple UEs 101 and multiple RAN nodes 111 communicate (e.g., transmit and receive) data over a licensed medium (also referred to as a "licensed spectrum" or "licensed band") and an unlicensed shared medium (also referred to as an "unlicensed spectrum" and / or "unlicensed band"). The licensed spectrum may include channels operating in a frequency range of approximately 400 MHz to approximately 3.8 GHz, and the unlicensed spectrum may include a 5 GHz band.

[0047] To operate in an unlicensed spectrum, multiple UEs 101 and multiple RAN nodes 111 may operate using licensed assisted access (LAA), enhanced LAA (eLAA), or additional enhanced LAA (feLAA) mechanisms. In these specific implementations, multiple UEs 101 and multiple RAN nodes 111 may perform one or more known medium sensing operations or carrier sensing operations or both to determine whether one or more channels in the unlicensed spectrum are unavailable or otherwise occupied before transmitting in the unlicensed spectrum. The medium / carrier sensing operation may be performed according to a listen-before-talk (LBT) protocol. LBT is a mechanism for equipment (e.g., multiple UEs 101, multiple RAN nodes 111) to sense a medium (e.g., a channel or carrier frequency) and transmit when the medium is sensed to be idle (or when a particular channel in the medium is sensed to be unoccupied). The medium sensing operation may include a clear channel assessment (CCA), which uses energy detection to determine whether there are other signals on the channel in order to determine whether the channel is occupied or clear. The LBT mechanism allows cellular / LAA networks to coexist with existing systems in unlicensed spectrum and with other LAA networks. Energy detection may include sensing RF energy over an intended transmission band over a period of time and comparing the sensed RF energy to a predefined or configured threshold.

[0048] The existing system in the 5 GHz band may be a WLAN based on IEEE 802.11 technology. The WLAN adopts a contention-based channel access mechanism (e.g., CSMA with collision avoidance (CSMA / CA). In some examples, when a WLAN node (e.g., a mobile station (MS) such as UE 101, AP 106, etc.) intends to transmit, the WLAN node may first perform CCA before transmitting. In addition, in the case where more than one WLAN node senses the channel as idle and transmits at the same time, a backoff mechanism is used to avoid conflicts. The backoff mechanism can be a counter randomly drawn within the contention window size (CWS), which increases exponentially when a conflict occurs and is reset to a minimum value when the transmission is successful. In some examples, the LBT mechanism designed for LAA is similar to CSMA / CA for WLAN. In some examples, the LBT process for a DL or UL transmission burst (including PDSCH or PUSCH transmission) may have a LAA contention window of variable length between X and Y extended CAA (ECCA) time slots, where X and Y are the minimum and maximum values ​​of the CWS for LAA. In one example, the minimum CWS for LAA transmission may be 9 microseconds (μs); however, the size of the CWS and the maximum channel occupancy time (e.g., transmission burst) may be based on government regulatory requirements.

[0049] In some examples, the LAA mechanism is built on the carrier aggregation technology of the LTE-Advanced system. In CA, each aggregated carrier is called a component carrier. In some examples, the component carrier may have a bandwidth of 1.4MHz, 3MHz, 5MHz, 10MHz, 15MHz, or 20MHz, and up to five component carriers may be aggregated to provide a maximum aggregate bandwidth of 100MHz. In a frequency division duplex (FDD) system, the number of aggregated carriers may be different for DL ​​and UL. For example, the number of UL component carriers may be equal to or less than the number of DL component carriers. In some cases, each component carrier may have a different bandwidth from other component carriers. In a time division duplex (TDD) system, the number of component carriers and the bandwidth of each component carrier are typically the same for DL ​​and UL.

[0050] Carrier aggregation may also include separate serving cells to provide separate component carriers. The coverage of the serving cells may be different, for example, because component carriers on different frequency bands may experience different path losses. The primary serving cell (PCell) may provide a primary component carrier for both UL and DL, and may handle RRC and non-access stratum (NAS) related activities. Other serving cells are referred to as secondary component carriers (SCells), and each SCell may provide a separate secondary component carrier for both UL and DL. Secondary component carriers may be added and removed as needed, and changing the primary component carrier may require UE 101 to undergo switching. In LAA, eLAA, and feLAA, some or all of the SCells may operate in an unlicensed spectrum (referred to as "LAA SCells"), and the LAA SCells are assisted by the PCells operating in a licensed spectrum. When a UE is configured with more than one LAA SCell, the UE may receive UL authorizations on the configured LAA SCells, indicating different PUSCH start positions within the same subframe.

[0051] The PDSCH carries user data and higher layer signaling to multiple UEs 101. The PDCCH carries, among other information, information about the transport format and resource allocation related to the PDSCH channel. It may also inform the UE 101 about the transport format, resource allocation, and hybrid automatic repeat request (HARQ) information related to the uplink shared channel. Downlink scheduling (e.g., allocating control and shared channel resource blocks to UE 101b within a cell) may be performed at any of the RAN nodes 111 based on channel quality information fed back from any of the UEs 101. Downlink resource allocation information may be sent on the PDCCH for (e.g., allocated to) each of the UEs 101.

[0052] PDCCH uses control channel elements (CCE) to transmit control information. Before being mapped to resource elements, the PDCCH complex-valued symbols can first be organized into quadruplets, which can then be arranged using a sub-block interleaver for rate matching. In some examples, one or more of these CCEs can be used to transmit each PDCCH, where each CCE can correspond to four sets of nine physical resource elements, collectively referred to as resource element groups (REGs). Four quadrature phase shift keying (QPSK) symbols can be mapped to each REG. Depending on the size of the downlink control information (DCI) and channel conditions, one or more CCEs can be used to transmit the PDCCH. In LTE, there may be four or more different PDCCH formats defined with different numbers of CCEs (e.g., aggregation levels, L=1, 2, 4, or 8).

[0053] Some implementations may use the concept of resource allocation for control channel information, which is an extension of the above concept. For example, some implementations may utilize an enhanced PDCCH (EPDCCH) that uses PDSCH resources for control information transmission. One or more enhanced CCEs (ECCEs) may be used to transmit EPDCCH. Similar to the above, each ECCE may correspond to nine sets of four physical resource elements, collectively referred to as enhanced REGs (EREGs). In some examples, ECCEs may have other numbers of EREGs.

[0054] The RAN nodes 111 are configured to communicate with each other using an interface 112. In an example, such as when the system 100 is an LTE system (e.g., when the core network 120 is an evolved packet core (EPC) network), the interface 112 may be an X2 interface 112. The X2 interface may be defined between two or more RAN nodes 111 (e.g., two or more eNBs, etc.) connected to the EPC 120, or between two eNBs connected to the EPC 120, or both. In some examples, the X2 interface may include an X2 user plane interface (X2-U) and an X2 control plane interface (X2-C). The X2-U may provide a flow control mechanism for user packets transmitted over the X2 interface, and may be used to transmit information about the delivery of user data between eNBs. For example, X2-U may provide specific sequence number information about user data transmitted from the primary eNB to the secondary eNB; information about successful in-sequence delivery of PDCP protocol data units (PDUs) from the secondary eNB to the UE 101 for user data; information about PDCP PDUs that were not delivered to the UE 101; information about the current minimum expected buffer size at the secondary eNB for transmitting user data to the UE; etc. X2-C may provide intra-LTE access mobility functions, including context transfer from a source eNB to a target eNB, or user plane transmission control; load management functions; inter-cell interference coordination functions; etc.

[0055] In some examples, such as when system 100 is a 5G NR system (e.g., when core network 120 is such as Figure 3), the interface 112 may be an Xn interface 112. The Xn interface may be defined between two or more RAN nodes 111 (e.g., two or more gNBs, etc.) connected to the 5G core network 120, between a RAN node 111 (e.g., a gNB) and an eNB connected to the 5G core network 120, or between two eNBs connected to the 5G core network 120, or a combination of the above. In some examples, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. The Xn-U may provide non-guaranteed delivery of user plane PDUs and support / provide data forwarding and flow control functions. The Xn-C may provide management and error handling functions for managing functions of the Xn-C interface; mobility support for UE 101 in a connected mode (e.g., CM-CONNECTED), including functions for managing UE mobility in a connected mode between one or more RAN nodes 111; and the like. Mobility support may include context transfer from the old (source) serving RAN node 111 to the new (target) serving RAN node 111, and control of the user plane tunnel between the old (source) serving RAN node 111 and the new (target) serving RAN node 111. The protocol stack of Xn-U may include a transport network layer built on an Internet Protocol (IP) transport layer, and a GPRS Tunneling Protocol (GTP-U) layer for carrying user plane PDUs on top of a user datagram protocol (UDP) or IP layer or both. The Xn-C protocol stack may include an application layer signaling protocol (referred to as the Xn Application Protocol (Xn-AP)) and a transport network layer built on a stream control transmission protocol (SCTP). SCTP may be on top of the IP layer and may provide guaranteed delivery of application layer messages. In the transport IP layer, point-to-point transport is used to deliver signaling PDUs. In other specific implementations, the Xn-U protocol stack or the Xn-C protocol stack or both may be the same or similar to the user plane and / or control plane protocol stacks shown and described herein.

[0056] RAN 110 is shown as being communicatively coupled to a core network 120 (referred to as "CN 120"). The CN 120 includes one or more network elements 122 configured to provide various data and telecommunication services to customers / subscribers (e.g., users of UE 101) connected to CN 120 using RAN 110. Components of CN 120 may be implemented in one physical node or separate physical nodes and may include components for reading and executing instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In some examples, network function virtualization (NFV) may be used to virtualize some or all of the network node functions described herein using executable instructions stored in one or more computer-readable storage media, as will be described in further detail below. A logical instance of CN 120 may be referred to as a network slice, and a logical instance of a portion of CN 120 may be referred to as a network sub-slice. NFV architecture and infrastructure may be used to virtualize one or more network functions onto physical resources comprising a combination of industry-standard server hardware, storage hardware, or switches (alternatively performed by proprietary hardware). In other words, a NFV system may be used to perform virtual or reconfigurable implementations, or both, of one or more network components or functions.

[0057] In general, the application server 130 may be an element that provides applications that use IP bearer resources with the core network (e.g., UMTS packet service (PS) domain, LTE PS data service, etc.). The application server 130 may also be configured to utilize the CN 120 to support one or more communication services for the UE 101 (e.g., VoIP sessions, PTT sessions, group communication sessions, social network services, etc.).

[0058] In some examples, CN 120 may be a 5G core network (referred to as "5GC 120"), and RAN 110 may be connected to CN 120 using a next generation interface 113. In some examples, next generation interface 113 may be divided into two parts: a next generation user plane (NG-U) interface 114, which carries traffic data between multiple RAN nodes 111 and a user plane function (UPF); and an S1 control plane (NG-C) interface 115, which is a signaling interface between the RAN node 111 and an access and mobility management function (AMF). Reference Figure 3 Discussed in more detail, CN 120 is an example of 5GC 120.

[0059] In some examples, CN 120 may be an EPC (referred to as “EPC 120” or the like), and RAN 110 may be connected to CN 120 using an S1 interface 113. In some examples, S1 interface 113 may be divided into two parts: an S1 user plane (S1-U) interface 114, which carries traffic data between RAN node 111 and a serving gateway (S-GW); and an S1-MME interface 115, which is a signaling interface between RAN node 111 and a mobility management entity (MME).

[0060] Figure 2 An example of infrastructure equipment 400 is shown. Infrastructure equipment 400 (or "system 400") can be implemented as a base station, a radio head, a RAN node (such as the RAN node 111 or AP 106 shown and described previously), an application server 130, or any other component or device described herein. In other examples, system 400 can be implemented in or by a UE.

[0061] System 400 includes: application circuit 405, baseband circuit 410, one or more radio front end modules (RFEM) 415, memory circuit 420, power management integrated circuit (PMIC) 425, power tee circuit 430, network controller circuit 435, network interface connector 440, satellite positioning circuit 445 and user interface circuit 450. In some examples, system 400 may include additional elements such as, for example, memory, storage, display, camera, one or more sensors or input / output (I / O) interface or a combination thereof. In other examples, the components described with reference to system 400 may be included in more than one device. For example, various circuits may be separately included in more than one device for CRAN, vBBU or other specific implementations.

[0062] The application circuit 405 may include circuits such as, but not limited to, one or more processors (or processor cores), cache memory, one or more of the following: a low dropout regulator (LDO), an interrupt controller, a serial interface such as SPI, I2C or a general programmable serial interface module, a real-time clock (RTC), a timer-counter including an interval timer and a watchdog timer, a general input / output (I / O or IO), a memory card controller such as a secure digital (SD) multimedia card (MMC) or similar products, a universal serial bus (USB) interface, a mobile industry processor interface (MIPI) interface, and a joint test access group (JTAG) test access port. The processor (or core) of the application circuit 405 may be coupled to or may include a memory or storage element, and may be configured to execute instructions stored in the memory or storage element to enable various applications or operating systems to run on the system 400. In some examples, the memory or storage element may include an on-chip memory circuit, which may include any suitable volatile or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, or a combination thereof, etc.

[0063] The processor of the application circuit 405 may include, for example, one or more processor cores (CPUs), one or more application processors, one or more graphics processing units (GPUs), one or more reduced instruction set computing (RISC) processors, one or more Acorn RISC Machine (ARM) processors, one or more complex instruction set computing (CISC) processors, one or more digital signal processors (DSPs), one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, or a combination thereof, etc. In some examples, the application circuit 405 may include or may be a dedicated processor or controller configured to perform various techniques described herein. As an example, the processor of the application circuit 405 may include one or more Intel FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, or a combination thereof. or Processor: Advanced Micro Devices (AMD) Processor, Accelerated Processing Unit (APU) or processors; ARM-based processors licensed by ARM Holdings, Ltd., such as the ARM Cortex-A series processors provided by Cavium(TM), Inc. and A MIPS-based design from MIPS Technologies, Inc., such as a MIPS Warrior P-class processor; etc. In some examples, system 400 may not utilize application circuit 405, and instead may include a dedicated processor or controller to process IP data received, for example, from an EPC or 5GC.

[0064] In some examples, the application circuit 405 may include one or more hardware accelerators, which may be microprocessors, programmable processing devices, etc. The one or more hardware accelerators may include, for example, computer vision (CV) or deep learning (DL) accelerators or both. In some examples, the programmable processing device may be one or more field programmable devices (FPDs), such as field programmable gate arrays (FPGAs), etc.; programmable logic devices (PLDs), such as complex PLDs (CPLDs) or high-capacity PLDs (HCPLDs); ASICs, such as structured ASICs; programmable SoCs (PSoCs), or combinations thereof, etc. In such specific implementations, the circuits of the application circuit 405 may include logic blocks or logic architectures, as well as other interconnected resources that can be programmed to perform various functions such as the processes, methods, functions described herein. In some examples, the circuitry of application circuit 405 may include memory cells (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, static memory (e.g., static random access memory (SRAM), or anti-fuse)) for storing logic blocks, logic architectures, data, or other data in a look-up table (LUT), etc.

[0065] Baseband circuit 410 may be implemented, for example, as a solder-in substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more integrated circuits. Figure 4 Various hardware electronic components of baseband circuit 410 are discussed.

[0066] The user interface circuit 450 may include one or more user interfaces designed to enable a user to interact with the system 400 or a peripheral component interface designed to enable a peripheral component to interact with the system 400. The user interface may include, but is not limited to, one or more physical or virtual buttons (e.g., a reset button), one or more indicators (e.g., light emitting diodes (LEDs)), a physical keyboard or keypad, a mouse, a touch pad, a touch screen, a speaker or other audio transmitting device, a microphone, a printer, a scanner, a headset, a display screen or display device, or a combination thereof, etc. The peripheral component interface may include, but is not limited to, a non-volatile memory port, a universal serial bus (USB) port, an audio jack, a power interface, etc.

[0067] The radio front end module (RFEM) 415 may include a millimeter wave (mmWave) RFEM and one or more sub-millimeter wave radio frequency integrated circuits (RFICs). In some examples, the one or more sub-millimeter wave RFICs may be physically separated from the mmWave RFEM. The RFIC may include connections to one or more antennas or antenna arrays (see, e.g., Figure 4 The antenna array 611) can be connected to multiple antennas, and the RFEM can be connected to multiple antennas. In some examples, both millimeter wave and sub-millimeter wave radio functions can be implemented in the same physical RFEM 415 that combines both millimeter wave antennas and sub-millimeter waves.

[0068] Memory circuit 420 may include one or more of the following: volatile memory, such as dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM); and non-volatile memory (NVM), such as high-speed electrically erasable memory (commonly referred to as flash memory), phase change random access memory (PRAM), or magnetoresistive random access memory (MRAM), or a combination thereof. In some examples, memory circuit 420 may include a memory device obtained from and For example, the memory circuit 420 may be implemented as one or more of the following: a solder-in package integrated circuit, a socket memory module, and a plug-in memory card.

[0069] The PMIC 425 may include a voltage regulator, a surge protector, a power alarm detection circuit, and one or more backup power sources, such as a battery or capacitor. The power alarm detection circuit may detect one or more of a brownout (undervoltage) and a surge (overvoltage) condition. The power tee circuit 430 may provide power extracted from the network cable to provide both power and data connections for the infrastructure equipment 400 using a single cable.

[0070] The network controller circuit 435 may provide connectivity to the network using a standard network interface protocol such as Ethernet, Ethernet based on a GRE tunnel, Ethernet based on a multi-protocol label switching (MPLS), or some other suitable protocol. Network connectivity may be provided to and from the infrastructure equipment 400 using a network interface connector 440 using a physical connection, which may be an electrical connection (commonly referred to as a "copper interconnect"), an optical connection, or a wireless connection. The network controller circuit 435 may include one or more dedicated processors or FPGAs, or both, for communicating using one or more of the aforementioned protocols. In some examples, the network controller circuit 435 may include multiple controllers for providing connectivity to other networks using the same or different protocols.

[0071] The positioning circuit 445 includes a circuit for receiving and decoding signals transmitted or broadcast by a positioning network of a global navigation satellite system (GNSS). Examples of GNSS include the Global Positioning System (GPS) of the United States, the Global Navigation System (GLONASS) of Russia, the Galileo system of the European Union, the Beidou Navigation Satellite System of China, a regional navigation system or a GNSS augmentation system (e.g., using the Indian constellation (NAVIC), the Quasi-Zenith Satellite System (QZSS) of Japan, the Doppler Orbit Chart and Satellite Integrated Radio Positioning (DORIS) of France for navigation), etc. The positioning circuit 445 may include various hardware elements (e.g., including hardware devices such as switches, filters, amplifiers, antenna elements, etc. for facilitating OTA communication) to communicate with components of the positioning network such as navigation satellite constellation nodes. In some examples, the positioning circuit 445 may include a micro technology (micro PNT) IC for positioning, navigation and timing, which uses a master timing clock to perform position tracking and estimation without GNSS assistance. The positioning circuit 445 may also be part of or interact with the baseband circuit 410 or RFEM 415 or both to communicate with nodes and components of the positioning network. The positioning circuitry 445 may also provide data (eg, location data, time data) to the application circuitry 405 , which may use the data to synchronize operations with various infrastructure (eg, RAN node 111 , etc.).

[0072] Figure 2 The components shown can communicate with each other using interface circuits that can include any number of bus or interconnect (IX) technologies, such as industry standard architecture (ISA), extended ISA (EISA), peripheral component interconnect (PCI), peripheral component interconnect extended (PCIx), PCI express (PCIe), or any number of other technologies. The bus or IX can be a proprietary bus, for example, used in a SoC-based system. Other bus or IX systems can be included, such as an I2C interface, an SPI interface, a point-to-point interface, and a power bus, etc.

[0073] Figure 3 An example of a platform 500 (or "device 500") is shown. In some examples, the computer platform 500 may be suitable for use as a UE 101, 201, 301, an application server 130, or any other component or device discussed herein. The platform 500 may include any combination of the components shown in the examples. The components (or portions thereof) of the platform 500 may be implemented as integrated circuits (ICs), discrete electronic devices, or other modules, logic, hardware, software, firmware, or combinations thereof adapted in the computer platform 500, or as components otherwise incorporated within the chassis of a larger system. Figure 3The block diagram is intended to show a high-level view of the components of platform 500. However, in some examples, platform 500 may include fewer, additional, or alternative components, or include Figure 3 Different arrangements of components are shown.

[0074] The application circuit 505 includes circuits such as, but not limited to, one or more processors (or processor cores), cache memory, and one or more LDOs, interrupt controllers, serial interfaces (such as SPI), I2C or general programmable serial interface modules, RTCs, timers-counters (including interval timers and watchdog timers), general I / Os, memory card controllers (such as SD MMC or similar controllers), USB interfaces, MIPI interfaces, and JTAG test access ports. The processor (or core) of the application circuit 505 may be coupled to or may include a memory / storage element, and may be configured to execute instructions stored in the memory or storage device to enable various applications or operating systems to run on the system 500. In some examples, the memory or storage element may be an on-chip memory circuit, which may include any suitable volatile or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, or a combination thereof.

[0075] The processor of application circuit 405 may include, for example, one or more processor cores, one or more application processors, one or more GPUs, one or more RISC processors, one or more ARM processors, one or more CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, multi-threaded processors, ultra-low voltage processors, embedded processors, some other known processing elements, or any suitable combination thereof. In some examples, application circuit 405 may include or may be a dedicated processor / controller for performing techniques described herein.

[0076] As an example, the processor of the application circuit 505 may include a processor based on Architecture TM Processors such as Quark TM 、Atom TM , i3, i5, i7 or MCU class processors, or available from Santa Clara, CA The processor of application circuit 505 may also be one or more of the following: Advanced Micro Devices (AMD) Processor or Accelerated Processing Unit (APU); from Inc.'s A5-A9 processors, Snapdragon by Technologies, Inc. TM Processor, Texas Instruments, OpenMultimedia Applications Platform(OMAP) TM processors; MIPS-based designs from MIPS Technologies, Inc., such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings, Ltd., such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; etc. In some examples, application circuit 505 can be part of a system on a chip (SoC), in which application circuit 505 and other components are formed as a single integrated circuit or a single package, such as company( Edison Corporation TM or Galileo TM SoC board.

[0077] Additionally or alternatively, the application circuit 505 may include circuits such as, but not limited to, one or more field programmable devices (FPDs) such as FPGAs; programmable logic devices (PLDs), such as complex PLDs (CPLDs), high capacity PLDs (HCPLDs); ASICs, such as structured ASICs; programmable SoCs (PSoCs), or combinations thereof, etc. In some examples, the application circuit 505 may include logic blocks or logic structures, and other interconnected resources that may be programmed to perform various functions such as the processes, methods, functions described herein. In some examples, the application circuit 505 may include memory cells (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, static memory (e.g., static random access memory (SRAM) or antifuse)) for storing logic blocks, logic structures, data or other data in a lookup table (LUT), etc.

[0078] Baseband circuit 510 may be implemented, for example, as a solder-in substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more integrated circuits. Figure 4 Various hardware electronic components of baseband circuit 510 are discussed.

[0079] The RFEM 515 may include a millimeter wave (mmWave) RFEM and one or more sub-millimeter wave radio frequency integrated circuits (RFICs). In some examples, the one or more sub-millimeter wave RFICs may be physically separated from the mmWave RFEM. The RFIC may include connections to one or more antennas or antenna arrays (see, e.g., Figure 4 The antenna array 611) can be connected to multiple antennas, and the RFEM can be connected to multiple antennas. In some examples, both millimeter wave and sub-millimeter wave radio functions can be implemented in the same physical RFEM 515 that combines both millimeter wave antennas and sub-millimeter waves.

[0080] The memory circuit 520 may include any number and type of memory devices for providing a fixed amount of system memory. As an example, the memory circuit 520 may include one or more of the following: volatile memory, such as random access memory (RAM), dynamic RAM (DRAM) or synchronous dynamic RAM (SDRAM); and non-volatile memory (NVM), such as high-speed electrically erasable memory (commonly referred to as flash memory), phase change random access memory (PRAM), or magnetoresistive random access memory (MRAM) or a combination thereof. The memory circuit 520 may be developed according to the Joint Electron Device Engineering Council (JEDEC) based low power double data rate (LPDDR) design such as LPDDR2, LPDDR3, LPDDR4, etc. The memory circuit 520 may be implemented as one or more of the following: a solder-in package integrated circuit, a single die package (SDP), a dual die package (DDP) or a quad die package (Q17P), a socketed memory module, a dual in-line memory module (DIMM) including a micro DIMM or a mini DIMM, or soldered to a motherboard using a ball grid array (BGA). In a low-power implementation, the memory circuit 520 may be an on-chip memory or register associated with the application circuit 505. To provide persistent storage of information such as data, applications, operating systems, etc., the memory circuit 520 may include one or more mass storage devices, which may include, for example, a solid-state disk drive (SSDD), a hard disk drive (HDD), a micro HDD, a resistive change memory, a phase change memory, a holographic memory, or a chemical memory. In some examples, the computer platform 500 may be combined with a computer obtained from and Three-dimensional (3D) cross-point (XPOINT) memory.

[0081] The removable memory circuit 523 may include a device, circuit, housing, casing, port or socket, etc., for coupling a portable data storage device to the platform 500. These portable data storage devices may be used for mass storage and may include, for example, flash memory cards (e.g., Secure Digital (SD) cards, micro SD cards, xD picture cards), as well as USB flash drives, optical disks, or external HDDs, or combinations thereof, etc.

[0082] The platform 500 may further include an interface circuit (not shown) for connecting external devices to the platform 500. External devices connected to the platform 500 using the interface circuit include a sensor circuit 521 and an electromechanical component (EMC) 522, and a removable memory device coupled to a removable memory circuit 523.

[0083] Sensor circuit 521 includes a device, module, or subsystem that is intended to detect events or changes in its environment and send information about the detected events (e.g., sensor data) to one or more other devices, modules, or subsystems. Examples of such sensors include: an inertial measurement unit (IMU), such as an accelerometer, gyroscope, or magnetometer; a microelectromechanical system (MEMS) or nanoelectromechanical system (NEMS) including a three-axis accelerometer, a three-axis gyroscope, or a magnetometer; a liquid level sensor; a flow sensor; a temperature sensor (e.g., a thermistor); a pressure sensor; a barometric pressure sensor; a gravity meter; an altimeter; an image capture device (e.g., a camera or a lensless aperture); a light detection and ranging (LiDAR) sensor; a proximity sensor (e.g., an infrared radiation detector, etc.), a depth sensor, an ambient light sensor, an ultrasonic transceiver; a microphone or other audio capture device, or a combination thereof, etc.

[0084] The EMC 522 includes devices, modules or subsystems that are intended to enable the platform 500 to change its state, position, or orientation or to move or control a mechanism, system or subsystem. In addition, the EMC 522 may be configured to generate messages or signaling and send messages or signaling to other components of the platform 500 to indicate the current state of the EMC 522. Examples of EMC 522 include one or more power switches, relays (such as electromechanical relays (EMRs) or solid-state relays (SSRs)), actuators (e.g., valve actuators), audible sound generators, visual warning devices, motors (e.g., DC motors or stepper motors), wheels, thrusters, propellers, claws, clamps, hooks, or combinations thereof, in addition to other electromechanical components. In some examples, the platform 500 is configured to operate one or more EMCs 522 based on one or more capture events, instructions or control signals received from a service provider or client or both.

[0085] In some examples, the interface circuit may connect the platform 500 to the positioning circuit 545. The positioning circuit 545 includes a circuit for receiving and decoding signals transmitted or broadcast by a positioning network of a GNSS. Examples of GNSS may include the United States' GPS, Russia's GLONASS, the European Union's Galileo system, China's Beidou navigation satellite system, a regional navigation system or a GNSS augmentation system (e.g., NAVIC), Japan's QZSS, France's DORIS, etc. The positioning circuit 545 includes various hardware elements (e.g., including hardware devices such as switches, filters, amplifiers, antenna elements, etc. for facilitating OTA communications) to communicate with components of the positioning network such as navigation satellite constellation nodes. In some examples, the positioning circuit 545 may include a micro PNT IC that uses a master timing clock to perform position tracking or estimation without GNSS assistance. The positioning circuit 545 may also be part of or interact with the baseband circuit 410 or RFEM 515 or both to communicate with nodes and components of the positioning network. Positioning circuitry 545 may also provide data (eg, position data, time data) to application circuitry 505, which may use the data to synchronize operations with various infrastructure (eg, radio base stations), for turn-by-turn navigation applications, and the like.

[0086] In some examples, the interface circuit may connect the platform 500 with a near field communication (NFC) circuit 540. The NFC circuit 540 is configured to provide contactless short-range communication based on the radio frequency identification (RFID) standard, wherein a magnetic field is sensed to enable communication between the NFC circuit 540 and an NFC-enabled device (e.g., an "NFC touch point") external to the platform 500. The NFC circuit 540 includes an NFC controller coupled to an antenna element and a processor coupled to the NFC controller. The NFC controller may be a chip or IC that provides NFC functionality to the NFC circuit 540 by executing an NFC controller firmware and an NFC stack. The NFC stack may be executed by the processor to control the NFC controller, and the NFC controller firmware may be executed by the NFC controller to control the antenna element to transmit a short-range RF signal. The RF signal may power a passive NFC tag (e.g., a microchip embedded in a sticker or wristband) to transfer stored data to the NFC circuit 540, or initiate data transfer between the NFC circuit 540 and another active NFC device (e.g., a smart phone or an NFC-enabled POS terminal) close to the platform 500.

[0087] The driver circuit 546 may include software and hardware elements for controlling specific devices embedded in, attached to, or otherwise communicatively coupled to the platform 500. The driver circuit 546 may include various drivers to allow other components of the platform 500 to interact with or control various input / output (I / O) devices that may be present in or connected to the platform 500. For example, the driver circuit 546 may include: a display driver for controlling and allowing access to a display device, a touch screen driver for controlling and allowing access to a touch screen interface of the platform 500, a sensor driver for obtaining sensor readings of the sensor circuit 521 and controlling and allowing access to the sensor circuit 521, an EMC driver for obtaining an actuator position of the EMC 522 or controlling and allowing access to the EMC 522, a camera driver for controlling and allowing access to an embedded image capture device, and an audio driver for controlling and allowing access to one or more audio devices.

[0088] A power management integrated circuit (PMIC) 525 (also referred to as “power management circuit 525”) may manage power provided to various components of the platform 500. Specifically, the PMIC 525 may control power selection, voltage scaling, battery charging, or DC-DC conversion with respect to the baseband circuit 510. The PMIC 525 may be included when the platform 500 is capable of being powered by a battery 530, for example, when the device is included in a UE 101, 201, 301.

[0089] In some examples, the PMIC 525 may control or otherwise be part of various power saving mechanisms of the platform 500. For example, if the platform 500 is in the RRC_Connected state, in which the platform is still connected to the RAN node because it expects to receive traffic soon, then after a period of inactivity, the platform may enter a state known as discontinuous reception mode (DRX). During this state, the platform 500 may be powered off for short time intervals, thereby saving power. If there is no data traffic activity for a longer period of time, the platform 500 may transition to the RRC_Idle state, in which it is disconnected from the network and does not perform operations such as channel quality feedback or switching. This may allow the platform 500 to enter a very low power state in which it periodically wakes up to listen to the network and then powers off again. In some examples, the platform 500 may not receive data in the RRC_Idle state, but must transition back to the RRC_Connected state to receive data. Additional power saving modes may prevent the device from using the network for longer than the paging interval (ranging from a few seconds to a few hours). During this period, the device may not be able to connect to the network and may be completely powered off. Any data sent during this period may be significantly delayed, and it is assumed that the delay is acceptable.

[0090] Battery 530 can power platform 500, but in some examples, platform 500 can be deployed in a fixed location and can have a power source coupled to a power grid. Battery 530 can be a lithium-ion battery, a metal-air battery such as a zinc-air battery, an aluminum-air battery, or a lithium-air battery, etc. In some examples, such as in V2X applications, battery 530 can be a typical lead-acid car battery.

[0091] In some examples, the battery 530 may be a "smart battery" that includes or is coupled to a battery management system (BMS) or a battery monitoring integrated circuit. The BMS may be included in the platform 500 to track the state of charge (SoCh) of the battery 530. The BMS may be used to monitor other parameters of the battery 530, such as the state of health (SoH) and state of function (SoF) of the battery 530 to provide fault prediction. The BMS may transmit information about the battery 530 to the application circuit 505 or other components of the platform 500. The BMS may also include an analog-to-digital (ADC) converter that allows the application circuit 505 to directly monitor the voltage of the battery 530 or the current from the battery 530. The battery parameters may be used to determine actions that the platform 500 may perform, such as transmission frequency, network operation, sensing frequency, etc.

[0092] A power block or other power source coupled to the grid can be coupled to the BMS to charge the battery 530. In some examples, the power block 530 can be replaced with a wireless power receiver to obtain power wirelessly, for example, through a loop antenna in the computer platform 500. In these examples, a wireless battery charging circuit can be included in the BMS. The specific charging circuit selected can depend on the size of the battery 530 and therefore the required current. Charging can be performed using the aviation fuel standard published by the Aviation Fuel Alliance, the Qi wireless charging standard published by the Wireless Power Alliance, or the Rezence charging standard published by the Wireless Power Alliance.

[0093] The user interface circuit 550 includes various input / output (I / O) devices present in or connected to the platform 500, and includes one or more user interfaces designed to implement user interaction with the platform 500 or peripheral component interfaces designed to implement interaction with peripheral components of the platform 500. The user interface circuit 550 includes input device circuits and output device circuits. The input device circuit includes any physical or virtual means for accepting input, including one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, a keypad, a mouse, a touchpad, a touch screen, a microphone, a scanner, or a headset, or a combination thereof, etc. The output device circuit includes any physical or virtual means for displaying information or otherwise conveying information (such as sensor readings, actuator positions, or other information). The output device circuitry may include any number or combination of audio or visual displays, including one or more simple visual outputs or indicators (e.g., binary state indicators (e.g., light emitting diodes (LEDs)), multi-character visual outputs, or more complex outputs, such as a display device or touch screen (e.g., a liquid crystal display (LCD), an LED display, a quantum dot display, or a projector), where the output of characters, graphics, or multimedia objects is generated or produced by the operation of the platform 500. The output device circuitry may also include a speaker or other audio emitting device, or a printer. In some examples, the sensor circuitry 521 may be used as an input device circuit (e.g., an image capture device or a motion capture device) and one or more EMCs may be used as an output device circuit (e.g., an actuator for providing tactile feedback). In another example, an NFC circuit may be included to read an electronic tag or connect to another NFC-enabled device, the NFC circuitry including an NFC controller and a processing device coupled to an antenna element. The peripheral component interface may include, but is not limited to, a non-volatile memory port, a USB port, an audio jack, or a power interface.

[0094] Although not shown, the components of platform 500 can communicate with each other using a suitable bus or interconnect (IX) technology, which can include any number of technologies, including ISA, EISA, PCI, PCIx, PCIe, time-triggered protocol (TTP) systems, FlexRay systems, or any number of other technologies. The bus or IX can be a proprietary bus or IX, for example, used in a SoC-based system. Other bus or IX systems can be included, such as an I2C interface, an SPI interface, a point-to-point interface, and a power bus, etc.

[0095] Figure 4 6 and 615. The baseband circuit 610 may correspond to Figure 4 The baseband circuit 410 and Figure 5The baseband circuit 510 of FIG. RFEM 615 may correspond to Figure 4 RFEM415 and Figure 5 RFEM 515. As shown in the figure, RFEM 615 may include a radio frequency (RF) circuit 606, a front end module (FEM) circuit 608, and an antenna array 611 coupled together.

[0096] The baseband circuit 610 includes circuits or control logic components or both, which are configured to execute various radio or network protocols and control functions that enable communication with one or more radio networks using the RF circuit 606. The radio control functions may include, but are not limited to, signal modulation and demodulation, encoding and decoding, and radio frequency shifting. In some examples, the modulation and demodulation circuits of the baseband circuit 610 may include fast Fourier transform (FFT), precoding or constellation mapping and demapping functions. In some examples, the encoding and decoding circuits of the baseband circuit 610 may include convolution, tail-biting convolution, turbo, Viterbi, or low-density parity check (LDPC) encoder and decoder functions. The modulation and demodulation and encoder and decoder functions are not limited to these examples and may include other suitable functions in other examples. The baseband circuit 610 is configured to process baseband signals received from the receive signal path of the RF circuit 606 and generate baseband signals for the transmit signal path of the RF circuit 606. The baseband circuit 610 is configured to communicate with application circuits (e.g., Figure 4 and Figure 5 4 and 505) to generate and process baseband signals and control the operation of RF circuitry 606. Baseband circuitry 610 may handle various radio control functions.

[0097] The aforementioned circuits and control logic components of the baseband circuit 610 may include one or more single-core or multi-core processors. For example, the one or more processors may include a 3G baseband processor 604A, a 4G or LTE baseband processor 604B, a 5G or NR baseband processor 604C, or some other baseband processors 604D for other existing generations, generations under development or generations to be developed in the future (e.g., the sixth generation (6G)). In some examples, some or all of the functions of the baseband processors 604A-604D may be included in a module stored in the memory 604G and executed using a central processing unit (CPU) 604E. In some examples, some or all of the functions of the baseband processors 604A-604D may be provided as a hardware accelerator (e.g., FPGA or ASIC) loaded with an appropriate bitstream or logic block stored in a corresponding memory unit. In some examples, the memory 604G may store program code of a real-time OS (RTOS), which, when executed by the CPU 604E (or other baseband processor), is used to enable the CPU 604E (or other baseband processor) to manage resources of the baseband circuit 610, schedule tasks, or perform other operations. Examples of RTOS may include Operating System Embedded (OSE) provided TM , by Mentor Nucleus RTOS provided TM , by Mentor Versatile Real-Time Executive (VRTX) provided by Express Provided by ThreadX TM ,Depend on FreeRTOS and REX OS provided by Open Kernel (OK) OKL4 is provided, or any other suitable RTOS, such as those discussed herein. In addition, the baseband circuit 610 includes one or more audio digital signal processors (DSPs) 604F. The audio DSP 604F includes elements for compression and decompression and echo cancellation, and may include other suitable processing elements in some examples.

[0098] In some examples, each of processors 604A-604E includes a corresponding memory interface to send data to and receive data from memory 604G. Baseband circuit 610 may also include one or more interfaces for communicatively coupling to other circuits or devices, such as an interface for sending data to and receiving data from a memory external to baseband circuit 610; an interface for sending data to and receiving data from a memory external to the baseband circuit; Figure 4 and Figure 6The application circuit interface for sending data to and receiving data from the application circuit 405, 505; Figure 4 RF circuit interface for sending data to and receiving data from the RF circuit 606; for receiving data from one or more wireless hardware elements (e.g., near field communication (NFC) components, Low power consumption components, components, etc.) to send data and receive data from these wireless hardware elements; and a power management interface for sending power or control signals to the PMIC 525 and receiving power or control signals from the PMIC.

[0099] In some examples (which may be combined with the above examples), the baseband circuit 610 includes one or more digital baseband systems, which are coupled to each other and to the CPU subsystem, the audio subsystem, and the interface subsystem using an interconnection subsystem. The digital baseband subsystem may also be coupled to the digital baseband interface and the mixed signal baseband subsystem using another interconnection subsystem. Each of the interconnection subsystems may include a bus system, a point-to-point connector, a network on chip (NOC) structure, or some other suitable bus or interconnection technology, such as those discussed herein. The audio subsystem may include a DSP circuit, a buffer memory, a program memory, a voice processing accelerator circuit, a data converter circuit such as an analog-to-digital converter circuit and a digital-to-analog converter circuit, an analog circuit including one or more of an amplifier and a filter, etc. In some examples, the baseband circuit 610 may include a protocol processing circuit having one or more control circuit instances (not shown) to provide control functions for a digital baseband circuit or a radio frequency circuit (e.g., a radio front end module 615).

[0100] although Figure 4Not shown, but in some examples, the baseband circuit 610 includes various processing devices (e.g., a "multi-protocol baseband processor" or "protocol processing circuit") to operate one or more wireless communication protocols and various processing devices to implement PHY layer functions. In some examples, the PHY layer functions include the aforementioned radio control functions. In some examples, the protocol processing circuit operates or implements various protocol layers or entities of one or more wireless communication protocols. For example, when the baseband circuit 610 or the RF circuit 606 or both are part of a millimeter wave communication circuit or some other suitable cellular communication circuit, the protocol processing circuit may operate an LTE protocol entity or a 5G NR protocol entity or both. In this example, the protocol processing circuit may operate MAC, RLC, PDCP, SDAP, RRC, and NAS functions. In some examples, when the baseband circuit 610 or the RF circuit 606 or both are part of a Wi-Fi communication system, the protocol processing circuit may operate one or more IEEE-based protocols. In this example, the protocol processing circuit may operate Wi-Fi MAC and logical link control (LLC) functions. The protocol processing circuitry may include one or more memory structures (e.g., 604G) for storing program code and data for operating protocol functions, and one or more processing cores for executing program code and performing various operations using data. The baseband circuitry 610 may also support radio communications for more than one wireless protocol.

[0101] The various hardware elements of the baseband circuit 610 discussed herein may be implemented as, for example, a solder-in substrate including one or more integrated circuits (ICs), a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more ICs. In some examples, the components of the baseband circuit 610 may be appropriately combined in a single chip or a single chipset, or disposed on the same circuit board. In some examples, some or all of the components of the baseband circuit 610 and the RF circuit 606 may be implemented together, such as, for example, a system on a chip (SoC) or a system-level package (SiP). In some examples, some or all of the components of the baseband circuit 610 may be implemented as a separate SoC communicatively coupled to the RF circuit 606 (or multiple instances of the RF circuit 606). In some examples, some or all of the components of the baseband circuit 610 and the application circuits 405, 505 may be implemented together as a separate SoC mounted to the same circuit board (e.g., a "multi-chip package").

[0102] In some examples, baseband circuitry 610 may provide communications compatible with one or more radio technologies. For example, baseband circuitry 610 may support communications with E-UTRAN or other WMANs, WLANs, or WPANs. Examples in which baseband circuitry 610 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

[0103] RF circuit 606 can use modulated electromagnetic radiation to achieve communication with a wireless network through a non-solid medium. In some examples, RF circuit 606 may include components such as switches, filters, or amplifiers to facilitate communication with a wireless network. RF circuit 606 may include a receive signal path, which may include circuits for down-converting RF signals received from FEM circuit 608 and providing baseband signals to baseband circuit 610. RF circuit 606 may also include a transmit signal path, which may include circuits for up-converting baseband signals provided by baseband circuit 610 and providing RF output signals for transmission to FEM circuit 608.

[0104] The receive signal path of the RF circuit 606 includes a mixer circuit 606a, an amplifier circuit 606b, and a filter circuit 606c. In some examples, the transmit signal path of the RF circuit 606 may include a filter circuit 606c and a mixer circuit 606a. The RF circuit 606 also includes a synthesizer circuit 606d for synthesizing frequencies used by the mixer circuit 606a for the receive signal path and the transmit signal path. In some examples, the mixer circuit 606a of the receive signal path may be configured to down-convert the RF signal received from the FEM circuit 608 based on the synthesized frequency provided by the synthesizer circuit 606d. The amplifier circuit 606b may be configured to amplify the down-converted signal, and the filter circuit 606c may be a low pass filter (LPF) or a band pass filter (BPF) configured to remove unwanted signals from the down-converted signal to generate an output baseband signal. The output baseband signal may be provided to the baseband circuit 610 for further processing. In some examples, the output baseband signal can be a zero frequency baseband signal, although this is not required.In some examples, the mixer circuit 606a of the receive signal path can include a passive mixer.

[0105] In some examples, mixer circuit 606a of the transmit signal path can be configured to upconvert an input baseband signal based on a synthesized frequency provided by synthesizer circuit 606d to generate an RF output signal for FEM circuit 608. The baseband signal can be provided by baseband circuit 610 and can be filtered by filter circuit 606c.

[0106] In some examples, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may include two or more mixers and may be arranged for orthogonal down-conversion and up-conversion, respectively. In some examples, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may include two or more mixers and may be arranged for image suppression (e.g., Hartley image suppression). In some examples, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may be arranged for direct down-conversion and direct up-conversion, respectively. In some examples, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may be configured for superheterodyne operation.

[0107] In some examples, the output baseband signal and the input baseband signal may be analog baseband signals. In some examples, the output baseband signal and the input baseband signal may be electronic baseband signals, and the RF circuit 606 may include an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) circuit, and the baseband circuit 610 may include a digital baseband interface to communicate with the RF circuit 606.

[0108] In some dual-mode examples, separate radio IC circuits may be provided to process signals for each spectrum, but the techniques described herein are not limited in this respect.

[0109] In some examples, synthesizer circuit 606d can be a fractional-N synthesizer or a fractional N / N+1 synthesizer, although other types of frequency synthesizers can be used. For example, synthesizer circuit 606d can be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer including a phase-locked loop with a frequency divider.

[0110] Synthesizer circuit 606d can be configured to synthesize an output frequency based on the frequency input and the divider control input for use by mixer circuit 606a of RF circuit 606. In some examples, synthesizer circuit 606d can be a fractional-N / N+1 synthesizer.

[0111] In some examples, the frequency input may be provided by a voltage controlled oscillator (VCO), although this is not required. The divider control input may be provided by the baseband circuit 610 or the application circuit 405 / 505 according to the desired output frequency. In some examples, the divider control input (e.g., N) may be determined from a lookup table based on the channel indicated by the application circuit 405, 505.

[0112] The synthesizer circuit 606d of the RF circuit 606 may include a frequency divider, a delay locked loop (DLL), a multiplexer, and a phase accumulator. In some examples, the frequency divider may be a dual-mode frequency divider (DMD), and the phase accumulator may be a digital phase accumulator (DPA). In some examples, the DMD may be configured to divide the input signal by N or N+1 (e.g., based on a carry) to provide a fractional division ratio. In some examples, the DLL may include a cascaded, tunable, delay element, a phase detector, a charge pump, and a set of D-type flip-flops. The delay element may be configured to divide the VCO cycle into Nd equal phase groups, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[0113] In some examples, the synthesizer circuit 606d can be configured to generate a carrier frequency as an output frequency, while in other examples, the output frequency can be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and can be used with a quadrature generator and divider circuit to generate multiple signals with multiple different phases relative to each other at the carrier frequency. In some examples, the output frequency can be an LO frequency (fLO). In some examples, the RF circuit 606 can include an IQ or polarity converter.

[0114] FEM circuitry 608 may include a receive signal path that may include circuitry configured to operate on RF signals received from antenna array 611, amplify the received signals, and provide an amplified version of the received signals to RF circuitry 606 for further processing. FEM circuitry 608 may also include a transmit signal path that may include circuitry configured to amplify transmit signals provided by RF circuitry 606 for transmission by one or more antenna elements in antenna array 611. Amplification by either the transmit signal path or the receive signal path may be accomplished only in RF circuitry 606, only in FEM circuitry 608, or in both RF circuitry 606 and FEM circuitry 608.

[0115] In some examples, FEM circuit 608 may include a TX / RX switch to switch between transmit mode and receive mode operation. FEM circuit 608 may include a receive signal path and a transmit signal path. The receive signal path of FEM circuit 608 may include an LNA to amplify a received RF signal and provide the amplified received RF signal as an output (e.g., to RF circuit 606). The transmit signal path of FEM circuit 608 may include a power amplifier (PA) for amplifying an input RF signal (e.g., provided by RF circuit 606), and one or more filters for generating an RF signal for subsequent transmission by one or more antenna elements of antenna array 611.

[0116] The antenna array 611 includes one or more antenna elements, each of which is configured to convert an electrical signal into a radio wave to travel through the air and convert the received radio wave into an electrical signal. For example, a digital baseband signal provided by the baseband circuit 610 is converted into an analog RF signal (e.g., a modulated waveform), which is amplified and transmitted using the antenna elements of the antenna array 611 including one or more antenna elements (not shown). The antenna elements may be omnidirectional, directional, or a combination thereof. The antenna elements may be formed into a variety of arrangements as known and / or discussed herein. The antenna array 611 may include a microstrip antenna or a printed antenna fabricated on the surface of one or more printed circuit boards. The antenna array 611 may be formed as a patch of metal foil (e.g., a patch antenna) of various shapes and may be coupled to the RF circuit 606 and / or the FEM circuit 608 using a metal transmission line or the like.

[0117] The processors of the application circuits 405 / 505 and the processors of the baseband circuits 610 may be used to execute elements of one or more instances of the protocol stack. For example, the processor of the baseband circuit 610 may be used alone or in combination to perform layer 3, layer 2, or layer 1 functions, while the processors of the application circuits 405, 505 may utilize data received from these layers (e.g., packet data) and further perform layer 4 functions (e.g., TCP and UDP layers). As mentioned herein, layer 3 may include an RRC layer, which will be described in further detail below. As mentioned herein, layer 2 may include a MAC layer, an RLC layer, and a PDCP layer, which will be described in further detail below. As mentioned herein, layer 1 may include a PHY layer of a UE / RAN node, which will be described in further detail below.

[0118] Figure 5 2 shows exemplary components of communication circuit 700. In some examples, communication circuit 700 may be implemented as Figure 4 and Figure 5 The communication circuit 700 may be communicatively coupled (e.g., directly or indirectly) to one or more antennas, such as antennas 702a-c. In some examples, the communication circuit 700 includes or is communicatively coupled to dedicated receive chains for multiple RATs (e.g., a first receive chain for LTE and a second receive chain for 5G NR), a processor, or a radio component, or a combination thereof. For example, as Figure 5 As shown, the communication circuit 700 includes a modem 710 and a modem 720, which may correspond to or be Figure 4 and Figure 5A portion of baseband circuits 410 and 510 are shown. Modem 710 may be configured to communicate in accordance with a first RAT, such as LTE or LTE-A, and modem 720 may be configured to communicate in accordance with a second RAT, such as 5G NR.

[0119] The modem 710 includes one or more processors 712 and a memory 716 in communication with the processor 712. The modem 710 is in communication with a radio frequency (RF) front end 730, which may correspond to Figure 4 and Figure 5 RFEM 415 and 515 shown or part thereof. RF front end 730 may include circuits for transmitting and receiving radio signals. For example, RF front end 730 includes receiving circuit (RX) 732 and transmitting circuit (TX) 734. In some examples, receiving circuit 732 communicates with DL front end 750, which may include circuits for receiving radio signals from antenna 702a. Switch 770 may selectively couple modem 710 to UL front end 772, which may include circuits for transmitting radio signals using antenna 702c.

[0120] Similarly, the modem 720 includes one or more processors 722 and a memory 726 in communication with the processor 722. The modem 720 communicates with the RF front end 740, which may correspond to Figure 4 and Figure 5 RFEM 415 and 515 shown or part thereof. RF front end 740 may include circuits for transmitting and receiving radio signals. For example, RF front end 740 includes receiving circuit 742 and transmitting circuit 744. In some examples, receiving circuit 742 communicates with DL front end 760, which may include circuits for receiving radio signals from antenna 702b. Switch 770 may selectively couple modem 720 to UL front end 772 for transmitting radio signals using antenna 702c.

[0121] The modem 710 may include hardware and software components for time division multiplexing UL data (e.g., for NSA NR operation) and various other techniques described herein. The processor 712 may include one or more processing elements configured to implement the various features described herein, such as by executing program instructions stored on a memory 716 (e.g., a non-transitory computer-readable memory medium). In some examples, the processor 712 may be configured as a programmable hardware element, such as an FPGA or an ASIC. In some examples, the processor 712 may include one or more ICs configured to perform the functions of the processor 712. For example, each IC may include a circuit configured to perform the functions of the processor 712.

[0122] The modem 720 may include hardware and software components for time division multiplexing UL data (e.g., for NSA NR operation) and various other techniques described herein. The processor 722 may include one or more processing elements configured to implement the various features described herein, such as by executing instructions stored on a memory 726 (e.g., a non-transitory computer-readable memory medium). In some examples, the processor 722 may be configured as a programmable hardware element, such as an FPGA or an ASIC. In some examples, the processor 722 may include one or more ICs configured to perform the functions of the processor 722. For example, each IC may include a circuit configured to perform the functions of the processor 522.

[0123] Figure 6 Various protocol functions that can be implemented in a wireless communication device are shown. Specifically, Figure 6 An arrangement 800 is included to illustrate the interconnection between various protocol layers / entities. Various protocol layers and entities operating in conjunction with the 5G NR system standard and the LTE system standard are provided. Figure 6 The following description, but Figure 6 Some or all aspects of the invention may also be applicable to other wireless communication network systems.

[0124] In addition to other higher layer functions not shown, the protocol layers of arrangement 800 may also include one or more of PHY 810, MAC 820, RLC 830, PDCP 840, SDAP 847, RRC 855, and NAS layer 857. These protocol layers may include one or more service access points (e.g., Figure 6 Items 859, 856, 850, 849, 845, 835, 825 and 815).

[0125] PHY 810 can transmit and receive physical layer signals 805, which can be received from or transmitted to one or more other communication devices. Physical layer signals 805 may include one or more physical channels, such as those discussed herein. PHY 810 may also perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and switching purposes) and other measurements used by higher layers (e.g., RRC 855). PHY 810 may further perform error detection on transmission channels, forward error correction (FEC) encoding and decoding of transmission channels, modulation and demodulation of physical channels, interleaving, rate matching, mapping to physical channels, and MIMO antenna processing. In some examples, an instance of PHY 810 may use one or more PHY-SAP 815 to process requests from an instance of MAC 820 and provide instructions thereto. In some examples, requests and instructions transmitted using PHY-SAP 815 may include one or more transmission channels.

[0126] An instance of MAC 820 may process requests from and provide indications to an instance of RLC 830 using one or more MAC-SAPs 825. These requests and indications transmitted using MAC-SAPs 825 may include one or more logical channels. MAC 820 may perform mapping between logical channels and transport channels, multiplexing MAC service data units (SDUs) from one or more logical channels onto transport blocks (TBs) to be delivered to PHY 810 using transport channels, demultiplexing MAC SDUs from TBs delivered from PHY 810 using transport channels to one or more logical channels, multiplexing MAC SDUs onto TBs, scheduling information reporting, error correction through HARQ, and logical channel prioritization.

[0127] An instance of RLC 830 may utilize one or more radio link control service access points (RLC-SAPs) 835 to process requests from an instance of PDCP 840 and provide indications thereto. These requests and indications transmitted using RLC-SAPs 835 may include one or more logical channels. RLC 830 may operate in a variety of operating modes, including: transparent mode (TM), unacknowledged mode (UM), and acknowledged mode (AM). RLC 830 may perform transmission of upper layer protocol data units (PDUs), error correction through automatic repeat request (ARQ) for AM data transmission, and concatenation, segmentation, and reassembly of RLC SDUs for UM and AM data transmission. RLC 830 may also perform resegmentation of RLC data PDUs for AM data transmission, reorder RLC data PDUs for UM and AM data transmission, detect duplicate data for UM and AM data transmission, discard RLC SDUs for UM and AM data transmission, detect protocol errors for AM data transmission, and perform RLC re-establishment.

[0128] An instance of PDCP 840 may utilize one or more Packet Data Convergence Protocol Service Access Points (PDCP-SAP) 845 to process requests from an instance of RRC 855 or an instance of SDAP 847, or both, and provide indications thereto. These requests and indications transmitted using PDCP-SAP 845 may include one or more radio bearers. PDCP 840 may perform header compression and decompression of IP data, maintain PDCP sequence numbers (SNs), perform in-order delivery of higher layer PDUs when lower layers are reestablished, eliminate duplication of lower layer SDUs when lower layers are reestablished for radio bearers mapped on RLC AM, encrypt and decrypt control plane data, perform integrity protection and integrity verification on control plane data, control timer-based data discard, and perform security operations (e.g., encryption, decryption, integrity protection, or integrity verification).

[0129] An instance of SDAP 847 may utilize one or more SDAP-SAPs 849 to process requests from one or more higher layer protocol entities and provide instructions thereto. These requests and instructions transmitted using SDAP-SAPs 849 may include one or more QoS flows. SDAP 847 may map QoS flows to data radio bearers (DRBs) and vice versa, and may also mark QoS flow identifiers (QFIs) in DL and UL packets. A single SDAP entity 847 may be configured for a separate PDU session. In the UL direction, NG-RAN 110 may control the mapping of QoS flows to DRBs in two different ways (reflective mapping or explicit mapping). For reflective mapping, SDAP 847 of UE 101 may monitor the QFI of the DL packets of each DRB, and may apply the same mapping to packets flowing in the UL direction. For DRBs, SDAP 847 of UE 101 may map UL packets belonging to a QoS flow corresponding to the QoS flow ID and PDU session observed in the DL packets of the DRB. To implement the reflective mapping, the NG-RAN 310 may mark the DL packets with a QoS flow ID over the Uu interface. The explicit mapping may involve the RRC 855 configuring the SDAP 847 with explicit mapping rules of QoS flows to DRBs, which may be stored and followed by the SDAP 847. In some examples, the SDAP 847 may be used only in NR implementations and may not be used in LTE implementations.

[0130] The RRC 855 may configure aspects of one or more protocol layers using one or more management service access points (M-SAPs), which may include one or more instances of PHY 810, MAC 820, RLC 830, PDCP 840, and SDAP 847. In some examples, instances of the RRC 855 may process requests from one or more NAS entities 857 using one or more RRC-SAPs 856 and provide indications thereto. The main services and functions of the RRC 855 may include broadcasting of system information (e.g., included in a master information block (MIB) or system information block (SIB) related to NAS), broadcasting of system information related to the access stratum (AS), paging, establishment, maintenance, and release of an RRC connection between the UE 101 and the RAN 110 (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), establishment, configuration, maintenance, and release of point-to-point radio bearers, security functions including key management, inter-RAT mobility, and measurement configuration for UE measurement reporting. The MIB and SIB may include one or more information elements, each of which may include separate data fields or data structures.

[0131] NAS 857 may form the highest layer of the control plane between UE 101 and AMF 321. NAS 857 may support the mobility and session management procedures of UE 101 to establish and maintain an IP connection between UE 101 and P-GW in the LTE system.

[0132] In some examples, one or more protocol entities of arrangement 800 may be implemented in UE 101, RAN node 111, AMF 321 in NR implementation or MME 221 in LTE implementation, UPF 302 in NR implementation or S-GW 222 and P-GW 223 in LTE implementation, etc., for control plane or user plane communication protocol stacks between the aforementioned devices. In some examples, one or more protocol entities that may be implemented in one or more of UE 101, gNB 111, AMF 321, etc. may communicate with corresponding peer protocol entities that may be implemented in or on another device (using services of corresponding lower layer protocol entities to perform such communication). In some examples, the gNB-CU of gNB 111 may host the gNB's RRC 855, SDAP 847, and PDCP 840 that control operations of one or more gNB-DUs, and the gNB-DUs of gNB 111 may each host the RLC 830, MAC 820, and PHY 810 of gNB 111.

[0133] In some examples, the control plane protocol stack may include, in order from the highest layer to the lowest layer, NAS 857, RRC 855, PDCP 840, RLC 830, MAC 820, and PHY 810. In this example, upper layers 860 may be built on top of NAS 857, which includes an IP layer 861, SCTP 862, and an application layer signaling protocol (AP) 863.

[0134] In some examples such as NR implementations, AP 863 may be an NG application protocol layer (NGAP or NG-AP) 863 for an NG interface 113 defined between an NG-RAN node 111 and an AMF 321, or AP 863 may be an Xn application protocol layer (XnAP or Xn-AP) 863 for an Xn interface 112 defined between two or more RAN nodes 111.

[0135] The NG-AP 863 may support the functionality of the NG interface 113 and may include an elementary procedure (EP). The NG-AP EP may be an interaction unit between the NG-RAN node 111 and the AMF 321. The NG-AP 863 services may include two groups: UE-associated services (e.g., services related to the UE 101) and non-UE-associated services (e.g., services related to the entire NG interface instance between the NG-RAN node 111 and the AMF 321). These services may include functions such as, but not limited to: a paging function for sending a paging request to the NG-RAN node 111 involved in a specific paging area; a UE context management function for allowing the AMF 321 to establish, modify or release the UE context in the AMF 321 and the NG-RAN node 111; a mobility function for the UE 101 in ECM-CONNECTED mode, for intra-system HO to support mobility within the NG-RAN, and for inter-system HO to support mobility from / to the EPS system; a NAS signaling transport function for transporting or rerouting NAS messages between the UE 101 and the AMF 321; a NAS node selection function for determining the association between the AMF 321 and the UE 101; an NG interface management function for setting up the NG interface and monitoring errors over the NG interface; a warning message transport function for providing a means to transport a warning message using the NG interface or to cancel an ongoing warning message broadcast; a function for utilizing the CN 120 is a configuration transmission function for requesting and transmitting RAN configuration information (eg, SON information, or performance measurement (PM) data) between two RAN nodes 111; or a combination thereof, etc.

[0136] The XnAP 863 may support the functions of the Xn interface 112 and may include XnAP basic mobility procedures and XnAP global procedures. The XnAP basic mobility procedures may include procedures for handling UE mobility within the NG RAN 111 (or E-UTRAN 210), such as handover preparation and cancellation procedures, SN state transfer procedures, UE context retrieval and UE context release procedures, RAN paging procedures, or procedures related to dual connectivity, etc. The XnAP global procedures may include procedures not related to a specific UE 101, such as Xn interface setup and reset procedures, NG-RAN update procedures, or cell activation procedures, etc.

[0137] In an LTE specific implementation, AP 863 can be an S1 application protocol layer (S1-AP) 863 for the S1 interface 113 defined between the E-UTRAN node 111 and the MME, or AP 863 can be an X2 application protocol layer (X2AP or X2-AP) 863 for the X2 interface 112 defined between two or more E-UTRAN nodes 111.

[0138] The S1 application protocol layer (S1-AP) 863 may support the functionality of the S1 interface, and similar to the NG-AP discussed previously, the S1-AP may include an S1-AP EP. The S1-AP EP may be an interaction unit between the E-UTRAN node 111 and the MME 221 within the LTE CN 120. The S1-AP 863 services may include two groups: UE-associated services and non-UE-associated services. The functions performed by these services include, but are not limited to: E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transmission, RAN Information Management (RIM), and configuration transmission.

[0139] The X2AP 863 may support the functions of the X2 interface 112 and may include an X2AP basic mobility procedure and an X2AP global procedure. The X2AP basic mobility procedure may include a procedure for handling UE mobility within the E-UTRAN 120, such as a handover preparation and cancellation procedure, an SN state transfer procedure, a UE context retrieval and a UE context release procedure, a RAN paging procedure, or a procedure related to dual connectivity, etc. The X2AP global procedure may include a procedure not related to a specific UE 101, such as an X2 interface setup and reset procedure, a load indication procedure, an error indication procedure, or a cell activation procedure, etc.

[0140] The SCTP layer (alternatively referred to as the SCTP / IP layer) 862 may provide guaranteed delivery of application layer messages (e.g., NGAP or XnAP messages in NR implementations, or S1-AP or X2AP messages in LTE implementations). The SCTP 862 may ensure reliable delivery of signaling messages between the RAN node 111 and the AMF 321 / MME 221 based in part on the IP protocol supported by the IP 861. The Internet Protocol layer (IP) 861 may be used to perform packet addressing and routing functions. In some implementations, the IP layer 861 may deliver and transmit PDUs using point-to-point transport. In this regard, the RAN node 111 may include L2 and L1 layer communication links (e.g., wired or wireless) with the MME / AMF to exchange information.

[0141] In some examples, the user plane protocol stack may include, in order from the highest layer to the lowest layer, SDAP 847, PDCP 840, RLC 830, MAC 820, and PHY 810. The user plane protocol stack may be used for communication between UE 101, RAN node 111, and UPF 302 in a NR implementation, or communication between S-GW 222 and P-GW 223 in a LTE implementation. In this example, the upper layer 851 may be built on top of the SDAP 847 and may include a user datagram protocol (UDP) and IP security layer (UDP / IP) 852, a general packet radio service (GPRS) tunneling protocol layer (GTP-U) 853 for the user plane, and a user plane PDU layer (UP PDU) 863.

[0142] The transport network layer 854 (also referred to as the "transport layer") may be built on top of the IP transport, and the GTP-U 853 may be used on top of the UDP / IP layer 852 (including the UDP layer and the IP layer) to carry the user plane PDU (UP-PDU). The IP layer (also referred to as the "Internet layer") may be used to perform packet addressing and routing functions. The IP layer may assign IP addresses to user data packets, for example, in any of the IPv4, IPv6, or PPP formats.

[0143] GTP-U 853 may be used to carry user data within the GPRS core network and between the radio access network and the core network. For example, the transmitted user data may be packets in any of the IPv4, IPv6 or PPP formats. UDP / IP 852 may provide a checksum for data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication of selected data flows. The RAN node 111 and the S-GW 222 may utilize the S1-U interface to exchange user plane data using a protocol stack including an L1 layer (e.g., PHY 810), an L2 layer (e.g., MAC 820, RLC 830, PDCP 840 and / or SDAP 847), a UDP / IP layer 852, and a GTP-U 853. The S-GW 222 and the P-GW 223 may utilize an S5 / S8a interface to exchange user plane data using a protocol stack including an L1 layer, an L2 layer, a UDP / IP layer 852, and a GTP-U 853. As previously discussed, the NAS protocol may support mobility of UE 101 and session management procedures to establish and maintain an IP connection between UE 101 and P-GW 223 .

[0144] In addition, despite Figure 6Not shown, but an application layer may exist above AP 863 and / or transport network layer 854. The application layer may be a layer where a user of UE 101, RAN node 111, or other network element interacts with a software application, for example, executed by application circuitry 405 or application circuitry 505, respectively. The application layer may also provide one or more interfaces for the software application to interact with a communication system (such as baseband circuitry 610) of UE 101 or RAN node 111. In some examples, the IP layer or the application layer, or both, may provide functionality the same or similar to layers 5 to 7 of the Open Systems Interconnection (OSI) model, or portions thereof (e.g., OSI layer 7—application layer, OSI layer 6—presentation layer, and OSI layer 5—session layer).

[0145] Figure 7 is a block diagram illustrating components for reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the techniques described herein. Specifically, Figure 7 A schematic diagram of hardware resources 1100 is shown, including one or more processors (or processor cores) 1110, one or more memories or storage devices 1120, and one or more communication resources 1130, each of which may be communicatively coupled using a bus 1140. For specific implementations in which node virtualization (e.g., NFV) is utilized, a hypervisor 1102 may be executed to provide an execution environment for one or more network slices or sub-slices to utilize the hardware resources 1100.

[0146] Processor 1110 may include processor 1112 and processor 1114. Processor 1110 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a DSP such as a baseband processor, an ASIC, an FPGA, a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0147] The memory / storage device 1120 may include main memory, disk storage, or any suitable combination thereof. The memory / storage device 1120 may include, but is not limited to, any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or solid-state storage devices, or combinations thereof.

[0148] The communication resources 1130 may include an interconnect or network interface component or other suitable device to communicate with one or more peripheral devices 1104 or one or more databases 1106 using the network 1108. For example, the communication resources 1130 may include a wired communication component (e.g., for coupling using USB), a cellular communication component, an NFC component, (or Low power consumption) components, components and other communication components.

[0149] The instructions 1150 may include software, programs, applications, applet, applications, or other executable code for causing at least any one of the processors 1110 to perform any one or more of the methodologies discussed herein. The instructions 1150 may reside in whole or in part in at least one of the processor 1110 (e.g., in a cache memory of the processor), the memory / storage device 1120, or any suitable combination thereof. In addition, any portion of the instructions 1150 may be transmitted to the hardware resources 1100 from any combination of the peripheral device 1104 or the database 1106. Thus, the memory of the processor 1110, the memory / storage device 1120, the peripheral device 1104, and the database 1106 are examples of computer-readable and machine-readable media.

[0150] Go to Figure 8 , shows an exemplary process 1200 of RACH. Figure 1 UE 101a-101b) and gNB node 1212 (e.g., similar to Figure 1 111a-b) of the UE 1210. This includes a 4-step RACH process for initial access. For process 1200, the UE 1210 transmits (1202) a physical random access channel (PRACH) in the uplink by randomly selecting a preamble signature, which allows the node 1212 to estimate the delay between the node and the UE for subsequent UL timing adjustment. The node 1212 then responds 1204 with a random access response (RAR). The RAR message carries timing advance (TA) command information and uplink grant for uplink transmission (1206). The UE 1210 expects to receive the RAR message 1204 within a time window, and the node 1212 uses a system information block (SIB) to configure the start and end of the time window. Generally speaking, the UE 1210 may adjust (1214) the UL timing before sending a data layer or network later message 1206 to the node 1212. The node 1212 sends a contention resolution message 1208 back to the UE 1210 .

[0151] As previously described, the RACH process 1200 can be improved to allow fast access and low-latency uplink transmissions for the UE 1210. The RACH process 1200 can be reduced from 4 steps to 2 steps, such as Fig. 9 1200. In process 1300, UE 1302 (which may be similar to UE 1210) is configured to transmit (1306) a PRACH preamble and an associated message (e.g., MsgA) on a physical uplink shared channel (PUSCH) on configured time and frequency resources. The MsgA PUSCH may carry at least equivalent content of message 3 (1206) in process 1200 for a 4-step RACH. In addition, after successfully detecting the PRACH preamble and decoding the MsgA PUSCH, gNB node 1304 (e.g., similar to gNB node 1212) transmits MsgB (1308). MsgB may include a message for the UE 1210 with respect to the PRACH preamble. Figure 8 Message 2 (1204) and message 4 (1208) of the 4-step RACH process 1200 are equivalent.

[0152] In general, PUSCH resource elements may be defined as PUSCH opportunities and demodulation reference signal (DMRS) ports and / or DMRS sequences for payload transmission of MsgA (1306). Both or either one-to-one mapping and many-to-one mapping between PRACH preambles and corresponding associated PUSCH resource elements may be supported. In an embodiment, many-to-one mapping between PRACH preambles and associated PUSCH resource elements is beneficial in reducing resource overhead for MsgA PUSCH (1306). This may help improve system-level spectral efficiency. If both one-to-one mapping and many-to-one mapping are supported for the 2-step RACH procedure 1300, the detailed signaling mechanism and mapping rules are defined as described subsequently.

[0153] The mapping between the PRACH preamble and the PUSCH resource unit is now described. As previously described, the PUSCH resource unit is defined as the PUSCH opportunity and DMRS port and / or DMRS sequence (1306) for MsgA payload transmission. In addition, for the 2-step RACH process 1200, both one-to-one mapping and many-to-one mapping between the PRACH preamble and the associated PUSCH resource unit can be supported.

[0154] There are at least several different implementations for the mapping rules between PRACH preambles and PUSCH resource units. In one implementation, in order to define the mapping between PRACH preambles and PUSCH resource units, the PRACH preambles may be sorted similarly to the association rules between PRACH preambles and synchronization signal blocks (SSBs) as defined in Section 5.1 of TS36.231. The first order may include an increasing order of preamble indexes within a single PRACH opportunity. The second order may include an increasing order of frequency resource indexes of frequency multiplexed PRACH opportunities. The third order may include an increasing order of time resource indexes of time multiplexed PRACH opportunities within a PRACH time slot. The fourth order may include an increasing order of indices of PRACH time slots.

[0155] In an embodiment, if multiple MsgA PUSCH opportunities in a slot are supported, the PUSCH resource units can be ordered in several ways. First, the order may include an increasing order of DMRS ports / sequences within a single PUSCH opportunity. Second, the order may include an increasing order of frequency resource indices of frequency multiplexed MsgA PUSCH opportunities. Third, the order may include an increasing order of time resource indices of time multiplexed MsgA PUSCH opportunities within an MsgA PUSCH slot. Fourth, the order may include an increasing order of indices of MsgA PUSCH slots.

[0156] In general, if multiple MsgA PUSCH opportunities in a time slot are not supported, the PUSCH resource units may be ordered as follows. First, the order may include an increasing order of DMRS ports / sequences within a single PUSCH opportunity. Second, the order may include an increasing order of frequency resource indices of frequency-multiplexed MsgA PUSCH opportunities. Third, the order may include an increasing order of time resource indices of time-multiplexed MsgA PUSCH opportunities of MsgAPUSCH time slots. In an embodiment, any of the above orders may be defined for PUSCH opportunities associated with the same modulation and coding scheme (MCS) and / or transport block size (TBS).

[0157] Taking into account that MsgA PUSCH opportunities may partially overlap in time, multiple non-intersecting PUSCH opportunity sets may be determined based on the start and length indicator value (SLIV) of each PUSCH opportunity in the time slot. The determination using SLIV may be similar to the semi-static codebook generation as defined in TS 38.214 Section 5.1. In this example, if multiple MsgA PUSCH opportunities are configured within a time slot, the multiple PUSCH opportunity sets are multiplexed in a TDM manner. The ordering of the time resource indexes of the time-multiplexed MsgA PUSCH opportunities within the MsgA PUSCH time slot is based on the non-intersecting PUSCH opportunity sets as described above. Generally speaking, within the MsgA PUSCH opportunity set, the frequency resource indexes are sorted first.

[0158] Alternatively or in addition, for a contention-based 2-step RACH procedure (e.g., process 1300), the preamble index is mapped immediately after the preamble index of a contention-based 4-step RACH procedure (e.g., process 1200). This may depend on the association of SSBs with PRACH preambles in one PRACH opportunity, and whether the 2-step RACH procedure 1300 and the 4-step RACH procedure 1200 share the same RACH opportunity.

[0159] In general, as specified in TS 36.231 Section 5.1, N synchronization signal / physical broadcast channel (SS / PBCH) blocks associated with one PRACH opportunity are provided to a UE (e.g., UE 1210 or 1302). For each SS / PBCH block per valid PRACH opportunity (e.g., via an ssb-perRACH-OccasionAndCB-PreamblesPerSSB object), R contention-based preambles are provided to the UE. For example, if N<1, one SS / PBCH block is mapped to 1 / N consecutive valid PRACH opportunities and R contention-based preambles, where consecutive indices associated with the SS / PBCH blocks for each valid PRACH opportunity start from preamble index 0. In an example, one SSB is associated with more than one PRACH opportunity. For a contention-based 2-step RACH procedure (e.g., procedure 1300), the preamble index associated with the PUSCH resource element is mapped starting from the Rth for all 1 / N consecutive valid PRACH opportunities associated with one SSB. This is the case when the 2-step RACH procedure 1300 and the 4-step RACH procedure 1200 share the same RACH opportunity. When the 2-step RACH procedure 1300 and the 4-step RACH procedure 1200 are configured with separate RACH opportunities, the preamble index associated with the PUSCH resource element is mapped starting from 0 for all 1 / N consecutive valid PRACH opportunities associated with one SSB.

[0160] In general, for a contention-based 2-step RACH procedure, if different PUSCH opportunities are associated with different MCSs or TBSs, the preamble indexes of the 2-step RACH procedure 1300 may be ordered from the PUSCH opportunity with the smallest modulation and coding scheme (MCS) to the largest MCS, or from the PUSCH opportunity with the smallest ID to the largest ID. The IDs may be configured with different MCSs or transport block sizes (TBSs).

[0161] Fig.10 An example of PRACH preamble ordering 1400 for 2-step and 4-step RACH procedures (e.g., procedures 1300 and 1200, respectively) is shown when one SSB is associated with more than one PRACH opportunity. For this example, N=1 / 2, which indicates that 1 SSB is associated with 2 PRACH opportunities. In this example, R=32, which indicates that preambles #0-31 (e.g., preambles 1406a and 1406b) in both PRACH opportunity #0 (e.g., block 1402) and PRACH opportunity #1 (e.g., block 1404) associated with 1 SSB are allocated for contention-based 4-step RACH. In addition, assuming that 16 preambles are configured for contention-based (CBRA) 2-step RACH, preamble indexes #32-47 (e.g., preambles 1408a, 1408b) are allocated for 2-step RACH in both PRACH opportunities 1402 and 1404. The remaining PRACH preambles (1406a and 1406b), including #48-63, may be allocated for other purposes, such as for contention-free random access.

[0162] In an embodiment, the preamble index associated with a PUSCH resource element is from the preamble index associated with an SSB. Mapping begins. This occurs under the following conditions. First, more than one SSB is associated with one PRACH opportunity. Second, 2-step RACH and 4-step RACH share the same RACH opportunity (e.g., if N ≥ 1). Third, R contention-based preambles with consecutive indices are associated with SS / PBCH block n, 0 ≤ n ≤ N-1. Fourth, for the contention-based 2-step RACH procedure, each valid PRACH opportunity starts with the preamble index Start, where Provided by the object (e.g., totalNumberOfRA-Preambles) and is an integer multiple of N. In an embodiment, when 2-step RACH and 4-step RACH are configured with separate RACH opportunities, for the contention-based 2-step RACH procedure, the preamble index associated with the PUSCH resource element is increased from Mapping begins. In an embodiment, N may be configured separately for 2-step RACH compared to 4-step RACH.

[0163] Fig.11 An example of PRACH preamble ordering 1500 for 2-step and 4-step RACH is shown when more than one SSB is associated with one PRACH opportunity. In this example, N=2 and R=16, so that two SSBs are associated with one PRACH opportunity. Generally speaking, preambles #0-15 (1502) are associated with SSB#0. For CBRA 4-step RACH, preambles #32-47 (1508) are associated with SSB#1. Generally speaking, eight preambles are configured for CBRA 2-step RACH. Therefore, preambles #16-23 (1504) are associated with SSB#0. In addition, for CBRA 2-step RACH, preambles #48-55 (1510) are associated with SSB#1. Preambles #24-31 (1506) and preambles #56-63 (1512) may be reserved for other purposes.

[0164] In an implementation scheme, the parameter rach-Occasion-perPUSCHoccasionAndCB-PreamblesPerPRACH may be configured for the association between PRACH and PUSCH opportunities and the number of preambles for the 2-step RACH process. This parameter may be configured per PUSCH opportunity associated with a specific MCS and / or TBS. Based on this parameter, N1 PRACH opportunities associated with one PUSCH opportunity and R1 contention-based preambles per PUSCH opportunity per PRACH opportunity may be derived. If N1<1, one PRACH opportunity is mapped to 1 / N1 consecutive PUSCH opportunities that may or may not be configured with the same MCS and / or TBS. If N1≥1, N1 PRACH opportunities are associated with one PUSCH opportunity.

[0165] In an embodiment, for a contention-based 2-step RACH procedure, preamble indices associated with PUSCH opportunities are mapped consecutively. The parameter preamble-perPUSCHresourceunit may be configured by higher layers to indicate a number (e.g., N pre-puschunit ) preambles are associated with PUSCH resource units. In an embodiment, if N pre-puschunit =1, there is a one-to-one mapping between the preamble and the PUSCH resource unit. In addition, if N pre-puschunit >1, there is a many-to-one mapping between the preamble and the PUSCH resource unit. pre-puschunit ≤1, there is a one-to-many mapping between the preamble and the PUSCH resource elements.

[0166] Generally speaking, in the case of one-to-one mapping, the DMRS port indexes associated with the PRACH occasion are mapped continuously. For many-to-one mapping, the N pre-puschunit preamble indexes associated with the PUSCH resource units are mapped continuously. In addition, for consecutive PUSCH resource units or DMRS ports, the DMRS port group indexes are mapped continuously.

[0167] Generally speaking, the starting position of the PUSCH resource unit or DMRS can be determined as follows. When a PRACH occasion is associated with a PUSCH occasion (e.g., N1 = 1), the PUSCH resource unit or DMRS antenna port (AP) associated with the PRACH occasion is mapped starting from 0 and is mapped continuously. When a PRACH occasion is associated with more than one PUSCH occasion (e.g., N1 < 1), the PUSCH resource unit or DMRS AP associated with the PRACH occasion is mapped starting from 0 and is mapped continuously. When more than one PRACH occasion is associated with a PUSCH occasion (e.g., N1 ≥ 1), the PUSCH resource unit or DMRS AP associated with the PRACH occasion k (0 < k ≤ N1 - 1) is mapped starting from and is mapped continuously, where is the total number of PUSCH resource units or DMRS APs of a PUSCH occasion. This parameter can be configured according to PUSCH occasions including the same MCS and / or TBS. In an embodiment, the PUSCH resource unit or DMRS AP associated with the PRACH occasion is mapped starting from k·R1, where R1 is the number of preambles associated with a PUSCH occasion. If the PUSCH resource unit is not mapped or is associated with a PRACH preamble, the PUSCH resource is not used for the two-step RACH procedure 1300.

[0168] Fig.12 、 Fig.13 and Fig.14 respectively show examples of one-to-one mapping, one-to-many mapping, and many-to-one mapping between the PRACH occasion and the PUSCH occasion. For these examples, there is a one-to-one mapping between the PRACH preamble and the PUSCH resource unit. In addition, there is one SSB associated with one PRACH occasion. In addition, the two-step RACH procedure and the four-step RACH procedure for this example share the same RACH occasion. When the two-step RACH procedure and the four-step RACH procedure are configured with separate RACH occasions, depending on the number of SSBs associated with one PRACH occasion, the PRACH preamble index of the two-step RACH is mapped starting from 0 or

[0169] ​Go to Fig.12 , an example of a one-to-one mapping 1600 is shown. In this example, preambles #32-39 are mapped to PUSCH resource elements or DMRS APs #0-7 for PUSCH opportunity #0 (1604). For example, preamble #32 is associated with DMRS AP #0, preamble #33 is associated with DRMS ​​AP #1, and so on until preamble #39 is associated with DRMS ​​AP #7. Here, preambles #0-63 are associated with PRACH opportunity #0 (1602). PUSCH resource elements or DMRS APs are associated with PUSCH opportunity #0 (1604).

[0170] Go to Fig.13 , an example of a one-to-many mapping 1700 is shown. Here, preambles #0-63 are associated with PRACH opportunity #0 (1702). In this example, preambles #32-39 are mapped to PUSCH resource elements or DMRS APs #0-7 of PUSCH opportunity #0 (1706). For example, preamble #32 is associated with DMRS AP #0, preamble #33 is associated with DRMS ​​AP #1, and so on, until preamble #39 is associated with DRMS ​​AP #7 of PUSCH opportunity #0. In addition, preambles #40-47 are associated with PUSCH opportunity #1 (1704). For example, preamble #40 is associated with DMRS AP #0, preamble #41 is associated with DRMS ​​AP #1, and so on, until preamble #47 is associated with DRMS ​​AP #7 of PUSCH opportunity #1 (1704).

[0171] Go to Fig.14 , an example of a many-to-many mapping 1800 is shown. Here, preambles #0-63 are associated with PRACH opportunity #0 (1802), and a second group of preambles #0-63 are associated with PRACH opportunity #1 (1804). In this example, preambles #32-35 of PRACH opportunity #0 (1802) are mapped to PUSCH resource elements or DMRS APs #0-3 of PUSCH opportunity #0 (1806). For example, preamble #32 is associated with DMRS AP #0, preamble #33 is associated with DRMS ​​AP #1, and so on, until preamble #35 is associated with DRMS ​​AP #3 of PUSCH opportunity #0 (1806). In addition, preambles #32-35 of PRACH opportunity #1 (1804) are mapped to PUSCH resource elements or DMRS APs #6-9 of PUSCH opportunity #0 (1806). For example, preamble #32 is associated with DMRSAP #6, preamble #33 is associated with DRMS ​​AP #7, and so on, until preamble #35 is associated with DRMS ​​AP #9 of PUSCH opportunity #0 (1806).

[0172] Fig.15 An example of a many-to-one mapping 1900 between PRACH preambles and PUSCH resource elements is shown. In this example, there is a one-to-one mapping between PRACH opportunities 1902 and PUSCH opportunities 1904. Here, preamble #32 is mapped to DMRS AP#0 and preamble #33 is also mapped to DMRS AP#0. In addition, preamble #34 is mapped to DMRS AP#1 and preamble #35 is also mapped to DMRS AP#1. In addition, preamble #36 is mapped to DMRS AP#2 and preamble #37 is also mapped to DMRS AP#2. In addition, preamble #38 is mapped to DMRS AP#3 and preamble #39 is also mapped to DMRSAP#3. Preambles #0-31 are used for a 4-step RACH process. Preambles #40-63 are used for other purposes.

[0173] In an embodiment, different MsgA PUSCH opportunities may be targeted at different applications and use cases. For example, a first MsgA PUSCH opportunity may be used to carry user data, and a second MsgA PUSCH opportunity may be used to carry a small payload. A separate preamble index in a RACH opportunity or in a separate RACH opportunity may indicate the corresponding MCS or TBS used to transmit a MsgA PUSCH or MsgAPUSCH opportunity.

[0174] Fig.16 and Fig.17 Examples of separate preamble indexes in RACH opportunities for PUSCH opportunity indication and separate RACH opportunities are shown, respectively. Generally, one SSB is associated with one PRACH opportunity. Generally, the 2-step RACH procedure and the 4-step RACH procedure each share the same RACH opportunity. When the 2-step RACH procedure and the 4-step RACH procedure are configured with separate RACH opportunities, the number of SSBs associated with one PRACH opportunity is 0 or 1. Start mapping the PRACH preamble index for the 2-step RACH procedure.

[0175] Fig.16An example of mapping 2000 individual preamble indexes in RACH opportunities is shown. In this example, there is a one-to-many mapping between PRACH opportunities 2002 and PUSCH opportunities 2004 and 2006, and there is a one-to-one mapping between preambles and DMRS APs or resource units. Here, for PUCSH opportunity #0 (2004) with MSC #0, preamble #32 is mapped to DMRS AP #0, preamble #33 is mapped to DMRS AP #1, preamble #34 is mapped to DMRS AP #2, and so on, until preamble #39 is mapped to DMRS AP #7. Similarly, for PUCSH opportunity #1 (2006) with MSC #1, preamble #40 is mapped to DMRS AP #0, preamble #41 is mapped to DMRS AP #1, preamble #42 is mapped to DMRS AP #2, and so on, until preamble #47 is mapped to DMRS AP #7. Preamble #0-31 is used for 4-step RACH procedure. Preamble #48-63 is used for other purposes.

[0176] Fig.17 An example of mapping 2100 for individual RACH opportunities indicated by PUSCH opportunities is shown. In this example, there is a many-to-many mapping between PRACH opportunities 2102 and 2104 and PUSCH opportunities 2106 and 2108, and there is a one-to-one mapping between the preamble of each PRACH opportunity and a DMRS AP or resource element. Here, for PUCSH opportunity #0 (2106) with MSC #0, preamble #32 of PRACH opportunity #0 (2102) is mapped to DMRS AP #0, preamble #33 of PRACH opportunity #0 is mapped to DMRS AP #1, preamble #34 of PRACH opportunity #0 is mapped to DMRS AP #2, and preamble #35 is mapped to DMRS AP #3 of PUSCH opportunity #0. Similarly, for PUCSH opportunity #1 (2108) with MSC #1, preamble #32 of PRACH opportunity #1 (2104) is mapped to DMRS AP #0, preamble #33 of PRACH opportunity #1 is mapped to DMRS AP #1, preamble #34 of PRACH opportunity #1 is mapped to DMRS AP #2, and preamble #35 is mapped to DMRS AP #3 of PUSCH opportunity #1. For each of PRACH opportunities #0, #1, the corresponding preambles #0-31 are used for the 4-step RACH process, and preambles #36-63 are used for other purposes.

[0177] Go to Fig.18, an exemplary process 2200 for generating, by a node (e.g., a gNB), a mapping between a PRACH preamble and a PUSCH resource element for a 2-step RACH. In a general aspect, the process 2200 for generating, by a node (e.g., a gNB), a mapping between a PRACH preamble and a PUSCH resource element for a 2-step RACH includes: mapping (2202) or causing mapping of one or more PRACH opportunities to one or more PUSCH resource elements; and generating (2204) or causing generation of one or more PUSCH resource elements based on the mapping. In an embodiment, the process includes acquiring or causing acquisition of one or more PRACH opportunities.

[0178] In an embodiment, process 2200 includes determining one or more rules for mapping one or more PRACH opportunities to one or more PUSCH resource units. In an embodiment, the one or more rules for mapping are configured by the gNB. In an embodiment, the one or more rules for mapping are used to convert a 4-step RACH process into a 2-step RACH process. In an embodiment, one or more PRACH opportunities respectively include multiple PRACH preambles. In an embodiment, the multiple PRACH preambles include N SS / PBCH blocks, where R contention-based preambles are associated with each SS / PBCH block in the N SS / PBCH blocks. In an embodiment, the N SS / PBCH blocks and the R contention-based preambles are configured by ssb-perRACH-OccasionAndCB-PreamblesPerSSB. In an embodiment, process 2200 also includes sorting or causing sorting of the plurality of PRACH preambles based on any or all of the following rules: in ascending order of corresponding preamble indices within a single PRACH opportunity; in ascending order of frequency resource indices of frequency multiplexed PRACH opportunities; in ascending order of time resource indices of time multiplexed PRACH opportunities within a PRACH slot; or in ascending order of indices of PRACH slots. In an embodiment, all of these ascending orders are changed to descending orders.

[0179] In one aspect, process 2200 includes determining or causing determination of mapping a preamble index corresponding to contention-based 4-step RACH before mapping a preamble index corresponding to contention-based 2-step RACH. In an embodiment, process 2200 includes sorting or causing sorting of one or more PUSCH resource units based on any or all of the following rules: in ascending order of DMRS port / sequence within a single PUSCH opportunity; in ascending order of frequency resource index of frequency-multiplexed MsgA PUSCH opportunity; in ascending order of time resource index of time-multiplexed MsgAPUSCH opportunity within MsgA PUSCH slot; or in ascending order of index of MsgA PUSCH slot. In an embodiment, any or all ascending orders are changed to descending orders.

[0180] In one aspect, process 2200 includes determining one or more of a plurality of disjoint PUSCH opportunity sets based on a start and length indicator (SLIV) of each PUSCH opportunity in a slot. Ordering of time resource indexes of time multiplexed MsgA PUSCH opportunities within a MsgA PUSCH slot is based on disjoint PUSCH opportunity sets.

[0181] In one aspect, process 2200 includes: if for a contention-based 2-step RACH process, one synchronization signal block (SSB) is associated with more than one PRACH opportunity, mapping or causing mapping of preamble indexes associated with PUSCH resource elements starting from the Rth for all 1 / N consecutive valid PRACH opportunities associated with one SSB. In an embodiment, the mapping is performed or caused if the 2-step RACH shares the PRACH opportunity with the 4-step RACH.

[0182] In one aspect, process 2200 includes: if more than one SSB is associated with one PRACH opportunity for a contention-based 2-step RACH procedure, Begin mapping or cause mapping of preamble indices associated with PUSCH resource elements. In an embodiment, this mapping is performed or causes mapping if 2-step RACH shares a PRACH opportunity with 4-step RACH.

[0183] In an embodiment, rach-Occasion-perPUSCHoccasionAndCB-PreamblesPerPRACH is configured for the association between PRACH and PUSCH occasions and the number of preambles for a two-step RACH. N1 PRACH occasions associated with a PUSCH occasion and R1 contention-based preambles for each PUSCH occasion of each PRACH occasion can be derived. In an embodiment, if N1 < 1, one PRACH occasion is mapped to 1 / N1 consecutive PUSCH occasions that may or may not be configured with the same MCS and / or TBS. Alternatively, if N1 ≥ 1, N1 PRACH occasions are associated with a PUSCH occasion.

[0184] In an embodiment, the preamble indices associated with a PUSCH occasion are mapped consecutively. In an embodiment, the parameter preamble-perPUSCHresourceunit can be configured by a higher layer to indicate that N pre-puschunit preambles are associated with a PUSCH resource unit. In an embodiment, the DMRS port indices associated with a PRACH occasion are mapped consecutively. In an embodiment, for a many-to-one mapping, the N pre-puschunit preamble indices associated with a PUSCH resource unit are mapped consecutively. In an example, when one PRACH occasion is associated with a PUSCH occasion, for example, N1 = 1, the PUSCH resource unit or DMRS AP associated with the PRACH occasion is mapped starting from 0 and is mapped consecutively. In an embodiment, when one PRACH occasion is associated with more than one PUSCH occasion, for example, N1 < 1, the PUSCH resource unit or DMRS AP associated with the PRACH occasion is mapped starting from 0 and is mapped consecutively. In an embodiment, when more than one PRACH occasion is associated with a PUSCH occasion, for example, N1 ≥ 1, the PUSCH resource unit or DMRS AP associated with PRACH occasion k (0 < k ≤ N1 - 1) is mapped starting from where is the total number of PUSCH resource units or DMRS APs of a PUSCH occasion.

[0185] In one aspect, a separate preamble index or a separate RACH occasion in a RACH occasion can be used to indicate the corresponding MCS or TBS for transmitting a MsgA PUSCH or a MsgA PUSCH occasion.

[0186] In one aspect, process 2200 includes mapping preamble indices associated with PUSCH resource elements starting from 0 for all 1 / N consecutive valid PRACH opportunities associated with one SSB when 2-step RACH and 4-step RACH are configured with separate RACH opportunities.

[0187] In an embodiment, if 2-step RACH and 4-step RACH are configured with separate RACH occasions and more than one SSB is associated with one PRACH occasion, then for the contention-based 2-step RACH procedure, Begin mapping preamble indices associated with PUSCH resource elements. N may be configured separately for 2-step RACH compared to 4-step RACH. In an embodiment, process 2200 is performed by a UE or a portion thereof. In an embodiment, the process is performed by a gNB or a portion thereof.

[0188] In an embodiment, process 2200 may include wireless communications for a 5G or NR system. In an embodiment, the gNodeB configures multiple PRACH opportunities associated with a PUSCH opportunity, multiple contention-based preambles for each PRACH opportunity for each PUSCH opportunity, and multiple preambles associated with a PUSCH resource unit.

[0189] Generally speaking, the PRACH preambles may be ordered based on the following. First, the order may be the ascending order of the preamble index within a single PRACH opportunity. Second, the order may be the ascending order of the frequency resource index of a frequency multiplexed PRACH opportunity. Third, the order may be the ascending order of the time resource index of a time multiplexed PRACH opportunity within a PRACH slot. Fourth, the order may be the ascending order of the index of the PRACH slot.

[0190] In an implementation scheme, the PUSCH resource units may be ordered as follows. First, the order may be the increasing order of the DMRS ports or DMRS sequences within a single PUSCH opportunity. Second, the order may be the increasing order of the frequency resource index of the frequency multiplexed MsgA PUSCH opportunity. Third, the order may be the increasing order of the time resource index of the time multiplexed MsgAPUSCH opportunity within the MsgA PUSCH slot. Fourth, the order may be the increasing order of the index of the MsgA PUSCH slot.

[0191] In an embodiment, multiple disjoint PUSCH opportunity sets are determined based on the start and length indicator value (SLIV) of each PUSCH opportunity in the slot.In an embodiment, the ordering of the time resource indexes of the time multiplexed MsgAPUSCH opportunities within the MsgA PUSCH slot is based on disjoint PUSCH opportunity sets.

[0192] In an implementation scheme, for a contention-based 2-step RACH procedure, the preamble index is mapped just after the preamble index for a contention-based 4-step RACH. In an implementation scheme, when one synchronization signal block (SSB) is associated with more than one PRACH opportunity, for a contention-based 2-step RACH procedure, the preamble index associated with the PUSCH resource element is mapped starting from the Rth for all 1 / N consecutive valid PRACH opportunities associated with one SSB.

[0193] In an embodiment, when more than one SSB is associated with one PRACH opportunity for a contention-based 2-step RACH procedure, Start mapping preamble indices associated with PUSCH resource elements. In an embodiment, parameters including rach-Occasion-perPUSChoccasionAndCB-PreamblesPerPRACH may be configured for the association between PRACH and PUSCH opportunities and the number of preambles for 2-step RACH. N1 PRACH opportunities associated with one PUSCH opportunity and R1 contention-based preambles per PUSCH opportunity per PRACH opportunity may be derived.

[0194] In an embodiment, if N1<1, one PRACH opportunity is mapped to 1 / N1 consecutive PUSCH opportunities that may or may not be configured with the same MCS and / or TBS. If N1≥1, N1 PRACH opportunities are associated with one PUSCH opportunity. In an embodiment, the preamble indexes associated with the PUSCH opportunities are mapped consecutively. In an embodiment, the parameter preamble-perPUSCHresourceunit may be configured by higher layers to indicate N pre-puschunit A preamble is associated with a PUSCH resource element.

[0195] In an embodiment, the DMRS port indices associated with the PRACH opportunities are mapped consecutively. In an embodiment, for many-to-one mapping, the N associated with the PUSCH resource elements are mapped consecutively. pre-puschunit Preamble code indices are mapped continuously. In an implementation scheme, when one PRACH opportunity is associated with one PUSCH opportunity, for example, N1=1, the PUSCH resource elements or DMRS APs associated with the PRACH opportunity are mapped starting from 0 and are mapped continuously. In an implementation scheme, when one PRACH opportunity is associated with more than one PUSCH opportunity, for example, N1<1, the PUSCH resource elements or DMRS APs associated with the PRACH opportunity are mapped starting from 0 and are mapped continuously.

[0196] In an embodiment, when more than one PRACH occasion is associated with a PUSCH occasion, e.g., N1≥1, the PUSCH resource element or DMRS AP associated with PRACH occasion k (0 < k ≤ N1 - 1) is mapped from starting, where is the total number of PUSCH resource elements or DMRS APs of a PUSCH occasion. In an embodiment, a separate preamble index or a separate RACH occasion in a RACH occasion can be used to indicate the corresponding MCS or TBS for transmitting MsgA PUSCH or MsgA PUSCH occasion.

[0197] In an example, a method is for a user equipment (UE) to generate a mapping between a physical random access channel (PRACH) preamble and a physical uplink shared channel (PUSCH) resource element in a fifth generation (5G) new radio (NR) network. The method includes: configuring a first number of PRACH occasions each associated with a PUSCH occasion; configuring a second number of contention-based preambles for each PRACH occasion of each PUSCH occasion; configuring a third number of preambles associated with the PUSCH resource elements of at least one PUSCH occasion; receiving a message including preamble data and message data from the user equipment (UE); and sending a response message to the UE according to the first number, the second number, and the third number, the response message including random access response (RAR) data and contention resolution data.

[0198] In an example, the UE sorts the preambles among the third number of preambles based on the following order: an increasing order of preamble indices within a single PRACH occasion; an increasing order of frequency resource indices, where the PRACH occasion is a frequency multiplexing occasion; an increasing order of time resource indices, where the PRACH occasion is a time multiplexing occasion; an increasing order of the indices of PRACH time slots; or a combination thereof.

[0199] In an example, at least one PUSCH occasion includes a fourth number of PUSCH resource elements, and the UE sorts the fourth number of PUSCH resource elements based on the following order: an increasing order of demodulation reference signal (DMRS) ports or sequences within at least one PUSCH occasion; an increasing order of frequency resource indices, where at least one PUSCH occasion is frequency multiplexed; an increasing order of time resource indices, where at least one PUSCH occasion is used for time multiplexing within a PUSCH time slot; an increasing order of the indices of MsgA PUSCH time slots; or a combination thereof.

[0200] In an example, at least one PUSCH opportunity includes multiple PUSCH opportunities, and the UE is configured to determine multiple non-overlapping PUSCH opportunity sets based on a start and length indicator value (SLIV) of each PUSCH opportunity in the multiple PUSCH opportunities; wherein the ordering of time resource indexes of time-multiplexed PUSCH opportunities in the multiple PUSCH opportunities is based on multiple non-overlapping PUSCH opportunity sets.

[0201] In an example, a synchronization signal block (SSB) is associated with at least two PRACH opportunities, and the UE is configured to map preamble indices associated with PUSCH resource units starting from a given preamble among a third number of preambles for a fifth number of consecutive valid PRACH opportunities associated with the SSB, wherein the fifth number is inversely proportional to the first number of PRACH opportunities.

[0202] In an example, a plurality of SSBs are associated with each PRACH opportunity in a first number of PRACH opportunities, wherein the UE is configured to map a preamble index to a PUSCH resource element of a PUSCH opportunity based on a function of, for an SSB in the plurality of SSBs, a third number of preambles and a number of synchronization signal / physical broadcast channel (SS / PBCH) blocks associated with a PRACH opportunity in the first number of PRACH opportunities.

[0203] In an example, the UE is configured to map preamble indices associated with PUSCH opportunities in a consecutive order for a third number of preambles. In an example, the UE is configured to map DMRS port indices associated with PRACH opportunities in a first number of PRACH opportunities in a consecutive order. In an example, the PRACH opportunities in the first number of PRACH opportunities have a one-to-one association with the PUSCH opportunities, and the UE is configured to map the PUSCH resource elements or DMRS antenna ports associated with the PRACH opportunities starting from 0 and continuously increasing.

[0204] In an example, an individual preamble index of a PRACH opportunity indicates a corresponding modulation and coding scheme (MCS) or transport block size TBS used for transmission of MsgA PUSCH by the UE.

[0205] In an example, the UE determines multiple disjoint PUSCH opportunity sets based on a start and length indicator value (SLIV) of each PUSCH opportunity in a slot. In an example, the ordering of time resource indices of time multiplexed MsgA PUSCH opportunities within an MsgA PUSCH slot is based on disjoint PUSCH opportunity sets.

[0206] In the example, for the contention-based 2-step RACH procedure, the UE maps the preamble index just after the preamble index for the contention-based 4-step RACH. In the example, when one synchronization signal block (SSB) is associated with more than one PRACH opportunity, for the contention-based 2-step RACH procedure, the UE maps the preamble index associated with the PUSCH resource element starting from the Rth for all 1 / N consecutive valid PRACH opportunities associated with one SSB.

[0207] In the example, when more than one SSB is associated with one PRACH opportunity for the contention-based 2-step RACH procedure, the UE Start mapping preamble indices associated with PUSCH resource elements. In the example, the UE configuration includes parameters rach-Occasion-perPUSCHoccasionAndCB-PreamblesPerPRACH for the association between PRACH and PUSCH opportunities and the number of preambles for 2-step RACH. The UE derives N1 PRACH opportunities associated with one PUSCH opportunity and R1 contention-based preambles per PUSCH opportunity per PRACH opportunity.

[0208] In an example, if N1<1, the UE maps one PRACH opportunity to 1 / N1 consecutive PUSCH opportunities that may or may not be configured with the same MCS and / or TBS. If N1≥1, the UE associates N1 PRACH opportunities with one PUSCH opportunity. In an example, the UE maps the preamble index associated with the PUSCH opportunity continuously. In an example, the parameter preamble-perPUSCHresourceunit may be configured by a higher layer to indicate N pre-puschunit A preamble is associated with a PUSCH resource element.

[0209] In an example, the UE maps DMRS port indices associated with PRACH opportunities continuously. In an example, for many-to-one mapping, the UE maps N DMRS port indices associated with PUSCH resource elements continuously. pre-puschunit preamble indexes. In the example, when one PRACH opportunity is associated with one PUSCH opportunity, for example, N1=1, the PUSCH resource elements or DMRS APs associated with the PRACH opportunity are mapped by the UE starting from 0 and are mapped continuously. In the example, when one PRACH opportunity is associated with more than one PUSCH opportunity, for example, N1<1, the PUSCH resource elements or DMRS APs associated with the PRACH opportunity are mapped by the UE starting from 0 and are mapped continuously.

[0210] In an example, when more than one PRACH occasion is associated with a PUSCH occasion, e.g., N1 ≥ 1, the PUSCH resource element or DMRS AP associated with the PRACH occasion k (0 < k ≤ N1 - 1) is mapped by the UE starting from where is the total number of PUSCH resource elements or DMRS APs of a PUSCH occasion. In the example, the individual preamble index in the RACH occasion or the individual RACH occasion can be used by the UE to indicate the corresponding MCS or TBS for transmitting the MsgA PUSCH or MsgA PUSCH occasion.

[0211] In an example, a method is for generating a mapping between physical random access channel (PRACH) preambles and physical uplink shared channel (PUSCH) resource elements in a fifth generation (5G) new radio (NR) network by a next generation node (gNB). The method includes: mapping one or more PRACH occasions to one or more PUSCH resource elements; and generating one or more PUSCH resource elements based on the mapping. In the example, the gNB is configured to obtain one or more PRACH occasions. In the example, the gNB is configured to determine one or more rules for mapping one or more PRACH occasions to one or more PUSCH resource elements. In the example, the one or more rules for mapping are used to convert a 4-step RACH procedure into a 2-step RACH procedure.

[0212] In an example, one or more PRACH occasions each include a plurality of PRACH preambles. In the example, the plurality of PRACH preambles include N synchronization signal / physical broadcast channel (SS / PBCH) blocks, where R contention-based preambles are associated with each of the N SS / PBCH blocks. In the example, the N SS / PBCH blocks and the R contention-based preambles are configured by ssb-perRACH-OccasionAndCB-PreamblesPerSSB.

[0213] In an example, the gNB is configured to sort or cause to sort the plurality of PRACH preambles in the following order: in ascending order of the corresponding preamble index within a single PRACH occasion; in ascending order of the frequency resource index of frequency multiplexed PRACH occasions; in ascending order of the time resource index of time multiplexed PRACH occasions within a PRACH time slot; or in ascending order of the index of the PRACH time slot.

[0214] In an example, the gNB is configured to order or cause the plurality of PRACH preambles to be ordered according to: a decreasing order of corresponding preamble indices within a single PRACH opportunity; a decreasing order of frequency resource indices of a frequency multiplexed PRACH opportunity; a decreasing order of time resource indices of a time multiplexed PRACH opportunity within a PRACH slot; or a decreasing order of indices of the PRACH slots.

[0215] In an example, the gNB is configured to sort one or more PUSCH resource units according to: an increasing order of demodulation reference signal (DMRS) ports or DMRS sequences within a single PUSCH opportunity; an increasing order of frequency resource indices of frequency multiplexed MsgAPUSCH opportunities; an increasing order of time resource indices of time multiplexed MsgA PUSCH opportunities within an MsgA PUSCH slot; or an increasing order of indices of MsgA PUSCH slots.

[0216] In an example, a plurality of disjoint PUSCH opportunity sets are determined according to a start and length indicator value (SLIV) of each PUSCH opportunity in a slot.In an example, the ordering of time resource indices of time multiplexed MsgA PUSCH opportunities within an MsgA PUSCH slot is based on disjoint PUSCH opportunity sets.

[0217] In an example, for a contention-based 2-step RACH procedure, the preamble index is mapped just after the preamble index for a contention-based 4-step RACH. In an example, when one synchronization signal block (SSB) is associated with more than one PRACH opportunity, for a contention-based 2-step RACH procedure, the preamble index associated with the PUSCH resource element is mapped starting from the Rth for all 1 / N consecutive valid PRACH opportunities associated with one SSB.

[0218] In the example, when more than one SSB is associated with one PRACH opportunity for a contention-based 2-step RACH procedure, Start mapping preamble indices associated with PUSCH resource elements. In an example, parameters including rach-Occasion-perPUSChoccasionAndCB-PreamblesPerPRACH may be configured for association between PRACH and PUSCH opportunities and the number of preambles for 2-step RACH. N1 PRACH opportunities associated with one PUSCH opportunity and R1 contention-based preambles per PUSCH opportunity per PRACH opportunity may be derived.

[0219] In an example, if N1 < 1, one PRACH occasion is mapped to 1 / N1 consecutive PUSCH occasions that may or may not be configured with the same MCS and / or TBS. If N1 ≥ 1, N1 PRACH occasions are associated with one PUSCH occasion. In the example, the preamble indices associated with the PUSCH occasion are mapped consecutively. In the example, the parameter preamble-perPUSCHresourceunit can be configured by a higher layer to indicate N pre-puschunit preambles associated with a PUSCH resource unit.

[0220] In the example, the DMRS port indices associated with the PRACH occasion are mapped consecutively. In the example, for the many-to-one mapping, the N pre-puschunit preamble indices associated with the PUSCH resource unit are mapped consecutively. In the example, when one PRACH occasion is associated with one PUSCH occasion, e.g., N1 = 1, the PUSCH resource unit or DMRS AP associated with the PRACH occasion is mapped starting from 0 and is mapped consecutively. In the example, when one PRACH occasion is associated with more than one PUSCH occasion, e.g., N1 < 1, the PUSCH resource unit or DMRS AP associated with the PRACH occasion is mapped starting from 0 and is mapped consecutively.

[0221] In the example, when more than one PRACH occasion is associated with one PUSCH occasion, e.g., N1 ≥ 1, the PUSCH resource unit or DMRS AP associated with the PRACH occasion k (0 < k ≤ N1 - 1) starts to be mapped from where is the total number of PUSCH resource units or DMRS APs of one PUSCH occasion. In the example, the individual preamble index or the individual RACH occasion in the RACH occasion can be used to indicate the corresponding MCS or TBS for transmitting MsgA PUSCH or MsgA PUSCH occasion.

[0222] In some examples, at least one of the components shown in one or more of the foregoing figures can be configured to perform one or more of the operations, techniques, processes, and / or methods described in the example section below. For example, the baseband circuitry described above in connection with one or more of the foregoing figures can be configured to operate according to one or more of the following embodiments. In some examples, the circuitry associated with the UE, base station, network element, or other components described above in connection with one or more of the foregoing figures can be configured to operate according to one or more of the examples shown in the example section below.

[0223] It is understood that the use of personally identifiable information should be subject to privacy policies and practices that are generally recognized to meet or exceed industry or government requirements for maintaining user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of the authorized use should be clearly stated to users.

[0224] In different specific implementations, the methods described herein can be implemented in software, hardware, or a combination thereof. In addition, the order of the blocks of the method can be changed, and various elements can be added, reordered, combined, omitted, modified, etc. Various modifications and changes can be made, which will be apparent to those skilled in the art who benefit from this disclosure. The various specific implementations described herein are intended to be illustrative and not restrictive. Many variations, modifications, additions, and improvements are possible. Therefore, multiple examples can be provided for the components described herein as a single example. The boundaries between various components, operations, and data repositories are arbitrary to a certain extent, and specific operations are shown in the context of a specific exemplary configuration. Other allocations of functions are contemplated, and they may fall within the scope of the appended claims. Finally, the structure and function presented as discrete components in the exemplary configuration may be implemented as a combined structure or component.

[0225] The following terms and definitions may apply to the examples described herein.

[0226] As used herein, the term "circuit" refers to, is part of, or includes a hardware component such as an electronic circuit, a logic circuit, a processor (shared, dedicated, or group) and / or a memory (shared, dedicated, or group) configured to provide the described functions, an application specific integrated circuit (ASIC), a field programmable device (FPD) (e.g., a field programmable gate array (FPGA), a programmable logic device (PLD), a complex PLD (CPLD), a high capacity PLD (HCPLD), a structured ASIC, or a programmable SoC), a digital signal processor (DSP), etc. In some embodiments, the circuit may execute one or more software or firmware programs to provide at least some of the described functions. The term "circuit" may also refer to a combination of one or more hardware elements and a program code for performing the functions of the program code (or a combination of circuits used in an electrical or electronic system). In these embodiments, the combination of hardware elements and program code may be referred to as a specific type of circuit.

[0227] As used herein, the term "processor circuit" refers to, is part of, or includes a circuit capable of sequentially and automatically performing a series of arithmetic or logical operations or recording, storing, and / or transmitting digital data. The term "processor circuit" may refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single-core processor, a dual-core processor, a triple-core processor, a quad-core processor, and / or any other device capable of executing or otherwise operating computer-executable instructions (such as program code, software modules, and / or functional processes). The terms "application circuit" and / or "baseband circuit" may be considered synonymous with "processor circuit" and may be referred to as "processor circuit".

[0228] As used herein, the term "interface circuit" refers to a circuit that enables, is a part of, or includes information exchange between two or more components or devices. The term "interface circuit" may refer to one or more hardware interfaces, such as a bus, an I / O interface, a peripheral component interface, a network interface card, etc.

[0229] As used herein, the term "user equipment" or "UE" refers to a device that has radio communication capabilities and can describe a remote user of network resources in a communication network. In addition, the terms "user equipment" or "UE" may be considered synonymous and may be referred to as a client, mobile phone, mobile device, mobile terminal, user terminal, mobile unit, mobile station, mobile user, subscriber, user, remote station, access agent, user agent, receiver, radio equipment, reconfigurable radio equipment, reconfigurable mobile device, etc. In addition, the term "user equipment" or "UE" may include any type of wireless / wired device or any computing device that includes a wireless communication interface.

[0230] As used herein, the term "network element" refers to physical or virtualized equipment and / or infrastructure for providing wired or wireless communication network services. The term "network element" may be considered synonymous with and / or referred to as a networked computer, networking hardware, network equipment, network node, router, switch, hub, bridge, radio network controller, RAN equipment, RAN node, gateway, server, virtualized VNF, NFVI, etc.

[0231] As used herein, the term "computer system" refers to any type of interconnected electronic devices, computer devices, or components thereof. Additionally, the terms "computer system" and / or "system" may refer to various components of a computer that are communicatively coupled to one another. Furthermore, the terms "computer system" and / or "system" may refer to multiple computer devices and / or multiple computing systems that are communicatively coupled to one another and configured to share computing and / or networking resources.

[0232] As used herein, the terms "appliance", "computer appliance", etc. refer to a computer device or computer system with program code (e.g., software or firmware) that is specifically designed to provide specific computing resources. A "virtual appliance" is a virtual machine image to be implemented by a device equipped with a hypervisor that virtualizes or emulates a computer appliance or is otherwise dedicated to providing specific computing resources.

[0233] As used herein, the term "resource" refers to a physical or virtual device, a physical or virtual component within a computing environment, and / or a physical or virtual component within a specific device, such as a computer device, a mechanical device, a memory space, a processor / CPU time and / or a processor / CPU usage rate, a processor and accelerator load, a hardware time or usage rate, a power supply, an input / output operation, a port or a network socket, a channel / link allocation, throughput, memory usage rate, storage, a network, a database and an application, a unit of work, etc. "Hardware resources" may refer to computing, storage and / or network resources provided by physical hardware elements. "Virtualized resources" may refer to computing, storage and / or network resources provided by a virtualized infrastructure to an application, a device, a system, etc. The term "network resources" or "communication resources" may refer to resources that a computer device / system can access via a communication network. The term "system resources" may refer to any kind of shared entity that provides a service, and may include computing resources and / or network resources. System resources may be considered as a set of coherent functions, network data objects or services that can be accessed through a server, wherein such system resources reside on a single host or multiple hosts and can be clearly identified.

[0234] As used herein, the term "channel" refers to any tangible or intangible transmission medium for transmitting data or data streams. The term "channel" may be synonymous and / or equivalent to "communication channel", "data communication channel", "transmission channel", "data transmission channel", "access channel", "data access channel", "link", "data link", "carrier", "radio frequency carrier" and / or any other similar terms representing a path or medium through which data is transmitted. In addition, the term "link" as used herein refers to a connection between two devices for transmitting and receiving information over a RAT.

[0235] As used herein, the terms "instantiate," "instantiate," and the like refer to the creation of an instance. "Instance" also refers to a specific occurrence of an object, which may occur, for example, during the execution of program code.

[0236] The terms "coupled," "communicatively coupled," and their derivatives are used herein. The term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, may mean that two or more elements are in indirect contact with each other but still cooperate or interact with each other, and / or may mean that one or more other elements are coupled or connected between the elements said to be coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact with each other. The term "communicatively coupled" may mean that two or more elements may be in contact with each other by means of communication, including through a wire or other interconnect connection, through a wireless communication channel or link, etc.

[0237] The term "information element" refers to a structural element that contains one or more fields. The term "field" refers to the individual contents of an information element, or a data element that contains the contents.

[0238] The term "SMTC" refers to the SSB-based measurement timing configuration configured by SSB-MeasurementTimingConfiguration.

[0239] The term "SSB" refers to SS / PBCH block.

[0240] The term "primary cell" refers to an MCG cell operating on a primary frequency, where the UE either performs an initial connection establishment procedure or initiates a connection re-establishment procedure.

[0241] The term "primary SCG cell" refers to an SCG cell in which a UE performs random access when reconfiguration is performed using a synchronization procedure for DC operation.

[0242] The term "secondary cell" refers to a cell that provides additional radio resources on top of a special cell for a UE configured with CA.

[0243] The term "secondary cell group" refers to a subset of serving cells including a PSCell for a UE configured with DC and zero or more secondary cells.

[0244] The term "serving cell" refers to a primary cell for a UE in RRC_CONNECTED without CA / DC configured, where there is only one serving cell including the primary cell.

[0245] The term "serving cell" refers to a cell group including a special cell for a UE configured with CA / DC and in RRC_CONNECTED and all secondary cells.

[0246] The term "special cell" refers to the PCell of the MCG or the PSCell of the SCG for DC operation; otherwise, the term "special cell" refers to the Pcell.

Claims

1. One or more processors configured to perform operations including: configuring a first number of preambles per physical random access channel (PRACH) opportunity; configuring a plurality of disjoint physical uplink shared channel (PUSCH) opportunity sets, wherein the plurality of disjoint PUSCH opportunity sets are multiplexed in a time division multiplexing manner, and wherein an ordering of time resource indexes for the time multiplexed PUSCH opportunities is based on the plurality of disjoint PUSCH opportunity sets; associating a PRACH preamble in a PRACH opportunity with the time multiplexed PUSCH opportunity associated with a demodulation reference signal (DMRS); receiving a PUSCH transmission from a remote device based on the first number of preambles and the association; and A message is encoded for transmission to the remote device, the message comprising random access response (RAR) data in response to the received PUSCH transmission.

2. The one or more processors of claim 1 , wherein the preambles are sorted based on the following order: First, the increasing order of preamble indexes within a single PRACH opportunity; second, an increasing order of frequency resource indices, where the PRACH opportunities are frequency multiplexed opportunities; Third, an increasing order of time resource indices, where the PRACH opportunities are time multiplexed opportunities; Fourth, the increasing order of the index of the PRACH time slots; or A combination of them.

3. The one or more processors of claim 1 , wherein a PUSCH opportunity comprises a number of PUSCH resource elements, and wherein the number of PUSCH resource elements are ordered based on the following order: First, the increasing order of demodulation reference signal (DMRS) ports or sequences within the PUSCH opportunity; second, the increasing order of frequency resource indices, where the PUSCH opportunities are frequency multiplexed; third, an increasing order of time resource indices, where the PUSCH opportunities are used for time multiplexing within a PUSCH time slot; Fourth, the ascending order of the index of the MsgA PUSCH time slot; or A combination of them.

4. The one or more processors of claim 1, wherein the operations further comprise: The plurality of disjoint sets of PUSCH opportunities are determined based on a start and length indicator value (SLIV) of each of the PUSCH opportunities, the SLIV comprising the index of the first time slot.

5. The one or more processors of claim 1 , wherein a synchronization signal block (SSB) is associated with at least two PRACH opportunities, and wherein a preamble index associated with a PUSCH resource unit is mapped starting from a given preamble for a number of consecutive valid PRACH opportunities associated with the SSB, wherein the number is inversely proportional to the number of the PRACH opportunities.

6. The one or more processors of claim 1, wherein a plurality of SSBs are associated with each of the PRACH opportunities, wherein the operations further comprise: For an SSB among the plurality of SSBs, a preamble index is mapped to a PUSCH resource element of the PUSCH opportunity based on a function of a first number of the preambles and a number of synchronization signal / physical broadcast channel (SS / PBCH) blocks associated with a PRACH opportunity among the PRACH opportunities.

7. The one or more processors of claim 1, further comprising mapping DMRS port indices associated with PRACH opportunities in the PRACH opportunities in a consecutive order.

8. The one or more processors of claim 1, wherein a PRACH opportunity in the PRACH opportunities has a one-to-one association with the PUSCH opportunities, the operations further comprising: The DMRS antenna ports or PUSCH resource elements associated with the PRACH opportunity are mapped starting from 0 and continuously increasing.

9. The one or more processors of claim 1, wherein the individual preamble index of the PRACH opportunity indicates a corresponding modulation and coding scheme (MCS) or transport block size (TBS) used for transmitting the MsgA PUSCH.

10. A user equipment (UE) configured to generate a mapping between a physical random access channel (PRACH) preamble and a physical uplink shared channel (PUSCH) resource element, the UE comprising: at least one processor; and a memory storing one or more instructions that, when executed by the at least one processor, cause the at least one processor to perform operations including: Mapping one or more PRACH opportunities to one or more PUSCH resource elements; as well as generating a message including one or more PRACH opportunities and one or more PUSCH resource elements in a RACH procedure; as well as The message is transmitted to the next generation node (gNB).

11. The UE of claim 10, wherein the plurality of different PUSCH opportunities are associated with different modulation and coding schemes (MCS) or different transport block sizes (TBS), and wherein the operations further comprise: First, sorting the preamble code indexes of the multiple different PUSCH opportunities from the minimum MCS to the maximum MCS; or Second, the plurality of different PUSCH opportunities are sorted from smallest identifier (ID) value to largest ID value.

12. The UE of claim 10, wherein the operations further comprise determining one or more rules for mapping the one or more PRACH opportunities to one or more PUSCH resource elements.

13. The UE of claim 12, wherein the one or more rules for mapping are used to convert a 4-step RACH procedure into a 2-step RACH procedure.

14. The UE according to claim 10, wherein the one or more PRACH opportunities respectively include a plurality of PRACH preambles.

15. The UE of claim 10, wherein the plurality of PRACH preambles comprises a number N of synchronization signal / physical broadcast channel (SS / PBCH) blocks, wherein a number R of contention-based preambles are associated with each of the N SS / PBCH blocks.

16. The UE according to claim 15, wherein the N SS / PBCH blocks and the R contention-based preambles are configured by ssb-perRACH-OccasionAndCB-PreamblesPerSSB.

17. The UE of claim 10, wherein the operations further comprise: Order or cause multiple PRACH preambles to be ordered according to the following order: First, the increasing order of the corresponding preamble indexes within a single PRACH opportunity; Second, the ascending order of frequency resource indexes of frequency multiplexed PRACH opportunities; Third, the increasing order of the time resource indices of the time multiplexed PRACH opportunities within the PRACH time slot; or Fourth, the increasing order of the index of the PRACH time slots.

18. The UE of claim 10, wherein the operations further comprise: Order or cause multiple PRACH preambles to be ordered according to the following order: First, the decreasing order of the corresponding preamble indexes within a single PRACH opportunity; Second, the descending order of the frequency resource indexes of the frequency multiplexed PRACH opportunities; Third, the descending order of the time resource indexes of the time multiplexed PRACH opportunities within the PRACH time slot; or Fourth, the descending order of the index of the PRACH time slots.

19. The UE according to claim 10, further comprising: The one or more PUSCH resource elements are sorted according to the following order: First, the increasing order of demodulation reference signal (DMRS) ports or DMRS sequences within a single PUSCH opportunity; Second, the ascending order of the frequency resource index of the frequency multiplexing MsgA PUSCH opportunity; Third, the increasing order of the time resource indexes of the time multiplexed MsgA PUSCH opportunities within the MsgA PUSCH time slot; or Fourth, the increasing order of the index of the MsgA PUSCH time slot.

20. One or more processors configured to perform operations comprising: Determining a mapping of a physical random access channel (PRACH) preamble in a PRACH opportunity and a physical uplink shared channel (PUSCH) opportunity associated with a demodulation reference signal (DMRS) resource, the determining comprising: determining a first number of preambles per PRACH opportunity; as well as determining a plurality of disjoint sets of PUSCH opportunities in a first time slot, wherein an ordering of time resource indexes of time multiplexed PUSCH opportunities in the plurality of PUSCH opportunities is based on the plurality of disjoint sets of PUSCH opportunities in the first time slot; transmitting a PUSCH transmission to a remote device based on the first number of preambles and the determined mapping; as well as A message from the remote device is decoded, the message comprising random access response (RAR) data in response to the transmitted PUSCH transmission.

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