Epitaxial wafer, radio frequency device, terminal radio frequency module and terminal equipment

Abstract

The embodiment of the invention provides an epitaxial wafer, a radio frequency device, a terminal radio frequency module and terminal equipment. The epitaxial wafer comprises a silicon substrate layer and an epitaxial layer which are stacked, wherein the epitaxial layer comprises a nucleating layer stacked on the surface of the silicon substrate layer; and an air gap is arranged at the interface of the silicon substrate layer and the nucleating layer. Based on the special structure and parameter design at the interface of the silicon substrate layer and the nucleating layer in the epitaxial wafer, the epitaxial wafer can be used for providing a radio frequency device with lower radio frequency loss.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and specifically to epitaxial wafers, radio frequency devices, terminal radio frequency modules and terminal equipment. Background Art

[0002] At present, most RF devices use III-group nitride semiconductor devices represented by gallium nitride (GaN), especially RF devices with GaN-based heterostructures based on silicon carbide substrates. In theory, the above structures can also be grown on silicon substrates, and silicon substrates can be used to prepare larger and lower-cost RF devices. However, the use of silicon substrates will cause serious RF losses in the above RF devices, reducing the working efficiency of RF devices.

[0003] In order to reduce the serious RF loss caused by the conduction of the silicon substrate in GaN-based RF integrated circuit devices on silicon substrates, the industry often uses high-resistivity silicon wafers as silicon substrates, but the improvement effect is limited; this is largely attributed to the presence of parasitic conductive channels at the interface between the silicon substrate and the GaN-based epitaxial structure. Therefore, some technicians have tried to remove the silicon substrate in some areas to eliminate the parasitic conductive channels at the interface between the silicon substrate and the epitaxial structure, but such operations are not only difficult to process, but also affect the structural stability of the RF device, and are also not conducive to the promotion and application of GaN-based RF integrated circuit devices. Therefore, it is urgent to provide a new epitaxial wafer that can reduce the RF loss of the silicon substrate and ensure the structural stability and quality of the epitaxial structure and the RF device. Summary of the invention

[0004] In view of this, the embodiments of the present application provide an epitaxial wafer, a radio frequency device, a terminal radio frequency module and a terminal device. Based on the special structure and parameter design at the interface between the silicon substrate layer and the nucleation layer in the epitaxial wafer, it can be used to provide a radio frequency device with low radio frequency loss.

[0005] In a first aspect, an embodiment of the present application provides an epitaxial wafer, comprising a stacked silicon substrate layer and an epitaxial layer, wherein the epitaxial layer comprises a nucleation layer stacked on the surface of the silicon substrate;

[0006] The surface of the silicon substrate layer close to the nucleation layer has a plurality of first blind holes, and the surface of the nucleation layer close to the silicon substrate layer has a plurality of second blind holes, any of the second blind holes is arranged corresponding to one of the first blind holes, and the orthographic projection of the second blind hole on the silicon substrate layer overlaps with the corresponding first blind hole;

[0007] Wherein, the depth of the first blind hole is greater than or equal to 200 nm.

[0008] The above special structural design can make the interface between the silicon substrate layer and the nucleation layer have multiple "air gaps"; and the depth of the above "air gaps" in the silicon substrate layer is ≥200nm, which can effectively cut off the parasitic conductive channel at the interface between the silicon substrate layer and the nucleation layer, thereby better suppressing the parasitic conductivity effect at the above interface, and then the above epitaxial wafer can be used to provide a radio frequency device with lower radio frequency loss.

[0009] In some embodiments of the present application, the depth of the first blind hole is 200nm-500nm. When the depth of the first blind hole is controlled within the above range, the air gap formed by the first blind hole can fully exert its effect, cut off the parasitic conductive channel between the silicon substrate layer and the nucleation layer, and ensure that the silicon substrate layer has a strong support force for the superimposed structure on its surface, the epitaxial wafer is easy to manufacture and the crystal quality of the epitaxial layer is high, so when it is used in a radio frequency device, it is more conducive to improving its power and efficiency.

[0010] In some embodiments of the present application, the number of the second blind holes is the same as the number of the first blind holes, and the plurality of the first blind holes are arranged in one-to-one correspondence with the plurality of the second blind holes. The epitaxial wafer with the above structure is easy to manufacture and has a better effect of suppressing radio frequency loss.

[0011] In some embodiments of the present application, the depth of the second blind hole is 300nm-500nm. Controlling the depth of the second blind hole within the above range is beneficial to ensuring the structural strength and mechanical properties of the nucleation layer itself, and is beneficial for the air gap to play a better role in suppressing parasitic conduction.

[0012] In some embodiments of the present application, the inner diameter of the first blind hole is equal everywhere along the stacking direction of the silicon substrate layer and the epitaxial layer. In this way, in the area from the plane where the end face of the first blind hole is located to the surface of the silicon substrate layer away from the nucleation layer, the silicon substrate layer has good structural uniformity, which can better cut off the parasitic conductive channel, so that the air gap formed by it can have better benefits, which is more conducive to reducing the RF loss of the final RF device.

[0013] In some embodiments of the present application, the angle between the sidewall of the first blind hole and the surface of the silicon substrate layer close to the nucleation layer is 85°-90°. In this way, the inner diameter of the first blind hole changes little or remains the same along the stacking direction of the silicon substrate layer and the nucleation layer, which can avoid the phenomenon that the parasitic conductive channel is not completely destroyed due to the uneven structure of the first blind hole, thereby affecting the air gap gain.

[0014] In some embodiments of the present application, the opening diameter of the first blind hole is 100nm-1000nm. Controlling the opening diameter of the first blind hole within the above range is not only easy to prepare, but more importantly, can achieve a more ideal effect of cutting off the parasitic conductive channel.

[0015] In some embodiments of the present application, the opening of the first blind hole is circular or n-gonal, where n>8. In this way, the air gap formed by the first blind hole has a better benefit, which is beneficial to suppressing radio frequency loss when the epitaxial wafer is used in a radio frequency device.

[0016] In some embodiments of the present application, in the first direction, the plurality of first blind holes are arranged periodically; wherein the first direction is perpendicular to the stacking direction of the silicon substrate layer and the nucleation layer. This is to ensure the structural uniformity of the silicon substrate layer and fully reduce the risk of cracks in subsequent applications due to uneven internal stress distribution or insufficient bearing capacity; it is also considered that there may be many repeating units (a gate and the regions where a drain and a source are located on both sides thereof are regarded as the same repeating unit) or circuit elements in the RF device, so that in the subsequent application process, the parasitic conductive channels in different regions at the first interface are well cut off, which can better suppress the RF loss of the RF device.

[0017] In some embodiments of the present application, along the first direction, the minimum distance between the openings of two adjacent first blind holes on the silicon substrate layer is 200nm-1000nm. Controlling the arrangement period of the first blind holes within the above range also controls the distribution density of the first blind holes. In this way, when it is applied to a radio frequency device, it is beneficial to realize that there is an air gap in any repeating unit to suppress radio frequency loss, thereby improving the performance of the radio frequency device.

[0018] In some embodiments of the present application, in the first direction, the plurality of first blind holes are arranged in a regular hexagonal periodic pattern. The first blind holes are arranged in a regular hexagonal periodic pattern, which is beneficial to the subsequent growth of the epitaxial layer and also helps to ensure that the crystal quality of the epitaxial layer is good, so that when it is used in a radio frequency device, it is beneficial to improve its power and efficiency.

[0019] In some embodiments of the present application, the nucleation layer is a two-dimensional nucleation layer. The two-dimensional nucleation layer has high crystal quality, so when the epitaxial wafer is used in a radio frequency device, the power and efficiency of the radio frequency device can be improved, the device performance can be greatly improved, and its market competitiveness can be increased.

[0020] In some embodiments of the present application, the thickness of the nucleation layer is 300nm-1000nm. In this way, the structural integrity of the nucleation layer is high, the crystal quality of the nucleation layer itself is high, and it is also more conducive to ensuring the improvement of the overall crystal quality of the epitaxial layer; in addition, the appropriate thickness can avoid the risk of cracking of the nucleation layer, thereby improving the comprehensive performance of the epitaxial wafer.

[0021] In some embodiments of the present application, the nucleation layer includes a two-dimensional nucleation layer and a three-dimensional nucleation layer stacked in sequence, and the two-dimensional nucleation layer is arranged close to the silicon substrate layer. In this way, the crystal quality and production efficiency of the epitaxial layer can be taken into account, thereby improving the cost performance of the epitaxial layer.

[0022] In some embodiments of the present application, the thickness of the two-dimensional nucleation layer is 300nm-500nm; the thickness of the three-dimensional nucleation layer is 200nm-500nm. In this way, the crystal quality of the nucleation layer can be improved while improving the production efficiency of the epitaxial wafer, which is more conducive to the preparation and application of the epitaxial wafer.

[0023] In some embodiments of the present application, the nucleation layer is an aluminum nitride layer. Aluminum nitride has a high bandgap (up to 6.2 eV), and has the characteristics of high resistance, high hardness, high chemical stability, high breakdown electric field and low dielectric loss, which can further improve the performance of the final RF device.

[0024] In some embodiments of the present application, the dislocation density of the two-dimensional nucleation layer is less than 5×10 9 / cm 2 ; The surface roughness of the two-dimensional nucleation layer is less than 0.5 nm. When the two-dimensional nucleation layer meets the above conditions, it means that the crystal quality of the two-dimensional nucleation layer is high, which can improve the power and efficiency performance of the final RF device.

[0025] In some embodiments of the present application, the molar ratio of the group V element to the group III element in the two-dimensional nucleation layer is 1: (20-100). In this way, it is easy to obtain a two-dimensional nucleation layer, which is beneficial to improving the crystal quality of the epitaxial wafer and the power and efficiency of the final RF device.

[0026] In some embodiments of the present application, the molar ratio of the group V element to the group III element in the three-dimensional nucleation layer is 1:(100-2000). In this way, it is easy to obtain a three-dimensional nucleation layer and improve the production efficiency of epitaxial wafers.

[0027] In some embodiments of the present application, the epitaxial layer also includes a stress regulation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer stacked in sequence; wherein the stress regulation layer is arranged on the surface of the nucleation layer away from the silicon substrate layer.

[0028] In some embodiments of the present application, the room temperature resistivity of the silicon substrate layer is greater than or equal to 2000Ω·cm. In this way, the RF loss caused by the silicon substrate layer itself can be reduced, and the performance of the final RF device can be improved.

[0029] A second aspect of the embodiment of the present application provides a method for preparing an epitaxial wafer, comprising:

[0030] Providing a silicon substrate, and forming a plurality of the first blind holes on a surface of one side of the silicon substrate to obtain the silicon substrate layer;

[0031] The epitaxial layer is grown on the surface of the silicon substrate layer having the first blind hole, and the epitaxial layer includes the nucleation layer.

[0032] The preparation method has simple steps, strong process controllability, high production efficiency and is suitable for large-scale industrial production.

[0033] In some embodiments of the present application, a two-dimensional nucleation layer is grown on the surface of the silicon substrate layer having the first blind hole; the growth temperature of the two-dimensional nucleation layer is 1000°C-1200°C, the growth pressure is 50mbar-100mbar, and the amount ratio of the V group elements to the III group elements in the growth raw material is 1:(20-100). In this way, atoms can be induced to migrate laterally, thereby inducing lateral growth of atoms, and thus it is easy to prepare a two-dimensional nucleation layer, reduce its nucleation island density and increase the size of the nucleation island, thereby reducing the dislocation density introduced by the closing of the islands in the early stage of the growth of the two-dimensional nucleation layer, and thus it is beneficial to improve the crystal quality of the two-dimensional nucleation layer.

[0034] In some embodiments of the present application, a three-dimensional nucleation layer is grown on the surface of the two-dimensional nucleation layer away from the silicon substrate layer; the growth temperature of the three-dimensional nucleation layer is 900°C-1100°C, the growth pressure is 100mbar-300mbar, and the molar ratio of the group V elements to the group III elements in the growth raw material is 1:(100-2000). In this way, atoms can be induced to grow horizontally and vertically at the same time, thereby increasing the growth rate of the nucleation layer, and further increasing the production efficiency of the epitaxial wafer.

[0035] A third aspect of an embodiment of the present application provides a radio frequency device, comprising a drain, a source, a gate and the epitaxial wafer provided in the first aspect of the embodiment of the present application; the drain, the source and the gate are arranged on the surface of the epitaxial layer away from the silicon substrate layer, and the drain and the source are arranged on opposite sides of the gate and isolated from each other.

[0036] Due to the use of the epitaxial wafer provided in the embodiment of the present application, the above-mentioned radio frequency device has lower radio frequency loss, lower production cost and can be prepared into a larger size.

[0037] In some implementations of the present application, the radio frequency device is a power amplifier.

[0038] A fourth aspect of an embodiment of the present application provides a terminal radio frequency module, comprising the radio frequency device and antenna provided in the third aspect of the embodiment of the present application, wherein the radio frequency device is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

[0039] The above-mentioned terminal RF module has high efficacy, high efficiency and low RF loss, and has strong market competitiveness.

[0040] The fifth aspect of the embodiment of the present application provides a terminal device, including the terminal radio frequency module provided by the fourth aspect of the embodiment of the present application. The terminal device has a good market prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1A A top view of a silicon substrate layer provided in one embodiment of the present application;

[0042] Figure 1B A schematic diagram of the structure of a cross section of a silicon substrate layer provided in one embodiment of the present application;

[0043] Figure 2 A schematic diagram of the cross-section structure of a silicon substrate layer and a nucleation layer of an epitaxial wafer provided in one embodiment of the present application;

[0044] Figure 3 A schematic structural diagram of a cross section of a silicon substrate layer and a nucleation layer of an epitaxial wafer provided in another embodiment of the present application;

[0045] Figure 4 A schematic diagram of the cross-sectional structure of an epitaxial wafer provided in one embodiment of the present application;

[0046] Figure 5 A schematic diagram of the cross-sectional structure of an epitaxial wafer provided in another embodiment of the present application;

[0047] Figure 6 A schematic diagram of the structure of a radio frequency device provided in one embodiment of the present application;

[0048] Figure 7 A process flow chart for preparing a radio frequency device provided in one embodiment of the present application.

[0049] Explanation of the accompanying drawings: 100-epitaxial wafer; 10-silicon substrate layer; 20-epitaxial layer; 201-nucleation layer; 201a-two-dimensional nucleation layer; 201b-three-dimensional nucleation layer; 202-stress regulation layer; 203-high resistance buffer layer; 204-channel layer; 205-insertion layer; 206-barrier layer; 207-cap layer; 1-RF device; 2-drain; 3-source; 4-gate; 5-interconnect metal; 6-passivation layer. DETAILED DESCRIPTION

[0050] In the semiconductor industry chain, especially in the third-generation semiconductor industry chain, RF devices generally include epitaxial wafers and structures arranged on epitaxial wafers. Epitaxial wafers include substrate layers and epitaxial layers. If the materials of the substrate layer and the epitaxial layer are different, it is a heterogeneous structure. Among them, epitaxial wafers with epitaxial layers of Group III nitrides such as gallium nitride (GaN) can enable RF devices to achieve excellent performance such as large bandgap width, high breakdown electric field, high saturated electron drift velocity and strong polarization effect. In particular, RF devices based on GaN-based epitaxial wafers with silicon or silicon carbide as substrates also have excellent characteristics such as high power density and applicability at high frequencies. Currently, commercial GaN-based RF devices generally use relatively expensive silicon carbide substrates, which is mainly due to the serious RF losses of GaN RF devices on silicon. However, the production technology of silicon wafers is mature, high-quality, and large in size, and larger epitaxial wafers can be prepared. In addition, the cost of silicon wafers is relatively low. Based on the spare capacity of wafer foundries, GaN-based RF devices on silicon can have an absolute cost advantage. And due to the mature silicon-based large-scale integrated circuit production process, GaN-based RF devices on silicon also have good preparation potential. Therefore, solving the RF loss problem of GaN-based RF devices on silicon is particularly important, and it is also the key to promoting the large-scale application of low-cost GaN-based RF devices.

[0051] The industry has tried to use high-resistance silicon substrates to solve the above problems, but the improvement effect is limited. This may be because the strong polarization effect of group III nitrides causes electron channels to exist at the interface between the silicon substrate and the upper structure, forming parasitic conductance, which leads to large RF losses when the RF device is working.

[0052] In order to solve the above technical problems, an embodiment of the present application provides an epitaxial wafer, comprising: a stacked silicon substrate layer and an epitaxial layer, the epitaxial layer comprising a nucleation layer stacked on the surface of the silicon substrate; the surface of the silicon substrate layer close to the nucleation layer has a plurality of first blind holes 101, and the surface of the nucleation layer close to the silicon substrate layer has a plurality of second blind holes 210, any second blind hole 210 is arranged corresponding to a first blind hole 101, and the orthographic projection of the second blind hole 210 on the silicon substrate layer overlaps with the corresponding first blind hole 101; wherein the depth of the first blind hole 101 is greater than or equal to 200nm. In the embodiment of the present application, a scanning electron microscope (SEM) can be used to observe the slice section of the epitaxial wafer to characterize the existence and parameters of the first blind hole 101 and the second blind hole 210. The depth of the first blind hole 101 refers to the size of the first blind hole 101 in the stacking direction of the silicon substrate layer and the nucleation layer.

[0053] See also Figure 1A-Figure 5The epitaxial wafer 100 includes a stacked silicon substrate layer 10 and an epitaxial layer 20, wherein the epitaxial layer 20 includes a nucleation layer 201 stacked on the surface of the silicon substrate layer 10; the surface of the silicon substrate layer 10 close to the nucleation layer 201 has a plurality of first blind holes 101, and the surface of the nucleation layer 201 close to the silicon substrate layer 10 has a plurality of second blind holes 210, and any second blind hole 210 is arranged correspondingly to a first blind hole 101. Taking a group of correspondingly arranged first blind holes 101 and second blind holes 210 as an example, the orthographic projection of the second blind hole 210 on the silicon substrate layer 10 overlaps with the first blind hole 101; at this time, the interface between the silicon substrate layer 10 and the nucleation layer 201 has an "air gap" formed by the first blind hole 101 and the second blind hole 210, and the air gap extends from the inside of the silicon substrate layer 10 to the inside of the nucleation layer 201. Among them, Figure 1A The triangular notch in the middle is a common positioning hole for silicon substrate layers on the market.

[0054] It can be understood that the silicon substrate layer 10 has a first surface and a second surface that are arranged oppositely, and the nucleation layer 201 has a third surface and a fourth surface that are arranged oppositely; for the convenience of description, the first surface is defined as the surface of the silicon substrate layer 10 close to the nucleation layer 201, and the third surface is defined as the surface of the nucleation layer 201 close to the silicon substrate layer 10; the interface between the silicon substrate layer 10 and the nucleation layer 201 is defined as the "first interface", and it can be understood that the first interface is substantially also the interface between the silicon substrate layer 10 and the epitaxial layer 20. A first direction is defined, and the first direction is perpendicular to the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20; a second direction is defined, and the second direction is the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20.

[0055] In the embodiment of the present application, the nucleation layer 201 completely covers the first surface of the silicon substrate layer 10 .

[0056] The above special structural design can make the interface between the silicon substrate layer 10 and the nucleation layer 201 have multiple "air gaps"; and the depth of the above "air gap" in the silicon substrate layer 10 is ≥ 200nm (that is, the depth d of the first blind hole 101 is ≥ 200nm), which can effectively cut off the parasitic conductive channel at the first interface, so as to better suppress the parasitic conductivity effect at the first interface, and then the above epitaxial wafer 100 can be used to provide a radio frequency device with low radio frequency loss. If the depth of the above air gap in the silicon substrate layer 10 is too small, a continuous parasitic conductive layer will still be formed at the interface between the silicon substrate layer 10 and the epitaxial layer 20, and there will be a high concentration of hole conduction, so that the air gap cannot smoothly play its effect of cutting off the parasitic conductive channel, and it almost loses its inhibitory effect on radio frequency loss. Specifically, the depth of the first blind hole 101 (the depth of the air gap in the silicon substrate layer 10) can be but is not limited to 200nm, 220nm, 250nm, 280nm, 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, 500nm, 520nm, 550nm, etc.

[0057] In some embodiments of the present application, the depth (d) of the first blind hole 101 is 200nm-500nm. In other words, the depth of the air gap in the silicon substrate layer 10 is 200nm-500nm. The depth of the first blind hole 101 is controlled within the above range, and the air gap formed by it can fully exert its effect and cut off the parasitic conductive channel at the first interface, and can also ensure that the silicon substrate layer 10 has a strong support force for its surface superposition structure, the epitaxial wafer 100 is easy to manufacture and the crystal quality of the epitaxial layer 20 is high, so that when it is used in a radio frequency device, it is more conducive to improving its power and efficiency. Specifically, the depth (d) of the first blind hole 101 can be, but is not limited to, 200nm, 210nm, 240nm, 260nm, 290nm, 310nm, 340nm, 390nm, 410nm, 430nm, 440nm, 460nm, 490nm, 500nm, etc.

[0058] Considering that in some embodiments, the second blind holes 210 are caused by the preparation process adopted by the epitaxial wafer 100, specifically, the nucleation layer 201 is directly grown on the surface of the silicon substrate layer 10 having multiple first blind holes 101, and it is difficult for atoms to settle on the non-close-packed crystal plane (first blind hole region), the material of the nucleation layer 201 is settled and grown on the close-packed crystal plane (non-first blind hole region), and the material grown on the surface of the non-first blind hole region can be gradually closed, thereby forming the second blind hole 210. Therefore, in some specific embodiments, the number of the second blind holes 210 is the same as the number of the first blind holes 101, and the multiple first blind holes 101 and the second blind holes 210 are arranged in a one-to-one correspondence.

[0059] In some embodiments of the present application, the depth of the second blind hole 210 is 300nm-500nm. It can be understood that in some cases, other functional layers are superimposed on the surface of the nucleation layer 201 away from the silicon substrate layer 10. Controlling the depth of the second blind hole 210 within the above range can not only ensure its own structural strength and mechanical properties, but also provide better support for the subsequent upper structure, and facilitate the air gap to play a better effect of suppressing parasitic conduction. Specifically, the depth of the second blind hole 210 can be, but is not limited to, 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, 500nm, etc. At this time, the total depth of the air gap in the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20 is 500nm-1000nm. Specifically, the total depth of the air gap in the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20 may be, but is not limited to, 500 nm, 520 nm, 550 nm, 580 nm, 600 nm, 620 nm, 650 nm, 680 nm, 700 nm, 720 nm, 750 nm, 780 nm, 800 nm, 820 nm, 850 nm, 880 nm, 900 nm, 920 nm, 950 nm, 980 nm, 1000 nm, etc. Those skilled in the art may make a selection according to actual production needs.

[0060] In some implementations of the present application, the opening shape of the first blind hole 101 is circular or n-gon, wherein n>8; it can be understood that n is a positive integer. In this way, the benefit of the air gap formed by the first blind hole 101 is better, and when the epitaxial wafer 100 is used in a radio frequency device, it is beneficial to suppress radio frequency losses. Specifically, the opening shape of the first blind hole 101 can be a nonagon, a decagon, an eleventh angle, a dodecagon, a fourteenth angle, a pentagon, a seventeenth angle, an octagon, an icosagon, etc. In some specific embodiments of the present application, the opening shape of the first blind hole 101 is preferably circular. In this way, it is more conducive to suppressing the radio frequency loss of the radio frequency device.

[0061] In some embodiments of the present application, the inner diameter of the first blind hole 101 is equal everywhere along the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20. In this way, in the area between the plane where the end faces of the multiple first blind holes 101 are located and the first surface, the silicon substrate layer 10 has good structural uniformity, which can better cut off the parasitic conductive channel, so that the benefit of the air gap formed by its participation can be better, which is more conducive to reducing the RF loss of the final RF device. At this time, in some specific embodiments, the side wall of the first blind hole 101 is perpendicular to the first surface. However, considering the process accuracy and preparation difficulty, in other embodiments, the inner diameter of the first blind hole 101 gradually increases or decreases along the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20. At this time, there is an inclination angle between the side wall of the first blind hole 101 and the first surface.

[0062] In some implementations of this application, please see Figure 1B , the angle (α) between the sidewall of the first blind hole 101 and the first surface is 85°-90°. In some specific embodiments, the above angle is 90°, and the sidewall of the first blind hole 101 is perpendicular to the first surface. At this time, the first blind hole 101 has good structural uniformity, which is conducive to improving the benefit of the air gap and better cutting off the parasitic conductive channel at the first interface. When the above angle is greater than or equal to 85° and less than 90°, there is a small inclination angle between the sidewall of the first blind hole 101 and the first surface. Based on the depth of the first blind hole 101 ≥ 200nm, the inner diameter of the first blind hole 101 along the second direction changes little, which can avoid the phenomenon that the parasitic conductive channel is not completely destroyed due to the uneven structure of the first blind hole 101, thereby affecting the benefit of the air gap.

[0063] In order to increase the benefit of the air gap and better suppress the parasitic conductivity effect at the first interface, in some embodiments of the present application, the opening diameter of the first blind hole 101 is 100nm-1000nm. Controlling the opening diameter of the first blind hole 101 within the above range is not only easy to prepare, but more importantly, it can achieve a more ideal effect of cutting off the parasitic conductive channel. In the preparation process of the epitaxial wafer 100, the parameters of the first blind hole 101 are all the genetic structure of the silicon substrate layer 10, but at least in some cases, the nucleation layer 201 is gradually grown on the first surface of the silicon substrate layer 10, and the opening diameter of the first blind hole 101 may also affect the parameters of the second blind hole 210 (for example, depth) and the crystal quality of the nucleation layer 201. At this time, the opening diameter of the first blind hole 101 is controlled within the above range, and it can be ensured that the subsequently grown nucleation layer 201 is easy to close and has good crystal quality. Specifically, the opening diameter of the first blind hole 101 may be, but is not limited to, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, etc. In the embodiment of the present application, SEM may be used to test the opening diameter of the first blind hole 101. When the opening shape of the first blind hole 101 is circular, the opening diameter refers to the diameter of the opening; when the opening shape of the first blind hole 101 is an n-gon, the opening diameter refers to the diameter of the circumscribed circle of the n-gon.

[0064] Based on the preparation technology and process parameters of the epitaxial wafer 100, at least in some cases, the second blind hole 210 is formed during the growth of the nucleation layer 201. Therefore, the inner diameter of the second blind hole 210 may gradually decrease along the second direction, or may change irregularly, and the present application does not set a limit to this. In some specific embodiments, the inner diameter of the second blind hole 210 varies in the range of 100nm-1000nm along the second direction. Specifically, the inner diameter of the second blind hole 210 may be, but is not limited to, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc.

[0065] In some embodiments of the present application, in the first direction, a plurality of first blind holes 101 are arranged periodically. That is, a plurality of first blind holes 101 are arranged periodically on the first surface. In this way, it is not only to ensure the structural uniformity of the silicon substrate layer 10, but also to fully reduce the risk of cracks in the subsequent application process due to uneven internal stress distribution or insufficient bearing capacity; it is also considered that there may be many repeating units (a gate and a drain and a source area on both sides thereof are regarded as the same repeating unit) or circuit elements in the RF device, so that in the subsequent application process, the parasitic conductive channels in different areas at the first interface are well cut off, and the RF loss of the RF device can be better suppressed. It can be understood that the plurality of second blind holes 210 correspond to the plurality of first blind holes 101 one by one, and at this time, the plurality of second blind holes 210 are arranged periodically on the third surface. In other words, the air gap formed by the first blind hole 101 and the second blind hole 210 is arranged periodically at the first interface.

[0066] In some embodiments of the present application, in the first direction, a plurality of first blind holes 101 are arranged in a regular hexagonal periodic arrangement. Specifically, the regular hexagonal periodic arrangement can be understood as: except for the first blind hole 101 located at the edge of the epitaxial wafer 100, any first blind hole 101 is centered and surrounded by 6 first blind holes 101, and the lines connecting the geometric centers of the openings of the above 6 first blind holes 101 on the silicon substrate layer 10 in sequence form a regular hexagon. The first blind holes 101 are arranged in a regular hexagonal periodic arrangement, which is conducive to the subsequent growth of the epitaxial layer 20, and is also conducive to ensuring that the crystal quality of the epitaxial layer 20 is good, so that when it is used in a radio frequency device, it is conducive to improving its power and efficiency. It can be understood that at this time, the air gap formed by the first blind hole 101 and the second blind hole 210 is arranged in a regular hexagonal periodic arrangement at the first interface.

[0067] In some implementations of this application, please see Figure 1A, the arrangement period a of the first blind holes 101 is 200nm-1000nm. Specifically, in the first direction, the minimum distance a between the openings of two adjacent first blind holes 101 on the silicon substrate layer 10 is 200nm-1000nm. Controlling the arrangement period of the first blind holes 101 within the above range also controls the distribution density of the first blind holes 101 and the air gaps. In this way, when it is applied to radio frequency devices, it is beneficial to achieve that there are air gaps in any repeating unit to suppress radio frequency losses, thereby improving the performance of radio frequency devices. Specifically, the arrangement period of the first blind holes 101 can be, but is not limited to, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc. In some specific embodiments, please refer to Figure 1A The plurality of first blind holes 101 are arranged periodically in a regular hexagon, and the arrangement period a is 200nm-1000nm. Similarly, the arrangement period a of the air gaps formed by the first blind holes 101 and the second blind holes 210 is 200nm-1000nm.

[0068] In the embodiment of the present application, the specific material of the nucleation layer 201 can be selected from the III / V group compounds available on the GaN-based epitaxial wafer 100. In some specific embodiments, the two-dimensional nucleation layer 201a is an aluminum nitride layer.

[0069] In some embodiments of the present application, the nucleation layer 201 is a two-dimensional nucleation layer. The two-dimensional nucleation layer has high crystal quality, so when the epitaxial wafer 100 is used in a radio frequency device, the power and efficiency of the radio frequency device can be improved, the device performance can be greatly improved, and its market competitiveness can be increased.

[0070] For some specific implementations of this application, please refer to Figure 2 , the nucleation layer 201 is a two-dimensional nucleation layer, and the thickness of the nucleation layer 201 is 300nm-1000nm. In this way, the structural integrity of the nucleation layer 201 is high, and its own crystal quality is high, which is also more conducive to ensuring and improving the overall crystal quality of the epitaxial layer 20; in addition, the appropriate thickness can avoid the risk of cracking of the nucleation layer 201, thereby improving the comprehensive performance of the epitaxial wafer 100. Specifically, the thickness of the nucleation layer 201 can be, but is not limited to, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc.

[0071] In some implementations of this application, please see Figure 3, the nucleation layer 201 includes a two-dimensional nucleation layer 201a and a three-dimensional nucleation layer 201b stacked in sequence, and the two-dimensional nucleation layer 201a is arranged close to the silicon substrate layer 10. The two-dimensional nucleation layer 201a is a nucleation layer 201 obtained by the growth of atoms mainly along the first direction mentioned above, and the three-dimensional nucleation layer 201b is a nucleation layer 201 obtained by the simultaneous growth of atoms in the first direction and the second direction. Firstly, the two-dimensional nucleation layer 201a is grown on the surface of the silicon substrate layer 10, which can reduce the nucleation conduction density, reduce the dislocation density, and reduce the crystal size to improve the crystal quality of the nucleation layer 201, thereby improving the crystal quality of other epitaxial layer 20 structures subsequently grown on the surface of the nucleation layer 201, and improving the power and efficiency of the final RF device. Based on the above differences, the crystal quality of the two-dimensional nucleation layer 201a is relatively higher, and its arrangement close to the silicon substrate layer 10 can ensure a better quality of the epitaxial wafer 100; the growth rate of the three-dimensional nucleation layer 201b is relatively fast, so at this time, the production efficiency of the epitaxial wafer 100 can be improved while taking into account the quality of the epitaxial wafer 100.

[0072] In some specific embodiments, the thickness of the two-dimensional nucleation layer 201a is 300nm-500nm, and the thickness of the three-dimensional nucleation layer 201b is 200nm-500nm. In this way, the crystal quality of the nucleation layer 201 can be improved while the production efficiency of the epitaxial wafer 100 can be improved, which is more conducive to the preparation and application of the epitaxial wafer 100. Specifically, in the above case, the thickness of the two-dimensional nucleation layer 201a can be but not limited to 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, 500nm; the thickness of the three-dimensional nucleation layer 201b can be but not limited to 200nm, 220nm, 250nm, 280nm, 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, 500nm.

[0073] In some specific embodiments, the material of the two-dimensional nucleation layer 201a and the three-dimensional nucleation layer 201b is aluminum nitride. Aluminum nitride has a high band gap (up to 6.2eV), and has the characteristics of high resistance, high hardness, high chemical stability, high breakdown electric field and low dielectric loss, which can further improve the performance of the final RF device.

[0074] The high crystal quality of the two-dimensional nucleation layer 201a can be specifically reflected in the dislocation density and surface roughness. In some specific embodiments of the present application, the dislocation density of the two-dimensional nucleation layer 201a is less than 5×10 9 / cm 2 , for example, 1.5×10 9 / cm 2 -3×10 9 / cm 2; The surface roughness of the two-dimensional nucleation layer 201a is less than 0.5nm, for example, 0.2nm-0.35nm. The dislocation density is defined as the total length of the dislocation lines contained in a unit volume of the crystal, or the number of dislocation lines passing through a unit cross-sectional area of ​​the crystal. Specifically, the test method for the dislocation density of the two-dimensional nucleation layer 201a includes a transmission electron microscope (TEM); the test method for the surface roughness of the two-dimensional nucleation layer 201a includes an atomic force microscope (AFM).

[0075] In an embodiment of the present application, when the third surface of the nucleation layer 201 is provided with a second blind hole 210, and the nucleation layer 201 includes a stacked two-dimensional nucleation layer 201a and a three-dimensional nucleation layer 201b, the following situations may be included: the second blind hole 210 penetrates the two-dimensional nucleation layer 201a and extends into the three-dimensional nucleation layer 201b; or, the second blind hole 210 does not penetrate the two-dimensional nucleation layer 201a.

[0076] In some embodiments of the present application, the molar ratio of the group V elements to the group III elements in the two-dimensional nucleation layer 201a is 1:(20-100). For example, when the material of the two-dimensional nucleation layer 201a is AlN, the molar ratio of the N element to the Al element in the two-dimensional nucleation layer 201a is 1:(20-100). In this way, it is easy to obtain the two-dimensional nucleation layer 201a, which is beneficial to improving the crystal quality of the epitaxial wafer 100 and the power and efficiency of the final radio frequency device. Specifically, in the two-dimensional growth layer, the molar ratio of the group V elements to the group III elements can be, but is not limited to, 1:20, 1:30, 1:40, 1:50, 1:60, 1:70, 1:80, 1:90, 1:95, 1:98, etc.

[0077] In some embodiments of the present application, the ratio of the amount of the group V element to the group III element in the three-dimensional nucleation layer 201b is 1:(100-2000). For example, when the material of the three-dimensional nucleation layer 201b is AlN, the ratio of the amount of the N element to the Al element in the three-dimensional nucleation layer 201b is 1:(100-2000). In this way, it is easy to obtain the three-dimensional nucleation layer 201b, and the production efficiency of the epitaxial wafer 100 is improved. Specifically, in the three-dimensional nucleation layer 201b, the molar ratio of group V elements to group III elements can be but is not limited to 1:120, 1:150, 1:180, 1:200, 1:250, 1:300, 1:350, 1:400, 1:500, 1:600, 1:700, 1:800, 1:900, 1:1000, 1:1200, 1:1500, 1:1800, etc.

[0078] In some embodiments of the present application, the room temperature resistivity of the silicon substrate layer 10 is greater than or equal to 2000Ω·cm. For example, 3000Ω·cm-5000Ω·cm, or greater than 5000Ω·cm. In this way, the RF loss caused by the silicon substrate layer 10 itself can be reduced, and the performance of the final RF device can be improved.

[0079] In the embodiment of the present application, the thickness of the silicon substrate layer 10 is not specifically limited, and can be a thickness known in the art, but it can be understood that since the depth of the first blind hole 101 is ≥ 200nm, the thickness of the silicon substrate layer 10 is at least > 200nm. Exemplarily, the thickness of the silicon substrate layer 10 can be 100μm-1000μm.

[0080] In some implementations of this application, please see Figure 4-Figure 5 The epitaxial layer 20 also includes a stress regulation layer 202, a high resistance buffer layer 203, a channel layer 204, an insertion layer 205, a barrier layer 206 and a cap layer 207 which are stacked in sequence; wherein the stress regulation layer 202 is arranged on the surface of the nucleation layer 201 away from the silicon substrate layer 10. At this time, the epitaxial wafer 100 includes a silicon substrate layer 10, a nucleation layer 201 (the nucleation layer 201 is a two-dimensional nucleation layer), a stress regulation layer 202, a high resistance buffer layer 203, a channel layer 204, an insertion layer 205, a barrier layer 206 and a cap layer 207 which are stacked in sequence, and a plurality of air gaps are periodically arranged at the interface between the silicon substrate layer 10 and the nucleation layer 201; or, the epitaxial wafer 100 includes a silicon substrate layer 10, a two-dimensional nucleation layer 201a, a three-dimensional nucleation layer 201b, a stress regulation layer 202, a high resistance buffer layer 203, a channel layer 204, an insertion layer 205, a barrier layer 206 and a cap layer 207 which are stacked in sequence, and a plurality of air gaps are periodically arranged at the interface between the silicon substrate layer 10 and the two-dimensional nucleation layer 201a. The cap layer 207 can be used to provide ohmic contact.

[0081] The above-mentioned stress regulation layer 202 includes but is not limited to a single layer of GaN, a single layer of AlGaN, a multi-layer Al component gradient AlGaN layer, an Al component linear gradient AlGaN layer, an AlN / GaN superlattice layer, an AlGaN / GaN superlattice layer, and an AlN / AlGaN superlattice layer. In the embodiment of the present application, there is no specific restriction on the thickness of the stress regulation layer 202, and ordinary technicians in this field can adjust it according to the actual application needs. Specifically, the thickness of the stress regulation layer 202 can be 50nm-1000nm. In the embodiment of the present application, there is no restriction on the thickness of the AlN / GaN superlattice layer, the AlGaN / GaN superlattice layer, the AlN single layer, the GaN single layer, the AlGaN single layer in the AlN / AlGaN superlattice layer, and the number of repetition periods of the above-mentioned superlattice layers.

[0082] The above-mentioned high-resistance buffer layer 203 includes but is not limited to an AlGaN layer (Al%<10%) and a GaN layer. In some specific embodiments, when the high-resistance buffer layer 203 includes an AlGaN layer, the molar content of Al in the AlGaN layer is <10%, for example, 1%, 2%, 5%, 6%, 8%, etc. In this way, it is beneficial to improve the resistivity of the AlGaN layer, ensure the quality of the AlGaN layer, and avoid introducing parallel channels in the epitaxial wafer 100, thereby ensuring the performance of the final RF device. In the embodiment of the present application, there is no specific restriction on the thickness of the high-resistance buffer layer 203, and ordinary technicians in this field can adjust it according to actual application needs. Specifically, the thickness of the high-resistance buffer layer 203 can be 200nm-2000nm.

[0083] The channel layer 204 includes but is not limited to a GaN layer. In the embodiment of the present application, there is no specific limitation on the thickness of the channel layer 204, and a person skilled in the art may adjust the thickness according to actual application requirements. Specifically, the thickness of the channel layer 204 may be 150 nm to 400 nm.

[0084] The above-mentioned insertion layer 205 includes but is not limited to an AlN layer. In the embodiment of the present application, there is no specific limitation on the thickness of the insertion layer 205, and a person skilled in the art can adjust it according to actual application requirements. Specifically, the thickness of the insertion layer 205 can be 0.5 nm-1.5 nm.

[0085] The barrier layer 206 includes but is not limited to a III-N barrier layer 206, for example, an AlN layer, an AlGaN layer, an InAlN layer, and an InAlGaN layer. In the embodiment of the present application, there is no specific limitation on the thickness of the barrier layer 206, and a person skilled in the art may adjust the thickness according to actual application requirements. Specifically, the thickness of the barrier layer 206 may be 5nm-30nm.

[0086] The cap layer 207 includes but is not limited to a GaN layer. In the embodiment of the present application, there is no specific limitation on the thickness of the cap layer 207, and a person skilled in the art may adjust the thickness according to actual application requirements. Specifically, the thickness of the GaN cap layer may be 1 nm to 5 nm.

[0087] The embodiment of the present application further provides a method for preparing an epitaxial wafer, which can be used to prepare the aforementioned epitaxial wafer 100, comprising:

[0088] S01, providing a silicon substrate, forming a plurality of first blind holes on a surface of one side of the silicon substrate, wherein the depth of the first blind holes is ≥200 nm, to obtain a silicon substrate layer;

[0089] S02. Growing an epitaxial layer on the surface of the silicon substrate layer having the first blind hole (i.e., the aforementioned first surface), the epitaxial layer including a nucleation layer. On a non-atomic close-packed crystal plane, atoms are basically unable to settle, so the first blind hole can be retained in the obtained epitaxial wafer, and a second blind hole is formed during the closing process of the nucleation layer. In some specific embodiments, a second blind hole is formed at a corresponding position of any first blind hole.

[0090] The preparation method has simple steps, strong process controllability, high production efficiency and is suitable for large-scale industrial production.

[0091] In some embodiments of the present application, in step S01, the method of forming a plurality of first blind holes on the first surface includes but is not limited to nano-imprinting, etching, electrochemical corrosion, etc.

[0092] In some embodiments of the present application, before performing step S02, the silicon substrate having the first blind hole is further subjected to surface treatment, and the surface treatment method includes but is not limited to cleaning with at least one of organic solvents such as acetone, ethanol, isopropanol, etc., and then cleaning with hydrofluoric acid, or an aqueous solution of hydrofluoric acid and hydrochloric acid, or Piranha solution, and then rinsing with deionized water and drying.

[0093] In some implementations of the present application, in step S02, a vapor phase epitaxial process is used to grow an epitaxial layer.

[0094] In some embodiments of the present application, in step S02, growing an epitaxial layer on the first surface includes: growing a two-dimensional nucleation layer on the first surface.

[0095] In some specific embodiments, at this time, growing a two-dimensional nucleation layer on the first surface includes: placing a silicon substrate in a reaction chamber, introducing growth materials required for growing the two-dimensional nucleation layer into the reaction chamber, and controlling the amount of the substance ratio of the V group element to the III group element in the growth material to be 1: (20-100), the growth temperature to be 900°C-1200°C, and the growth pressure (pressure in the reaction chamber) to be 50mbar-100mbar. In this way, atoms can be induced to migrate laterally, thereby inducing atoms to grow laterally, and thus it is easy to prepare a two-dimensional nucleation layer, reduce its nucleation island density and increase the size of the nucleation island, thereby reducing the dislocation density introduced by the closing of the islands in the early stage of the growth of the two-dimensional nucleation layer, and thus it is beneficial to improve the crystal quality of the two-dimensional nucleation layer. Specifically, the amount ratio of the group V element (for example, N element) to the group III element (for example, Al element) in the growth raw material can be, but is not limited to, 1:20, 1:30, 1:40, 1:50, 1:60, 1:70, 1:80, 1:90, 1:95, 1:98. The growth temperature of the two-dimensional nucleation layer can be, but is not limited to, 900°C, 920°C, 950°C, 980°C, 1000°C, 1020°C, 1050°C, 1080°C, 1100°C, 1120°C, 1150°C, 1180°C, 1200°C, etc. The growth pressure of the two-dimensional nucleation layer can be, but is not limited to, 5mbar, 60mbar, 80mbar, 100mbar, etc. In some specific embodiments of the present application, the nucleation island density is 10 10 cm 2 -5×10 10 cm 2 , the size of the nucleation islands is 10nm-50nm. Specifically, in the above steps, the growth of the two-dimensional nucleation layer is interrupted and the density and size of the nucleation islands are measured by SEM or AFM.

[0096] In some embodiments of the present application, in step S02, growing an epitaxial layer on the first surface includes: sequentially growing a two-dimensional nucleation layer and a three-dimensional nucleation layer on the first surface. In some specific embodiments, after the two-dimensional growth layer is obtained, the temperature and pressure in the reaction chamber are changed, and the growth material is adjusted to grow a three-dimensional nucleation layer, wherein the growth temperature of the three-dimensional nucleation layer is 900°C-1100°C, the growth pressure is 100mbar-300mbar, and the ratio of the amount of Group V elements to Group III elements in the growth material is 1:(100-2000). In this way, atoms can be induced to grow horizontally and vertically at the same time, thereby increasing the growth rate of the nucleation layer, and further increasing the production efficiency of the epitaxial wafer.

[0097] Specifically, the amount ratio of the group V element (e.g., N element) to the group III element (e.g., Al element) in the growth raw material of the three-dimensional nucleation layer may be, but is not limited to, 1:120, 1:150, 1:180, 1:200, 1:250, 1:300, 1:350, 1:400, 1:500, 1:600, 1:700, 1:800, 1:900, 1:1000, 1:1200, 1:1500, 1:1800. The growth temperature of the three-dimensional nucleation layer may be, but is not limited to, 900°C, 920°C, 950°C, 980°C, 1000°C, 1020°C, 1050°C, 1080°C, 1100°C, etc. The growth pressure of the three-dimensional nucleation layer may be, but is not limited to, 100 mbar, 120 mbar, 150 mbar, 180 mbar, 200 mbar, 220 mbar, 250 mbar, 280 mbar, 300 mbar, etc.

[0098] In the above steps, the aforementioned growth raw materials can be selected from materials known to those skilled in the art according to the composition of the nucleation layer, as long as the nucleation layer can be grown smoothly. When the nucleation layer is an AlN layer, the growth raw materials include an aluminum source and a nitrogen source, wherein the aluminum source includes but is not limited to trimethylaluminum, and the nitrogen source includes but is not limited to ammonia.

[0099] In some implementations of the present application, step S02 further includes sequentially growing a stress regulating layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on the surface of the nucleation layer away from the silicon substrate layer.

[0100] In the above step S02, when growing the stress regulation layer, high resistance buffer layer, channel layer, insertion layer, barrier layer and cap layer, the growth materials and process parameter control required for each of them can be any growth materials and process parameters known in the art, and technicians in this field can select and adjust them according to application requirements.

[0101] See also Figure 6 The embodiment of the present application also provides a radio frequency device 1, including a drain 2, a source 3, a gate 4 and an epitaxial wafer 100 provided in the embodiment of the present application, wherein the drain 2, the source 3 and the gate 4 are arranged on the surface of the epitaxial layer 20 away from the silicon substrate layer 10, and the drain 2 and the source 3 are arranged on opposite sides of the gate 4 and isolated from each other. Due to the use of the epitaxial wafer 100 provided in the embodiment of the present application, the radio frequency loss of the radio frequency device 1 is low, the production cost is low and it can be prepared into a larger size, and has good market competitiveness. In some specific embodiments, the above-mentioned radio frequency device 1 is a power amplifier.

[0102] In some embodiments of the present application, the drain electrode 2 is in contact with the cap layer 207, the source electrode 3 is in contact with the cap layer 207, and there is an ohmic contact between the source electrode 3 and the cap layer 207, and there is an ohmic contact between the drain electrode 2 and the cap layer 207. The materials of the source electrode 3 and the drain electrode 2 can be Ti layer, Al layer, Ni layer and Au layer stacked in sequence.

[0103] In some embodiments of the present application, the RF device 1 further includes a passivation layer 6, which is disposed on the surface of the epitaxial layer 201 away from the silicon substrate layer 10; a plurality of openings are disposed on the passivation layer 6, and the drain 2, the source 3, and the gate 4 are respectively located in the plurality of openings. The passivation layer 6 can suppress the trap effect of the surface state and thus improve the performance of the RF device 1. In the embodiments of the present application, the material of the passivation layer 6 is not limited, and those skilled in the art can select it according to actual needs. For example, SiO2, SiNx, etc.

[0104] In some embodiments of the present application, the surfaces of the source 3, the drain 2 and the gate 4 facing away from the epitaxial wafer 100 are all provided with interconnection metal 5, and the interconnection metal 5 is exposed from the passivation layer 6. A single RF device 1 may have multiple repeating units, or circuit elements, and the interconnection metal 5 is used to connect different repeating units or circuit elements, transmit electronic signals and power them. The material of the interconnection metal 5 can be a conductive metal commonly used in the art, such as copper and gold.

[0105] In some implementations of this application, please see Figure 7 , the preparation of the radio frequency device 1 may include:

[0106] S11, preparing an ohmic contact on the surface of the epitaxial wafer 100 facing away from the silicon substrate layer 10 to obtain a drain 2 and a source 3;

[0107] S12, considering that multiple groups of radio frequency devices 1 can be prepared simultaneously on one epitaxial wafer 100, at this time, different regions are insulated and isolated to avoid mutual influence between multiple devices;

[0108] S13, preparing a passivation layer 6 and performing a hole opening process;

[0109] S14, performing gate groove etching and gate preparation.

[0110] In some implementations of the present application, the further step S15 is further included: forming interconnect metals 5 on the surfaces of the source 3 , the drain 2 , and the gate 4 facing away from the epitaxial wafer 100 .

[0111] In some embodiments of the present application, at least one first blind hole is included between the orthographic projection of the drain 2 on the silicon substrate layer 10 and the orthographic projection of the gate 4 on the silicon substrate layer 10. In this way, at least one air gap is included in a repeating unit of the RF device 1, thereby ensuring that the RF loss of any repeating unit can be effectively suppressed, thereby greatly reducing the RF loss of the RF device. The above-mentioned air gap can be composed of the first blind hole, or can be composed of the first blind hole and the second blind hole.

[0112] In some specific embodiments of the present application, the above effect can be achieved by adjusting the arrangement period of the first blind hole (that is, the arrangement period of the air gap) and the distance between the source and the drain. Specifically, the arrangement period of the first blind hole is a, the distance between the source and the drain is b, and the opening diameter of the first blind hole is c, then a, b, c satisfy b≥a+2c, where a, b, c are in the same unit. In some specific embodiments, the distance b between the source and the drain is 1μm-3μm. In this way, it is easy to manufacture and helps to ensure the performance of the RF device.

[0113] The embodiment of the present application also provides a terminal radio frequency module, including the radio frequency device and antenna provided in the embodiment of the present application, wherein the radio frequency device is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

[0114] In some specific embodiments, the terminal RF module is a 5G RF module.

[0115] The embodiment of the present application also provides a terminal device, including the terminal radio frequency module provided in the embodiment of the present application. Due to the terminal radio frequency module provided in the embodiment of the present application, the terminal device has good market competitiveness. In some specific embodiments, the above-mentioned terminal device includes but is not limited to a mobile phone.

[0116] In the embodiment of the present application, “-” represents a range value, including the endpoint values ​​at both ends. For example, the value of a can be 0.5-15, which means that the value of a can be between 0.5 and 15, and includes the endpoint values ​​0.5 and 15.

Claims

1. An epitaxial wafer, characterized in that: It comprises a stacked silicon substrate layer and an epitaxial layer, wherein the epitaxial layer comprises a nucleation layer stacked on the surface of the silicon substrate; The surface of the silicon substrate layer close to the nucleation layer has a plurality of first blind holes, and the surface of the nucleation layer close to the silicon substrate layer has a plurality of second blind holes, any of the second blind holes is arranged corresponding to one of the first blind holes, and the orthographic projection of the second blind hole on the silicon substrate layer overlaps with the corresponding first blind hole; Wherein, the depth of the first blind hole is greater than or equal to 200 nm.

2. The epitaxial wafer according to claim 1, characterized in that: The depth of the first blind hole is 200nm-500nm.

3. The epitaxial wafer according to claim 1 or 2, characterized in that: The number of the second blind holes is the same as the number of the first blind holes, and the plurality of the first blind holes and the plurality of the second blind holes are arranged in a one-to-one correspondence.

4. The epitaxial wafer according to any one of claims 1 to 3, characterized in that: The depth of the second blind hole is 300nm-500nm.

5. The epitaxial wafer according to any one of claims 1 to 4, characterized in that: The inner diameter of the first blind hole is equal everywhere along the stacking direction of the silicon substrate layer and the epitaxial layer.

6. The epitaxial wafer according to any one of claims 1 to 5, characterized in that: The angle between the side wall of the first blind hole and the surface of the silicon substrate layer close to the nucleation layer is 85°-90°.

7. The epitaxial wafer according to any one of claims 1 to 6, characterized in that: The opening diameter of the first blind hole is 100nm-1000nm.

8. The epitaxial wafer according to any one of claims 1 to 7, characterized in that: The opening of the first blind hole is circular or n-gonal, wherein n>8.

9. The epitaxial wafer according to any one of claims 1 to 8, characterized in that: In a first direction, the plurality of first blind holes are arranged periodically; wherein the first direction is perpendicular to a stacking direction of the silicon substrate layer and the nucleation layer; Along the first direction, a minimum distance between openings of two adjacent first blind holes on the silicon substrate layer is 200 nm-1000 nm.

10. The epitaxial wafer according to claim 9, characterized in that: In the first direction, the plurality of first blind holes are periodically arranged in a regular hexagon.

11. The epitaxial wafer according to any one of claims 1 to 10, characterized in that: The nucleation layer is a two-dimensional nucleation layer.

12. The epitaxial wafer according to claim 11, characterized in that: The thickness of the nucleation layer is 300nm-1000nm.

13. The epitaxial wafer according to any one of claims 1 to 10, characterized in that: The nucleation layer includes a two-dimensional nucleation layer and a three-dimensional nucleation layer stacked in sequence, and the two-dimensional nucleation layer is arranged close to the silicon substrate layer.

14. The epitaxial wafer according to claim 13, characterized in that: The thickness of the two-dimensional nucleation layer is 300nm-500nm; the thickness of the three-dimensional nucleation layer is 200nm-500nm.

15. The epitaxial wafer according to any one of claims 1 to 14, characterized in that: The nucleation layer is an aluminum nitride layer.

16. The epitaxial wafer according to any one of claims 11 to 15, characterized in that: The dislocation density of the two-dimensional nucleation layer is less than 5×10 9 / cm 2 ; The surface roughness of the two-dimensional nucleation layer is less than 0.5nm.

17. The epitaxial wafer according to any one of claims 11 to 16, characterized in that: The molar ratio of the group V elements to the group III elements in the two-dimensional nucleation layer is 1:(20-100).

18. The epitaxial wafer according to any one of claims 13 to 14, characterized in that: The molar ratio of the group V elements to the group III elements in the three-dimensional nucleation layer is 1:(100-2000).

19. The epitaxial wafer according to any one of claims 1 to 18, characterized in that: The epitaxial layer also includes a stress regulating layer, a high resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer which are stacked in sequence; Wherein, the stress regulating layer is arranged on a surface of the nucleation layer away from the silicon substrate layer.

20. The epitaxial wafer according to any one of claims 1 to 19, characterized in that: The room temperature resistivity of the silicon substrate layer is greater than or equal to 2000Ω·cm.

21. The method for preparing an epitaxial wafer according to any one of claims 1 to 20, characterized in that: include: Providing a silicon substrate, and forming a plurality of the first blind holes on a surface of one side of the silicon substrate to obtain the silicon substrate layer; The epitaxial layer is grown on the surface of the silicon substrate layer having the first blind hole, and the epitaxial layer includes the nucleation layer.

22. The preparation method according to claim 21, characterized in that: The step of growing the nucleation layer on the surface of the silicon substrate layer having the first blind hole comprises: A two-dimensional nucleation layer is grown on the surface of the silicon substrate layer having the first blind hole; the growth temperature of the two-dimensional nucleation layer is 1000°C-1200°C, the growth pressure is 50mbar-100mbar, and the amount of substance ratio of the group V elements to the group III elements in the growth raw material is 1:(20-100).

23. The preparation method according to claim 22, characterized in that: It also includes growing a three-dimensional nucleation layer on the surface of the two-dimensional nucleation layer away from the silicon substrate layer; the growth temperature of the three-dimensional nucleation layer is 900℃-1100℃, the growth pressure is 100mbar-300mbar, and the amount of substance ratio of group V elements to group III elements in the growth raw material is 1:(100-2000).

24. A radio frequency device, characterized in that: It includes a drain, a source, a gate and an epitaxial wafer as described in any one of claims 1 to 20; the drain, source and gate are arranged on the surface of the epitaxial layer away from the silicon substrate layer, and the drain and the source are arranged on opposite sides of the gate and isolated from each other.

25. The radio frequency device according to claim 24, characterized in that: The drain electrode includes at least one first blind hole between an orthographic projection of the drain electrode on the silicon substrate layer and an orthographic projection of the gate electrode on the silicon substrate layer.

26. A terminal radio frequency module, characterized in that: It comprises the radio frequency device and antenna as described in claim 24 or 25, wherein the radio frequency device is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

27. A terminal device, characterized in that: Including the terminal radio frequency module as described in claim 26.

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