Display panel and display device

Abstract

The invention discloses a display panel and display equipment. The display panel comprises an array substrate (10), a color film substrate (20) and a liquid crystal layer (LC) located between the array substrate (10) and the color film substrate (20), wherein the array substrate (10) and the color film substrate (20) are oppositely arranged; the liquid crystal box thickness of the liquid crystal layer (LC) in the light-transmitting area of the display panel meets the condition that when the refresh rate of the display panel is larger than or equal to 60 Hz and does not exceed 480 Hz, the reciprocal of the refresh rate of the display panel and the liquid crystal box thickness conform to the quadratic polynomial relation. The thickness of the liquid crystal box of the display panel is only related to the refresh rate of the display panel, so that the design complexity is more simplified and the design efficiency is higher.

Description

Display panel and display device

[0001] The present disclosure relates to a display panel and a display device.

[0002] With the continuous development of thin-film transistor liquid crystal display (TFT-LCD) products and the continuous improvement of users' requirements for display quality, the demand for high refresh rate products is increasing day by day. High refresh rate requires a lower cell gap.

[0003] The Cell Gap is measured in the opening area, and it is difficult to measure in the photo spacer (PS) area because it is opaque. For LCD products, there are many factors affecting the Cell Gap, including the TFT Pillow (the height difference between the PS spacer position or setting position on the TFT substrate and the pixel light-transmitting area), the color resistance step difference of the color film substrate CF, the PS spacer height, and the amount of internal liquid crystal. Too many influencing factors increase the complexity of the Cell Gap and reduce the design accuracy; since high refresh rate LCD display products require a lower Cell Gap, the reduction in Cell Gap design accuracy will significantly affect the design efficiency of display products.

[0004]

[0005] The purpose of the present disclosure is at least in part to provide a display panel and a display device that at least to some extent solve the technical problem of reduced efficiency in display product design due to complex and low-precision design of liquid crystal cell thickness.

[0006] In a first aspect, the present disclosure provides a display panel, comprising an array substrate, a color film substrate and a liquid crystal layer located between the array substrate and the color film substrate; the liquid crystal box thickness of the liquid crystal layer in the light-transmitting area of ​​the display panel satisfies: when the refresh rate of the display panel is greater than or equal to 60 Hz and not more than 480 Hz, the inverse of the refresh rate of the display panel and the liquid crystal box thickness conform to a quadratic polynomial relationship.

[0007] In some embodiments, the liquid crystal cell thickness and the refresh rate satisfy: 1 / f=C2×d 2 +C1×d+C0;

[0008] In the above formula, f is the refresh rate, in Hz; d is the thickness of the liquid crystal box, in μm; the value range of C2 is 0.003 to 0.004, the value range of C1 is -0.02 to -0.01, and the value range of C0 is 0.01 to 0.02.

[0009] In some embodiments, when the refresh rate of the display panel is greater than 480 Hz and does not exceed 1000 Hz, the thickness of the liquid crystal cell ranges from 1.044 μm to 1.6 μm.

[0010] In some embodiments, the array substrate includes a first substrate and a first spacer layer, and the first spacer layer is arranged on a side of the first substrate close to the color film substrate; the color film substrate includes a second substrate and a second spacer layer, and the second spacer layer is arranged on a side of the second substrate close to the array substrate; the first spacer layer includes at least one first main spacer and a plurality of first sub-spacers, and the first main spacer is spaced apart from the first sub-spacers; the second spacer layer includes at least one second main spacer and a plurality of second sub-spacers, and the second main spacer is spaced apart from the second sub-spacers; the first main spacer is in contact with the second main spacer, and the first sub-spacer and the second sub-spacer are arranged opposite to each other.

[0011] In some embodiments, the array substrate further includes a color resist layer and an organic film layer stacked on the first substrate, and the organic film layer is located between the color resist layer and the first spacer layer.

[0012] In some embodiments, a first groove is provided on the organic film layer, the first sub-spacer is disposed in the first groove, and the first main spacer is disposed on the organic film layer outside the first groove.

[0013] In some embodiments, the second main spacer and the second sub-spacer include a black matrix layer, and the color film substrate includes a flat protective layer covering the black matrix layer and the second substrate; in a direction perpendicular to the second substrate, the thickness of the black matrix layer is greater than the thickness of the flat protective layer covering the second substrate, and the flat protective layer on the second main spacer abuts against the first main spacer.

[0014] In some embodiments, the sum of the thicknesses of the black matrix layer and the flat protection layer in the second main spacer after cell alignment and the height of the first main spacer after cell alignment do not deviate by more than 20%.

[0015] In some embodiments, the color film substrate includes a black matrix layer and a flat protective layer arranged on the side of the second substrate close to the array substrate, and the black matrix layer is located between the second substrate and the flat protective layer; a second groove is provided on the flat protective layer, the second sub-spacer is arranged in the second groove, and the second main spacer is arranged on the flat protective layer outside the second groove.

[0016] In some embodiments, the color film substrate includes a black matrix layer and a color resist layer arranged on the same layer on the second substrate, and a flat protective layer covering the black matrix layer and the color resist layer; the second main spacer and the second sub-spacer are arranged on the color resist layer, and their orthographic projections on the second substrate are located within the orthographic projections of the black matrix layer on the second substrate; in a direction perpendicular to the second substrate, the sum of the thicknesses of the black matrix layer and the flat protective layer is less than the sum of the thicknesses of the color resist layer and the flat protective layer.

[0017] In some embodiments, in the vertical direction of the color filter substrate, the top surface of the second sub-spacer is lower than the top surface of the second main spacer, and the height difference is 0.45μm to 0.55μm; or, in the vertical direction of the array substrate, the top surface of the first sub-spacer is lower than the top surface of the first main spacer, and the height difference is 0.45μm to 0.55μm.

[0018] In some embodiments, the product of the height of the first main spacer before aligning the box and the compression rate after aligning the box, and the sum of the height of the second main spacer after aligning the box are equal to the thickness of the liquid crystal box, and the compression rate ranges from 0.86 to 0.88.

[0019] In some embodiments, the deviation between the height of the first main spacer after the box is assembled and the height of the second main spacer after the box is assembled does not exceed 10%.

[0020] In some embodiments, the first main spacer is at the same height as the first sub-spacer, and the second sub-spacer is lower than the second main spacer; or, the second sub-spacer is at the same height as the second main spacer, and the first sub-spacer is lower than the first main spacer.

[0021] In a second aspect, the present disclosure provides a display device, comprising any display panel provided by the embodiments of the first aspect.

[0022] The display panel provided by the present invention has a liquid crystal cell thickness (cell gap) designed to satisfy a quadratic polynomial relationship with the inverse of the refresh rate of the display panel when the refresh rate of the display panel is greater than or equal to 60 Hz and not more than 480 Hz; by constructing a quadratic polynomial fitting relationship between the liquid crystal cell thickness and the inverse of the refresh rate, compared with the conventional method of designing the liquid crystal cell thickness based on the TFT Pillow, the color resistance step difference, the spacer height and the amount of liquid crystal, the influencing factors of the liquid crystal cell thickness are significantly reduced, which is beneficial to reducing the design complexity of the liquid crystal cell thickness and improving the design accuracy, thereby improving the design efficiency of liquid crystal display products.

[0023] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0024] FIG1 is a schematic diagram showing the testing principle of the liquid crystal cell thickness;

[0025] FIG2 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0026] FIG3 is a schematic diagram showing the fitting of the refresh rate and the liquid crystal cell thickness according to an embodiment of the present disclosure;

[0027] FIG4 is a schematic diagram of a sub-spacer Sub PS missing according to an embodiment of the present disclosure;

[0028] FIG5 is a schematic diagram of a display panel with an XPS design according to an embodiment of the present disclosure;

[0029] FIG6 is a schematic diagram of the arrangement of the first main spacer and the first auxiliary spacer according to an embodiment of the present disclosure;

[0030] FIG7 is a schematic diagram of a film structure of a display panel designed by combining XPS with COA according to an embodiment of the present disclosure;

[0031] FIG8A is a schematic diagram of disposing a first auxiliary spacer in a first groove according to an embodiment of the present disclosure;

[0032] 8B is a schematic diagram of disposing a first main spacer and a first auxiliary spacer in a first groove according to an embodiment of the present disclosure;

[0033] FIG9 is a schematic diagram of forming a second spacer layer through a black matrix layer and a flat protective layer according to an embodiment of the present disclosure;

[0034] FIG10 is a schematic diagram of disposing a second auxiliary spacer in a second groove according to an embodiment of the present disclosure;

[0035] FIG11 is a microscopic photograph of the second auxiliary spacer according to an embodiment of the present disclosure;

[0036] FIG. 12 is a spacer structure design on the CF side of an XPS display panel according to an embodiment of the present disclosure;

[0037] FIG13 is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0038] Figure numerals: 10, array substrate; 11, first substrate; 12, first groove; 20, color filter substrate; 21, second substrate; 22, second groove; BM, black matrix layer; OC, flat protection layer; CRL, color resist layer; ORG, organic film layer; PS1, first spacer layer; Main PS1, first main spacer; Sub PS1, first sub-spacer; PS2, second spacer layer; Main PS2, second main spacer; Sub PS2, second sub-spacer.

[0039] The present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0040] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0041] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0042] In the context of the present disclosure, unless otherwise specified, the light emitting side of the display panel is referred to as the "top side" or "upper side", and the opposite side is referred to as the "bottom side" or "lower side" for ease of describing relative directions. Accordingly, the direction from the bottom side to the top side is the thickness direction of the display panel, and the direction perpendicular to the thickness direction is the "plane direction" or "extension direction" of the display panel. It should be understood that these directions are relative directions rather than absolute directions.

[0043] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0044] Cell Gap is an important parameter in TFT-LCD design. With the development of the industry and the improvement of quality technology, LCD display products with high refresh rate and extremely low Cell Gap have emerged, which brings challenges to the design of Cell Gap.

[0045] The principle of Cell Gap measurement is shown in Figure 1. After light is projected onto the liquid crystal cell, the linear polarized light is affected by the birefringence effect of the liquid crystal and changes into elliptical light. The reason is that there is a phase difference between the x and y directions of the light. The magnitude of the phase deviation is determined by the thickness d of the liquid crystal cell and the refractive index difference Δn. The relationship expression is as follows: Re = Δn × d (1)

[0046] Therefore, the solution to the liquid crystal cell thickness d is: d = Re / Δn (2)

[0047] Re in the above formula is the birefringence phase difference (Retardation), which means that when the linear polarized light E is incident at a certain fixed angle, the phase of the decomposed vectors Ex and Ey before the incident is the same, but after the light passes through the sample, the refractive index of x and y is different, resulting in a phase change, which is the birefringence phase difference. Δn = Ne-No, Ne and No are the characteristic parameters of the liquid crystal material.

[0048] The process of measuring the thickness of the liquid crystal cell by the system is as follows:

[0049] Spectral measurement of elliptically polarized light → Analyze the Re value every 10nm within the wavelength range of 400nm to 800nm ​​→ Use the least square method to calculate the fitting formula for the above data and determine the Re of any wavelength.

[0050] The design of the thickness of the liquid crystal box is related to the structural design of the columnar spacer (PS). According to the structural design of the columnar spacer, it can be divided into an ordinary panel and an XPS panel. In the manufacturing process of an ordinary liquid crystal display panel, it is necessary to separately manufacture an array substrate (TFT) and a color film substrate (CF), and then use a frame sealant to bond the edges of the color film substrate and the array substrate together, and fill the liquid crystal in the area sealed by the frame sealant to realize the manufacture of the liquid crystal display device; wherein, a columnar spacer (PS) is provided in the pixel area used for display and between the pixel area and the frame sealant to play a supporting role, and the PS is usually provided on the color film substrate. For the liquid crystal display panel manufactured by XPS technology, a layer of columnar spacer PS is formed on each of the color film substrate and the array substrate and abuts against each other. In some embodiments, the two PS abutting against each other on the array substrate and the color film substrate are set to approximately equal heights. In some embodiments, the cross-sections of the two PS abutting against each other on the array substrate and the color film substrate in the direction parallel to the display panel are set to strips and cross them to optimize PS Mura (unevenness) and Panel panel strength.

[0051] The design of the cell gap of an XPS-designed liquid crystal display product is as follows: Cell Gap = PSH × 2 × PS compression ratio - pixel step difference + TFTPillow (3)

[0052] PSH (Photo Space Height) in the above formula is the free height of the columnar spacer PS on the array substrate side (TFT side) or the color film substrate (CF side) before box alignment, and the two are designed to be of the same height; the PS compression rate is the compression rate of the columnar spacer PS after box alignment, for example, the optional value of the compression rate is about 87%; the pixel step difference is the pixel step difference of the sub-pixel RGB after the OC (flat protection layer), which is the step difference between the sub-pixel RGB and the black matrix; TFTPillow is the height difference between the setting position of the spacer PS on the TFT substrate and the light-transmitting area of ​​the pixel Pixel.

[0053] At present, the extremely low PSH technology can reduce the height of the single-side spacer of the XPS product to 0.9μm, that is, the single-side PSH ≥ 0.9μm. According to formula (3) and the common pixel step difference and TFT Pillow values, it can be known that the liquid crystal cell thickness of the XPS liquid crystal display panel will not be less than 1.57μm.

[0054] For ordinary LCD products, a design of the cell gap is: Cell Gap = PSH × compression ratio - pixel step difference + TFT Pillow (4)

[0055] Among them, PSH (Photo Space Height) is the height of the columnar spacer PS on the color filter substrate side. Similarly, if PSH is not less than 0.9μm, it can be determined that the liquid crystal cell thickness of a common liquid crystal display panel will not be less than 0.78μm.

[0056] According to the above content, there are many factors that affect the Cell Gap, including TFT Pillow, CF color resistance step difference and spacer height, and the internal liquid crystal volume is also one of the influencing factors. With the development of high refresh display products, smaller Cell Gap is required, so the deviation of Cell Gap design accuracy has a more significant impact on high refresh display products.

[0057] In order to solve the above problems, in the first aspect, please refer to Figure 2, the present disclosure provides a display panel, including an array substrate 10, a color film substrate 20 and a liquid crystal layer LC located between the array substrate 10 and the color film substrate 20; the liquid crystal box thickness of the liquid crystal layer LC in the light-transmitting area of ​​the display panel satisfies: when the refresh rate of the display panel is greater than or equal to 60 Hz and not more than 480 Hz, the inverse of the refresh rate of the display panel and the liquid crystal box thickness conform to a quadratic polynomial relationship.

[0058] The relationship between the liquid crystal cell thickness and the refresh rate provided in the embodiments of the present disclosure is determined from the following sources:

[0059] The higher the refresh rate of the display panel means a smaller or faster response time is required; the response time is the time it takes for the LCD display to react to the input signal, that is, the time required for the pixel to change from dark to bright or from bright to dark. The smaller the response time, the faster the response speed when the screen switches, and the smoother the screen switching.

[0060] The formula for response time is as follows:

[0061] In formula (5) and (6):

[0062] τ r The rise time indicates the time interval for the brightness to drop from 90% to 10% (normally white mode) or the time interval for the brightness to rise from 10% to 90% (normally black mode) during the process from power-off state to power-on state.

[0063] τ d Delay time, which means the time interval when the brightness reaches 10% of the maximum brightness during power off.

[0064] γ1: viscosity coefficient of liquid crystal material;

[0065] d: LCD cell thickness;

[0066] V: driving voltage;

[0067] V th : threshold voltage;

[0068] Δε: Dielectric constant of liquid crystal material.

[0069] Let τ on =τ r +τ d , the refresh rate is f, then:

[0070] Right now:

[0071] It can be seen that under the premise of the same liquid crystal material and driving voltage, the response time τ on，off It is proportional to the square of the liquid crystal cell thickness d, and the refresh rate is inversely correlated with the square of d.

[0072] Combined with the above theoretical derivation, the liquid crystal cell thickness design, simulation and data verification are carried out. By integrating the data, when the refresh rate is in the range of [60Hz, 480Hz], the following fitting relationship is obtained: 1 / f=C2×d 2 +C1×d+C0(9)

[0073] In the above formula, f is the refresh rate in Hz; d is the thickness of the liquid crystal cell in μm; the value range of C2 is [0.003, 0.004], the value range of C1 is [-0.02, -0.01], and the value range of C0 is [0.01, 0.02].

[0074] Optionally, the coefficient term is: C2 = 0.0038, C1 = -0.0127, C2 = 0.0125, which satisfies: 1 / f = 0.0038d 2 –0.0127d+0.0125 (10)

[0075] The determination coefficient R of the fitting relationship of formula (10) 2 =0.9999, as shown in Figure 3; the coefficient of determination R 2 The numerical value of reflects the degree of fit between the estimated value of the trend line and the corresponding actual data. When the square value of R is equal to 1 or close to 1, it indicates the highest reliability, otherwise the reliability is low.

[0076] According to equations (9) and (10), the display panel provided by the present invention has a liquid crystal box thickness (cell gap) designed to construct a quadratic polynomial fitting relationship between the inverse of the refresh rate and the liquid crystal box thickness when the refresh rate of the display panel is greater than or equal to 60 Hz and not more than 480 Hz. Compared with the conventional method of designing the liquid crystal box thickness based on TFT Pillow, color resistance step difference, spacer height and liquid crystal amount, the influencing factors of the liquid crystal box thickness are significantly reduced, which is beneficial to reducing the design complexity of the liquid crystal box thickness and improving the design accuracy, thereby improving the design efficiency of liquid crystal display products and providing a new Cell Gap design benchmark.

[0077] Optionally, for high refresh display products with a refresh rate f greater than 480Hz, such as [480Hz, 1000Hz], the value range of the liquid crystal box thickness is [1.044μm, 1.6μm]. The trend is that the higher the refresh rate, the smaller the value of the liquid crystal box thickness. In some embodiments, under the premise of meeting the refresh rate, a higher liquid crystal box thickness can also be selected. The higher the liquid crystal box thickness, the higher the product transmittance. In addition, the liquid crystal box thickness can also be adjusted according to the customer's grayscale response time (GTG, gray to gray) requirements. According to the corresponding relationship between the liquid crystal box thickness and the refresh rate of the embodiment of the present disclosure, the range of the liquid crystal box thickness Cell Gap is 1.044μm to 3.8μm.

[0078] The correspondence between the liquid crystal cell thickness and the refresh rate provided in the embodiments of the present disclosure can be used for ordinary liquid crystal display panels and can also be used for XPS liquid crystal display panels. Taking the XPS liquid crystal display products used in notebook computers as an example, the common refresh rate range is 60Hz to 360Hz, and ≥120Hz is a high refresh product. The liquid crystal cell thickness requirements of high refresh products are also related to the response time. When the liquid crystal material is determined, the faster the response time and the higher the refresh rate, the lower the liquid crystal cell thickness.

[0079] The liquid crystal box thickness of some XPS LCD display products is designed as follows: the liquid crystal box thickness of 60Hz NB products is about 3.6μm, the liquid crystal box thickness of 90Hz NB products is about 3.18μm, the liquid crystal box thickness of 120Hz NB products is about 2.92μm, the liquid crystal box thickness of 240Hz NB products is about 2.4μm (GTG is 3ms), the liquid crystal box thickness of 360Hz NB products is about 2.0μm (GTG is 2ms), and the liquid crystal box thickness of 480Hz NB products is about 1.6μm (GTG is 1ms).

[0080] In order to ensure that there is enough liquid crystal safety margin (LC Margin) for the XPS liquid crystal display panel, the main spacer Main PS and the sub-spacer Sub PS can be set in the PS layer on the TFT side and the CF side respectively, where the Sub PS is thinner or lower; but if the Sub PS is too thin or too low, it is easy to have problems such as Sub PS missing, morphological deformation or molding failure, as shown in Figure 4. In order to avoid Sub PS missing, its height should be controlled above 0.5μm. Therefore, the thickness of the liquid crystal box Cell Gap cannot be reduced indefinitely. If it is too small, it is easy to cause problems such as PS missing during production. The current extremely low PSH technology can reduce the Main PS height of the XPS product to 0.9μm while ensuring that the Sub PS is not missing.

[0081] For the XPS liquid crystal display panel, on the one hand, the PS layer is designed on the TFT side and the CF side respectively, which reduces the height of the PS layer on one side. On the other hand, due to the increase in refresh rate, it is required to further reduce the thickness of the liquid crystal box, thereby further reducing the height of the PS layer on one side. As mentioned above, if the height of the PS layer is too low, the process capability cannot be met and the problem of PS missing is likely to occur, which will also limit the design of the liquid crystal box thickness.

[0082] In order to solve the above problems, in some embodiments, referring to the liquid crystal display panel with an XPS structure provided in FIG. 5 , a spacer layer is formed by a combination structure of a main spacer (Main PS) and a sub-spacer (Sub PS), including:

[0083] The array substrate 10 includes a first substrate 11 and a first spacer layer PS1, and the first spacer layer PS1 is arranged on a side of the first substrate 11 close to the color filter substrate 20; the color filter substrate 20 includes a second substrate 21 and a second spacer layer PS2, and the second spacer layer PS2 is arranged on a side of the second substrate 21 close to the array substrate 10; the first spacer layer PS1 includes at least one first main spacer Main PS1 and a plurality of first sub-spacers Sub PS1, and the first main spacer Main PS1 and the first sub-spacer Sub PS1 are arranged at intervals; the second spacer layer PS2 includes at least one second main spacer Main PS2 and a plurality of second sub-spacers Sub PS2, and the second main spacer Main PS2 and the second sub-spacer Sub PS2 are arranged at intervals; the first main spacer Main PS1 abuts against the second main spacer Main PS2, and the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are arranged opposite to each other.

[0084] In some embodiments, the first substrate 11 is the base of the array substrate 10, also called the base substrate or TFT substrate, and a transparent glass substrate TFT Glass can be used; the second substrate 21 is the base of the color film substrate 20, also called the CF substrate, and a transparent glass substrate CF Glass can also be used.

[0085] The structural options for the main spacer and the secondary spacer include:

[0086] ① When the PS step difference is formed on the color film substrate 20 side (CF), as shown in FIG5 , the spacers on the TFT side are of equal height, that is, the heights of the first main spacer Main PS1 and the first sub-spacer Sub PS1 are equal, and the first main spacer Main PS1 can be designed to be thicker than the first sub-spacer Sub PS1; the spacers on the CF side are of unequal heights, and the height of the second sub-spacer Sub PS2 is lower than that of the second main spacer Main PS2; after the liquid crystal panel is assembled, the first main spacer Main PS1 and the second main spacer Main PS2 are arranged against each other, and the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are arranged opposite to each other;

[0087] ② When the PS step difference is formed on the array substrate 10 side (TFT), the spacers on the CF side are of the same height, that is, the second main spacer Main PS2 and the second sub-spacer Sub PS2 are of the same height, and the second main spacer Main PS2 is thicker than the second sub-spacer Sub PS2; the spacers on the TFT side are of different heights, and the height of the first sub-spacer Sub PS1 is lower than the height of the first main spacer Main PS1; after the liquid crystal panel is assembled, the first main spacer Main PS1 and the second main spacer Main PS2 are set against each other, and the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are set opposite to each other.

[0088] Taking the first main spacer MainPS1 and the first sub-spacer SubPS1 as examples, the first main spacer MainPS1 being thicker means that in the plane direction of the display panel, the cross-sectional area of ​​the first main spacer MainPS1 is larger than the cross-sectional area of ​​the first sub-spacer SubPS1. Both the first main spacer MainPS1 and the first sub-spacer SubPS1 can be designed as a columnar structure, and the cross-section of the columnar structure can be a triangle, a polygon, a circle, an ellipse, etc., which can be designed according to actual needs; the first main spacer MainPS1 and the first sub-spacer SubPS1 are arranged at intervals, and multiple first sub-spacers SubPS1 can be arranged between two first main spacers MainPS1, as shown in FIG6; or multiple first main spacers MainPS1 can be arranged between two first sub-spacers SubPS1. The preferred solution is the former. The quantity ratio of the first main spacer Main PS1 to the first sub-spacer Sub PS1 can be determined according to actual needs. For example, the quantity ratio of the first main spacer MainPS1: the first sub-spacer Sub PS1 is set to 1:10-300, which is not limited in the embodiments of the present disclosure.

[0089] When the shapes of the first main spacer MainPS1, the first sub-spacer SubPS1, the second main spacer MainPS2 and the second sub-spacer SubPS2 are designed using the above solution, the liquid crystal margin LC of the liquid crystal display panel can be further increased.

[0090] In some embodiments, the first main spacer Main PS1 and the first sub-spacer Sub PS1 on the TFT side, and the second main spacer MainPS2 and the second sub-spacer Sub PS2 on the CF side can be in the shape of strips, and their arrangement directions can be crossed with each other, such as the first main spacer MainPS1 and the second main spacer MainPS2 that are offset from each other are arranged in a cross pattern that is perpendicular to each other or in a non-cross pattern that is not perpendicular to each other, and the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 that are opposite to each other are arranged in a cross pattern or a non-cross pattern, which can further optimize the PS mura problem and improve the panel strength.

[0091] The above scheme provides an overall design of the spacer structure in the XPS liquid crystal display panel. Next, the film layer structures on the TFT side and the CF side are further described respectively.

[0092] For the film layer structure on the TFT side, in some embodiments, please refer to the schematic diagram of the stacked structure of the display panel shown in FIG7 , the array substrate 10 also includes a color resist layer CRL (Color resist Layer) and an organic film layer ORG stacked on the first substrate 11, and the organic film layer ORG is located between the color resist layer CRL and the first spacer layer PS1. In other words, the array substrate 10 provided here is a COA substrate (Color Filter on Array), which is a technology that integrates the organic film layer ORG and the color resist layer CRL on the array substrate 10. The advantage of the COA substrate is that there is no light leakage problem caused by the box, and the width of the black matrix layer BM can be effectively reduced, thereby increasing the pixel aperture ratio, and further increasing the transmittance of the display panel.

[0093] For the COA substrate, please refer to FIG. 7. In the thickness direction, the display panel includes a gate metal layer Gate, a gate dielectric layer GI, an amorphous silicon active layer a-Si, a source-drain metal layer SD and a passivation layer PVX stacked in sequence on the first substrate 11 (TFT substrate). These film layer structures form a thin film transistor located in the display area A-A' and a thin film transistor located in the peripheral area B-B'. Then, a color resist layer CRL and an organic film layer ORG are stacked in sequence on the passivation layer. Among them, the color resist layer CRL located in the blue sub-pixel area is a blue color resist layer B-CRL, the color resist layer CRL located in the green sub-pixel area is a green color resist layer G-CRL, and the color resist layer CRL located in the red sub-pixel area is a red color resist layer R-CRL. The color resist layer CRL and the organic film layer ORG form a color filter film layer, which realizes filtering of light on the one hand and flattening of the opening area on the other hand. The first spacer layer PS1 on the TFT side is arranged on the side of the organic film layer ORG close to the color filter substrate 20. In addition, an ITO transparent electrode is stacked on the organic film layer ORG.

[0094] Since the RGB color filter film layer in the COA substrate is arranged on one side of the TFT substrate and is planarized by the organic film layer ORG, the position of the spacer layer and the pixel opening area on the TFT side does not need to consider the pixel step difference.

[0095] It should be noted that the COA substrate integrates the color resist layer CRL into the TFT side of the array substrate 10. Although there is no color filter layer on the color film substrate 20 side, in order to facilitate the description and distinction of the array substrate 10 on the TFT side, it will still be referred to as the CF side in the following content.

[0096] In some embodiments, please refer to FIG. 8A , a first groove 12 is provided on the organic film layer ORG, a first sub-spacer Sub PS1 is provided in the first groove 12, and a first main spacer Main PS1 is provided on the organic film layer ORG outside the first groove 12. The first groove 12 may be a blind hole formed by digging a groove on the organic film layer ORG, or a through hole penetrating the organic film layer ORG, and then a spacer material is deposited to form a first sub-spacer Sub PS1 in the through hole or the blind hole, and a first main spacer Main PS1 is formed on the organic film layer ORG outside the through hole or the blind hole. By forming the first sub-spacer Sub PS1 in the first groove 12, on the one hand, the top surface of the first sub-spacer Sub PS1 can be made lower than the top surface of the first main spacer MainPS1 in the vertical direction of the array substrate 10, so that a certain PS step difference is formed between the first main spacer Main PS1 and the first sub-spacer Sub PS1, such as 0.45μm~0.55μm, and a preferred value is 0.5μm. When this step difference is met, the normal mask Normal Mask can be used instead of the halftone mask Halftone Mask to manufacture the first spacer layer PS1, thereby saving the Mask production cost; on the other hand, while maintaining the PS step difference and further reducing the thickness of the liquid crystal box, it is ensured that the height of the first sub-spacer Sub PS1 will not be too low, thereby avoiding the problem of PS missing caused by the first sub-spacer Sub PS1 being too low.

[0097] In some embodiments, please refer to FIG. 8B , more first grooves 12 may be provided on the organic film layer ORG, and the first main spacer Main PS1 and the first sub-spacer Sub PS1 may be provided in the first grooves 12, and the first main spacer Main PS1 and the first sub-spacer Sub PS1 may form a PS step difference. At this time, the second main spacer Main PS2 and the second sub-spacer Sub PS2 on the CF side may adopt an equal height design or a nearly equal height design, so that the first spacer layer PS1 may be manufactured using a normal mask plate Normal Mask instead of a halftone mask plate Halftone Mask, and the thickness of the liquid crystal cell may be further reduced.

[0098] For the membrane structure on the CF side, the following two design schemes can be adopted:

[0099] Solution 1: Using the black matrix layer BM to form the second spacer layer PS2.

[0100] Please refer to Figures 7 and 9. The second main spacer Main PS2 and the second sub-spacer Sub PS2 include a black matrix layer BM, and the color film substrate 20 includes a flat protective layer OC (Over Coat) covering the black matrix layer BM and the second substrate 21; in a direction perpendicular to the second substrate 21, the thickness of the black matrix layer BM is greater than the thickness of the flat protective layer OC covering the second substrate 21, and the flat protective layer OC in the second main spacer Main PS2 abuts against the first main spacer Main PS1.

[0101] The common XPS display panel design is to deposit a layer of PS material on the TFT side and the CF side to form a spacer layer. The display panel provided by Scheme 1 only needs to deposit a layer of PS material on the TFT side, and make the first spacer layer PS1 through a composition process; on the CF side, at a position on the second substrate 21 opposite to the first spacer layer PS1, a black matrix material thicker than conventional is deposited to form a second spacer layer PS2. Among them, the black matrix layer BM and the flat protective layer OC abutting the first main spacer Main PS1 form the second main spacer Main PS2, the black matrix layer BM and the flat protective layer OC opposite to the first sub-spacer Sub PS1 form the second sub-spacer Sub PS2, and the other black matrix layers BM can be used normally as a shading structure. Therefore, Scheme 1 does not need to deposit PS material on the CF side to form the second spacer layer PS2, which can save a PS Mask process, thereby reducing manufacturing costs and improving production efficiency.

[0102] 9 shows the film structure of the second main spacer Main PS2 and the second sub-spacer Sub PS2 formed by the black matrix layer BM and the flat protection layer OC, wherein the height of the second spacer layer PS2 on the CF side can be adjusted by the thickness of the black matrix layer BM and the flat protection layer OC.

[0103] In some embodiments, the second main spacer Main PS2 and the second sub-spacer Sub PS2 formed by the black matrix layer BM and the flat protection layer OC may be of equal height or unequal height, and the PS step difference may be adjusted depending on whether it is formed on the TFT side or the CF side. Optionally, the sum of the thickness of the black matrix layer BM and the flat protection layer OC in the second main spacer Main PS2 after the box is aligned, and the deviation between the height of the first main spacer Main PS1 after the box is aligned does not exceed 20%, that is, the first main spacer Main PS1 and the second main spacer Main PS2 may be designed with equal height or approximately equal height.

[0104] Considering that the first main spacer Main PS1 formed by the deposition of PS material will be compressed after the cell is assembled, while the black matrix layer BM will hardly be compressed, the XPS combined with COA liquid crystal display panel of Scheme 1 satisfies: the product of the height of the first main spacer Main PS1 before the cell is assembled and the compression rate after the cell is assembled, and the sum of the height of the second main spacer Main PS2 is equal to the thickness of the liquid crystal cell, that is: d = H1 × k + H t (11)

[0105] In the above formula, d is the thickness of the liquid crystal cell, H1 is the free height of the first main spacer Main PS1 before the cell is aligned, and H t is the height of the second main spacer Main PS2, which is equal to the height of the black matrix layer BM after box alignment, or the sum of the heights of the black matrix layer BM + the flat protective layer OC after box alignment. k is the compression rate of the first main spacer MainPS1 after box alignment, and the value range of k is 0.86-0.88, such as 0.87.

[0106] It can also be known from formula (11) that the sum of the free height of the first main spacer Main PS1 on the TFT side before the cell is aligned or the height after the cell is disassembled and the height of the second main spacer Main PS2 is greater than the liquid crystal cell thickness d, that is, the thickness of the opening area. In addition, as shown in FIG. 7 , the first main spacer Main PS1 on the TFT side is arranged above the TFT device in the pixel area, which is conducive to reducing the thickness of the opening area.

[0107] In some embodiments, the height PSH (H1×k) of the first main spacer Main PS1 on the TFT side after being compressed by the box alignment is equal or approximately equal to the height Ht of the second main spacer Main PS2 on the CF side, so as to ensure that the height of the PS layer on one side will not be too small to cause PS missing. Wherein, approximately equal means that the deviation between the height PSH1 of the first main spacer Main PS1 after the box alignment and the height Ht of the second main spacer Main PS2 after the box alignment does not exceed 10%.

[0108] It should be noted that if the height PSH of the first main spacer Main PS1 on the TFT side is ≥ 0.9 μm, and is consistent with the height of the second main spacer Main PS2, which is the sum of the thickness of the black matrix layer BM and the flat protection layer OC, the first main spacer Main PS1 and the first sub-spacer Sub PS1 can have different heights, and the PS step difference is formed on the TFT side. Since the COA product can flatten the array substrate 10 through the color resistance layer CRL and the organic film layer ORG, the position of the first spacer layer PS1 on the TFT side and the pixel opening area position can ignore the pixel step difference, and the liquid crystal cell thickness Cell Gap can be controlled to not less than 1.56 μm.

[0109] Solution 2: deposit PS material to form a second spacer layer PS2.

[0110] Please refer to Figure 10. The color filter substrate 20 includes a black matrix layer BM and a flat protective layer OC arranged on the side of the second substrate 21 close to the array substrate 10, and the black matrix layer BM is located between the second substrate 21 and the flat protective layer OC; a second groove 22 is provided on the flat protective layer OC, and a second sub-spacer Sub PS2 is arranged in the second groove 22, and a second main spacer MainPS2 is arranged on the flat protective layer OC outside the second groove 22.

[0111] In some embodiments, the width or area of ​​the black matrix layer BM is greater than the second spacer layer PS2 on the CF side, and the orthographic projection of the second groove 22 on the second substrate 21 is located within the orthographic projection of the black matrix layer BM on the second substrate 21, that is, the second groove 22 is located above the black matrix layer BM. The second groove 22 can be a blind hole formed by digging a groove on the flat protective layer OC, or it can be a through hole that penetrates the flat protective layer OC, and can be designed according to actual needs. A spacer material is deposited in the second groove 22 to form a second sub-spacer Sub PS2, and the orthographic projection of the second sub-spacer Sub PS2 on the second substrate 21 is located within the orthographic projection of the second groove 22 on the second substrate 21.

[0112] In some embodiments, in the vertical direction of the color filter substrate 20 or in the thickness direction of the color filter substrate 20, the top surface of the second sub-spacer Sub PS2 located in the second groove 22 is lower than the top surface of the second main spacer Main PS2, that is, the upper surface of the second sub-spacer Sub PS2 is lower than the upper surface of the surrounding second main spacer Main PS2, and the height difference between the two is about 0.45μm to 0.55μm, thereby forming a PS step difference on the color filter substrate 20 side, and the preferred value can be controlled at 0.5μm. In this way, on the one hand, Halftone Mask can no longer be used, and Normal Mask can be used to manufacture the spacers on the CF side, saving the Mask production cost; on the other hand, it supports the design of the second main spacer MainPS2 and the second sub-spacer Sub PS2 to be lower, while further reducing the thickness of the liquid crystal box, avoiding the PS loss caused by the excessively low height of the second sub-spacer Sub PS2. Studies have shown that when the height of the second sub-spacer Sub PS2 is less than or equal to 0.5μm, the PS loss problem is easy to occur. It should be noted that, since the PS step is formed on the color filter substrate 20 side, the top surface of the first main spacer Main PS1 and the top surface of the first sub-spacer Sub PS1 are designed to be equal in height in the vertical direction or thickness direction on the array substrate 10 side.

[0113] The micrograph of the second sub-spacer Sub PS2 can be found in Figure 11. The second sub-spacer Sub PS2 "stands" in the blind hole or trench of the flat protective layer OC. The depth of the trench can be adjusted according to the design requirements to ensure that the top surface of the second sub-spacer Sub PS2 is about 0.5μm lower than the top surface of the surrounding second main spacer Main PS2, just forming a PS step difference. On this basis, the actual height of the second sub-spacer Sub PS2 can be designed to be equal to the actual height of the second main spacer Main PS2 to ensure that the second sub-spacer Sub PS2 is not missing. At this time, the minimum height of the second main spacer Main PS2 and the second sub-spacer Sub PS2 can be reduced to 0.6μm, thereby significantly reducing the thickness of the liquid crystal box.

[0114] When the heights of the first main spacer Main PS1 and the second main spacer Main PS2 are the same, the liquid crystal cell thickness Cell Gap satisfies: d = H1 × 2 × PS compression ratio (12)

[0115] H1 in the formula (12) is the free height of the first main spacer Main PS1 on the TFT side before the cell assembly, and is equal to the free height of the second main spacer Main PS2 before the cell assembly compression.

[0116] At this moment, if the PS compression rate is 0.87, then d=0.6×2×0.87=1.044 μm, so the liquid crystal box thickness d can be controlled to a minimum of 1.044 μm, that is, d≥1.044 μm.

[0117] In general, the XPS-based liquid crystal display panel provided in the above embodiments has the following characteristics:

[0118] 1) The color resist layer CRL is fabricated on one side of the array substrate 10 and is planarized in combination with the organic film layer ORG. This eliminates the need to consider the effect of pixel step difference when designing the liquid crystal cell thickness, and eliminates the effect of TFT Pillow. This simplifies the influencing factor of the liquid crystal cell thickness Cell Gap, and the liquid crystal cell thickness can be controlled to be ≥1.56 μm.

[0119] 2) A first groove 12 is provided on the organic film layer ORG on the TFT side, and a first sub-spacer Sub PS1 is formed in the first groove 12, or a second groove 22 is provided on the flat protective layer OC on the CF side, and a second sub-spacer Sub PS2 is formed in the second groove 22, so that: when the actual heights of the first main spacer MainPS1 and the first sub-spacer Sub PS1 on the TFT side are equal or similar, and the actual heights of the second main spacer MainPS2 and the second sub-spacer Sub PS2 on the CF side are equal or similar, a PS step difference is formed between the main spacer Main PS and the sub-spacer Sub PS by means of the first groove 12 or the second groove 22, on the one hand, a Normal Mask can be used instead of a Halftone Mask to prepare a PS layer, thereby saving the Mask production cost, and on the other hand, the main spacer Main PS and the sub-spacer Sub PS can be designed to be lower, which can further reduce the thickness of the liquid crystal cell while avoiding the PS loss caused by the excessively low height of the Sub PS, thereby achieving the goal of reducing the thickness of the liquid crystal cell. The gap is reduced from 1.5μm to 1.044μm, allowing XPS products to break through existing limitations and be designed towards higher refresh rates.

[0120] The above scheme provides a structural design of the COA substrate. For a common display panel in which the color resistance layer CRL (color filter layer) is arranged on the CF side, the following design can be adopted:

[0121] In some embodiments, referring to FIG. 12 , the color filter substrate 20 includes a black matrix layer BM and a color resist layer CRL disposed on the same layer on the second substrate 21, and a flat protective layer OC covering the black matrix layer BM and the color resist layer CRL; a second main spacer Main PS2 and a second sub-spacer Sub PS2 are disposed on the color resist layer CRL, and their orthographic projections on the second substrate 21 are located within the orthographic projections of the black matrix layer BM on the second substrate 21; in a direction perpendicular to the second substrate 21, the sum of the thicknesses of the black matrix layer BM and the flat protective layer OC is less than the sum of the thicknesses of the color resist layer CRL and the flat protective layer OC.

[0122] The black matrix layer BM is arranged in the non-light-transmitting area of ​​the color filter substrate 20, the color resist layer CRL is arranged in the light-transmitting area of ​​the color filter substrate 20, the second main spacer Main PS2 and the second sub-spacer Sub PS2 are arranged on the flat protective layer OC directly above the black matrix layer BM, and the bottom area of ​​the second main spacer Main PS2 and the second sub-spacer Sub PS2 is smaller than the area of ​​the black matrix layer BM to avoid affecting the light transmittance.

[0123] This solution does not dig grooves on the flat protective layer OC, but thins the total thickness of the black matrix layer BM and the flat protective layer OC at the second main spacer Main PS2 and the second sub-spacer Sub PS2 to make it smaller than the total thickness of the color resistance layer CRL and the flat protective layer OC in the surrounding area. While reducing the overall height of the second spacer layer PS2 and reducing the thickness of the liquid crystal cell, it can also save a groove digging process.

[0124] In some embodiments, the thickness of the flat protective layer OC located directly above the black matrix layer BM is greater than the thickness of the flat protective layer OC located directly above the color resist layer CRL outside the BM area, and the second main spacer Main PS2 and the second sub-spacer Sub PS2 are arranged on the flat protective layer OC located directly above the black matrix layer BM, so that the structure under the spacer can be more stable and not easy to peel off.

[0125] Optionally, a groove may be dug on the flat protective layer OC to arrange a second main spacer Main PS2 and a second sub-spacer Sub PS2, which can also reduce the overall height of the second spacer layer PS2, thereby reducing the thickness of the liquid crystal cell.

[0126] It should be noted that the structure adopted in this case has orientation layers on both the upper and lower sides of the liquid crystal layer LC, and the orientation layer and the liquid crystal layer are in direct contact. Because an orientation layer has a uniform thickness, it is not shown in the figure in this case, and its thickness is not considered. Its existence is ignored in the description of the embodiment, but it does not mean that it does not actually exist.

[0127] In the second aspect, please refer to Figure 13, the present disclosure provides a display device, including the display panel provided by the embodiment of the first aspect. The display device can be a desktop computer monitor, an all-in-one computer, a notebook computer, a tablet computer, an all-in-one conference machine, a smart phone, and other electronic devices with a display screen.

[0128] Although some embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including some embodiments and all changes and modifications falling within the scope of the present disclosure.

[0129] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

A display panel comprises an array substrate and a color film substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the color film substrate; the liquid crystal box thickness of the liquid crystal layer in the light-transmitting area of ​​the display panel satisfies: when the refresh rate of the display panel is greater than or equal to 60 Hz and does not exceed 480 Hz, the inverse of the refresh rate of the display panel and the liquid crystal box thickness conform to a quadratic polynomial relationship. The display panel according to claim 1, wherein: The liquid crystal cell thickness and the refresh rate satisfy: 1 / f = C2×d 2 +C1×d+C0; in the above formula, f is the refresh rate, in Hz; d is the thickness of the liquid crystal box, in μm; the value range of C2 is 0.003 to 0.004, the value range of C1 is -0.02 to -0.01, and the value range of C0 is 0.01 to 0.

02. The display panel according to claim 1, wherein: When the refresh rate of the display panel is greater than 480 Hz and does not exceed 1000 Hz, the thickness of the liquid crystal cell ranges from 1.044 μm to 1.6 μm. The display panel according to claim 1, wherein: The array substrate includes a first substrate and a first spacer layer, the first spacer layer is arranged on a side of the first substrate close to the color film substrate; the color film substrate includes a second substrate and a second spacer layer, the second spacer layer is arranged on a side of the second substrate close to the array substrate; the first spacer layer includes at least one first main spacer and a plurality of first sub-spacers, the first main spacer is spaced apart from the first sub-spacers; the second spacer layer includes at least one second main spacer and a plurality of second sub-spacers, the second main spacer is spaced apart from the second sub-spacers; the first main spacer is in contact with the second main spacer, and the first sub-spacer is arranged opposite to the second sub-spacer. The display panel according to claim 4, wherein: The array substrate further includes a color resist layer and an organic film layer stacked on the first substrate, and the organic film layer is located between the color resist layer and the first spacer layer. The display panel according to claim 5, wherein: A first groove is provided on the organic film layer, the first sub-spacer is arranged in the first groove, and the first main spacer is arranged on the organic film layer outside the first groove. The display panel according to claim 4, wherein: The second main spacer and the second sub-spacer include a black matrix layer, and the color film substrate includes a flat protective layer covering the black matrix layer and the second substrate; in a direction perpendicular to the second substrate, the thickness of the black matrix layer is greater than the thickness of the flat protective layer covering the second substrate, and the flat protective layer on the second main spacer abuts against the first main spacer. The display panel according to claim 7, wherein: The deviation between the sum of the thickness of the black matrix layer in the second main spacer and the flat protection layer after cell alignment and the height of the first main spacer after cell alignment does not exceed 20%. The display panel according to claim 4, wherein: The color film substrate includes a black matrix layer and a flat protective layer arranged on the side of the second substrate close to the array substrate, the black matrix layer is located between the second substrate and the flat protective layer; a second groove is provided on the flat protective layer, the second sub-spacer is arranged in the second groove, and the second main spacer is arranged on the flat protective layer outside the second groove. The display panel according to claim 4, wherein: The color film substrate includes a black matrix layer and a color resist layer arranged on the same layer on the second substrate, and a flat protective layer covering the black matrix layer and the color resist layer; the second main spacer and the second sub-spacer are arranged on the color resist layer, and the orthographic projection of the second substrate on the second substrate is located within the orthographic projection of the black matrix layer on the second substrate; in a direction perpendicular to the second substrate, the sum of the thickness of the black matrix layer and the flat protective layer is less than the sum of the thickness of the color resist layer and the flat protective layer. The display panel according to claim 4, wherein: In the vertical direction of the color filter substrate, the top surface of the second sub-spacer is lower than the top surface of the second main spacer, and the height difference is 0.45μm to 0.55μm; or, in the vertical direction of the array substrate, the top surface of the first sub-spacer is lower than the top surface of the first main spacer, and the height difference is 0.45μm to 0.55μm. The display panel according to claim 4, wherein: The product of the height of the first main spacer before aligning the box and the compression rate after aligning the box, and the sum of the height of the second main spacer after aligning the box are equal to the thickness of the liquid crystal box, and the compression rate ranges from 0.86 to 0.

88. The display panel according to claim 4, wherein: The deviation between the height of the first main spacer after the box is assembled and the height of the second main spacer after the box is assembled does not exceed 10%. The display panel according to claim 4, wherein: The first main spacer is as high as the first sub-spacer, and the second sub-spacer is lower than the second main spacer; or the second sub-spacer is as high as the second main spacer, and the first sub-spacer is lower than the first main spacer. A display device comprises the display panel according to any one of claims 1 to 14.

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