Chip output level test method, system and device, medium and program product

Abstract

The invention provides a chip output level test method and system, an electronic device, a storage medium and a program product, and the method comprises the following steps: collecting a plurality of level data for a data output pin of a tested chip based on a preset sampling rate; providing a preset threshold value, taking the level data higher than the preset threshold value as a first level data group, and taking the level data lower than the preset threshold value as a second level data group; and taking the mode of the first level data set as an output high level of the tested chip, and taking the mode of the second level data set as an output low level of the tested chip. The invention provides a method for testing high and low levels when the output position of a test chip is unstable.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a chip output level testing method, system, electronic equipment, storage medium and program product. Background Art

[0002] In chip testing, the purpose of testing VOH (output high voltage) and VOL (output low voltage) is mainly to ensure that the chip's IO pins can maintain a predetermined output level under a specified current load, thereby ensuring the chip's performance and reliability in actual applications. Traditional testing methods require the chip to be able to output high and low levels at a stable time, and then be equipped with a measurement unit for testing. If the chip's output high and low levels are not fixed on the time axis, they can only be observed with an oscilloscope. If you want to use ATE machines for mass production measurements, there is no better way. The industry lacks a simple and effective technical solution to solve the above technical problems. Summary of the invention

[0003] The object of the present invention is to provide a chip output level testing method, system, electronic device, storage medium and program product to provide a solution for testing high and low levels when the output position of the test chip is unstable.

[0004] To achieve the above-mentioned purpose, the present invention provides a chip output level testing method, comprising the following steps: for the data output pin of the tested chip, based on a preset sampling rate, collecting multiple level data; providing a preset threshold, taking the level data higher than the preset threshold as a first level data group, and taking the level data lower than the preset threshold as a second level data group; taking the mode of the first level data group as the output high level of the tested chip, and taking the mode of the second level data group as the output low level of the tested chip.

[0005] Optionally, the method of using the mode of the first level data group as the output high level of the chip under test includes: drawing a first histogram based on the first level data group; and selecting the level data corresponding to the rectangle with the highest vertical axis height in the first histogram as the output high level.

[0006] Optionally, the mode of the second level data group is used as the output low level of the chip under test. The specific implementation method includes: drawing a second histogram according to the second level data group; and selecting the level data corresponding to the rectangle with the highest vertical axis height in the second histogram as the output low level.

[0007] Optionally, it also includes: providing a first preset range so that the first level data group becomes a subset of the first preset range; dividing the first preset range into multiple first intervals on average so that the data in the first level data group falls into the first intervals according to the numerical value; selecting the first interval in which the data in the first level data group falls in the largest number, and obtaining one of the mean, median and mode of the numerical values ​​of the level data in the interval; and changing the numerical values ​​of the level data in the interval to one of the mean, median and mode of the numerical values ​​of the level data in the interval.

[0008] Optionally, it also includes: providing a second preset range so that the second level data group becomes a subset of the second preset range; dividing the second preset range into multiple second intervals on average so that the data in the second level data group falls into the second intervals according to their numerical values; selecting the second interval in which the data in the second level data group falls with the largest number, and obtaining one of the mean, median and mode of the numerical values ​​of the level data in the interval; and changing the numerical values ​​of the level data in the interval to one of the mean, median and mode of the numerical values ​​of the level data in the interval.

[0009] Optionally, the chip under test is in a working state after being configured.

[0010] The present invention also provides a chip output level test system, comprising: a sampling module, used to collect multiple level data for the data output pin of the tested chip based on a preset sampling rate; a processing module, used to provide a preset threshold, use the level data higher than the preset threshold as a first level data group, use the level data lower than the preset threshold as a second level data group, and use the majority of the first level data group as the output high level of the tested chip, and use the majority of the second level data group as the output low level of the tested chip.

[0011] The present invention also provides an electronic device, comprising: a memory storing a computer program; a processor communicating with the memory and executing the chip output level test method as described in any one of the above claims when calling the computer program; and a display communicating with the processor and the memory and used to display a GUI interaction interface related to the chip output level test method.

[0012] To achieve the above object, the present invention further provides a readable storage medium storing a computer program, which, when executed by a processor, implements any of the above chip output level testing methods.

[0013] To achieve the above object, the present invention further provides a computer program product, which, when executed by a processor, implements any of the above chip output level testing methods.

[0014] The chip output level testing method, system, electronic device, storage medium and program product provided by the present invention have the following beneficial effects:

[0015] The present invention provides a chip output level test method, comprising the following steps: for the data output pin of the tested chip, based on a preset sampling rate, collecting multiple level data; providing a preset threshold, taking the level data higher than the preset threshold as the first level data group, and taking the level data lower than the preset threshold as the second level data group; taking the mode of the first level data group as the output high level of the tested chip, and taking the mode of the second level data group as the output low level of the tested chip. With such a configuration, the present invention can collect multiple level data through high-frequency sampling even when the chip output level is unstable on the time axis, so as to capture the output high level and output low level of the tested chip, and then determine the output high level and output low level based on data statistics.

[0016] The present invention also provides a chip output level test system, and since the chip output level test system is used to execute any of the chip output level test methods described above, the chip output level test system can collect a plurality of level data through high-frequency sampling even when the chip output level is unstable on the time axis, thereby capturing the output high level and output low level of the tested chip, and then determining the output high level and output low level based on data statistics.

[0017] The present invention also provides an electronic device, which is used to perform any of the chip output level test methods described above. Therefore, the electronic device can collect multiple level data through high-frequency sampling even when the chip output level is unstable on the time axis, thereby capturing the output high level and output low level of the tested chip, and then determining the output high level and output low level based on data statistics.

[0018] The present invention also provides a readable storage medium, which is used to execute any of the chip output level test methods described above. Therefore, the readable storage medium can collect multiple level data through high-frequency sampling even when the chip output level is unstable on the time axis, thereby capturing the output high level and output low level of the tested chip, and then determining the output high level and output low level based on data statistics.

[0019] The present invention also provides a computer program product, which is used to execute any of the chip output level test methods described above. Therefore, the computer program product can collect multiple level data through high-frequency sampling even when the chip output level is unstable on the time axis, thereby capturing the output high level and output low level of the tested chip, and then determining the output high level and output low level based on data statistics. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a chip output level testing method according to an embodiment of the present invention.

[0021] Figure 2 A schematic diagram of the block structure of an electronic device provided by an embodiment of the present invention.

[0022] The accompanying drawings are denoted as follows:

[0023] 101 - processor; 102 - communication interface; 103 - memory; 104 - communication bus; 105 - display. DETAILED DESCRIPTION

[0024] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0025] It should be understood that when an element or layer is referred to as "on...", "connected to" other elements or layers, it can be directly on other elements or layers, connected to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on...", "directly connected to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be expressed as a second element, component, region, layer or part. Spatial relationship terms such as "under...", "below", "below", "above...", "above", "above", etc., can be used here for the convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the devices in use and operation. For example, if the device in the accompanying drawings is turned over, then, the elements or features described as "under...", "below", "below" will be oriented to be "on" other elements or features. The device can be oriented in addition (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly. The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "one" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "include" is used to determine the presence of features, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] The object of the present invention is to provide a chip output level testing method, system, electronic device, storage medium and program product to provide a solution for testing high and low levels when the output position of the test chip is unstable.

[0027] Please refer to Figure 1 , Figure 1 FIG. 1 is a flow chart of a chip output level testing method provided by an embodiment of the present invention. Figure 1As shown, to achieve the above purpose, the present invention provides a chip output level test method, comprising the following steps: for the data output pin of the tested chip, based on a preset sampling rate, collect multiple level data; provide a preset threshold, take the level data higher than the preset threshold as the first level data group, and take the level data lower than the preset threshold as the second level data group; take the mode of the first level data group as the output high level of the tested chip, and take the mode of the second level data group as the output low level of the tested chip. Based on this, it can be compared with the test specification to determine whether it is qualified.

[0028] With such a configuration, even when the chip output level is not stable on the time axis, the present invention can collect a plurality of level data through high frequency sampling, thereby being able to capture the output high level and output low level of the tested chip, and then determine the output high level and output low level based on data statistics. In an exemplary embodiment, the preset threshold value may be 1V.

[0029] The mode may be obtained by using a histogram. Specifically, the mode of the first level data group is used as the output high level of the chip under test, and the specific implementation method includes: drawing a first histogram according to the first level data group; and selecting the level data corresponding to the rectangle with the highest vertical axis height in the first histogram as the output high level.

[0030] Similarly, the mode of the second level data group is used as the output low level of the chip under test. The specific implementation method includes: drawing a second histogram according to the second level data group; and selecting the level data corresponding to the rectangle with the highest vertical axis height in the second histogram as the output low level.

[0031] In an exemplary embodiment, an API may be called to generate histograms respectively.

[0032] Furthermore, it also includes: providing a first preset range so that the first level data group becomes a subset of the first preset range; dividing the first preset range into a plurality of first intervals on average so that the data in the first level data group falls into the first intervals according to the numerical value; selecting the first interval in which the data in the first level data group falls into the largest number, and obtaining one of the average, median and mode of the numerical values ​​of the level data in the interval; and changing the numerical values ​​of the level data in the interval to one of the average, median and mode of the numerical values ​​of the level data in the interval. At this time, one of the average, median and mode of the numerical values ​​of the level data in the interval becomes the mode of the first level data group. With such a setting, it is possible to further simplify and accurately obtain the mode.

[0033] Similarly, it also includes: providing a second preset range so that the second level data group becomes a subset of the second preset range; dividing the second preset range into a plurality of second intervals on average so that the data in the second level data group fall into the second intervals according to the numerical value; selecting the second interval in which the data in the second level data group falls into the largest number, and obtaining one of the average, median and mode of the numerical values ​​of the level data in the interval; changing the numerical values ​​of the level data in the interval to one of the average, median and mode of the numerical values ​​of the level data in the interval. At this time, one of the average, median and mode of the numerical values ​​of the level data in the interval becomes the mode of the second level data group. With such a setting, it is possible to further simplify and accurately obtain the mode.

[0034] It should be noted that the chip under test is in a working state after configuration. In an exemplary embodiment, the present invention uses an ATE tester V93000 to test the output high and low levels of the chip. The prior art is based on the traditional solution of using the PPMU or boardADC test of the digital board. The prior art can only test the output high and low levels to be fixed on the time axis, and then configure the chip output through runpattern, stop at the high level position or low level position of the chip output and then measure. If the chip is configured, the high and low levels of the output are not fixed on the time axis, and cannot be measured. The present invention adopts the digitizer of the analog board MBAV8+ to capture the output voltage of the chip. First, the chip output is configured through the pattern, and the digitizer of MBAV8+ is started to continuously sample the voltage of multiple points (the VHF digitizer can take up to 14M points), and the background selects the low level voltage VOL and the high level VOH. For example, the data output position of a network interface chip is unstable, and VOH and VOL need to be tested. The data output pin of the chip is cut to the VHFdigitizer of MBAV8+ through a relay, and a sampling rate of 180Msps is used to collect up to 14M points (the actual number of points can be reasonably adjusted during debugging to reduce calculation time). The collected data is the output voltage of the chip data pin, and then the collected data is split according to the approximate range of low level and high level, for example, those below 1V are divided into group A, and those above 1V are divided into group B, and then the API is called to make histograms respectively, and the voltages with the most points in groups A and B are selected as VOL and VOH, and then compared with the spec of the test specification to determine whether they are qualified.

[0035] The present invention also provides a chip output level test system, comprising: a sampling module, used to collect multiple level data for the data output pin of the tested chip based on a preset sampling rate; a processing module, used to provide a preset threshold, use the level data higher than the preset threshold as a first level data group, use the level data lower than the preset threshold as a second level data group, and use the majority of the first level data group as the output high level of the tested chip, and use the majority of the second level data group as the output low level of the tested chip.

[0036] The present invention also provides a chip output level test system, and since the chip output level test system is used to execute any of the chip output level test methods described above, the chip output level test system can collect a plurality of level data through high-frequency sampling even when the chip output level is unstable on the time axis, thereby capturing the output high level and output low level of the tested chip, and then determining the output high level and output low level based on data statistics.

[0037] Since the chip output level test system provided by the present invention and the chip output level test method described above belong to the same inventive concept, the electronic device provided by the present invention has all the advantages of the chip output level test method described above, so the beneficial effects of the electronic device provided by the present invention will not be described one by one here.

[0038] To achieve the above object, the present invention also provides an electronic device, please refer to Figure 2 , Figure 2 FIG. 1 is a block diagram of an electronic device provided by an embodiment of the present invention. Figure 2 As shown, the electronic device includes:

[0039] A memory 103 storing a computer program;

[0040] A processor 101 is connected to the memory for communication, and executes any one of the above chip output level testing methods when calling the computer program;

[0041] The display 105 is connected to the processor and the memory for displaying a GUI interaction interface related to the chip output level test method.

[0042] like Figure 2As shown, the electronic device also includes a communication interface 102 and a communication bus 104, wherein the processor 101, the communication interface 102, and the memory 103 communicate with each other through the communication bus 104. The communication bus 104 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus 104 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The communication interface 102 is used for communication between the above-mentioned electronic device and other devices.

[0043] The processor 101 referred to in the present invention may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor 101 is the control center of the electronic device, and various interfaces and lines are used to connect various parts of the entire electronic device.

[0044] The memory 103 may be used to store the computer program. The processor 101 implements various functions of the electronic device by running or executing the computer program stored in the memory 103 and calling the data stored in the memory 103 .

[0045] The memory 103 may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0046] Since the electronic device is used to perform any of the chip output level test methods described above, the electronic device can collect multiple level data through high-frequency sampling even when the chip output level is unstable on the time axis, thereby capturing the output high level and output low level of the tested chip, and then determining the output high level and output low level based on data statistics.

[0047] Since the electronic device provided by the present invention and the chip output level testing method described above belong to the same inventive concept, the electronic device provided by the present invention has all the advantages of the chip output level testing method described above, so the beneficial effects of the electronic device provided by the present invention will not be described one by one here.

[0048] To achieve the above object, the present invention provides a readable storage medium storing a computer program, which implements the chip output level test method as described in any one of the above when executed by a processor. Since the readable storage medium is used to execute any one of the chip output level test methods described above. Therefore, the readable storage medium can collect multiple level data through high-frequency sampling even when the chip output level is unstable on the time axis, based on which the output high level and output low level of the tested chip can be captured, and then the output high level and output low level can be determined based on data statistics.

[0049] Since the readable storage medium provided by the present invention and the chip output level testing method described above belong to the same inventive concept, the readable storage medium provided by the present invention has all the advantages of the chip output level testing method described above, so the beneficial effects of the readable storage medium provided by the present invention will not be described one by one here.

[0050] The readable storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer hard disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this article, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, a device or a device or used in combination with it.

[0051] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program codes. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0052] The present invention also provides a computer program product, which implements any of the above chip output level testing methods when executed by a processor.

[0053] The present invention also provides a computer program product, which is used to execute any of the chip output level test methods described above. Therefore, the computer program product can collect multiple level data through high-frequency sampling even when the chip output level is unstable on the time axis, thereby capturing the output high level and output low level of the tested chip, and then determining the output high level and output low level based on data statistics.

[0054] Since the computer program product provided by the present invention and the chip output level testing method described above belong to the same inventive concept, the computer program product provided by the present invention has all the advantages of the chip output level testing method described above, and the beneficial effects of the computer program product provided by the present invention will not be described one by one here.

[0055] It should be noted that the various embodiments in this specification are described in a progressive manner, and any embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0056] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0057] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0058] It should also be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A chip output level testing method, characterized in that: The following steps are involved: For the data output pins of the chip under test, multiple level data are collected based on a preset sampling rate; Providing a preset threshold, taking the level data higher than the preset threshold as a first level data group, and taking the level data lower than the preset threshold as a second level data group; The majority of the first level data group is used as the output high level of the chip under test, and the majority of the second level data group is used as the output low level of the chip under test.

2. The chip output level testing method according to claim 1, characterized in that: The method of using the mode of the first level data group as the output high level of the chip under test includes: According to the first level data group, drawing a first histogram; The level data corresponding to the rectangle with the highest vertical axis height in the first histogram is selected as the output high level.

3. The chip output level testing method according to claim 1, characterized in that: The mode of the second level data group is used as the output low level of the chip under test, and the specific implementation method includes: According to the second level data group, drawing a second histogram; The level data corresponding to the rectangle with the highest vertical axis height in the second histogram is selected as the output low level.

4. The chip output level testing method according to claim 1, characterized in that: Also includes: Providing a first preset range, so that the first level data group becomes a subset of the first preset range; Divide the first preset range into a plurality of first intervals evenly, so that the data in the first level data group respectively fall into the first intervals according to the value; Select the first interval in which the data in the first level data group falls into the largest number, and obtain one of the mean, median and mode of the values ​​of the level data in the interval; The values ​​of the level data in the interval are all changed to one of the average, median and mode of the values ​​of the level data in the interval.

5. The chip output level testing method according to claim 1, characterized in that: Also includes: Providing a second preset range so that the second level data group becomes a subset of the second preset range; Divide the second preset range into a plurality of second intervals evenly, so that the data in the second level data group respectively fall into the second intervals according to the value; Select the second interval in which the data in the second level data group falls into the largest number, and obtain one of the mean, median and mode of the values ​​of the level data in the interval; The values ​​of the level data in the interval are all changed to one of the average, median and mode of the values ​​of the level data in the interval.

6. The chip output level testing method according to claim 1, characterized in that: The chip under test is in a configured working state.

7. A chip output level test system, applied to the chip output level test method as claimed in any one of claims 1 to 6, characterized in that: include: The sampling module is used to collect multiple level data based on a preset sampling rate from the data output pin of the chip under test; A processing module is used to provide a preset threshold, use the level data higher than the preset threshold as a first level data group, use the level data lower than the preset threshold as a second level data group, and use the mode of the first level data group as the output high level of the tested chip, and use the mode of the second level data group as the output low level of the tested chip.

8. An electronic device, characterized in that: The electronic device comprises: a memory storing a computer program; a processor, communicatively connected to the memory, and executing the chip output level testing method according to any one of claims 1 to 6 when calling the computer program; A display is communicatively connected with the processor and the memory, and is used to display a GUI interaction interface related to the chip output level test method.

9. A readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the chip output level testing method according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that When the computer program product is executed by a processor, the chip output level testing method according to any one of claims 1 to 6 is implemented.

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