LED chip defect detection method, device and equipment and storage medium

Abstract

The invention relates to the technical field of defect detection, in particular to an LED chip defect detection method, device and equipment and a storage medium. The method comprises the following steps: obtaining structure data of an LED chip sample; performing chip electrical connection on the LED chip based on the structure data of the LED chip sample to generate chip electrical connection data; performing electrical connection key level confirmation on the chip electrical connection data, and performing three-dimensional reconstruction on the confirmed electrical connection key level to obtain three-dimensional structure data of an electrical connection metallization layer; dividing the three-dimensional structure data of the metallization layer into metallization layer external three-dimensional structure data and metallization layer internal three-dimensional structure data; and carrying out temperature equalization defect detection on the external three-dimensional structure data of the metallization layer to generate metallization layer surface defect detection data. According to the invention, automatic three-dimensional structure reconstruction, comprehensive defect detection and intelligent prediction and evaluation are realized, and the accuracy of hierarchical defect detection of fine materials in the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of defect detection technology, and in particular to an LED chip defect detection method, device, equipment and storage medium. Background Art

[0002] Initially, defect detection of LED chips mainly relied on manual inspection. Although this method is simple, it is inefficient and easily affected by human factors, resulting in poor accuracy and consistency of detection results. With the development of the LED industry, manual inspection cannot meet the needs of high-precision and mass production, and visual-based automatic inspection technology has gradually emerged. After entering the 21st century, the introduction of computer vision technology and image processing algorithms has gradually automated LED chip defect detection. The initial detection system used a simple image acquisition and processing method, which was able to detect common surface defects such as cracks, bubbles, scratches, etc., but had poor recognition ability for subtle defects. With the development of deep learning and artificial intelligence technology, defect detection methods based on convolutional neural networks (CNNs) have gradually become mainstream. However, traditional technologies mostly focus on chip surface defect detection, while the detection of the internal metallization layer is difficult due to its smallness, concealment and complexity, resulting in many existing technologies failing to involve or not having sufficient processing capabilities. At the same time, the metallization layer is usually composed of a thin metal film with a small thickness and a smooth surface. Traditional detection methods such as surface scanning and optical detection are difficult to accurately identify tiny defects in the metal layer, which leads to low accuracy in chip subtle defect detection. Summary of the invention

[0003] Based on this, it is necessary to provide a method, device, equipment and storage medium for LED chip defect detection to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for detecting defects in LED chips is provided, the method comprising the following steps: Step S1: Acquire the structural data of the LED chip sample; perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; confirm the electrical connection key level of the chip electrical connection data, and perform three-dimensional reconstruction on the confirmed electrical connection key level to obtain three-dimensional structural data of the electrical connection metallization layer; Step S2: dividing the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; performing particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrating the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; Step S3: Model training is performed on the electrical connection metallization layer defect detection data to generate an LED chip electrical connection defect prediction model; the three-dimensional structure data of the electrical connection metallization layer is imported into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data; Step S4: Evaluate the chip circuit connection stability of the LED chip according to the electrical connection defect prediction data to generate chip circuit connection stability evaluation data; visualize the chip circuit connection stability evaluation data to generate an LED chip circuit defect detection report.

[0005] The present invention can accurately capture the metallization layer structure of the chip electrical connection by acquiring the structural data of the LED chip sample and performing three-dimensional reconstruction, ensuring the comprehensiveness and accuracy of the detection. This step provides reliable basic data for subsequent defect detection, especially when dealing with complex electrical connection metallization layers, the three-dimensional reconstruction technology improves the accuracy of detection. The three-dimensional structural data of the metallization layer is divided into external and internal structures, and different defect detection technologies (temperature balance and particle group image) are applied in a targeted manner to make the detection more targeted and accurate. External detection focuses on surface defects, while internal detection deals with hidden defects in the metallization layer to ensure all-round defect detection, especially to identify subtle internal problems. By training the defect detection data and generating a prediction model for the electrical connection defects of the LED chip, potential defects can be predicted automatically in actual detection. By combining the three-dimensional structural data with the prediction model, potential problems of the chip electrical connection can be identified in advance, which significantly improves the efficiency and accuracy of detection and reduces errors caused by human intervention. By evaluating the circuit connection stability of LED chips based on the electrical connection defect prediction data, the chip stability can be understood in real time, and a circuit defect detection report can be generated through data visualization to help engineers quickly identify problems and make adjustments. This step not only improves the efficiency of fault diagnosis, but also provides a scientific basis for chip quality control and promotes chip production and application optimization. Therefore, the present invention improves the accuracy of fine material level defect detection inside the chip through automated three-dimensional structure reconstruction, comprehensive defect detection, intelligent prediction and evaluation.

[0006] Preferably, step S1 comprises the following steps: Step S11: using an electron microscope to obtain structural data of an LED chip sample; Step S12: performing chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; Step S13: using the chip electrical connection data to perform structural screening on the structural data of the LED chip sample to obtain the electrical connection structural data of the LED chip sample; Step S14: confirming the electrical connection key level of the electrical connection structure data of the LED chip sample, and performing three-dimensional reconstruction on the confirmed electrical connection key level to obtain three-dimensional structure data of the electrical connection metallization layer.

[0007] The present invention obtains high-resolution structural data of LED chip samples through an electron microscope, ensuring that detailed and accurate structural information is obtained at the microscopic level, laying a solid foundation for subsequent analysis. By electrically connecting the chip, the flow of current inside the chip can be understood to ensure that the electrical performance of the chip is within the expected range, which provides key data support for the design and optimization of the performance of the LED chip. Screening the electrical connection structure of the LED chip can eliminate unqualified or unoptimized connection structures, ensure that the performance of the chip is maximized, and improve the yield rate of the production process. By three-dimensionally reconstructing the electrical connection metallization layer, the spatial distribution of the chip structure can be accurately presented, which is helpful for further design, adjustment and optimization of the chip. At the design level, this helps to improve the reliability, durability and manufacturing accuracy of the LED chip.

[0008] Preferably, step S14 further includes: Performing energy spectrum analysis on the electrical connection structure data of the LED chip sample to generate electrical connection energy spectrum data; performing elemental composition analysis on the electrical connection structure data of the LED chip sample using the electrical connection energy spectrum data, and when the elemental composition is analyzed, marking the corresponding structure as an electrical connection metal layer; Performing element distribution analysis on the electrical connection metal layer to generate element distribution data of the electrical connection metal layer; identifying key metal layers of the electrical connection metal layer according to the element distribution data of the electrical connection metal layer to obtain key metal layers of the electrical connection; The electrical connection structure data of the LED chip sample is three-dimensionally reconstructed based on the electrical connection key metal layer to generate the three-dimensional structure data of the metallization layer.

[0009] The present invention can effectively obtain the energy distribution and chemical composition of each material in the chip by performing energy spectrum analysis on the electrical connection structure data of the LED chip sample, which provides an accurate physical basis for subsequent analysis, making the element composition analysis at different levels and regions more efficient and accurate. Performing element composition analysis on the electrical connection structure of the LED chip not only reveals the distribution of various elements in the chip, but also marks the electrical connection metal layer. This provides key data support for subsequent design and fault diagnosis, and helps to improve the stability and reliability of the chip in terms of electrical performance. Analyzing the element distribution of the electrical connection metal layer can identify the uniformity and integrity of the metal layer, ensure the quality of the metallization layer, and avoid electrical performance instability or premature failure of the chip due to defects in the metallization layer. Through the identification of the key metal layer, the metal layer that is critical to the electrical connection of the chip can be accurately found. This step helps to locate the weak links in the chip structure that affect the performance and provides a clear direction for the design optimization of the chip. Based on the identification of the key metal layer of the electrical connection, three-dimensional reconstruction is performed to generate three-dimensional structural data of the metallization layer, which can help engineers intuitively understand the internal and external structures of the chip, facilitate the optimization of the electrical connection design, and improve the performance and reliability of the chip.

[0010] Preferably, step S2 comprises the following steps: Step S21: dividing the three-dimensional structure data of the metallization layer into external three-dimensional structure data of the metallization layer and internal three-dimensional structure data of the metallization layer based on the thickness of the three-dimensional structure of the metallization layer; Step S22: using an infrared imaging sensor to analyze the surface temperature distribution of the metallization layer of the LED chip to generate the surface temperature distribution data of the metallization layer of the chip; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer according to the surface temperature distribution data of the metallization layer of the chip to generate the surface defect detection data of the metallization layer; Step S23: using particle pulse technology to perform high-speed particle emission on the LED chip to obtain high-speed particle pulse data; using the high-speed particle pulse data to perform particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; Step S24: integrating the metallization layer surface defect detection data and the metallization layer internal defect detection data to obtain electrical connection metallization layer defect detection data.

[0011] The present invention provides a more detailed perspective for subsequent defect detection and analysis by dividing the three-dimensional structural data of the metallization layer into external and internal data according to thickness, which helps to accurately identify the structural characteristics of different levels, solve different external and internal problems in a targeted manner, and improve the accuracy and efficiency of the analysis. By using an infrared imaging sensor to analyze the surface temperature distribution of the chip metallization layer, abnormal temperature areas can be quickly found. These anomalies indicate uniformity problems or other potential defects in the metallization layer. Combined with temperature balance defect detection, it is possible to identify places that cause thermal damage or unstable electrical performance at an early stage, thereby improving the quality control and thermal management capabilities of the product. By emitting the chip using high-speed particle pulse technology, tiny defects such as voids and cracks inside the metallization layer can be effectively identified. Traditional methods cannot detect these hidden structural problems. Particle pulse data provides a more accurate and non-destructive detection method, which helps to optimize the internal structure of the metallization layer and improve the long-term stability and reliability of the chip. By integrating the defect detection data on the surface and inside of the metallization layer, comprehensive electrical connection metallization layer defect detection data is obtained. This comprehensive detection method can analyze from multiple dimensions and levels, providing a comprehensive fault detection view, which helps to improve the yield rate in the chip manufacturing process and reduce potential performance problems.

[0012] Preferably, step S22 includes the following steps: Step S221: using an infrared imaging sensor to collect a surface temperature image of a metallization layer of an LED chip to obtain a surface temperature image of the metallization layer; Step S222: performing image preprocessing on the metallization layer surface temperature image to generate a standard metallization layer surface temperature image, wherein the image preprocessing includes image correction and image denoising; performing image data conversion on the standard metallization layer surface temperature image to generate metallization layer temperature information data; Step S223: mapping the metallization layer temperature information data to a temperature distribution to generate chip metallization layer surface temperature distribution data; calculating the temperature difference of adjacent pixels of the standard metallization layer surface temperature image according to the chip metallization layer surface temperature distribution data to obtain the temperature difference of each group of adjacent pixels; Step S224: Analyze the uniformity of the temperature distribution data on the surface of the chip metallization layer through the temperature difference of each group of adjacent pixels to generate the temperature uniformity data of the chip metallization layer surface; use the temperature uniformity data of the chip metallization layer surface to perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate the metallization layer surface defect detection data.

[0013] The present invention collects the surface temperature image of the chip metallization layer through an infrared imaging sensor, and can provide high-resolution temperature data. This precise temperature image collection provides high-quality basic data for subsequent defect detection, ensuring the accuracy and reliability of the analysis results. Image correction and denoising processing can eliminate errors caused by imaging equipment, environmental interference or data damage, and generate standardized temperature images. This step ensures the consistency and clarity of the input data and provides accurate temperature information data for subsequent analysis. Through image data conversion and temperature distribution mapping, the temperature information of the chip metallization layer can be extracted, and detailed temperature distribution data can be generated. These data are crucial for evaluating the thermal management performance and uniformity of the metallization layer, and provide a clear basis for defect detection. By calculating the temperature difference of adjacent pixels, the uneven area of ​​the surface temperature of the chip metallization layer can be identified. Temperature differences are often potential indicators of defects in the metallization layer, such as weak areas, heat source concentration areas or material unevenness. This process helps to discover and locate thermal management problems at an early stage. By analyzing the temperature uniformity, it is possible to comprehensively evaluate whether the temperature distribution on the surface of the metallization layer is uniform. Temperature uniformity analysis can help identify irregular thermal patterns and locate temperature uniformity defect areas, which is important for improving the thermal stability of LED chips and avoiding overheating problems. Temperature uniformity defect detection can not only accurately locate surface defect areas, but also provide data support for subsequent optimization designs. By identifying surface defects in the metallization layer, it helps to improve the quality of the chip, extend its service life, and ensure its stable electrical performance.

[0014] Preferably, step S23 includes the following steps: Step S231: using particle pulse technology to perform high-speed particle emission on the LED chip to obtain high-speed particle pulse data; Step S232: performing particle signal feature recognition on the high-speed particle pulse data to generate particle signal feature data; performing particle propagation path analysis on the high-speed particle pulse data according to the particle signal feature data to generate particle propagation path data; Step S233: Structural mapping is performed on the particle propagation path data and the three-dimensional structure data inside the metallization layer to generate particle structure mapping data inside the metallization layer; particle reflection and scattering analysis is performed on the particle structure mapping data inside the metallization layer to generate particle group image data of the metallization layer; Step S234: quantify the uniformity of the particle pulse signal of the metallization layer particle group image data to generate a particle pulse signal uniformity value; perform particle internal defect detection on the internal three-dimensional structure data of the metallization layer based on the particle pulse signal uniformity value to generate internal defect detection data of the metallization layer.

[0015] The present invention uses high-speed particle emission through particle pulse technology to obtain data inside the metallization layer of the chip. This non-invasive method can penetrate into the material and detect tiny defects that cannot be found by traditional technology. Through high-speed particle pulse data, higher-precision chip internal structure analysis can be achieved. Feature recognition of particle signals can help extract key information, thereby accurately analyzing the propagation path of particles. The generation of particle propagation path data provides detailed particle flow trajectories for subsequent analysis, allowing researchers to gain an in-depth understanding of how particles propagate inside the chip and identify potential sources of defects. By mapping the particle propagation path data with the three-dimensional structure data inside the metallization layer, the propagation route of the particles can be accurately calibrated in the three-dimensional space inside the chip. This process provides visualization support for subsequent particle reflection and scattering analysis, helping to reveal the physical properties and potential problem areas inside the chip. Particle reflection and scattering analysis can detect tiny defects inside the metallization layer, such as cracks, voids or uneven structures. This process can reveal the heterogeneity inside the metallization layer, promptly discover potential problems such as material unevenness or electrical connections, and help improve the long-term reliability and stability of the chip. Particle pulse signal uniformity quantification can quantify the uniformity of particle propagation and analyze the impact of internal defect areas, which helps to accurately evaluate the quality and uniformity of the metallization layer and promptly discover defects that lead to thermal runaway, electrical short circuits or other performance problems. Internal defect detection of the metallization layer based on the particle pulse signal uniformity value can accurately identify defective areas inside the chip that affect performance. This process provides strong data support for chip quality control, helps avoid defective products during the production process, and improves product reliability.

[0016] Preferably, step S3 comprises the following steps: Step S31: extracting defect features from the electrical connection metallization layer defect detection data to obtain metallization layer defect feature data; dividing the metallization layer defect feature data into data sets to generate a model training set and a model test set; Step S32: using a support vector machine algorithm to perform model training on the model training set to generate an LED chip electrical connection defect prediction pre-model; using a model test set to perform model optimization iteration on the LED chip electrical connection defect prediction pre-model, thereby generating an LED chip electrical connection defect prediction model; Step S33: importing the three-dimensional structure data of the electrical connection metallization layer into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data.

[0017] The present invention can extract the most meaningful features for defect diagnosis from a large amount of data by extracting features from the defect detection data of the electrical connection metallization layer. This data processing method can effectively reduce noise and improve the accuracy of the prediction model. At the same time, the generalization ability and reliability of the model are ensured by dividing the data set (training set and test set), so that the model can perform stably under different data environments. The support vector machine algorithm can provide accurate predictions for the electrical connection defects of LED chips with its excellent classification ability and powerful performance in high-dimensional data space. In the model training stage, SVM can find the best classification hyperplane based on the feature data in the training set, thereby effectively distinguishing normal and defective electrical connections. The optimization iteration of the model further improves the accuracy of the prediction and adapts it to more complex defect modes. By importing the three-dimensional structure data of the electrical connection metallization layer into the trained defect prediction model, real-time defect prediction can be performed, which not only provides reliable support for troubleshooting in the production process, but also can discover potential problems in advance in the chip design stage, reducing the cost and time of later repairs. By continuously iterating during the model optimization process, the algorithm can learn more accurate defect prediction patterns. This intelligent optimization not only improves the prediction accuracy, but also enables the model to continuously adapt to new data and defect types, enhancing the system's adaptability and flexibility. By predicting electrical connection defects in advance, defective products in the LED chip manufacturing process can be discovered and eliminated at an early stage. This process greatly reduces the rework and scrap rate caused by defects, while also improving production efficiency and product quality, ultimately reducing manufacturing costs. Accurate defect prediction can avoid performance failures in chips in actual applications and improve their long-term reliability. Especially in high-demand application scenarios, such as communications, lighting and other fields, avoiding electrical connection defects is crucial to ensuring stable system operation.

[0018] In this specification, a LED chip defect detection device is provided, which is used to perform the above-mentioned LED chip defect detection method. The LED chip defect detection device includes: A three-dimensional reconstruction module is used to obtain the structural data of the LED chip sample; based on the structural data of the LED chip sample, the LED chip is electrically connected to generate chip electrical connection data; the electrical connection key level of the chip electrical connection data is confirmed, and the confirmed electrical connection key level is reconstructed in three dimensions to obtain the three-dimensional structural data of the electrical connection metallization layer; The defect detection module is used to divide the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; perform particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; The defect prediction module is used to perform model training on the defect detection data of the electrical connection metallization layer to generate an electrical connection defect prediction model for the LED chip; the three-dimensional structure data of the electrical connection metallization layer is imported into the electrical connection defect prediction model for the LED chip to perform chip electrical connection defect prediction and generate electrical connection defect prediction data; The circuit stability evaluation module is used to evaluate the chip circuit connection stability of the LED chip based on the electrical connection defect prediction data, and generate chip circuit connection stability evaluation data; the chip circuit connection stability evaluation data is visualized to generate an LED chip circuit defect detection report.

[0019] The present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the above-mentioned LED chip defect detection method is implemented.

[0020] The present invention also provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned LED chip defect detection method is implemented.

[0021] The beneficial effect of the present invention is that the structural data of the LED chip is accurately obtained through the three-dimensional reconstruction module, and the electrical connection of the chip is further analyzed, so that the integrity of the electrical connection inside the chip can be better understood, and solid data support can be provided for subsequent defect detection and stability evaluation. By dividing the metallization layer into external and internal data, and performing temperature balance defect detection and particle group image defect detection respectively, the potential defects on the surface and inside are effectively identified, the comprehensiveness and accuracy of defect detection are improved, and the early detection of problems in the chip production process is ensured. The machine learning model is used to train the detection data to generate a prediction model for the electrical connection defects of the LED chip, so that the system can not only perform real-time defect detection, but also predict the electrical connection problems that will occur in the future, so as to give early warning and carry out targeted optimization. Through the electrical connection defect prediction data, the stability evaluation of the circuit connection of the LED chip is carried out, which can accurately reflect the risks of the circuit, predict the stability of the circuit in advance, and provide guarantee for the long-term stable operation of the chip. The system presents the evaluation results through data visualization, generates a detailed circuit defect detection report, helps engineers quickly understand the quality and stability of the chip, and provides data support for subsequent improvements. Therefore, the present invention improves the accuracy of detecting subtle material-level defects inside the chip through automated three-dimensional structure reconstruction, comprehensive defect detection, and intelligent prediction and evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the steps of a method for detecting defects in LED chips; Figure 2 for Figure 1 Detailed implementation steps of step S2 in the flowchart; Figure 3 for Figure 1 Detailed implementation steps of step S3 in FIG. The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0023] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0025] It should be understood that although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit, and the term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0026] To achieve this, please refer to Figures 1 to 3 , a method for detecting defects in LED chips, the method comprising the following steps: Step S1: Acquire the structural data of the LED chip sample; perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; confirm the electrical connection key level of the chip electrical connection data, and perform three-dimensional reconstruction on the confirmed electrical connection key level to obtain three-dimensional structural data of the electrical connection metallization layer; Step S2: dividing the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; performing particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrating the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; Step S3: Model training is performed on the electrical connection metallization layer defect detection data to generate an LED chip electrical connection defect prediction model; the three-dimensional structure data of the electrical connection metallization layer is imported into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data; Step S4: Evaluate the chip circuit connection stability of the LED chip according to the electrical connection defect prediction data to generate chip circuit connection stability evaluation data; visualize the chip circuit connection stability evaluation data to generate an LED chip circuit defect detection report.

[0027] The present invention can accurately capture the metallization layer structure of the chip electrical connection by acquiring the structural data of the LED chip sample and performing three-dimensional reconstruction, ensuring the comprehensiveness and accuracy of the detection. This step provides reliable basic data for subsequent defect detection, especially when dealing with complex electrical connection metallization layers, the three-dimensional reconstruction technology improves the accuracy of detection. The three-dimensional structural data of the metallization layer is divided into external and internal structures, and different defect detection technologies (temperature balance and particle group image) are applied in a targeted manner to make the detection more targeted and accurate. External detection focuses on surface defects, while internal detection deals with hidden defects in the metallization layer to ensure all-round defect detection, especially to identify subtle internal problems. By training the defect detection data and generating a prediction model for the electrical connection defects of the LED chip, potential defects can be predicted automatically in actual detection. By combining the three-dimensional structural data with the prediction model, potential problems of the chip electrical connection can be identified in advance, which significantly improves the efficiency and accuracy of detection and reduces errors caused by human intervention. By evaluating the circuit connection stability of LED chips based on the electrical connection defect prediction data, the chip stability can be understood in real time, and a circuit defect detection report can be generated through data visualization to help engineers quickly identify problems and make adjustments. This step not only improves the efficiency of fault diagnosis, but also provides a scientific basis for chip quality control and promotes chip production and application optimization. Therefore, the present invention improves the accuracy of fine material level defect detection inside the chip through automated three-dimensional structure reconstruction, comprehensive defect detection, intelligent prediction and evaluation.

[0028] In the embodiment of the present invention, reference Figure 1 The above is a schematic diagram of the steps of a method for detecting defects in an LED chip according to the present invention. In this example, the method for detecting defects in an LED chip includes the following steps: Step S1: Acquire the structural data of the LED chip sample; perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; confirm the electrical connection key level of the chip electrical connection data, and perform three-dimensional reconstruction on the confirmed electrical connection key level to obtain three-dimensional structural data of the electrical connection metallization layer; In an embodiment of the present invention, the physical structure data of the LED chip is obtained from the LED chip manufacturer or by using a scanning device. The microstructure image of the chip can be obtained by using high-precision equipment such as an electron microscope and a scanning electron microscope (SEM). Through image processing technology, these data are converted into a digital 3D structure model for subsequent analysis. According to the obtained 3D structure data, a circuit design software (such as Cadence, Altium Designer, etc.) is used to simulate the electrical connection. By connecting the elements such as the pins, pads, and wires of the chip, a virtual model of the electrical connection is formed. During the electrical connection process, it is necessary to ensure that the power supply, signal pins, and ground wires of the chip are correctly connected to ensure the normal operation of the chip. Based on the simulation of the electrical connection of the chip, the connection data is extracted to form an electrical connection data set, including current flow direction, voltage distribution, signal transmission path, etc., which can be further converted into circuit board design data or directly used for electrical verification in the manufacturing process. In the electrical connection data, key layers, such as power layers, signal layers, and ground layers, are identified, and their connection relationships and stability are confirmed. Each key layer is evaluated to ensure that it meets electrical performance requirements, such as current carrying capacity and signal integrity. Use 3D modeling software (such as SolidWorks, ANSYS, etc.) to perform 3D reconstruction of key layers based on electrical connection data. In this step, ensure that the reconstructed 3D structural model accurately reflects the actual situation of the electrical connection and takes into account factors such as current flow direction and thermal effects. Based on the 3D reconstructed data, extract the geometric information of the metallization layer, including metal lines, welding points, connection channels, etc., and generate the final 3D structural data of the electrical connection metallization layer for further analysis or manufacturing process optimization.

[0029] Step S2: dividing the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; performing particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrating the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; In an embodiment of the present invention, the overall three-dimensional structural data of the metallization layer is divided by using three-dimensional modeling and data segmentation tools (such as CAD software, MeshLab, etc.). According to the design and physical structure of the chip, the external and internal areas of the metallization layer are distinguished. The external area is usually the surface of the metallization layer, mainly involving the contact surface of the electrical connection. The internal area refers to the conductive lines and connection channels inside the metallization layer, involving the current path and signal transmission inside the chip. Thermal analysis tools (such as ANSYS Thermal, COMSOL, etc.) are used to simulate the thermal distribution to identify the temperature imbalance areas on the surface of the metallization layer. These areas are caused by heat concentration due to poor connection or material defects, affecting the long-term reliability of the chip. Based on the thermal simulation results, the temperature balance difference is analyzed to detect the hot spot area. Potential surface defects such as microcracks, bubbles, short circuits, etc. are identified by abnormal patterns of temperature changes. The position, size, properties, etc. of the detected surface defects are recorded to form surface defect detection data of the metallization layer. The particle swarm optimization (PSO) algorithm is applied to internal defect detection. This method can identify tiny defects in the three-dimensional structural data by simulating the optimization behavior of the particle swarm in the search space. In the internal three-dimensional structure of the metallization layer, the particle swarm algorithm scans each area to identify potential defects, such as microcracks, voids, uneven thickness of the conductive layer, etc. The internal three-dimensional structure data can be obtained by using technologies such as CT scanning or X-ray imaging to further verify the test results. The spatial position, size, morphology, etc. of all internal defects are recorded to generate internal defect detection data of the metallization layer. The surface and internal defect detection data of the metallization layer are unified and integrated. The detection results of different data sources can be integrated into a unified defect data set through data fusion techniques such as weighted averaging and principal component analysis (PCA). Based on the integrated defect data, the overall quality of the metallization layer is analyzed, including indicators such as the distribution, size, and number of surface and internal defects. This will help evaluate the reliability and durability of the electrical connection and generate complete electrical connection metallization layer defect detection data, including information on all surface and internal defects, for reference in subsequent optimization and manufacturing processes.

[0030] Step S3: Model training is performed on the electrical connection metallization layer defect detection data to generate an LED chip electrical connection defect prediction model; the three-dimensional structure data of the electrical connection metallization layer is imported into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data; In an embodiment of the present invention, the electrical connection metallization layer defect detection data is preprocessed, including data cleaning, standardization and feature engineering. Irrelevant features can be removed and missing values ​​can be filled to ensure the integrity and consistency of the data. Important features such as the type, location, size, morphology, depth, etc. of the defect can be extracted from the defect detection data. Feature selection techniques such as correlation analysis, principal component analysis (PCA), etc. can be used to extract key features related to electrical connection defects. An appropriate machine learning or deep learning model is selected to train the defect prediction model. Commonly used models include: Support vector machine (SVM): suitable for smaller data sets and can effectively classify different types of defects. Decision trees and random forests can handle nonlinear features, are suitable for larger data sets, and have good prediction accuracy. Neural networks, especially convolutional neural networks (CNNs), are suitable for processing structured data and image data, and can capture complex patterns. The model is trained using the electrical connection metallization layer defect detection data, and cross-validation is performed to prevent overfitting. The optimal model is selected by comparing the performance of different models (such as accuracy, precision, recall, etc.). After training and verification, a LED chip electrical connection defect prediction model is generated. The model can predict defects in electrical connections based on the input metallization layer data. The three-dimensional structure data of the metallization layer is used as input and imported into the trained LED chip electrical connection defect prediction model. The data can be 3D mesh data, surface texture data or other structured data. The model predicts electrical connection defects based on the input three-dimensional structure data and identifies potential defect areas and problems. The prediction results include the location, type, and impact of the defects. Based on the model output, electrical connection defect prediction data is generated. The data includes detailed information for each predicted defect, such as the predicted defect type, impact, and risk level of electrical performance degradation. The accuracy of the prediction results is verified through actual testing. The prediction results can be compared with the actual defects to evaluate the effectiveness and accuracy of the model. If necessary, the model can be further optimized. As more samples and data are accumulated, the prediction model can be updated regularly to improve its prediction accuracy and robustness.

[0031] Step S4: Evaluate the chip circuit connection stability of the LED chip according to the electrical connection defect prediction data to generate chip circuit connection stability evaluation data; visualize the chip circuit connection stability evaluation data to generate an LED chip circuit defect detection report.

[0032] In an embodiment of the present invention, the stability evaluation target of the chip circuit connection is determined according to the electrical connection defect prediction data. The main goal of the evaluation is to determine whether the electrical connection meets the requirements of stable operation and avoid chip failure due to connection defects. Based on the defect prediction data and the electrical connection model, a stability evaluation model is established. The stability of the connection can be evaluated using engineering mechanics analysis, material science principles, and standards in electrical engineering. For example, the stability of the current path, the integrity of signal transmission, and the impact of thermal effects on the connection are evaluated. During the evaluation process, finite element analysis (FEA) can be used to simulate the response of the chip circuit under different working conditions, including current load, thermal effects, mechanical stress, etc. Analyze whether there is an overheating area in the electrical connection and predict failures caused by overheating. Evaluate whether the connection part is affected by stress or vibration, resulting in poor contact or breakage. Analyze whether the circuit can withstand long-term working conditions such as current and voltage fluctuations based on the integrity of the electrical connection. Based on the above model and evaluation indicators, chip circuit connection stability evaluation data is generated. The data should contain information such as stability score, predicted failure probability, and influencing factor analysis for each connection point. Select appropriate data visualization tools, such as MATLAB, Tableau, Power BI, etc., to clearly display the stability evaluation data. You can choose 2D or 3D visualization to present the stability information of electrical connections. Allow users to interact with the data, such as viewing detailed information on a specific area, or filtering and comparing results based on different evaluation criteria. Build LED chip circuit defect detection reports based on visualization results and stability evaluation data.

[0033] Preferably, step S1 comprises the following steps: Step S11: using an electron microscope to obtain structural data of an LED chip sample; Step S12: performing chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; Step S13: using the chip electrical connection data to perform structural screening on the structural data of the LED chip sample to obtain the electrical connection structural data of the LED chip sample; Step S14: confirming the electrical connection key level of the electrical connection structure data of the LED chip sample, and performing three-dimensional reconstruction on the confirmed electrical connection key level to obtain three-dimensional structure data of the electrical connection metallization layer.

[0034] In an embodiment of the present invention, the LED chip sample is subjected to appropriate pretreatment, including cleaning, cutting, etc., so that it is suitable for electron microscope observation. A high-resolution electron microscope (such as a scanning electron microscope, SEM) is used to scan the LED chip sample to capture the microstructure image of the chip surface and inside. A detailed microstructure map of the LED chip is constructed through the image data collected by the microscope, focusing on key structures such as the metal layer, the insulating layer, and the semiconductor layer. The microscope image is analyzed to extract key information such as the size, shape, material composition, and layout of the chip to generate a structural data set. According to the physical structure data of the chip, the electrical connection path, such as solder joints, electrodes, and wires, is identified. A model of the chip electrical connection is established using electrical principles and the geometric structure of the chip. It can be verified by finite element analysis (FEA) or a current flow model. The parameters of the electrical connection are extracted from the modeling process, including information such as the current path, the thickness of the conductive layer, and the conductive material, to form an electrical connection data set. The electrical connection data is used to optimize the structural design of the chip and screen out structural parts that are critical to electrical performance, such as the electrode contact surface and the wire spacing. Apply machine learning or optimization algorithms to screen the structural data and remove unnecessary parts based on the stability and conductivity of the electrical connection. The final screened data reflects the optimal electrical connection layout of the chip, which can be used as a reference for subsequent chip manufacturing and improvement. According to the electrical connection structure data, identify the connection levels (such as metallization layer, conductive layer, etc.) that are critical to the electrical performance of the chip. Through electrical performance analysis, confirm the key metallization layer, contact layer, etc., and calibrate the specific position and function of each layer. Use structural data and electrical connection level information to perform three-dimensional modeling and reconstruction, especially in the construction of the metallization layer, accurately locate the hierarchical structure of each electrical connection. Generate detailed three-dimensional structural data of the LED chip electrical connection metallization layer through three-dimensional reconstruction software (such as CAD or 3D modeling tools), including layer thickness, material distribution, and electrical contact points.

[0035] Preferably, step S14 further includes: Performing energy spectrum analysis on the electrical connection structure data of the LED chip sample to generate electrical connection energy spectrum data; performing elemental composition analysis on the electrical connection structure data of the LED chip sample using the electrical connection energy spectrum data, and when the elemental composition is analyzed, marking the corresponding structure as an electrical connection metal layer; Performing element distribution analysis on the electrical connection metal layer to generate element distribution data of the electrical connection metal layer; identifying key metal layers of the electrical connection metal layer according to the element distribution data of the electrical connection metal layer to obtain key metal layers of the electrical connection; The electrical connection structure data of the LED chip sample is three-dimensionally reconstructed based on the electrical connection key metal layer to generate the three-dimensional structure data of the metallization layer.

[0036] In the embodiment of the present invention, the LED chip sample is scanned and analyzed by using energy spectrum analysis technology, such as X-ray energy spectrum (EDS) or electron probe microanalysis (EPMA). These technologies can accurately analyze the element composition at different positions. By scanning the surface and internal structure of the chip, the energy spectrum data of each area is obtained, which reflects the distribution and concentration of the elements. The analysis is mainly aimed at the electrical connection parts such as the metallization layer, electrode layer and conductive path. According to the scanning results, the element composition and concentration information of each scanning point are extracted, the electrical connection energy spectrum data is generated, and the distribution and intensity changes of different elements are recorded. The energy spectrum data obtained by the energy spectrum analysis is processed to identify the element composition of each area, especially the metal elements (such as copper, aluminum, gold, etc.) and semiconductor elements (such as nitrogen, gallium, etc.) of special concern. In the energy spectrum data, the metallization layer area of ​​the electrical connection is marked according to the concentration and distribution of the metal elements. These areas are usually associated with the electrical conductive path and the electrical connection layer, and the metallization layer is identified as the key part of the electrical connection. According to the analysis results, an element composition analysis report is generated for the electrical connection structure data of the LED chip, indicating the specific element composition of the metallization layer and other important areas. In the area marked as the electrical connection metal layer, further element distribution analysis is performed to analyze the uniformity and distribution law of metal elements (such as copper, silver, etc.) in the layer. Through scanning and data processing, element distribution data of the electrical connection metal layer is generated. These data will show the concentration distribution of different metal elements in the metallization layer and help evaluate the quality and stability of the connection layer. According to the element distribution data, areas with uneven element distribution are identified, which will affect the electrical performance of the chip. Further optimization analysis can be performed to improve the electrical connection structure. According to the element distribution data of the electrical connection metal layer, those metal layers that are critical to electrical performance are identified. These layers usually include the metallization layers of the electrical contact surface, solder joint area and conductive path. According to the element distribution and electrical connection requirements, "critical metal layers" are defined. These layers have a decisive influence on the electrical conductivity and reliability of the LED chip. Through further structural analysis and experimental verification, the location, thickness and element composition of the critical metal layer are confirmed to ensure that it meets the requirements of electrical connection and conductive performance. Using the structural data and the element distribution data of the electrical connection metal layer, the metallization layer of the electrical connection is 3D modeled. Detailed modeling can be performed using 3D modeling software (such as CAD, 3DMax, SolidWorks, etc.). Based on the location and element distribution of the key metal layer, combined with electron microscopy and energy spectrum analysis data, appropriate reconstruction algorithms (such as surface reconstruction, hierarchical analysis, etc.) are used to perform 3D modeling of the metallization layer. Based on the modeling results, detailed 3D structural data of the metallization layer is generated, including important parameters such as the thickness, shape, contact points, and connection methods of the metallization layer. Through simulation and experimental verification, the performance of the 3D reconstructed metallization layer structure in terms of electrical performance, thermal stability, etc. is evaluated.If necessary, the structure can be further optimized to improve the reliability and performance of the chip.

[0037] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes: Step S21: dividing the three-dimensional structure data of the metallization layer into external three-dimensional structure data of the metallization layer and internal three-dimensional structure data of the metallization layer based on the thickness of the three-dimensional structure of the metallization layer; Step S22: using an infrared imaging sensor to analyze the surface temperature distribution of the metallization layer of the LED chip to generate the surface temperature distribution data of the metallization layer of the chip; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer according to the surface temperature distribution data of the metallization layer of the chip to generate the surface defect detection data of the metallization layer; Step S23: using particle pulse technology to perform high-speed particle emission on the LED chip to obtain high-speed particle pulse data; using the high-speed particle pulse data to perform particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; Step S24: integrating the metallization layer surface defect detection data and the metallization layer internal defect detection data to obtain electrical connection metallization layer defect detection data.

[0038] In an embodiment of the present invention, the complete three-dimensional structural data of the metallization layer is obtained by the aforementioned three-dimensional modeling technology or scanning technology (such as electron microscopy, X-ray CT scanning, etc.). This data should include the external and internal features of the metallization layer (such as thickness, density, material distribution, etc.). The metallization layer is divided into external and internal regions using the thickness data. The external three-dimensional structural data usually refers to a layer close to the surface, while the internal three-dimensional structural data refers to the inner part of the metallization layer. A threshold value (for example, a demarcation value based on thickness) can be set to divide the different thicknesses of the metallization layer. Based on the thickness division principle, the external and internal regions of the metallization layer are marked to form two types of data sets - the external three-dimensional structural data of the metallization layer and the internal three-dimensional structural data of the metallization layer. This division is crucial for subsequent defect detection, thermal analysis, and particle pulse analysis. Use an infrared thermal imaging sensor (such as a FLIR camera) and aim it at the surface of the metallization layer of the LED chip to measure the temperature distribution. These sensors can measure the temperature at different positions on the chip surface and record it. The temperature data obtained by infrared imaging technology generates a temperature distribution map. These temperature data are usually presented in the form of a heat map, and each point represents the temperature value of a certain position on the surface of the chip metallization layer. The infrared temperature data is post-processed to eliminate noise and optimize the visualization of the temperature distribution to ensure the accuracy of the temperature distribution data for defect analysis in subsequent steps. By analyzing the temperature distribution data on the surface of the metallization layer, areas with uneven temperatures are identified. These areas usually indicate potential defects or thermal imbalance problems, such as poor welding, uneven thermal conductivity, and inconsistent thickness of the metallization layer. Based on the temperature uniformity analysis, a temperature deviation threshold (such as a certain temperature difference) is set to detect those areas that exceed the threshold. The generated metallization layer surface defect detection data will include information such as the location, size, and temperature deviation of these abnormal areas. Using particle pulse flaw detection technology, a high-speed particle source (such as a proton or electron beam) is used to emit the inside of the metallization layer of the LED chip. These particles can penetrate the metallization layer and interact with the internal structure to generate measurable signals (for example, backscattering, scattered particles, etc.). The backscattered signals are collected by the particle pulse detector to record the interaction information between high-speed particles and internal defects (such as pores, cracks, voids, etc.) when passing through the metallization layer. These data provide a detailed view of the internal structure of the metallization layer. The collected particle pulse data is converted into a processable format (such as signal intensity, particle scattering angle, etc.), and particle pulse data related to the internal structure of the metallization layer is generated. By analyzing the particle pulse data, areas with abnormal particle scattering intensity are identified, which usually indicate defects inside the metallization layer. Based on the particle pulse data, defect detection algorithms (such as image processing algorithms, pattern recognition algorithms) are applied to locate defects inside the metallization layer (such as voids, cracks, missing materials, etc.).Through detection and analysis, the internal defect detection data of the metallization layer is generated, which includes the location, size and properties of the internal defects. The surface defect detection data of the metallization layer is fused with the internal defect detection data of the metallization layer. Data fusion algorithms (such as weighted average, decision tree fusion, etc.) can be used to integrate the information of surface defects and internal defects. In the integration process, the impact of surface defects and internal defects on the overall performance of the metallization layer is comprehensively considered. For example, surface defects affect electrical contact, while internal defects affect structural stability and conductivity. Based on the integrated data, the electrical connection metallization layer defect detection data is generated. The data will provide a comprehensive metallization layer defect analysis report, including key information such as defect type (surface or internal), location, size, and influencing factors.

[0039] Preferably, step S22 includes the following steps: Step S221: using an infrared imaging sensor to collect a surface temperature image of a metallization layer of an LED chip to obtain a surface temperature image of the metallization layer; Step S222: performing image preprocessing on the metallization layer surface temperature image to generate a standard metallization layer surface temperature image, wherein the image preprocessing includes image correction and image denoising; performing image data conversion on the standard metallization layer surface temperature image to generate metallization layer temperature information data; Step S223: mapping the metallization layer temperature information data to a temperature distribution to generate chip metallization layer surface temperature distribution data; calculating the temperature difference of adjacent pixels of the standard metallization layer surface temperature image according to the chip metallization layer surface temperature distribution data to obtain the temperature difference of each group of adjacent pixels; Step S224: Analyze the uniformity of the temperature distribution data on the surface of the chip metallization layer through the temperature difference of each group of adjacent pixels to generate the temperature uniformity data of the chip metallization layer surface; use the temperature uniformity data of the chip metallization layer surface to perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate the metallization layer surface defect detection data.

[0040] In an embodiment of the present invention, an infrared imaging sensor (such as a FLIR series thermal imager) is used to image the metallization layer of an LED chip. This sensor can measure and capture the temperature information on the chip surface and generate a high-resolution temperature image. The infrared imaging sensor is aimed at the metallization layer surface of the LED chip, and a temperature scan is performed at different positions and at different times to record the temperature of each point on the chip surface. The temperature information is displayed in real time through an infrared imaging device, and an image file containing temperature data is generated. Each image reflects the distribution of the chip surface temperature, and the color or grayscale value of the image represents the temperature value of different areas. The final output metallization layer surface temperature image will serve as the basic data for subsequent analysis. In the collected temperature image, there will be deviations caused by sensor errors, environmental factors, etc. Image correction is performed to ensure the accuracy of the temperature data by adjusting the response curve of the infrared sensor and the image contrast. The color mapping of the infrared image is adjusted so that the color comparison relationship between different temperature values ​​and the image is accurate. Correct the geometric deformation in the image (for example, distortion caused by the imaging angle) to ensure that the image is consistent with the actual physical shape. Since infrared imaging is affected by background noise, equipment noise or external interference, image denoising is performed. Common denoising methods include: using a Gaussian filter to remove high-frequency noise, smoothing temperature fluctuations in the image, using a median filter to remove noisy pixels, and retaining the overall trend of the temperature data. After image correction and denoising, a standardized metallization layer surface temperature image is obtained. This image will provide a reliable basis for subsequent temperature information extraction and data analysis. The standardized image is converted into a temperature information data format (such as CSV, JSON or other data table format), which will contain the temperature value of each pixel position as the input for subsequent analysis. The temperature value of each pixel in the standard metallization layer surface temperature image is data mapped. Using the pixel coordinates and temperature values ​​in the temperature information data, the temperature data is visualized in the form of a heat map for subsequent analysis. Based on the temperature information data, a temperature distribution map of the chip metallization layer surface is generated. This map shows the temperature gradient of the entire chip metallization layer surface and the temperature fluctuations in different areas. Areas with higher or lower temperatures are usually associated with structural defects or performance problems in the metallization layer. For ease of analysis, hot spots or abnormal areas are marked in the temperature distribution map. The temperatures in these areas are significantly higher or lower than the surrounding areas, indicating potential defect locations. For each group of adjacent pixels in the standard metallization layer surface temperature image (such as four directions: up, down, left, and right), the temperature difference between each group of adjacent pixels is calculated, which can help evaluate the uniformity of temperature distribution. For two adjacent pixels p1 (x1, y1) and p2 (x2, y2), their temperature difference ΔT can be calculated by the formula: ΔT=|T(p1)−T(p2)|; where T(p1) and T(p2) represent the temperature values ​​of pixels p1 and p2 respectively, and ΔT represents the temperature difference.According to the temperature difference of each group of adjacent pixels, the temperature uniformity of the surface of the chip metallization layer is analyzed. If the temperature difference between adjacent pixels is large, it means that the temperature is uneven, and there are problems such as poor heat conduction, uneven thickness of the metallization layer, or local material defects. The calculated temperature difference data is used to evaluate the temperature uniformity of the surface of the metallization layer. The generated chip metallization surface temperature uniformity data will quantify the uniformity of the temperature distribution and express it in numerical form (such as uniformity index, standard deviation, etc.). According to the temperature uniformity data, areas with large temperature differences are identified and marked as potential defective areas. These areas usually correspond to uneven temperature or overheating of the chip metallization layer, which is related to poor electrical connection or thermal expansion problems. By performing threshold analysis on the temperature uniformity data, the areas where the temperature difference exceeds the preset range are located. These areas can be marked with thermal images to help engineers further diagnose and analyze the problem. According to the test results, the metallization surface defect detection data is generated, including information such as the location, size, and temperature difference of the defective area. This data can be used for subsequent quality control and chip optimization.

[0041] Preferably, step S23 includes the following steps: Step S231: using particle pulse technology to perform high-speed particle emission on the LED chip to obtain high-speed particle pulse data; Step S232: performing particle signal feature recognition on the high-speed particle pulse data to generate particle signal feature data; performing particle propagation path analysis on the high-speed particle pulse data according to the particle signal feature data to generate particle propagation path data; Step S233: Structural mapping is performed on the particle propagation path data and the three-dimensional structure data inside the metallization layer to generate particle structure mapping data inside the metallization layer; particle reflection and scattering analysis is performed on the particle structure mapping data inside the metallization layer to generate particle group image data of the metallization layer; Step S234: quantify the uniformity of the particle pulse signal of the metallization layer particle group image data to generate a particle pulse signal uniformity value; perform particle internal defect detection on the internal three-dimensional structure data of the metallization layer based on the particle pulse signal uniformity value to generate internal defect detection data of the metallization layer.

[0042] In an embodiment of the present invention, high-speed particle emission is performed on the LED chip by using particle pulse technology (for example, proton or electron pulse emission). This technology can reveal the defects or inhomogeneities of the internal structure of the metallization layer through the interaction between high-speed particles and atoms inside the material. A particle source (such as a particle accelerator) is used to perform particle pulse emission on the LED chip. The particles will penetrate the metallization layer of the chip and interact with different parts of the material inside the chip according to different paths and scattering degrees. In the process of the particles penetrating the material, a certain pulse signal will be generated. The interaction information between the particles and the material is recorded in real time by a sensor (such as a particle detector or a time-of-flight detector) to obtain high-speed particle pulse data, which includes information such as the incident time, energy loss, and propagation path of the particles. The basic signal characteristics of the particles are extracted from the obtained high-speed particle pulse data, which include the energy loss, flight time, propagation direction, attenuation rate, etc. of the particles. Signal processing techniques such as Fourier transform and wavelet analysis can be used to extract features from the signal. A pattern recognition algorithm (such as a support vector machine (SVM) or a neural network) is applied to classify the particle pulse signal to identify the signal pattern related to the internal defects of the material. For example, if some particle signals show abnormal energy loss or scattering patterns, they correspond to internal defect areas. Through feature extraction and recognition, particle signal feature data are generated, including basic information of each particle signal and its classification results, which can provide a basis for subsequent particle propagation path analysis and defect detection. According to the particle signal feature data, the propagation path of the particle from the source to the detector is analyzed. This analysis takes into account various physical phenomena of particle propagation inside the metallization layer, such as scattering, absorption and reflection. Based on the particle signal feature data, simulation software (such as Monte Carlo method or other particle tracking algorithms) is used to simulate the propagation path of the particle inside the metallization layer. The propagation path data of the particle in the metallization layer is obtained by detailed simulation of the space and interaction area passed by the particle. The particle propagation path data is compared and mapped with the internal three-dimensional structure data of the metallization layer. Using three-dimensional data visualization technology, the particle path is matched with the specific structure of the metallization layer (such as lattice, grain boundary, void, etc.), forming the particle structure mapping data inside the metallization layer, which provides the spatial relationship between particles and structures for subsequent analysis. According to the particle propagation path, the reflection and scattering behavior of the particle when encountering different substances in the metallization layer is analyzed. Generally, particles propagating in the metallization layer will scatter or reflect when encountering metal particles, defects, voids and other materials. By combining the particle propagation path with the structure mapping data, the scattering and reflection phenomena can be quantitatively evaluated. By analyzing the particle reflection and scattering, the distribution images of the particle group inside the metallization layer are obtained. These images show the aggregation of the particle group in different areas, as well as the propagation and scattering effects in the metallization layer. This data is called the metallization layer particle group image data.The uniformity analysis of the particle group image data is performed, that is, whether the distribution of particles in the metallization layer is uniform. If the particles are unevenly distributed, it indicates that there are inhomogeneities or defective areas in the metallization layer. The uniformity indicators of the particle group image, such as standard deviation and uniformity index, are calculated using statistical methods. These indicators can quantify the uniformity of the particle group distribution and reflect the quality and internal defects of the metallization layer. According to the uniformity analysis results, the particle pulse signal uniformity value is generated. The lower the value, the more uniform the particle distribution; conversely, the higher the value, the greater the inhomogeneity or defects inside the metallization layer. The particle pulse signal uniformity value is used to detect the defective area inside the metallization layer. If the particle pulse signal uniformity value exceeds the preset threshold, it means that there are defects in some areas of the metallization layer, which are manifested as local voids, cracks, thermal deformation, etc. The defective area is located by comparing with the three-dimensional structure data inside the metallization layer. The deviation of the particle propagation path, the area of ​​abnormal reflection or scattering often corresponds to the location of the structural defect. Based on the particle pulse signal uniformity value and the defect location results, the internal defect detection data of the metallization layer is generated. This data includes the type, location, size, and impact of the defect.

[0043] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes: Step S31: extracting defect features from the electrical connection metallization layer defect detection data to obtain metallization layer defect feature data; dividing the metallization layer defect feature data into data sets to generate a model training set and a model test set; Step S32: using a support vector machine algorithm to perform model training on the model training set to generate an LED chip electrical connection defect prediction pre-model; using a model test set to perform model optimization iteration on the LED chip electrical connection defect prediction pre-model, thereby generating an LED chip electrical connection defect prediction model; Step S33: importing the three-dimensional structure data of the electrical connection metallization layer into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data.

[0044] In an embodiment of the present invention, the metallization layer defect detection data is preprocessed to ensure the consistency and reliability of the data. This includes noise removal, missing data supplementation and outlier processing. Statistical analysis methods are used to extract key information of metallization layer defects, such as defect type (cracks, holes, melting, fractures, etc.), defect location, defect size, shape, boundary features, defect distribution density, etc. These features can be extracted by image processing technology, signal processing methods or machine learning algorithms. The extracted metallization layer defect feature data is divided into a model training set and a model test set in proportion, for example, 70% as a training set and 30% as a test set. This division ensures that overfitting does not occur during model training and can effectively evaluate the generalization ability of the model. The training set is used to train the support vector machine (SVM) algorithm, and the model learns how to identify different types of defects through these data. The test set is used to verify and evaluate the performance of the trained model, and detect its accuracy, recall rate, precision, etc. According to the characteristics of the data, a suitable SVM kernel function (such as a linear kernel, a polynomial kernel, a radial basis kernel (RBF), etc.) is selected. If the data has a high nonlinear relationship, a radial basis kernel is usually selected. The defect feature data of the training set is input into the SVM algorithm for training. The SVM learns how to distinguish different types of defects (such as whether there are cracks or other defects) by optimizing the boundary classification hyperplane. The SVM model learns the support vector of each sample by maximizing the classification boundary, forms a classification model, and establishes a decision function for each defect category. The model is optimized using the cross-validation method to ensure the stability and accuracy of the model. The performance of the model on different data is evaluated by dividing the training set and the test set multiple times. The hyperparameters of the SVM (such as the penalty parameter C, the kernel function parameters, etc.) are optimized by grid search or random search to improve the accuracy and generalization ability of the model. After the SVM model is trained, a preliminary electrical connection defect prediction model is obtained. This model can classify and predict different metallization layer defects and give the probability distribution of each defect type. The test set is input into the prediction pre-model to evaluate the prediction performance of the model and detect whether the predicted defect type is consistent with the actual situation. The classification effect of the model is evaluated by calculating indicators such as accuracy, recall rate, F1-score, etc., especially for different types of defect detection, to ensure that the model performs evenly on all defect types. Based on the performance of the model on the test set, necessary model optimization is performed. If the model performance is poor, it is necessary to readjust the model parameters or introduce more features. During the optimization process, more training samples can be added, especially for defect types with weak model prediction performance, more samples can be collected and learned. After multiple rounds of optimization and verification, a reliable LED chip electrical connection defect prediction model is finally obtained. This model can accurately predict the potential defects of the chip on the electrical connection metallization layer.Import the three-dimensional structure data of the electrical connection metallization layer of the LED chip into the final trained LED chip electrical connection defect prediction model. The three-dimensional structure data includes the shape, size, defect location, etc. of the metallization layer on the chip surface. Use the trained SVM model to predict defects on the three-dimensional data of the metallization layer to determine whether there are defects in the electrical connection layer. By comparing the three-dimensional structure of the chip with the defect pattern in the model, predict the type of defect (such as cracks, overheating, disconnection, etc.). Based on the prediction results of the model, generate electrical connection defect prediction data, including the predicted location, type, size of the defect and its impact on chip performance.

[0045] In this specification, a LED chip defect detection device is provided, which is used to perform the above-mentioned LED chip defect detection method. The LED chip defect detection device includes: A three-dimensional reconstruction module is used to obtain the structural data of the LED chip sample; based on the structural data of the LED chip sample, the LED chip is electrically connected to generate chip electrical connection data; the electrical connection key level of the chip electrical connection data is confirmed, and the confirmed electrical connection key level is reconstructed in three dimensions to obtain the three-dimensional structural data of the electrical connection metallization layer; The defect detection module is used to divide the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; perform particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; The defect prediction module is used to perform model training on the defect detection data of the electrical connection metallization layer to generate an electrical connection defect prediction model for the LED chip; the three-dimensional structure data of the electrical connection metallization layer is imported into the electrical connection defect prediction model for the LED chip to perform chip electrical connection defect prediction and generate electrical connection defect prediction data; The circuit stability evaluation module is used to evaluate the chip circuit connection stability of the LED chip based on the electrical connection defect prediction data, and generate chip circuit connection stability evaluation data; the chip circuit connection stability evaluation data is visualized to generate an LED chip circuit defect detection report.

[0046] The present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the above-mentioned LED chip defect detection method is implemented.

[0047] The present invention also provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned LED chip defect detection method is implemented.

[0048] The beneficial effect of the present invention is that the structural data of the LED chip is accurately obtained through the three-dimensional reconstruction module, and the electrical connection of the chip is further analyzed, so that the integrity of the electrical connection inside the chip can be better understood, and solid data support can be provided for subsequent defect detection and stability evaluation. By dividing the metallization layer into external and internal data, and performing temperature balance defect detection and particle group image defect detection respectively, the potential defects on the surface and inside are effectively identified, the comprehensiveness and accuracy of defect detection are improved, and the early detection of problems in the chip production process is ensured. The machine learning model is used to train the detection data to generate a prediction model for the electrical connection defects of the LED chip, so that the system can not only perform real-time defect detection, but also predict the electrical connection problems that will occur in the future, so as to give early warning and carry out targeted optimization. Through the electrical connection defect prediction data, the stability evaluation of the circuit connection of the LED chip is carried out, which can accurately reflect the risks of the circuit, predict the stability of the circuit in advance, and provide guarantee for the long-term stable operation of the chip. The system presents the evaluation results through data visualization, generates a detailed circuit defect detection report, helps engineers quickly understand the quality and stability of the chip, and provides data support for subsequent improvements. Therefore, the present invention improves the accuracy of detecting subtle material-level defects inside the chip through automated three-dimensional structure reconstruction, comprehensive defect detection, and intelligent prediction and evaluation.

[0049] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0050] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for detecting defects in LED chips, characterized in that: The following steps are involved: Step S1: Acquire the structural data of the LED chip sample; perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; confirm the electrical connection key level of the chip electrical connection data, and perform three-dimensional reconstruction on the confirmed electrical connection key level to obtain three-dimensional structural data of the electrical connection metallization layer; Step S2: dividing the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; performing particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrating the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; Step S3: Model training is performed on the electrical connection metallization layer defect detection data to generate an LED chip electrical connection defect prediction model; the three-dimensional structure data of the electrical connection metallization layer is imported into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data; Step S4: evaluating the chip circuit connection stability of the LED chip according to the electrical connection defect prediction data, and generating chip circuit connection stability evaluation data; Visualize the chip circuit connection stability assessment data to generate an LED chip circuit defect detection report.

2. The LED chip defect detection method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: using an electron microscope to obtain structural data of an LED chip sample; Step S12: performing chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; Step S13: using the chip electrical connection data to perform structural screening on the structural data of the LED chip sample to obtain the electrical connection structural data of the LED chip sample; Step S14: confirming the electrical connection key level of the electrical connection structure data of the LED chip sample, and performing three-dimensional reconstruction on the confirmed electrical connection key level to obtain three-dimensional structure data of the electrical connection metallization layer.

3. The LED chip defect detection method according to claim 2, characterized in that: Step S14 also includes: Performing energy spectrum analysis on the electrical connection structure data of the LED chip sample to generate electrical connection energy spectrum data; performing elemental composition analysis on the electrical connection structure data of the LED chip sample using the electrical connection energy spectrum data, and when the elemental composition is analyzed, marking the corresponding structure as an electrical connection metal layer; Performing element distribution analysis on the electrical connection metal layer to generate element distribution data of the electrical connection metal layer; identifying key metal layers of the electrical connection metal layer according to the element distribution data of the electrical connection metal layer to obtain key metal layers of the electrical connection; The electrical connection structure data of the LED chip sample is three-dimensionally reconstructed based on the electrical connection key metal layer to generate the three-dimensional structure data of the metallization layer.

4. The LED chip defect detection method according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: dividing the three-dimensional structure data of the metallization layer into external three-dimensional structure data of the metallization layer and internal three-dimensional structure data of the metallization layer based on the thickness of the three-dimensional structure of the metallization layer; Step S22: using an infrared imaging sensor to analyze the surface temperature distribution of the metallization layer of the LED chip to generate the surface temperature distribution data of the metallization layer of the chip; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer according to the surface temperature distribution data of the metallization layer of the chip to generate the surface defect detection data of the metallization layer; Step S23: using particle pulse technology to perform high-speed particle emission on the LED chip to obtain high-speed particle pulse data; using the high-speed particle pulse data to perform particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; Step S24: integrating the metallization layer surface defect detection data and the metallization layer internal defect detection data to obtain electrical connection metallization layer defect detection data.

5. The LED chip defect detection method according to claim 4, characterized in that: Step S22 includes the following steps: Step S221: using an infrared imaging sensor to collect a surface temperature image of a metallization layer of an LED chip to obtain a surface temperature image of the metallization layer; Step S222: performing image preprocessing on the metallization layer surface temperature image to generate a standard metallization layer surface temperature image, wherein the image preprocessing includes image correction and image denoising; performing image data conversion on the standard metallization layer surface temperature image to generate metallization layer temperature information data; Step S223: mapping the metallization layer temperature information data to a temperature distribution to generate chip metallization layer surface temperature distribution data; calculating the temperature difference of adjacent pixels of the standard metallization layer surface temperature image according to the chip metallization layer surface temperature distribution data to obtain the temperature difference of each group of adjacent pixels; Step S224: Analyze the uniformity of the temperature distribution data on the surface of the chip metallization layer through the temperature difference of each group of adjacent pixels to generate the temperature uniformity data of the chip metallization layer surface; use the temperature uniformity data of the chip metallization layer surface to perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate the metallization layer surface defect detection data.

6. The LED chip defect detection method according to claim 4, characterized in that: Step S23 includes the following steps: Step S231: using particle pulse technology to perform high-speed particle emission on the LED chip to obtain high-speed particle pulse data; Step S232: performing particle signal feature recognition on the high-speed particle pulse data to generate particle signal feature data; performing particle propagation path analysis on the high-speed particle pulse data according to the particle signal feature data to generate particle propagation path data; Step S233: Structural mapping is performed on the particle propagation path data and the three-dimensional structure data inside the metallization layer to generate particle structure mapping data inside the metallization layer; particle reflection and scattering analysis is performed on the particle structure mapping data inside the metallization layer to generate particle group image data of the metallization layer; Step S234: quantify the uniformity of the particle pulse signal of the metallization layer particle group image data to generate a particle pulse signal uniformity value; perform particle internal defect detection on the internal three-dimensional structure data of the metallization layer based on the particle pulse signal uniformity value to generate internal defect detection data of the metallization layer.

7. The LED chip defect detection method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: extracting defect features from the electrical connection metallization layer defect detection data to obtain metallization layer defect feature data; dividing the metallization layer defect feature data into data sets to generate a model training set and a model test set; Step S32: using a support vector machine algorithm to perform model training on the model training set to generate an LED chip electrical connection defect prediction pre-model; using a model test set to perform model optimization iteration on the LED chip electrical connection defect prediction pre-model, thereby generating an LED chip electrical connection defect prediction model; Step S33: importing the three-dimensional structure data of the electrical connection metallization layer into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data.

8. An LED chip defect detection device, characterized in that: Used to perform the LED chip defect detection method according to claim 1, the LED chip defect detection device comprises: A three-dimensional reconstruction module is used to obtain the structural data of the LED chip sample; based on the structural data of the LED chip sample, the LED chip is electrically connected to generate chip electrical connection data; the electrical connection key level of the chip electrical connection data is confirmed, and the confirmed electrical connection key level is reconstructed in three dimensions to obtain the three-dimensional structural data of the electrical connection metallization layer; The defect detection module is used to divide the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; perform particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; The defect prediction module is used to perform model training on the defect detection data of the electrical connection metallization layer to generate an electrical connection defect prediction model for the LED chip; the three-dimensional structure data of the electrical connection metallization layer is imported into the electrical connection defect prediction model for the LED chip to perform chip electrical connection defect prediction and generate electrical connection defect prediction data; The circuit stability evaluation module is used to evaluate the chip circuit connection stability of the LED chip based on the electrical connection defect prediction data, and generate chip circuit connection stability evaluation data; the chip circuit connection stability evaluation data is visualized to generate an LED chip circuit defect detection report.

9. A computer device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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