Controller chip, configurable controller and radio frequency switch

Abstract

The invention provides a controller chip, a configurable controller and a radio frequency switch. The controller chip comprises a first logic circuit of a first type controller and a second logic circuit of a second type controller, wherein the first logic circuit and the second logic circuit are arranged on the same controller bare chip. The controller bare chip is provided with a first controller pin of the first type controller, a second controller pin of the second type controller and a mode configuration pin; the mode configuration pin is used for configuring different level states, and the first logic circuit or the second logic circuit is enabled based on the different level states of the mode configuration pin.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular to a controller chip, a configurable controller and a radio frequency switch. Background Art

[0002] In the field of electronic circuit technology, controllers are widely used. For example, controllers are needed in RF front-end modules to provide logic control and bias for PA (amplifier), switch or LNA (low noise amplifier). The process of these controllers may be different from that of PA, switch or LNA, and they usually need to be integrated with PA, switch or LNA in SIP (System In a Package). The types of controllers are also usually divided into GPIO (General-purpose input / output) mode and RFFEMIPI (MIPI RF Front-end) mode.

[0003] In compound RF switches (such as GaN HEMT switches), in order to control the on and off of the switch, a CMOS circuit is generally required to provide bias for the switch. For example, for depletion-type switches, whether GPIO logic or MIPI logic, the control principle is basically the same: add 0V to the gate to turn it on, and add negative voltage to the gate to turn it off. The main difference lies in whether the generation of positive and negative voltages is controlled by GPIO or by MIPI serial bus.

[0004] In order to adapt to different RF front-end modules, there will be a need for both GPIO controller and MIPI controller interface methods. The current known practice is to design the GPIO controller and MIPI controller separately. If the independent design method is adopted, the design and development cost will increase, the mask production cost will increase, and the difficulty of wafer production and delivery will also increase. Summary of the invention

[0005] In order to solve the existing technical problems, the present application provides a controller chip, a configurable controller and a radio frequency switch that can reuse a bare chip for different interface requirements.

[0006] In a first aspect, a controller chip is provided, comprising a first logic circuit of a first type controller and a second logic circuit of a second type controller disposed on the same controller bare chip;

[0007] The controller bare chip is provided with a first controller pin of the first type controller, a second controller pin of the second type controller, and a mode configuration pin;

[0008] The mode configuration pin is used to be configured to different level states, and the first logic circuit or the second logic circuit is enabled based on the different level states of the mode configuration pin.

[0009] In a second aspect, a configurable controller is provided, comprising the controller chip described in any embodiment of the present application and a packaging structure encapsulating the controller chip.

[0010] In a third aspect, a radio frequency switch is provided, comprising the controller chip according to any embodiment of the present application and a packaging structure encapsulating the controller chip, wherein the controller bare chip is further provided with a CMOS switch circuit connected to the first logic circuit and the second logic circuit;

[0011] Alternatively, the radio frequency switch includes the controller chip described in any embodiment of the present application, a switch chip provided with a switch circuit, and a packaging structure including the controller chip and the switch chip.

[0012] The controller chip provided in the above embodiment is provided with a first logic circuit of a first type of controller, a second logic circuit of a second type of controller and a mode configuration pin on the same controller bare chip, and the first logic circuit or the second logic circuit is enabled by configuring the mode configuration pin to a different level state. In this way, the controller chip can reuse the same controller bare chip, merge the logic circuits of the two types of controllers into the same design, and use the mode configuration pin to configure the controller chip as the first controller or the second controller according to the application requirements when the controller chip is used for different needs, thereby realizing different products, reducing development costs, and shortening the development cycle.

[0013] Taking the application of controller chip in RF front-end module as an example, the first type controller and the second type controller can be a GPIO controller and a MIPI controller respectively. By merging the GPIO logic circuit of the GPIO controller and the MIPI logic circuit of the MIPI controller on the same controller bare chip, a configurable multiplexing design is formed, which can be compatible with the requirements of different RF front-end modules for different interface methods, and can effectively reduce development costs and shorten development cycles.

[0014] The configurable controller and the radio frequency switch provided in the above embodiments respectively belong to the same concept as the corresponding controller chip embodiments, and thus have the same technical effects as the corresponding controller chip embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 4 is a schematic diagram showing a principle of a known GPIO controller.

[0016] Figure 2 FIG. 4 is a schematic diagram of a known MIPI controller.

[0017] Figure 3 Schematic diagram of the principle of a controller chip in one embodiment.

[0018] Figure 4 Schematic diagram of the circuit structure of a controller chip in one embodiment.

[0019] Figure 5 FIG. 4 is a schematic diagram of the circuit structure of a controller chip in another embodiment.

[0020] Figure 6 FIG. 4 is a schematic diagram of a transmission gate circuit in an embodiment.

[0021] Figure 7 Schematic diagram of the circuit structure of a radio frequency switch in one embodiment.

[0022] Figure 8 A flowchart of a configurable controller packaging method in an embodiment.

[0023] Fig. 9 for Figure 8 An optional application example of the configurable controller packaging method shown.

[0024] Fig.10 The figure is a flow chart of a configurable controller packaging method in another embodiment.

[0025] Fig.11 for Fig.10 An optional application example of the configurable controller packaging method shown. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0028] In the following description, the expression "some embodiments" is involved, which describes a subset of all possible embodiments. It should be noted that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0029] In the following description, the terms "first, second, third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first, second, third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0030] The inventors of this application have conducted the following research on the prior art in the study of how to reduce the development cost and development cycle of the controller: Figure 1 and Figure 2 As shown in the figure, they are schematic diagrams of the known GPIO controller and MIPI controller. The control principles of the two controllers are basically the same. The only difference is that the GPIO controller controls the generation of positive and negative voltages by GPIO, while the MIPI controller controls the generation of positive and negative voltages by MIPI serial bus. The existing practice is to design corresponding controller bare chips (dies) for the control logic of the GPIO controller and the control logic of the MIPI controller respectively. This dedicated design does not have any redundant circuit parts and can minimize the die size. However, the design of two controller dies requires increased design costs and development cycles. In wafer production, two sets of masks need to be cast and stocked in two sets, which increases costs, and the production delivery and management costs are high.

[0031] In this regard, the technical idea proposed by the inventor of this application is to combine the two control logics of GPIO controller and MIPI controller and set them on the same controller bare chip (die), and then use the mode configuration pins to configure different level states. When faced with different actual application requirements, the control logic of one of the controllers is enabled based on the different level states of the mode configuration pins, thereby realizing a configurable multiplexing design of multiple types of controllers.

[0032] Based on the technical idea of ​​configurable multiplexing design, the inventor of the present application further proposes to utilize the design of configurable mode configuration pins to different level states to realize multiple configurability of controller chips and realize more types of controller products, including: configurability of different working modes of the same controller, configurability of multiple function tests of the same controller, configurability of dual negative pressure modes, and configurability of programmable negative pressure output, etc. The technical solution based on the technical idea of ​​configurable multiplexing design is detailed as follows.

[0033] Please refer to Figure 3 and Figure 4, a controller chip provided in one embodiment of the present application, includes a first logic circuit 12 of a first type controller and a second logic circuit 13 of a second type controller arranged on the same controller bare chip 11; the controller bare chip 11 is provided with a first controller pin 121 of the first type controller, a second controller pin 131 of the second type controller, and a mode configuration pin 14; the mode configuration pin 14 is used to be configured to different level states, and the first logic circuit 12 or the second logic circuit 13 is enabled based on the different level states of the mode configuration pin 14.

[0034] The controller bare chip 11 refers to a single chip cut from a silicon wafer during the semiconductor manufacturing process, usually in its original form before packaging, and represents a single, unpackaged semiconductor device. The control logic circuit refers to the circuit portion of the controller used to implement the control function. In this embodiment, the first logic circuit 12 corresponds to the circuit portion of the first type controller used to implement the control function, the second logic circuit 13 corresponds to the circuit portion of the second type controller used to implement the control function, the first controller pin 121 corresponds to the original pin of the first type controller, and the second controller pin 131 corresponds to the original pin of the second type controller.

[0035] The mode configuration pin 14 refers to a control pin that is additionally added to the controller bare chip 11 in addition to the original pins of the first type controller and the second type controller when the two control logics of the first type controller and the second type controller are combined and set on the same controller bare chip 11.

[0036] In the above embodiment, the controller chip sets a first logic circuit 12 of a first type of controller, a second logic circuit 13 of a second type of controller and a mode configuration pin 14 on the same controller bare chip 11. The mode configuration pin 14 can be configured to different level states to enable the first logic circuit 12 or the second logic circuit 13 respectively. In this way, the controller chip can reuse the same controller bare chip 11, merge the logic circuits of the two types of controllers into the same design, and use the mode configuration pin 14 to configure the controller chip for different needs as a first type of controller or as a second type of controller according to application requirements. The same controller bare chip 11 can be reused to realize different controller products, thereby reducing development costs and shortening development cycles.

[0037] In an alternative example, Figure 4As shown, the first type of controller refers to a MIPI controller, the first logic circuit 12 is a control logic circuit of the MIPI controller, the second type of controller refers to a GPIO controller, the second logic circuit 13 is a control logic circuit of the GPIO controller, the first controller pin 121 includes the original pins clk and data for the controller die designed separately for the MIPI controller, the second controller pin 131 includes the original pins A0, A1, A2, and A3 for the controller die designed separately for the GPIO controller, and the mode configuration pin 14 includes a newly added control pin sel0 relative to the MIPI controller and the GPIO controller, and the first logic circuit 12 or the second logic circuit 13 on the controller bare chip 11 of the configurable controller is enabled by placing the control pin sel0 in a high level state or a low level state respectively. In this example, the control pin sel0 is high level by default, that is, inside the controller bare chip 11, the control pin sel0 is pulled up, and even if the sel0 PAD is suspended, it also indicates a high level. When sel0=1, the first logic circuit 12 is enabled, and the controller chip is configured to be used as a MIPI controller, as shown in Table 1 below.

[0038] Table 1: MIPI mode truth table corresponding to the controller chip configured as a MIPI controller

[0039]

[0040] When sel0=0, the second logic circuit 13 is enabled, and the controller chip is configured to be used as a GPIO controller, as shown in Table 2 below.

[0041] Table 2: GPIO mode truth table corresponding to the controller chip when it is configured as a GPIO controller

[0042]

[0043] In some embodiments, the controller bare chip 11 is also provided with a multiplexer selection circuit 18 connected to the outputs of the first logic circuit 12 and the second logic circuit 13. The multiplexer selection circuit 18 takes the output of the first logic circuit 12 and the output of the second logic circuit 13 as inputs, and can select the input corresponding to the corresponding logic circuit in the currently selected controller mode from multiple inputs as output, so that the first logic circuit 12 and the second logic circuit 13 can share the output of the multiplexer selection circuit 18 as the output end of the controller chip 11.

[0044] In some embodiments, the mode configuration pin 14 includes a plurality of mode configuration pins 14, and the plurality of mode configuration pins 14 are respectively configured to different level states, and based on the combination of the different level states of the plurality of mode configuration pins 14, different working modes of the first logic circuit 12 or different working modes of the second logic circuit 13 are enabled. Among them, by setting a plurality of mode configuration pins 14, the plurality of mode configuration pins 14 can be respectively configured to different level states, and based on the combination of the different level states of the plurality of mode configuration pins 14, the controller chip is configured as a MIPI controller or a GPIO controller, and then the enabling control instructions of the controller chip in different working modes are selected, thereby realizing more controller modes based on the reuse of the same controller bare chip 11.

[0045] In some embodiments, the mode configuration pin 14 includes a first configuration pin 141, and when the first configuration pin 141 is at a high level, the first logic circuit 12 is enabled, and when the first configuration pin 141 is at a low level, the second logic circuit 13 is enabled. The different level states of the first configuration pin 141 specifically refer to a high level and a low level. The default level state of the first configuration pin 141 can be set to a high level, and when the first configuration pin 141 is set to the default high level state, the default logic circuit of the first type controller is enabled. In this way, the controller chip is used as a first type controller by default, and according to actual application needs, the level state of the first configuration pin 141 can be changed to enable the controller chip to be used as a second type controller.

[0046] In some embodiments, the mode configuration pin 14 includes a second configuration pin 142; when the first configuration pin 141 is at a low level and the second configuration pin 142 is at a high level, the second logic circuit 13 is enabled to operate in the first operating mode; when the first configuration pin 141 is at a low level and the second configuration pin 142 is at a low level, the second logic circuit 13 is enabled to operate in the second operating mode. The first configuration pin 141 and the second configuration pin 142 have two different level states, high level and low level, respectively. After selecting the controller mode of the required type of controller based on the different level states of the first configuration pin 141, different operating modes of the corresponding type of controller can be further selected based on the different level states of the second configuration pin 142, thereby realizing more controller modes based on the reuse of the same controller bare chip 11. Still with Figure 4For example, the first configuration pin 141 refers to the control pin sel0, the second configuration pin 142 refers to the control pin sel2, the second type of controller refers to the GPIO controller, the first working mode of the second logic circuit 13 refers to the direct mapping control mode of the 2-wire-4-wire decoding of the GPIO controller, and the second working mode of the second logic circuit 13 refers to the single-wire control mode of the GPIO controller. Please refer to Table 2 again, which is the GPIO mode truth table. When sel0=0, the second logic circuit 13 is enabled, and the controller chip is configured to be used as a GPIO controller. At this time, when se2=0, it is the direct mapping control mode of the 2-wire-4-wire decoding of the GPIO controller, and two control lines are used to decode to realize 4 states. When se2=1, it is the single-wire control mode of the GPIO controller, and four control lines are used to realize 4 states. In this way, two different types of controller products, the GPIO controller and the MIPI controller, and two different GPIO controller products are integrated on the same controller bare chip 11 based on the technical idea of ​​configurable multiplexing design and using the different level states of the mode configuration pin 14. Using the same controller bare chip 11, the multiplexing of the GPIO controller and the MIPI controller is realized, and the multiplexing of two GPIO controllers of different modes is also realized.

[0047] In some embodiments, the controller bare chip 11 is further provided with a charge pump circuit 15, and the mode configuration pin 14 further includes a third configuration pin 143; when the third configuration pin 143 is at a high level, the charge pump circuit 15 is enabled to generate an internal negative voltage; when the third configuration pin 143 is at a low level, the charge pump circuit 15 is disabled, and the controller bare chip 11 receives an external negative voltage. A charge pump circuit is a DC-DC converter that uses switched capacitor technology to achieve voltage conversion. It changes the voltage level by periodically transferring charge without using a traditional transformer. The charge pump circuit 15 is usually composed of a capacitor and a switch (usually a clock-controlled field effect transistor or FET), and works by timing and controlling these switches to utilize the charge transfer characteristics of the capacitor. In this embodiment, the mode configuration pin 14 further includes a third configuration pin 143, and the third configuration pin 143 has two different level states of a high level and a low level. Based on the different level states of the third configuration pin 143, the controller chip selects a dual negative voltage mode of an internal negative voltage or an external negative voltage.

[0048] Still Figure 4Taking the example in as an example, a charge pump circuit connected to the first logic circuit 12 and the second logic circuit 13 is provided on the controller bare chip 11. The third configuration pin 143 refers to the control pin sel1. External negative pressure supply or internal negative pressure generation is selected by sel1=0 or sel=1. When internal negative pressure generation is adopted, the noise is relatively large. For a high-sensitivity receiving switch, its receiving sensitivity will be affected and reduced. At this time, external negative pressure supply can be adopted by configuring different level states of the control pin sel1, and the internal negative pressure generation function of the charge pump circuit can be disabled, which can effectively reduce noise.

[0049] In some embodiments, the first configuration pin 141 is at a high level, and the second configuration pin 142 is disabled, and different test functions of the first logic circuit 12 are enabled based on different level states of the second controller pin 131 of the second logic circuit 13. In the working mode corresponding to the first type of controller, the logic control of the second type of controller is reused, and the different level states of the second controller pin 131 are used to form tests for multiple functional modules of the first type of controller. In this way, compared with the prior art that requires different functional modules to be led out to corresponding test pins respectively, the number of pins on the controller bare chip 11 can be reduced, and the circuit area overhead of the controller bare chip 11 can be saved.

[0050] In an optional example, the number of the second controller pins 131 includes a plurality; the second controller pins 131 are combined to form n different level states, respectively enabling n functional tests of the first logic circuit 12. Figure 4 For example, the second type of controller is a GPIO controller, and the second controller pin 131 of the GPIO controller includes pins A0, A1, A2, and A3. Please refer to the following Table 3, Figure 5 and Figure 6 By sharing the same test pin test PAD, utilizing the second configuration pin 142 and combining the different level states of the controller pins A0, A1, A2, and A3 of the GPIO controller, four level states can be combined to correspond to the tests of the four functional modules of the controller, namely BandGap Gout, clkout, LDO1_out, and LDO2_out. By reusing the pins of the GPIO controller, there is no need to add additional control lines, thereby reducing the circuit area overhead of the controller chip.

[0051] BandGap Gout refers to testing the circuit module that generates a stable reference voltage. Its basic principle is to use the band structure of semiconductor materials to generate a reference voltage. The size of this reference voltage is related to the bandgap width of the material. clkout refers to testing the quality and stability of the clock output signal. LDO1_out refers to testing the output voltage and current characteristics of the LDO chip, such as testing whether the output voltage is within the specified range, the output voltage stability under different load conditions, the impact of input voltage changes on the output voltage, etc., to ensure its stability and working performance under different working conditions. LDO2_out can refer to testing the short-circuit protection test, startup time test, noise suppression test, etc. of the LDO chip.

[0052] Table 3:

[0053] Test Mode test PAD Sel2 A0 A1 A2 Testing BandGap Gout x 0 0 1 Test clkout x 0 1 1 Testing LDO1_out x 1 0 1 Testing LDO2_out x 1 1 1

[0054] Different types of controllers need to perform multiple test functions. Table 3 shows that in GPIO controller mode, the logic control bits of the GPIO controller are reused to implement the test of multiple functional modules with one test PAD. In MIPI controller mode, the MIPI register decoding control transmission gate circuit 16 can be reused to implement the test of multiple functional modules.

[0055] Figure 6 In an optional example, a transmission gate circuit 16 is further provided on the controller bare chip 11, and the transmission gate circuit 16 is used to output based on the different level states of the controller pins A0, A1, A2, and A3 of the GPIO controller to realize the principle schematic diagram of the selection control of the test of different functional modules. The transmission gate circuit 16 can be composed of a PMOS and an NMOS in parallel, C and / C are complementary logic, and are mutually inverse logic. The different level states of the controller pins A0, A1, A2, and A3 are used as the input of the transmission gate circuit 16 to realize the selection output of the test of the four functional modules. Figure 6 (1) to (4) are the equivalent schematics corresponding to the four types of selected outputs. When C is high and / C is low, NMOS is turned on, PMOS is also turned on, the transmission gate is turned on, and the input A is transmitted to B; when C is low and / C is high, NMOS is turned off, PMOS is also turned off, the transmission gate is turned off, and the output is in a high impedance state.

[0056] In some embodiments, the first configuration pin 141 is at a low level, and the second configuration pin 142 is disabled, and the negative voltage output value of the second logic circuit 13 is set based on the first controller pin 121 of the first logic circuit 12 as a serial port, and the negative voltage output of the second logic circuit 13 is modified to the negative voltage output value by controlling efuse burning. Figure 4For example, the first type of controller is a MIPI controller and the second type of controller is a GPIO controller. In the working mode of the MIPI controller, the user can write to the UDR register to select the desired negative pressure output. However, in the working mode of the GPIO controller, flexible changes are not supported. In this embodiment, as shown in Table 4 below:

[0057]

[0058] In the working mode of the GPIO controller, the MIPI logic circuit is used as a redundant functional circuit in the working mode of the GPIO controller, and the MIPI controller is enabled by using multiple mode configuration pins 14. The desired value is written to the reg0x02 register at one time, that is, the MIPI logic circuit is used to complete the efuse burning, so that the originally redundant MIPI logic circuit in the working mode of the GPIO controller is reused as a serial port to realize the efuse burning control of the GPIO mode. Since the efuse burning is one-time, if there is no MIPI controller, multiple independent GPIO control lines need to be added to control the efuse burning. In this way, this embodiment uses the technical idea of ​​configurable multiplexing design, so that the GPIO controller that originally does not have adjustable negative pressure output can realize one-time programmable negative pressure output without adding additional control lines.

[0059] In some embodiments, the mode configuration pin 14 can be an internal pin of the chip of the configurable controller, and can be based on a wafer of a pre-formed unified form of a configurable controller, and can be set high or low internally during chip packaging to select the desired type of controller. In a specific example, the first configuration pin 141, the second configuration pin 142, and the third configuration pin 143 can all be built-in to form a pin inside the chip. When the controller chip is packaged through a packaging structure to form a configurable controller, the level state of the first configuration pin 141, the second configuration pin 142, and the third configuration pin 143 can be set inside the packaging structure to realize the configurability of the controller chip. Optionally, the mode configuration pin 14 can also be a pin led out to the packaging shell, and the mode configuration pin 14 is led out to the packaging pin, which can support the user side to realize the choice of setting high or low in actual application. In a specific example, the first configuration pin 141, the second configuration pin 142, and the third configuration pin 143 can all be led out of the packaging structure. It is understandable that the mode configuration pins 14 may also be partially built-in and partially led out to the package shell according to actual application requirements, and there is no limitation here.

[0060] The controller chip provided in the embodiment of the present application has at least the following characteristics:

[0061] First, the control logics of the GPIO controller and the MIPI controller are merged, and an additional mode configuration pin 14 is added for selection, so as to achieve the purpose of multiplexing the controller bare chip 11 to form different controller products.

[0062] Second, the direct mapping control mode and the single-line control mode of the GPIO controller's 2-wire-4-wire decoding are also selected through the additional mode configuration pin 14, so as to achieve the purpose of multiplexing the controller bare chip 11 to further form more different controller products.

[0063] Third, a test pin is reused, and a single test PAD is used to test multiple internal functional modules in the GPIO controller working mode by setting the mode configuration pin 14 and reusing the logic circuit of the GPIO controller at the same time; of course, it is also possible to use a single test PAD to test multiple internal functional modules in the MIPI controller working mode by setting the mode configuration pin 14 and reusing the logic circuit of the MIPI controller at the same time.

[0064] Fourth, in the working mode of the GPIO controller, the logic circuit of the MIPI controller is reused as the dummy tube function to implement efuse burning control, so that the GPIO controller that originally does not have adjustable negative voltage output can be programmable for negative voltage output without adding additional control lines.

[0065] Fifth, the negative pressure can be flexibly selected: generated by the internal circuit or supplied by external negative pressure.

[0066] In general, the controller chip can realize multiple GPIO and MIPI controller products and dual negative pressure mode by using a controller bare chip 11 and combining the setting of the mode configuration pin 14. In the working mode of the GPIO controller, the GPIO logic circuit is reused in combination with the mode configuration pin 14 to realize multiple test functions. In the working mode of the MIPI controller, the MIPI logic circuit is reused in combination with the mode configuration pin 14 to realize multiple test functions. In the working mode of the MIPI controller, the MIPI logic circuit is reused to realize one-time programmable negative pressure output, saving circuit area overhead and reducing development costs and development cycles.

[0067] In another aspect, an embodiment of the present application further provides a configurable controller, comprising the controller chip described in any of the aforementioned embodiments and a packaging structure encapsulating the controller chip.

[0068] See also Figure 7On the other hand, the embodiment of the present application further provides a radio frequency switch, including the controller chip described in any embodiment of the present application and a packaging structure encapsulating the controller chip, wherein the controller bare chip 11 is further provided with a CMOS switch circuit 17 connected to the first logic circuit 12 and the second logic circuit 13. The CMOS switch circuit 17 and the logic circuits of the GPIO controller and the MIPI controller are arranged on the same bare chip, and then packaged to form a radio frequency switch.

[0069] Optionally, the RF switch may also include the controller chip described in any embodiment of the present application, a switch chip provided with a switch circuit, and a packaging structure including the controller chip and the switch chip. The switch circuit and the controller circuit are respectively provided on independent bare chips, and then packaged to form a RF switch.

[0070] On the other hand, please refer to Figure 8 and Fig. 9 , and also provides an optional packaging method for packaging the controller chip 11 to obtain a configurable controller, including:

[0071] S11, obtaining a controller chip; the controller chip is the controller chip described in any embodiment of the present application;

[0072] S12, performing a wafer probe test on the controller chip, and packaging the controller chip after the wafer probe test is completed.

[0073] Based on the integrated arrangement of the first logic circuit 12 of the first type controller, the second logic circuit 13 of the second type controller and the mode configuration pin 14 on the same controller bare chip 11, a wafer product of a unified form can be formed in advance, and a wafer probe test (CP test) can be performed on the configurable controller formed as a wafer. After the test is completed, the packaged configurable controller is formed through SIP packaging.

[0074] Among them, during the SIP packaging process, the mode configuration pins 14 can be set to be all or part of the chip built-in pins. After each mode configuration pin 14 is set high or low, the controller type finally formed by the controller chip 11 is set before packaging. If the MIPI controller is obtained by setting the first configuration pin 141 high internally, the write function of the register reg0 x02 in the MIPI mode can be used to select the desired negative pressure output when it is actually applied on the user side. It is understandable that the mode configuration pins 14 can also be set to be all or part of the external pins, and the pins reserved as external pins are led out to the packaging shell, and then the mode configuration pins 14 are set high or low when they are used by the user side to set the controller type finally formed by the controller chip 11.

[0075] On the other hand, please refer to Fig.10 and Fig.11 , another optional packaging method for packaging the controller chip 11 to obtain a configurable controller is also provided, including:

[0076] S11, obtaining a controller chip; the controller chip is the controller chip described in any embodiment of the present application;

[0077] S13, performing a wafer probe test on the controller chip, after the wafer probe test is completed, selecting the first logic circuit based on the mode configuration pin being placed in a preset level state and using the second controller pin to set the negative voltage output value of the first logic circuit, and controlling efuse burning to modify the negative voltage output of the first logic circuit to the negative voltage output value, and then packaging the controller chip.

[0078] Based on the integrated arrangement of the first logic circuit 12 of the first type controller, the second logic circuit 13 of the second type controller and the mode configuration pin 14 on the same controller bare chip 11, a wafer product of a unified form can be formed in advance, and a wafer probe test (CP test) is performed on the configurable controller formed as a wafer. After the test is completed, the GPIO controller is obtained by internally setting the first configuration pin 141 to a low level. At this time, the logic circuit of the multiplexed MIPI controller is the dummy tube function, the negative voltage output value of the GPIO controller is set and the efuse burning control is implemented, so as to realize one-time programming of the negative voltage output of the GPIO controller and obtain the desired negative voltage output; and then the packaged configurable controller is formed through SIP packaging. It can be understood that when the controller chip 11 is used as a GPIO controller, if it is hoped that the GPIO controller can set the current negative pressure output value through one-time programmable negative pressure output, it is necessary to first set the first configuration pin 141 to low, and use the write function of the register reg0 x02 of the MIPI controller's logic circuit in the MIPI mode to select the desired negative pressure output and then burn it, and then package it to set the controller chip 11 to ultimately form a GPIO controller with a preset negative pressure output value.

[0079] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0080] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A controller chip, characterized in that: including a first logic circuit of a first type controller and a second logic circuit of a second type controller disposed on the same controller bare chip; The controller bare chip is provided with a first controller pin of the first type controller, a second controller pin of the second type controller, and a mode configuration pin; The mode configuration pin is used to be configured to different level states, and the first logic circuit or the second logic circuit is enabled based on the different level states of the mode configuration pin.

2. The controller chip according to claim 1, characterized in that: The mode configuration pins include multiple mode configuration pins, and the multiple mode configuration pins are respectively used to be configured to different level states. Based on the combination of the different level states of the multiple mode configuration pins, different operating modes of the first logic circuit or different operating modes of the second logic circuit are enabled.

3. The controller chip according to claim 1, characterized in that: The mode configuration pin includes a first configuration pin. When the first configuration pin is at a high level, the first logic circuit is enabled. When the first configuration pin is at a low level, the second logic circuit is enabled.

4. The controller chip according to claim 3, characterized in that: The mode configuration pin also includes a second configuration pin; When the first configuration pin is at a low level and the second configuration pin is at a high level, the second logic circuit is enabled to operate in a first operating mode; when the first configuration pin is at a low level and the second configuration pin is at a low level, the second logic circuit is enabled to operate in a second operating mode.

5. The controller chip according to claim 4, characterized in that: The controller bare chip is also provided with a charge pump circuit, and the mode configuration pins further include a third configuration pin; When the third configuration pin is at a high level, the charge pump circuit is enabled to generate an internal negative voltage; when the third configuration pin is at a low level, the charge pump circuit is disabled, and the controller bare chip receives an external negative voltage.

6. The controller chip according to claim 4, characterized in that: The first configuration pin is at a high level and the second configuration pin is disabled, and different test functions of the first logic circuit are enabled based on different level states of the second controller pin of the second logic circuit.

7. The controller chip according to claim 6, characterized in that: The number of the second controller pins includes a plurality; The pin combination of the second controller forms n different level states, respectively enabling n functional tests of the first logic circuit.

8. The controller chip according to claim 4, characterized in that: The first configuration pin is at a low level and the second configuration pin is disabled. The negative voltage output value of the first logic circuit is set based on the first controller pin of the first logic circuit as a serial port, and the negative voltage output of the first logic circuit is modified to the negative voltage output value by controlling efuse burning.

9. The controller chip according to any one of claims 1 to 8, characterized in that: The first type controller is a MIPI controller, and the first logic circuit is a control logic circuit of the MIPI controller; The second type controller is a GPIO controller, and the second logic circuit is a control logic circuit of the GPIO controller.

10. The controller chip according to any one of claims 1 to 8, characterized in that: The mode configuration pin is an internal pin of the chip of the configurable controller; and / or, The mode configuration pins are pins led out to the package housing.

11. A configurable controller, characterized in that: A controller chip as claimed in any one of claims 1 to 10 and a packaging structure encapsulating the controller chip.

12. A radio frequency switch, characterized in that: A controller chip according to any one of claims 1 to 10 and a packaging structure encapsulating the controller chip, wherein the controller bare chip is further provided with a CMOS switch circuit connected to the first logic circuit and the second logic circuit; Or, comprising a controller chip as described in any one of claims 1 to 10, a switch chip provided with a switch circuit, and a packaging structure including the controller chip and the switch chip.

Images