Short-circuit failure analysis method for multilayer carrier plate of miniature microphone

Abstract

The invention relates to the technical field of multilayer support plate analysis, and discloses a miniature microphone multilayer support plate short circuit failure analysis method, which comprises the following steps: image acquisition: acquiring image data of a to-be-tested multilayer support plate through a thermal imager and a three-dimensional imager; carrying out image preprocessing, and carrying out denoising, gray level conversion and edge extraction on the acquired image data; circuit diagram modeling is carried out, each layer of circuit image is converted into a diagram structure, circuit nodes are vertexes in the diagram, circuit paths are edges in the diagram, and the weights of the edges are path resistance values; and performing multi-layer diagram optimization calculation, performing joint optimization on each layer of circuit diagram by adopting an optimization algorithm, minimizing the resistance of a current path, and considering a cross-layer coupled current flow path. According to the method, through combination of multilayer circuit diagram optimization and Bayesian reasoning, high-precision positioning and dynamic risk assessment of short circuit points in a complex circuit are realized, and the accuracy and efficiency of short circuit fault detection are greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-layer substrate analysis, and in particular to a short-circuit failure analysis method of a multi-layer substrate of a miniature microphone. Background Art

[0002] With the rapid development of modern electronic products, electronic devices have higher and higher requirements for circuit boards. Especially in consumer electronics and communication products, multi-layer circuit boards are widely used in mobile phones, computers, automotive electronics and other fields due to their high integration and complex functional requirements. However, these circuit boards may have short circuit problems during the production process, resulting in unstable product performance or even failure. Therefore, the detection and location of short circuit faults are crucial to ensure the quality of electronic products.

[0003] Currently, existing short circuit detection methods usually rely on manual inspection and simple imaging techniques, such as X-rays and thermal imaging, which can help detect short circuit problems in circuit boards to a certain extent, especially on single-layer circuit boards, and can more directly identify the fault location of the circuit. Thermal imaging technology can detect temperature changes caused by current flow in the circuit board, while X-rays can reveal defects or connection problems between layers within the circuit. Traditional technology has also introduced some rule-based inspection methods, which can effectively improve the efficiency of fault detection under specific circuit designs or single fault modes.

[0004] However, existing technologies have obvious shortcomings when dealing with multi-layer circuits or complex circuit layouts. First, traditional detection methods fail to fully consider the coupling effects between circuit layers. In particular, when the current path passes through multi-layer circuits, the risk of short-circuit failures and changes in current flow are not accurately simulated and predicted. Second, existing detection methods often rely on static preset thresholds and cannot be dynamically adjusted according to real-time data, resulting in limited accuracy in fault detection. Although thermal imaging and X-ray technologies provide data sources, their resolution and accuracy are often insufficient when dealing with complex circuit boards. In particular, when the short-circuit points are small or the current flow is more complex, existing methods find it difficult to accurately locate all potential short-circuit points. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention provides a short-circuit failure analysis method for a miniature microphone multi-layer carrier board, which solves the problems in the prior art that the complexity of multi-layer circuits cannot be effectively handled, the dynamic adaptability is poor, and the short-circuit point positioning is inaccurate.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: A short circuit failure analysis method for a multi-layer substrate of a miniature microphone comprises the following steps: Image acquisition: using thermal imagers and 3D imagers to collect image data of the multi-layer substrate to be tested; Image preprocessing: denoising, grayscale conversion and edge extraction of collected image data; Circuit diagram modeling: convert each layer of circuit image into a graph structure, where the circuit nodes are vertices in the graph, the circuit paths are edges in the graph, and the edge weights are the path resistance values; Multi-layer graph optimization calculation, using optimization algorithms to jointly optimize the circuit diagrams of each layer, minimize the resistance of the current path, and consider the current flow path of cross-layer coupling; Bayesian reasoning is used for probability estimation. Based on the real-time collected thermal imaging data and 3D imaging data, the posterior probability of the short-circuit point is updated through the Bayesian theorem to evaluate the probability of occurrence of each potential fault point. Combined optimization and short-circuit point location, the short-circuit point is accurately located based on the graph optimization results and the posterior probability of Bayesian reasoning, and confirmed in combination with partial discharge detection equipment.

[0007] Preferably, the image acquisition includes: Use a thermal imager to collect thermal imaging images of the multi-layer substrate to be tested to obtain temperature distribution information of each layer of circuits; Use a 3D imager to capture a 3D circuit image of the multi-layer substrate to be tested, so as to accurately obtain the 3D structural information of the circuit; Multilayer substrates are imaged using X-ray sensors to obtain cross-sectional images between layers within the circuit and reveal potential short-circuit areas.

[0008] Preferably, the image preprocessing includes: Perform grayscale conversion on each layer of image data and standardize the image data into grayscale images for easy subsequent processing; Denoising: remove noise from the image through median filtering and mean filtering to ensure image quality; Image segmentation and edge extraction: The relevant circuit areas in the circuit image are extracted through the image segmentation algorithm, and the edges are accurately extracted to facilitate the subsequent circuit diagram modeling.

[0009] Preferably, the image segmentation algorithm in the image preprocessing includes: Canny edge detection algorithm, used to accurately extract the edges of circuit paths and avoid noise interference; Otsu threshold segmentation method is used to standardize each layer of image into a grayscale image for subsequent processing; The region growing method,identifies the circuit region in image segmentation and divides the image region into,related circuit regions to ensure the validity and accuracy of the image region.

[0010] Preferably, the circuit diagram modeling includes: Assign impedance values ​​to the current paths in each layer of the circuit image, and define the edge weight as the resistance of the path; Calibrate the nodes of each layer of the circuit diagram to identify the electrical connection points and their corresponding current flow paths; Multi-layer circuit diagrams are expressed using graph structures to ensure that the coupling relationship between circuits at different layers is fully expressed in the graph model.

[0011] Preferably, the node calibration includes: Use Hough transform algorithm to identify straight current paths in circuit diagrams and calibrate them with electrical connection points; Automatically calibrate the nodes of each layer of the circuit diagram, and use the template matching algorithm to detect and match the electrical connection points; The current flow on the path is accurately modeled, and the current flow path tracing algorithm is used to simulate the current path in each layer of the circuit diagram.

[0012] Preferably, the multi-layer graph optimization calculation includes: By defining the objective function, the resistance value of each edge and the coupling strength of the cross-layer connection are combined for joint optimization; Use graph optimization algorithms to calculate the minimum resistance of each path and preliminarily determine the short-circuit area; The cross-layer circuit paths are optimized through heuristic algorithms to improve the accuracy of fault point identification.

[0013] Preferably, the Bayesian reasoning for probability estimation includes: Based on real-time thermal imaging data and 3D imaging data, a prior distribution is constructed to represent the probability of short circuit occurrence in each circuit path. The posterior probability of each potential short-circuit point is calculated by combining the observed data with the Bayesian theorem; Dynamically update the posterior probability of the fault point to locate the fault point in real time and accurately.

[0014] Preferably, the joint optimization and short-circuit point location includes: Combine the graph optimization calculation results with the posterior probability obtained by Bayesian reasoning to determine the final location of each potential short-circuit point; For the potential short-circuit point located, use partial discharge detection equipment to verify whether it is the real fault point; Feed the test results back to the system to optimize the subsequent short-circuit detection process.

[0015] Preferably, the partial discharge detection device comprises: Current fluctuation detector, used to monitor current changes and confirm fault points through current fluctuation analysis; Temperature sensor, used to detect temperature changes in the short-circuit area and confirm whether the current increases abnormally; The discharge signal capturer combines current fluctuations and temperature changes to record partial discharge signals in real time and analyze the fault points through software.

[0016] The present invention provides a short-circuit failure analysis method for a miniature microphone multilayer substrate. It has the following beneficial effects: 1. The present invention combines graph optimization calculation with Bayesian reasoning, and dynamically updates the probability of short circuit occurrence, making the short circuit point location more accurate. Compared with the traditional static detection method, the positioning strategy can be adjusted in real time, greatly improving the accuracy and efficiency of short circuit fault location.

[0017] 2. In the optimization of multi-layer circuit diagrams, the present invention simultaneously considers the resistance of the current path and the current coupling effect between different layers, and optimizes the current flow path. Unlike traditional technology that only optimizes a single layer path, it solves the problem of current mutual interference in multi-layer circuit boards and improves the overall performance of the system.

[0018] 3. By combining thermal imaging, 3D imaging data with Bayesian reasoning, the present invention not only relies on a single data source when conducting short circuit risk assessment, but also conducts multi-dimensional analysis. This method makes up for the data limitations of existing technologies and provides more accurate and comprehensive fault prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The present invention is a flow chart of the method. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the specification of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Please refer to the attached Figure 1 The embodiment of the present invention provides a short circuit failure analysis method of a miniature microphone multilayer substrate, comprising the following steps: S1, image acquisition, collecting image data of the multi-layer substrate to be tested by a thermal imager and a three-dimensional imager; Image acquisition is accomplished through the collaborative work of multiple devices, including thermal imagers, 3D imagers, and X-ray sensors. Each device has different functions and can comprehensively acquire information about multi-layer circuit boards from multiple dimensions, thus ensuring comprehensiveness and accuracy of the analysis.

[0022] The data after image acquisition will provide data support for subsequent steps to ensure the smooth progress of image preprocessing, circuit diagram modeling and optimization calculation. In this process, each device is set according to the actual situation of the circuit board to be tested to ensure the acquisition of high-quality image data. These devices work together to effectively avoid the acquisition blind spots caused by a single device.

[0023] Thermal imagers are mainly used to collect temperature distribution information on the surface of circuit boards. They can detect the heat generated when current passes through the circuit, thereby indirectly revealing potential short-circuit areas. Thermal imagers have a certain resolution and sensitivity, which are quantified using the following performance indicators: ; in: It is the performance parameter of the thermal imager, which reflects the accuracy of the thermal imager in detecting circuit short circuit; is the minimum temperature change threshold that can be detected by the thermal imager; is the resolution of the thermal imager, expressed as the temperature change per pixel.

[0024] 3D imagers are mainly used to obtain 3D structural information of circuit boards, especially in multi-layer circuit boards, which can effectively reveal the spatial layout of the circuit and the relative positions between the layers. Its performance is described by the following parameters: ; in: It is the performance parameter of the 3D imager, which measures its accuracy in obtaining circuit structure information; is the minimum scanning depth of the 3D imager, in millimeters; is the resolution of the 3D imager, expressed as the distance per pixel.

[0025] X-ray sensors can penetrate different layers of the circuit board, obtain cross-sectional images of the circuit, and reveal possible short circuits in multi-layer circuits. The accuracy of X-ray imaging is mainly measured by the following parameters: ; in: It is the performance parameter of the X-ray sensor, reflecting its imaging accuracy; The minimum number of penetration layers for X-ray imaging; It is the resolution of the X-ray sensor, usually expressed as the fineness of imaging per unit area.

[0026] In practical applications, the collaboration of these three devices is critical. Each device has its own advantages and limitations when collecting data, so their combination can ensure a comprehensive observation of the circuit board from multiple angles. In order to ensure that the collected data can accurately reflect the overall status of the circuit board, the data of each device is synchronized and integrated.

[0027] Data synchronization is mainly to align the image data collected by different devices on the time axis to ensure that the data of each device corresponds to the same physical time point. The specific implementation method can be calibrated through timestamp technology to ensure that the image data obtained by thermal imagers, 3D imagers and X-ray sensors in the same time period can be effectively integrated.

[0028] Data fusion is the process of combining data from different imaging devices to generate a unified, comprehensive image data set. In the process of image data fusion, image registration algorithms are often used to ensure that images obtained by different devices can be accurately aligned. Image registration calculates the spatial transformation relationship between images to achieve overlapping matching of images from different sources, thereby generating a comprehensive circuit board image.

[0029] For example, the fusion of thermal imaging images and 3D imaging images may require image scaling and rotation to ensure that the heat source of the circuit board and the structural image can be accurately aligned. Similarly, X-ray images need to be aligned with 3D imaging images to reveal possible short circuits in the deep circuit.

[0030] Through image acquisition, comprehensive image data of multi-layer substrates can be obtained. These data include information on temperature changes, three-dimensional structure and internal levels of the circuit, providing a comprehensive and multi-angle analysis perspective for the circuit board.

[0031] S2, image preprocessing, denoising, grayscale conversion and edge extraction of the collected image data; Image preprocessing performs denoising, grayscale conversion, and edge extraction on the collected images, making the images clearer and more accurate, providing reliable input data for subsequent circuit diagram modeling and short-circuit point positioning.

[0032] In this embodiment, after image acquisition, the image is first gray-scale converted to standardize the color image into a gray-scale image. The main purpose of this process is to reduce the influence of color information in the image on the analysis results. The fault characteristics of the circuit board are mainly reflected in the morphology and changes of the circuit path, and these characteristics can be more clearly displayed in the gray-scale image. By converting to a gray-scale image, subsequent image processing operations can focus more on structural features rather than color differences, thereby reducing data redundancy and computational complexity.

[0033] In another possible implementation, the processed image data will go through a denoising step to remove excess noise in the image. Circuit images may contain a variety of noises during the acquisition process, especially noises generated by thermal imagers and X-ray sensors, such as random noise or ambient light interference. The denoising step uses two methods: median filtering and mean filtering. Median filtering can effectively remove salt and pepper noise by replacing each pixel value in the image with the median of its neighboring pixels. Mean filtering calculates the mean of pixels within a certain range around each pixel to achieve the effect of smoothing the image and removing other types of noise. Through the combination of these two methods, image noise is effectively suppressed, providing high-quality images for subsequent steps.

[0034] Specifically, in the application of median filtering, each pixel By its neighbors The median substitution formula is: ; in, is the pixel value after denoising, Represents neighborhood The median of .

[0035] In mean filtering, each pixel The new value of is the mean of all pixels in its neighborhood, and the formula is: ; in, Represents neighborhood The size of Represents the value of all pixels in the neighborhood. is the pixel value after mean filtering; :Indicates the neighborhood Sum the values ​​of all pixels in to get the sum of these pixels; : is the normalization factor used to ensure that the new value of each pixel is the mean of all pixel values ​​in the neighborhood.

[0036] As an option, the edge extraction operation of the image occupies an important position in the image preprocessing process. Edge extraction can help identify the precise boundaries of the circuit path and is an indispensable step in image analysis. By extracting the edge, the circuit area can be effectively separated from the background, which is crucial for subsequent circuit diagram modeling and short-circuit point positioning. In the present invention, the Canny edge detection algorithm is adopted, which is widely used in edge extraction for its high efficiency and accuracy. The Canny algorithm can accurately extract the circuit path edge in the image through multiple stages of processing (such as smoothing, gradient calculation, non-maximum suppression, dual threshold detection, etc.).

[0037] Specifically, the core of the Canny edge detection algorithm is to detect edges by calculating the image gradient. The gradient calculation formula is: ; in, and Respectively represent images The gradients in the horizontal and vertical directions, is the total gradient value of the image.

[0038] After edge detection, the Canny algorithm also refines the edges through non-maximum suppression, making the edges in the image smoother and removing false edges. Subsequently, the algorithm uses dual threshold detection to determine which edges are real edges and which are noise or false edges.

[0039] In one possible implementation, after edge extraction, an image segmentation algorithm is applied to accurately extract the circuit area. Image segmentation can distinguish the circuit area from the background area in the image, thereby helping the model focus on the effective part of the circuit. In order to further improve the segmentation accuracy, the Otsu threshold segmentation method is used. This method determines the optimal threshold by maximizing the inter-class variance, so that the separation of the circuit area and the background area is clearer. The formula for Otsu threshold segmentation is as follows: ; in: is the between-class variance; and are the weights of foreground and background respectively; and is the mean of foreground and background.

[0040] In another possible implementation, in order to further refine the extraction of the circuit area, a region growing method can be combined, which can gradually expand the area according to the similarity between pixels and accurately extract the circuit path. The region growing method is suitable for processing complex circuit images, especially when the circuit structure has certain tortuosity or irregularity, and can effectively extract a coherent circuit area from the image.

[0041] Image preprocessing can improve the quality of the image and provide high-quality data input for subsequent steps. De-noising reduces interference information in the image, and edge extraction and image segmentation ensure accurate extraction of the circuit area, thereby ensuring accurate identification of circuit paths and fault features.

[0042] S3, circuit diagram modeling, converting each layer of circuit image into a graph structure, where the circuit nodes are vertices in the graph, the circuit paths are edges in the graph, and the edge weights are path resistance values; The goal of circuit diagram modeling is to convert these image data into actual circuit diagram models, including key information such as electrical connection points, connection paths and their resistance characteristics. This process provides basic data for subsequent diagram optimization calculations, short circuit detection and fault location.

[0043] In this embodiment, in the process of circuit diagram modeling, each electrical connection point (such as a solder joint, a joint, etc. on the circuit) is represented as a node in the diagram, and the current path is represented as an edge connecting these nodes. The weight of each edge is determined by the resistance value of the path, and this process is the core of circuit diagram modeling. The larger the resistance value, the higher the weight of the edge, which reflects the degree of resistance when the current passes through the path.

[0044] Specifically, when identifying electrical connection points in image data, the key nodes in the circuit diagram are first located through image processing technology. These nodes may be solder joints, electrical contact points or other connection points on the circuit board. Through automated algorithms, such as template matching and edge detection technology, the spatial locations of these nodes can be accurately identified and calibrated in the circuit diagram model.

[0045] Alternatively, the current path is identified by brightness changes or edge extraction results in the image. The circuit path is separated from the background by image segmentation and region growing methods to extract the path of current flow. On this basis, the resistivity formula can be used to calculate the resistance value of each current path to determine the weight of the edge in the circuit diagram.

[0046] In one possible implementation, the resistance value is calculated as follows: ; in: is the resistance value of the circuit path (unit: Ω); The resistivity of the circuit path material (unit: Ω·m), which usually depends on the material used for the circuit board (such as copper, aluminum, etc.); is the length of the circuit path (unit: m), that is, the distance the current flows in the circuit; is the cross-sectional area of ​​the circuit path (unit: m 2 ), which is usually calculated based on the width and thickness of the circuit path.

[0047] The above formula can be used to quantify the resistance of each current path and assign corresponding weights to the edges in the circuit diagram. The resistance value is directly related to the ease with which the current flows. The greater the resistance, the greater the resistance to current flowing through the path, and vice versa.

[0048] In some embodiments, for complex circuit diagrams, it may be necessary to consider the multi-layer structure of the circuit board, especially when there are circuit connections at different levels in the circuit. In order to better describe the structure of the multi-layer circuit board, a multi-layer graph structure modeling method is adopted. Each layer of the circuit is modeled by independent nodes and edges, and the circuit connections between different layers are represented by cross-layer connection edges. In this model, the current path of the cross-layer connection is described by the coupling strength of the edge.

[0049] Alternatively, in a multi-layer circuit diagram, the coupling strength of the cross-layer connections It can be calculated by the following formula: ; in: Indicates Layer and The cross-layer current coupling strength between layers (unit: S), that is, the effectiveness of current transmission from one layer to another; Indicates Layer and The resistance of the current path between layers; For the Layer and the resistivity of the circuit paths between layers; For the Layer and the length of the current path between layers; is the cross-sectional area of ​​the current path.

[0050] Specifically, the coupling strength calculated using the above formula will be used to optimize the cross-layer connections in the graph. This method can effectively describe the interaction between layers in a multi-layer circuit board and ensure that the interaction effect of the current paths between different layers is taken into account when calculating the graph optimization.

[0051] In another implementation, the calculation of capacitance and induction characteristics is also introduced in the process of circuit diagram modeling, especially for high-frequency circuits or circuits with high-speed signal transmission. For these circuits, factors such as resistance, capacitance, and induction will affect the flow behavior of current. In some cases, the influence of capacitance and induction cannot be ignored, especially in the process of signal transmission, where the capacitance effect may cause signal distortion or delay. In order to improve the modeling accuracy, the capacitance and induction parameters can be calculated according to the design standards or actual measured values ​​of the circuit and incorporated into the consideration of circuit diagram modeling.

[0052] Circuit diagram modeling can convert the circuit paths and electrical connection points in the image into a diagram structure, ensuring that the physical structure and electrical characteristics of the circuit board are accurately represented in the model.

[0053] S4, multi-layer diagram optimization calculation, using optimization algorithm to jointly optimize the circuit diagrams of each layer, minimize the resistance of the current path, and consider the current flow path of cross-layer coupling; The multilayer graph optimization calculation will optimize the current path based on these resistance values, with the goal of minimizing the resistance of the current path, thereby improving the overall efficiency of the circuit and reducing the risk of short circuit failures.

[0054] In this embodiment, the goal of graph optimization is to optimize the circuit graph by minimizing the total resistance on the current path. An objective function is defined, which represents the sum of all path resistances. By optimizing this objective function, the optimal path for current flow can be found and the current is ensured to flow through the path with the least resistance.

[0055] Specifically, in graph optimization calculations, an objective function is defined to minimize the total resistance of the current path. The resistance of the current path determines the efficiency of current flow, so optimizing the resistance of the current path is crucial to improving circuit performance. The objective function can be expressed as follows: ; in: is the objective function value after circuit diagram optimization, representing the total resistance of the current path; is the set of all edges in the circuit graph, each edge represents the current path; Is the circuit path The resistance value (in Ω) is determined by the material resistivity, length, and cross-sectional area of ​​the circuit path; is with the path An associated weight, which is used to indicate the importance or priority of the path.

[0056] In the optimization process, by minimizing the objective function , that is, to optimize the circuit diagram by reducing the total resistance of the current path and selecting those paths with the least resistance, thereby improving the efficiency of current flow.

[0057] As an option, in the case of multi-layer circuit boards, the optimization calculation is not limited to the internal paths of each layer of the circuit, but also needs to consider the current coupling effect between layers. Since there may be current coupling between different layers, the path of the current in one layer may affect the current flow in another layer. Therefore, the cross-layer coupling strength is introduced to describe the current interaction between different layers.

[0058] In one possible implementation, in order to improve the optimization effect, a heuristic algorithm, such as the Dijkstra algorithm or the A* algorithm, is used to calculate the shortest path of the current from the source node to the target node. These algorithms can calculate the optimal path of the current based on the resistance value and select the path with the least resistance to ensure the maximum efficiency of the current flow.

[0059] In general, in addition to optimizing the current path resistance in the objective function, the optimization algorithm also needs to consider some constraints to ensure that the circuit design is feasible in actual engineering. These constraints can include the minimum length of the circuit path, path width, material restrictions, etc. In the case of multi-layer circuit boards, the optimization process also needs to consider the current coupling effect between layers and the effectiveness of the cross-layer current path.

[0060] After introducing these constraints, the optimization objective function can be processed by weighted summation or Lagrange multiplier method to ensure that the current flow of the circuit is optimal.

[0061] Through multi-layer graph optimization calculation, the present invention can optimize the current path in the circuit and minimize the total resistance of the current path, thereby improving the efficiency of current flow.

[0062] S5. Bayesian reasoning is used for probability estimation. Based on the real-time collected thermal imaging data and 3D imaging data, the posterior probability of the short-circuit point is updated by Bayesian theorem to evaluate the probability of occurrence of each potential fault point. Bayesian reasoning for probability estimation will evaluate the probability of potential short-circuit points in the circuit based on real-time acquired thermal imaging data and three-dimensional imaging data. The Bayesian reasoning method combines prior information and observation data to dynamically update the probability of occurrence of each potential short-circuit point, thereby providing a more accurate basis for subsequent short-circuit location and risk assessment.

[0063] In this embodiment, the core idea of ​​Bayesian reasoning is to calculate the posterior probability through Bayesian theorem, that is, to infer the probability of a short circuit in each circuit path under the condition of given observation data. In order to achieve this goal, it is first necessary to construct a prior distribution for each circuit path, which is based on prior information such as circuit design and historical fault data. Subsequently, the prior distribution is updated using Bayesian theorem in combination with the real-time collected thermal imaging data and three-dimensional imaging data to obtain the posterior probability of each circuit path.

[0064] Bayesian inference relies on Bayes' theorem, which can be expressed as follows: ; in: is the posterior probability, indicating that given the observed data After that, assume the probability of a short circuit fault HHH. This posterior probability is the target to be calculated, which represents the possibility of a short circuit in the circuit path based on the existing data; is the likelihood function, indicating that under the assumption of a short circuit fault In the event of a This value is calculated based on thermal imaging data and 3D imaging data, usually obtained by fitting the model to the data; It is the prior probability, which indicates the initial probability of a short circuit failure in the absence of any observation data. This prior probability can be set based on historical data, circuit design, and material properties; is the marginal likelihood, which indicates that the observed data The total probability of occurrence, usually calculated using all possible assumptions Perform a weighted sum. Since it does not rely on the assumption , which is usually treated as a constant in actual calculations.

[0065] In practical applications, it is necessary to combine real-time thermal imaging data and three-dimensional imaging data to update the posterior probability of each circuit path. Thermal imaging data provides temperature changes on the circuit surface, which can reflect the resistance changes when the current passes through the path, while three-dimensional imaging data provides spatial structural information of the circuit, which helps to determine whether the current path is affected by the physical hierarchy or layout. By inputting these observation data into the Bayesian inference model, the posterior probability can be dynamically updated and a more accurate short-circuit fault prediction can be obtained.

[0066] Specifically, assuming that thermal imaging image data is obtained and 3D imaging data , these data will be used as observation data Enter the Bayesian formula to calculate the posterior probability of a short circuit in each circuit path .

[0067] As an option, by iteratively updating the posterior probability, the posterior probability can be gradually adjusted after each new observation data is obtained, thereby continuously improving the accuracy of fault location. This dynamic update process enables the system to make more accurate predictions based on real-time monitoring data. As data accumulates, the accuracy and real-time performance of the system are continuously improved, and it can respond to potential faults in the circuit in a timely manner.

[0068] Processing of thermal imaging data: Temperature changes in thermal imaging images reflect the thermal effect of current flowing through the circuit, especially on high current paths. Increased temperature often means that the resistance of the path is large, which may lead to short circuit failure. By analyzing temperature data, it is possible to determine which circuit paths have abnormal temperatures, thereby improving the estimation of short circuit risk.

[0069] Processing of 3D imaging data: 3D imaging images can provide detailed structural information of the circuit board. The physical structure of the current path, the relationship between layers and their spatial position may affect the way the current flows. By combining 3D imaging data, the current coupling effect between different layers can be accurately evaluated, thereby improving the prediction of short circuit points.

[0070] By using Bayesian reasoning to estimate the probability, the present invention can update the short-circuit fault probability of each circuit path in real time. As new data is continuously input into the system, the posterior probability will be dynamically adjusted, so that the accuracy of fault location is continuously improved, which can effectively reduce the false alarm rate and missed alarm rate.

[0071] S6. Combined optimization and short-circuit point location: Accurately locate the short-circuit point based on the graph optimization results and the posterior probability of Bayesian reasoning, and confirm it with partial discharge detection equipment; Joint optimization and short-circuit point location will accurately locate potential short-circuit points based on graph optimization results and the posterior probability of Bayesian reasoning. Through this step, the resistance of the circuit path and the probability of short circuit occurrence can be combined to accurately identify the area in the circuit where short circuits are most likely to occur, thereby effectively avoiding the impact of faults on circuit performance.

[0072] In this embodiment, the process of joint optimization and short-circuit point location first combines the graph optimization result of step S4 and the Bayesian reasoning result of step S5 to calculate the final risk value of each current path. It has been minimized through graph optimization calculation, and the posterior probability obtained through Bayesian inference The calculation of the final risk value takes these two factors into consideration, thus reflecting the actual risk of the current path.

[0073] Specifically, the goal of joint optimization is to combine the resistance value and the probability of short circuit occurrence to obtain the risk value of each path through weighted average. This comprehensive evaluation will help locate high-risk paths and further optimize the circuit layout. Calculate the risk value of each path The formula is: ; in: Is the path The final risk value represents the comprehensive short-circuit risk of the current path; Is the path The resistance value (unit: Ω) is derived from the result of the graph optimization in step S4; Is the path The posterior probability of comes from the result of the Bayesian inference calculation in step S5, which represents the probability of a short circuit on the path; and are weight coefficients, which are used to adjust the contribution of resistance value and short circuit probability to the final risk value, and control the influence of the two on the result.

[0074] As an option, the weight factor and The selection of is very important, as it controls the relative importance of the resistance value and the short circuit probability in the final risk value. In practical applications, these weight coefficients can be dynamically adjusted through experimental data, engineering experience, or optimization algorithms. Specifically, in some cases, the resistance value has a greater impact on the occurrence of short circuit failures, so a larger In other cases, the short-circuit probability of the current path may be more important, and the Make it bigger.

[0075] In another implementation, by calculating the final risk value of each path, high-risk paths can be screened out. These high-risk paths usually have larger resistance values ​​or higher short circuit probability, so they are the areas where short circuits are most likely to occur. Based on these screened high-risk paths, further detailed analysis and positioning can be performed to ensure accurate identification of the fault point.

[0076] For high-risk paths, the system can be verified in conjunction with partial discharge detection equipment. Partial discharge detection equipment can monitor current fluctuations and temperature changes, which are usually more obvious near the short-circuit point. The data provided by the partial discharge detection equipment can further verify whether there is a short-circuit fault and accurately determine the location of the short-circuit point.

[0077] In this embodiment, the process of joint optimization and short-circuit point location includes the following key steps: Calculate the resistance value of each circuit path (From optimization calculation results).

[0078] Calculate the posterior probability of a short circuit on each path (From Bayesian inference results).

[0079] According to the formula Calculate the final risk value for each path .

[0080] Paths with higher risk values ​​are screened out and tested in detail as potential short-circuit points.

[0081] Use partial discharge detection equipment to verify the existence of the short-circuit point and confirm whether it is the real fault point.

[0082] More accurate fault detection can be achieved through joint optimization and short-circuit point location. By comprehensively considering the resistance of the current path and the probability of short circuit occurrence, the area in the circuit where short circuit is most likely to occur can be effectively identified. This not only improves the accuracy of fault location, but also can dynamically adjust the weight coefficient to adapt to the characteristics and application scenarios of different circuits.

[0083] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A short circuit failure analysis method for a multi-layer substrate of a miniature microphone, characterized in that: The following steps are involved: Image acquisition: using thermal imagers and 3D imagers to collect image data of the multi-layer substrate to be tested; Image preprocessing: denoising, grayscale conversion and edge extraction of collected image data; Circuit diagram modeling: convert each layer of circuit image into a graph structure, where the circuit nodes are vertices in the graph, the circuit paths are edges in the graph, and the edge weights are the path resistance values; Multi-layer graph optimization calculation, using optimization algorithms to jointly optimize the circuit diagrams of each layer, minimize the resistance of the current path, and consider the current flow path of cross-layer coupling; Bayesian reasoning is used for probability estimation. Based on the real-time collected thermal imaging data and 3D imaging data, the posterior probability of the short-circuit point is updated through the Bayesian theorem to evaluate the probability of occurrence of each potential fault point. Combined optimization and short-circuit point location, the short-circuit point is accurately located based on the graph optimization results and the posterior probability of Bayesian reasoning, and confirmed in combination with partial discharge detection equipment.

2. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 1, characterized in that: The image acquisition includes: Use a thermal imager to collect thermal imaging images of the multi-layer substrate to be tested to obtain temperature distribution information of each layer of circuits; Use a 3D imager to capture a 3D circuit image of the multi-layer substrate to be tested, so as to accurately obtain the 3D structural information of the circuit; Multilayer substrates are imaged using X-ray sensors to obtain cross-sectional images between layers within the circuit and reveal potential short-circuit areas.

3. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 1, characterized in that: The image preprocessing comprises: Perform grayscale conversion on each layer of image data and standardize the image data into grayscale images for easy subsequent processing; Denoising: remove noise from the image through median filtering and mean filtering to ensure image quality; Image segmentation and edge extraction: The relevant circuit areas in the circuit image are extracted through the image segmentation algorithm, and the edges are accurately extracted to facilitate the subsequent circuit diagram modeling.

4. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 3, characterized in that: The image segmentation algorithm in the image preprocessing includes: Canny edge detection algorithm, used to accurately extract the edges of circuit paths and avoid noise interference; Otsu threshold segmentation method is used to standardize each layer of image into a grayscale image for subsequent processing; The region growing method identifies the circuit region in image segmentation and divides the image region into related circuit regions to ensure that the image region is complete and valid.

5. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 1, characterized in that: The circuit diagram modeling includes: Assign impedance values ​​to the current paths in each layer of the circuit image, and define the edge weight as the resistance of the path; Calibrate the nodes of each layer of the circuit diagram to identify the electrical connection points and their corresponding current flow paths; Multi-layer circuit diagrams are expressed using graph structures to ensure that the coupling relationship between circuits at different layers is fully expressed in the graph model.

6. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 5, characterized in that: The node calibration includes: Use Hough transform algorithm to identify straight current paths in circuit diagrams and calibrate them with electrical connection points; Automatically calibrate the nodes of each layer of the circuit diagram, and use the template matching algorithm to detect and match the electrical connection points; The current flow on the path is accurately modeled, and the current flow path tracing algorithm is used to simulate the current path in each layer of the circuit diagram.

7. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 1, characterized in that: The multi-layer graph optimization calculation includes: By defining the objective function, the resistance value of each edge and the coupling strength of the cross-layer connection are combined for joint optimization; Use graph optimization algorithms to calculate the minimum resistance of each path and preliminarily determine the short-circuit area; The cross-layer circuit paths are optimized through heuristic algorithms to improve the accuracy of fault point identification.

8. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 1, characterized in that: The Bayesian inference for probability estimation includes: Based on real-time thermal imaging data and 3D imaging data, a prior distribution is constructed to represent the probability of short circuit occurrence in each circuit path. The posterior probability of each potential short-circuit point is calculated by combining the observed data with the Bayesian theorem; Dynamically update the posterior probability of the fault point to locate the fault point in real time and accurately.

9. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 1, characterized in that: The joint optimization and short-circuit point location include: Combine the graph optimization calculation results with the posterior probability obtained by Bayesian reasoning to determine the final location of each potential short-circuit point; For the potential short-circuit point located, use partial discharge detection equipment to verify whether it is the real fault point; Feed the test results back to the system to optimize the subsequent short-circuit detection process.

10. The short circuit failure analysis method of a miniature microphone multilayer substrate according to claim 9, characterized in that: The partial discharge detection device comprises: Current fluctuation detector, used to monitor current changes and confirm fault points through current fluctuation analysis; Temperature sensor, used to detect temperature changes in the short-circuit area and confirm whether the current increases abnormally; The discharge signal capturer combines current fluctuations and temperature changes to record partial discharge signals in real time and analyze the fault points through software.

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